WO2020084858A1 - Semiconductor integrated optical device - Google Patents

Semiconductor integrated optical device Download PDF

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Publication number
WO2020084858A1
WO2020084858A1 PCT/JP2019/030503 JP2019030503W WO2020084858A1 WO 2020084858 A1 WO2020084858 A1 WO 2020084858A1 JP 2019030503 W JP2019030503 W JP 2019030503W WO 2020084858 A1 WO2020084858 A1 WO 2020084858A1
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layer
type
integrated device
optical integrated
semiconductor
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PCT/JP2019/030503
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French (fr)
Japanese (ja)
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直幹 中村
八木　哲哉
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三菱電機株式会社
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Priority to JP2020505940A priority Critical patent/JPWO2020084858A1/en
Priority to TW108137224A priority patent/TW202017269A/en
Publication of WO2020084858A1 publication Critical patent/WO2020084858A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30

Definitions

  • the present application relates to a semiconductor optical integrated device in which a plurality of optical semiconductor devices are integrated.
  • Patent Document 1 discloses a structure in which a semi-insulating Fe-doped InP layer and an n-type InP layer are stacked on an n-type InP substrate having conductivity, and an active layer and a p-type InP layer are stacked thereon.
  • a method for ensuring insulation between cathodes between adjacent elements by providing a cathode electrode in the n-type InP layer and an anode electrode in the p-type InP layer and forming a groove reaching the Fe-doped InP layer between the elements Is disclosed.
  • Patent Document 2 as a method for ensuring insulation between adjacent elements, a p-type-n-type-p type or an n-type-p-type-n structure is provided on a substrate and There is disclosed a method of ensuring cathode-to-cathode isolation between devices by forming a groove reaching the substrate.
  • JP-A-8-046279 (paragraphs 0025 to 0031, FIG. 1) Japanese Patent Laid-Open No. 11-274634 (paragraphs 0028 to 0110, FIG. 1)
  • Patent Document 1 in consideration of the energy band structure of each layer, at the junction boundary between the n-type InP layer and the Fe-doped InP layer or the p-type InP layer, a potential barrier for an electron that is a carrier for the n-type conductivity type is provided. Form. When the potential barrier is formed, it cannot penetrate into the Fe-doped InP layer or the p-type InP layer.
  • the amount of current (the amount of electrons) supplied to the n-type InP layer increases, there are not a few electrons that have the energy to overcome the potential barrier, which causes a leakage current and reduces the insulation between the elements.
  • the current supplied to the n-type InP layer cannot sufficiently block the current leaking toward the substrate only by inserting the Fe-doped InP layer or the p-type InP layer.
  • a leakage current flows between the cathode electrodes and the isolation cannot be secured.
  • the p-type InP layer is doped at a higher concentration in order to increase the potential barrier, but if a thick p-type-doped layer exists near the active layer, a p-type layer is formed. Light loss increases due to carrier absorption or valence band absorption by the carriers that are generated. Therefore, there is a problem that the optical output characteristics of the laser deteriorate.
  • Patent Document 2 has a problem that the structure is not suitable for manufacturing an element, for example, the layer thickness of each layer is 3 ⁇ m and a considerable layer thickness is required from the viewpoint of crystal growth.
  • the present application discloses a technique for solving the above problems, and suppresses a leakage current through a substrate and absorption loss of light, secures isolation, and is suitable for manufacturing an element.
  • An object is to provide a semiconductor optical integrated device that can realize a structure.
  • a semiconductor optical integrated device disclosed in the present application includes an epitaxial layer formed on a surface of an InP substrate by epitaxially growing a material having a wider bandgap than that of the InP substrate, and formed on the surface of the epitaxial layer to penetrate the epitaxial layer. And a plurality of optical semiconductor elements arranged in a row with an isolation groove reaching the InP substrate interposed therebetween.
  • the leakage current and the absorption of light through the substrate are formed by forming the isolation groove that penetrates the epitaxial layer made of a material having a wider band gap than the InP substrate and reaches the substrate between the optical semiconductor elements.
  • a structure suitable for manufacturing an element can be realized while suppressing loss and ensuring isolation.
  • FIG. 1 is a perspective view showing a configuration of a semiconductor optical integrated device according to a first embodiment.
  • FIG. 3 is a sectional view and a potential distribution diagram showing the configuration of the semiconductor optical integrated device according to the first embodiment.
  • FIG. 9 is a cross-sectional view and a potential distribution diagram showing a configuration of a conventional semiconductor optical integrated device.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. It is sectional drawing which shows the structure of the conventional semiconductor optical integrated device.
  • FIG. 4 is a diagram showing an example of a result of simulating an isolation resistance in the structure of the semiconductor optical integrated device according to the first embodiment.
  • FIG. 9 is a cross-sectional view showing a configuration of a semiconductor optical integrated device according to a second embodiment.
  • FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the second embodiment.
  • FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the second embodiment.
  • FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the second embodiment.
  • FIG. 1 is a perspective view showing the configuration of the semiconductor optical integrated device according to the first embodiment.
  • 2A is a cross-sectional view of the semiconductor optical integrated device at the position of arrow AA in FIG.
  • the semiconductor optical integrated device 503 is an array-type optical semiconductor device formed on a semi-insulating semiconductor substrate, and includes an Fe-doped semi-insulating InP substrate 101 and an Fe-doped semi-insulating InP substrate.
  • the InP cladding layer 106 is formed.
  • the semiconductor optical integrated device 503 includes a plurality of semiconductor laser devices 120 as semiconductor devices including the n-type InP clad layer 103, the active layer 104, the current blocking layer 105, and the p-type InP clad layer.
  • the anode electrode 108 is provided on the surface of the p-type InP clad layer at the top of the ridge portion 103a
  • the cathode electrode 109 is provided on the n-type InP clad layer 103 beside the ridge portion 103a.
  • an isolation groove 110 whose bottom reaches the surface of the p-type AlInAs layer 102 is provided between the semiconductor laser devices 120, and each semiconductor laser device 120 is electrically separated by the isolation groove 110. It is designed to be insulated.
  • An insulating film 107 is formed on the surface of the semiconductor optical integrated device 503 except for the portion where the anode electrode 108 and the cathode electrode 109 are provided.
  • the Fe-doped semi-insulating InP substrate 101 is a semi-insulating semiconductor substrate, and is a Fe-doped semi-insulating InP substrate.
  • the p-type AlInAs layer 102 is an epitaxial layer formed on the surface of the Fe-doped semi-insulating InP substrate 101 and made of a material having a wider band gap than the semiconductor material InP used for the semi-insulating semiconductor substrate.
  • the n-type InP clad layer 103 is laminated on the p-type AlInAs layer 102, and the ridge portion 103a is provided on the surface.
  • An active layer 104 is formed on the ridge portion 103a of the n-type InP clad layer 103, and current blocking layers 105 are provided on both sides of the ridge portion 103a and the active layer 104.
  • a quaternary mixed crystal semiconductor material such as InGaAsP is used.
  • the current blocking layer 105 constricts the current in the ridge 103a portion in order to increase the luminous efficiency of the active layer 104.
  • the p-type InP clad layer 106 is formed on the active layer 104 at the top of the ridge 103 a sandwiched by the current blocking layers 105.
  • FIG. 2B is a diagram showing a potential distribution in the Fe-doped semi-insulating InP substrate 101, the p-type AlInAs layer 102, and the n-type InP clad layer 103 in the semiconductor optical integrated device 503.
  • VB is a valence band
  • CB is a conduction band energy band.
  • bands are discontinuous at the interface between the Fe-doped semi-insulating InP substrate 101 and the p-type AlInAs layer 102, and the interface between the p-type AlInAs layer 102 and the n-type InP clad layer 103.
  • the potential for electrons E is increased between the n-type InP clad layer 103 and the Fe-doped semi-insulating InP substrate 101. Barriers can be provided. Due to this potential barrier, the electrons E are less likely to leak to the Fe-doped semi-insulating InP substrate side, and insulation can be secured.
  • the p-type AlInAs layer 102 serves as a layer for suppressing leakage current.
  • the carrier concentration of the p-type AlInAs layer may be any carrier concentration as long as it is p-type.
  • the p-type AlInAs layer can maintain a potential barrier for electrons regardless of the carrier concentration, and can suppress leakage current of electrons into the Fe-doped semi-insulating InP substrate 101.
  • the p-type InP layer 111 is used instead of the p-type AlInAs layer.
  • 3A is a cross-sectional view showing a configuration of a conventional semiconductor optical integrated device
  • FIG. 3B is a Fe-doped semi-insulating InP substrate 101 and p-type InP layer 111 in the semiconductor optical integrated device 503.
  • 3 is a diagram showing a potential distribution in the n-type InP clad layer 103.
  • FIG. In FIG. 3B VB is a valence band and CB is a conduction band energy band.
  • FIGS. 4 to 15 are sectional views showing the manufacturing steps of the semiconductor optical integrated device 503 according to the first embodiment.
  • AlInAs 102, n-type InP clad layer 103, active layer 104, and p-type InP clad layer 106 are sequentially laminated on the surface of Fe-doped semi-insulating InP substrate 101 by epitaxial growth. These are crystal-grown by a metal organic chemical vapor deposition (MOCVD, hereinafter MOCVD) method.
  • MOCVD metal organic chemical vapor deposition
  • an insulating film is formed on the surface of the p-type InP clad layer 106 and is etched to form a stripe-shaped insulating film 112. To form.
  • the p-type InP clad layer 106 and the active layer 104 are etched into stripes using the formed insulating film 112 as a mask, and the n-type InP clad layer 103 is formed to a thickness of about half the film thickness. Etching is performed up to the position in a stripe shape to form a ridge portion 103a in the n-type InP clad layer 103.
  • the insulating film 112 used for forming the ridge portion 103a is used as a mask to fill the n-type InP clad layer 103 with the current block layer 105 on both sides of the p-type InP clad layer 106.
  • Epitaxial growth is performed up to the position by the MOCVD method.
  • the insulating film 112 used as a mask for processing and forming the ridge portion 103a and growing the current blocking layer 105 is removed.
  • an etching solution such as hydrofluoric acid is used.
  • the p-type InP clad layer 106 is further epitaxially grown on the exposed p-type InP clad layer 106 and the current blocking layer 105.
  • an insulating film is formed on the entire surface of the grown p-type InP clad layer 106, and the active layer 104 and the current blocking layers 105 on both sides of the active layer 104 are partially included in the width. Etching is done in stripes.
  • the p-type InP clad layer 106 and the current block layer 105 are etched by using the formed insulating film 114 as a mask so as to reach the root portion of the ridge portion 103a of the n-type InP clad layer 103. , Mesa groove 115b is provided. After the etching process, the insulating film 114 is removed by etching with hydrofluoric acid or the like.
  • an insulating film 116 is formed on the entire surface provided with the mesa groove 115b, and the insulating film 116 covering the n-type InP clad layer 103 is etched at the bottom of the mesa groove 115b.
  • a stripe-shaped opening 116a is formed in a portion of the insulating film 116 that covers the n-type InP clad layer 103 next to the adjacent mesa 115a.
  • the isolation groove 110 is formed by performing etching processing until reaching. After the etching process, the insulating film 116 is removed by etching with hydrofluoric acid or the like.
  • an insulating film 107 is formed on the entire surface of the mesa groove 115b in which the isolation groove 110 is formed.
  • the film 107 is etched to form stripe-shaped openings 107a and 107b in the insulating film 107 portion covering the p-type InP clad layer 106 and the n-type InP clad layer 103, respectively.
  • an anode electrode 108 connected to the p-type InP clad layer 106 is formed in the opening 107a, and a cathode electrode 109 connected to the n-type InP clad layer 103 is formed in the opening 107b.
  • a semiconductor optical integrated device 503 as shown in a) is obtained.
  • a laser having a buried waveguide structure has been described here, a laser having a ridge waveguide structure may be used.
  • the conventional semiconductor optical integrated device corresponding to the semiconductor optical integrated device 503 uses the p-type InP layer 111 instead of the p-type AlInAs layer 102.
  • FIG. 17 is a diagram showing an example of a result of simulating the isolation resistance in the structure of the semiconductor optical integrated device 503 according to the second embodiment, in which a voltage is applied to the electrodes between adjacent cathodes and the voltage between the cathodes at that time is applied. Indicates the resistance value.
  • the Fe-doped semi-insulating InP substrate 101 is doped with Fe at 5 ⁇ 10 16 cm ⁇ 3
  • the p-type AlInAs layer 102 has a film thickness of 100 nm
  • the carrier concentration is 5 ⁇ 10 5.
  • n-type InP cladding layer 103 has a carrier concentration of 1 ⁇ 10 18 cm -3.
  • the conventional semiconductor optical integrated device was simulated with the structures shown in FIGS.
  • the p-type InP layer 111 has a film thickness of 100 nm and a carrier concentration of 5 ⁇ 10 16 cm ⁇ 3 .
  • the carrier concentration settings of the Fe-doped semi-insulating InP substrate 101 and the n-type InP cladding layer 103 of the conventional semiconductor optical integrated device were the same as those of the simulation model of the semiconductor optical integrated device 503.
  • the bottom of the isolation groove 110 penetrates the p-type AlInAs layer 102 and reaches the inside of the Fe-doped semi-insulating InP substrate 101.
  • the voltage applied across the cathodes of adjacent devices is almost the same. , A larger resistance value can be realized.
  • the isolation groove 110 is etched so as to penetrate the p-type AlInAs layer 102 and removed, so that the band discontinuity generated between the n-type InP clad layer 103 and the p-type AlInAs layer 102 is formed. Since it is possible to cut off the current path flowing therethrough, it is also possible to cut off the current flowing through the band discontinuity at the boundary between the Fe-doped semi-insulating InP substrate 101 and the p-type AlInAs layer 102. The resistance can be further increased. In particular, in the band structure at the boundary of these materials, electrons are easily trapped, and a so-called two-dimensional electron gas layer S1 is formed (see FIG. 2B).
  • the etching depth includes the boundary between the n-type InP clad layer 103 and the p-type AlInAs layer 102, and the etching is performed in the more substrate direction to penetrate the boundary (two-dimensional electron gas layer S1) of the material including the p-type AlInAs layer 102. It is desirable to provide it.
  • the p-type AlInAs layer 102 has a film thickness of only 100 nm and the carrier concentration is 5 ⁇ 10 16 cm ⁇ 3, which is close to the undoped level. Is also appropriate from the viewpoint of manufacturing and from the viewpoint of suppressing light loss due to carrier absorption.
  • the Fe-doped semi-insulating InP substrate 101 is formed on the surface of the Fe-doped semi-insulating InP substrate 101 via the two-dimensional electron gas layer S1.
  • Fe-doped semi-insulating InP substrate that penetrates the p-type AlInAs layer 102 and the two-dimensional electron gas layer S1 on the surface of the p-type AlInAs layer 102 which is obtained by epitaxially growing a material having a wider band gap than Since a plurality of semiconductor laser elements 120 are arranged in a row with an isolation groove 110 reaching the inside of 101 interposed therebetween, leakage current through the substrate and absorption loss of light are suppressed, Not only can isolation be ensured, a structure suitable for manufacturing devices can be realized, and further higher resistance can be achieved. Kill.
  • the isolation groove 110 is provided to separate and electrically insulate each semiconductor laser device 120, but in the second embodiment, ion implantation is performed instead of forming the isolation groove. About.
  • FIG. 18 is a sectional view showing the structure of the semiconductor optical integrated device according to the third embodiment.
  • the semiconductor optical integrated device 504 instead of forming the isolation groove 110 and separating each semiconductor laser device 120 in the first embodiment, a predetermined space is provided between the semiconductor laser devices 120 by ion implantation.
  • Each semiconductor laser element 120 is separated by implanting ions up to the depth of 1 to provide an ion implantation section 117 having a high resistance.
  • the other configurations of the semiconductor optical integrated device 504 according to the third embodiment are similar to those of the semiconductor optical integrated device 503 of the first embodiment, and corresponding parts are denoted by the same reference numerals and the description thereof will be omitted.
  • FIGS. 24 to 26 are cross-sectional views showing the manufacturing process of the semiconductor optical integrated device 504 according to the third embodiment.
  • a striped opening 116a is formed in a portion of the insulating film 116 covering the n-type InP cladding layer 103, and then the n-type InP exposed from the opening 116a is formed. Ions are implanted into the cladding layer 103 to form an ion-implanted portion 117, as shown in FIG. After forming the ion-implanted portion 117, the insulating film 116 is removed by etching with hydrofluoric acid or the like.
  • an insulating film 107 is formed on the entire surface of the mesa groove 115b on which the ion implantation portion 117 is formed.
  • an anode electrode 108 connected to the p-type InP clad layer 106 is formed in the opening 107a, and a cathode electrode 109 connected to the n-type InP clad layer 103 is formed in the opening 107b.
  • a semiconductor optical integrated device 504 as shown is obtained.
  • the ion implantation part 117 is provided instead of the isolation groove 110, so that the effects of the first and second embodiments can be obtained. Not only is it obtained, but since it is not necessary to form the isolation groove 110, the unevenness of the wafer surface at the time of device fabrication can be reduced, and the ease of manufacturing is improved.
  • the present invention is not limited to this.
  • An n-type or undoped AlInAs layer may be formed.
  • the p-type AlInAs layer 102 may be replaced with another material having a bandgap larger than that of InP.
  • the band gap of InP is 1.344 eV. growing.
  • the layer is not limited to the p-type Al y Ga x In (1-xy) As layer, and an n-type or undoped Al y Ga x In (1-xy) As layer may be formed. Good.
  • the n-type AlInAs layer or the n-type Al y Ga x In (1-xy) As is formed, the n-type InP clad layer 103 is a p-type InP clad layer, and the p-type InP clad layer 106 is an n-type.
  • the InP clad layer, the anode electrode 108 is a cathode electrode, and the cathode electrode 109 is an anode electrode.
  • the p-type Al y Ga x In (1-xy) As When the p-type Al y Ga x In (1-xy) As is formed, it has the same configuration as that of the first embodiment. When an undoped Al y Ga x In (1-xy) As layer is formed, either structure may be used. In any case, it is possible to obtain the same effect as that of the above embodiment.
  • the Fe-doped semi-insulating InP substrate 101 is used as the InP substrate, the present invention is not limited to this.
  • An n-type InP substrate or a p-type InP substrate may be used.
  • an n-type InP substrate may be doped with S or Si, and a p-type InP substrate may be doped with Zn, Mg or the like.
  • the same effect as that of the above embodiment can be obtained. Since the leakage current in the substrate direction is suppressed by a material having a wider bandgap than the substrate material formed on the substrate, the substrate polarity does not matter.
  • an n-type semiconductor substrate is preferable from the viewpoint of laser characteristics due to light absorption. It is generally known that absorption by electrons having n-type conductivity has a smaller light absorption coefficient than holes having p-type conductivity.
  • the invention is not limited to this.
  • the optical semiconductor element and the electronic device other than the optical semiconductor element may be arranged, and the cathode or the anode of the optical semiconductor element and the electronic device other than the optical semiconductor element may be electrically separated. Also in this case, the same effect as that of the above embodiment can be obtained.
  • 101 Fe-doped semi-insulating InP substrate 102 p-type AlInAs layer, 103 n-type InP clad layer, 103a ridge portion, 104 active layer, 105 current blocking layer, 106 p-type InP clad layer, 110 isolation groove, 117 ion implantation Part, 120 semiconductor laser device, 503, 504 semiconductor optical integrated device.

Abstract

This semiconductor integrated optical device is provided with a p-type AlInAs layer (102) which is formed on the surface of an Fe-doped semi-insulating InP substrate (101), with a two-dimensional electron gas layer (S1) interposed therebetween, by epitaxially growing a material that has a wider band gap than the Fe-doped semi-insulating InP substrate (101), and multiple semiconductor laser devices (120) which are formed on the surface of the p-type AlInAs layer (102) and which are arranged in a row separated by isolation grooves (110) which pass through the p-type AlInAs layer (102) and the two-dimensional electron gas layer (S1) and reach the inside of the Fe-doped semi-insulating InP substrate (101). This semiconductor integrated optical device suppresses absorption loss of light and leakage current through the substrate, ensures isolation, and enables achieving structure suitable for device manufacture.

Description

半導体光集積素子Semiconductor optical integrated device
　本願は、複数の光半導体素子を集積した半導体光集積素子に関するものである。 The present application relates to a semiconductor optical integrated device in which a plurality of optical semiconductor devices are integrated.
　半導体光集積素子において、各素子間のカソード間のアイソレーションを確保するための手段が、例えば特許文献１および特許文献２に開示されている。特許文献１には、導電性を有するｎ型ＩｎＰ基板上に、半絶縁性を示すＦｅドープＩｎＰ層と、ｎ型ＩｎＰ層を積層し、この上に活性層、ｐ型ＩｎＰ層を積層した構造で、ｎ型ＩｎＰ層にカソード電極を、ｐ型ＩｎＰ層にアノード電極を設け、素子間にＦｅドープＩｎＰ層に達する溝を形成することで、隣接素子間のカソード間の絶縁性を確保する方法が開示されている。また、特許文献２では、隣接素子間の絶縁を確保する手法として、基板上に、ｐ型－ｎ型－ｐ型もしくは、ｎ型－ｐ型－ｎ型の構造を有し、隣接素子間に基板まで達する溝を形成することで、素子間のカソード間アイソレーションを確保する方法が開示されている。 In a semiconductor optical integrated device, means for ensuring isolation between cathodes between the respective devices are disclosed in, for example, Patent Document 1 and Patent Document 2. Patent Document 1 discloses a structure in which a semi-insulating Fe-doped InP layer and an n-type InP layer are stacked on an n-type InP substrate having conductivity, and an active layer and a p-type InP layer are stacked thereon. A method for ensuring insulation between cathodes between adjacent elements by providing a cathode electrode in the n-type InP layer and an anode electrode in the p-type InP layer and forming a groove reaching the Fe-doped InP layer between the elements Is disclosed. Further, in Patent Document 2, as a method for ensuring insulation between adjacent elements, a p-type-n-type-p type or an n-type-p-type-n structure is provided on a substrate and There is disclosed a method of ensuring cathode-to-cathode isolation between devices by forming a groove reaching the substrate.
特開平８－０４６２７９号公報（段落００２５～００３１、図１）JP-A-8-046279 (paragraphs 0025 to 0031, FIG. 1) 特開平１１－２７４６３４号公報（段落００２８～０１１０、図１）Japanese Patent Laid-Open No. 11-274634 (paragraphs 0028 to 0110, FIG. 1)
　特許文献１では、各層のエネルギーバンド構造を考えた場合、ｎ型ＩｎＰ層とＦｅドープＩｎＰ層もしくはｐ型ＩｎＰ層の接合境界では、ｎ型の導電型を担うキャリアである電子にとってのポテンシャル障壁を形成する。ポテンシャル障壁が形成されると、ＦｅドープＩｎＰ層もしくは、ｐ型ＩｎＰ層に侵入することができなくなる。 In Patent Document 1, in consideration of the energy band structure of each layer, at the junction boundary between the n-type InP layer and the Fe-doped InP layer or the p-type InP layer, a potential barrier for an electron that is a carrier for the n-type conductivity type is provided. Form. When the potential barrier is formed, it cannot penetrate into the Fe-doped InP layer or the p-type InP layer.
　しかしながら、ｎ型ＩｎＰ層に供給される電流量（電子の量）が多くなると、ポテンシャル障壁を乗り越えるエネルギーを有する電子が少なからず存在し、これが漏れ電流となり素子間の絶縁性を低下させる。つまり、ｎ型ＩｎＰ層に供給された電流は、ＦｅドープＩｎＰ層、あるいはｐ型ＩｎＰ層を挿入しただけでは、基板方向へ漏れる電流を十分に遮断することができず、このため、基板を介してカソード電極間に漏れ電流が流れ、アイソレーションが確保できないという問題があった。 However, when the amount of current (the amount of electrons) supplied to the n-type InP layer increases, there are not a few electrons that have the energy to overcome the potential barrier, which causes a leakage current and reduces the insulation between the elements. In other words, the current supplied to the n-type InP layer cannot sufficiently block the current leaking toward the substrate only by inserting the Fe-doped InP layer or the p-type InP layer. As a result, there is a problem that a leakage current flows between the cathode electrodes and the isolation cannot be secured.
　また、ｐ型ＩｎＰ層においては、上記ポテンシャル障壁を高くするために、より高濃度にドーピングされるが、活性層近傍に高濃度にｐ型ドーピングされた厚い層が存在すると、ｐ型層を形成するキャリアによるキャリア吸収または価電子帯間吸収によって、光の損失が増加する。よって、レーザの光出力特性が悪化するという問題があった。 Further, the p-type InP layer is doped at a higher concentration in order to increase the potential barrier, but if a thick p-type-doped layer exists near the active layer, a p-type layer is formed. Light loss increases due to carrier absorption or valence band absorption by the carriers that are generated. Therefore, there is a problem that the optical output characteristics of the laser deteriorate.
　特許文献２の構造では、各層の層厚が３μｍなど、結晶成長の観点ではかなりの層厚を必要とするなど、素子を製造するに適した構造ではないという問題があった。 The structure of Patent Document 2 has a problem that the structure is not suitable for manufacturing an element, for example, the layer thickness of each layer is 3 μm and a considerable layer thickness is required from the viewpoint of crystal growth.
　本願は、上記のような課題を解決するための技術を開示するものであり、基板を介した漏れ電流および光の吸収損失を抑制し、アイソレーションを確保するとともに、素子を製造するに適した構造を実現できる半導体光集積素子を提供することを目的とする。 The present application discloses a technique for solving the above problems, and suppresses a leakage current through a substrate and absorption loss of light, secures isolation, and is suitable for manufacturing an element. An object is to provide a semiconductor optical integrated device that can realize a structure.
　本願に開示される半導体光集積素子は、ＩｎＰ基板の表面に、前記ＩｎＰ基板よりもバンドギャップが広い材料をエピタキシャル成長させたエピタキシャル層と、前記エピタキシャル層の表面に形成され、前記エピタキシャル層を貫通し、前記ＩｎＰ基板に達するアイソレーション溝を挟んで列状に配列して構成された複数の光半導体素子とを備えたことを特徴とする。 A semiconductor optical integrated device disclosed in the present application includes an epitaxial layer formed on a surface of an InP substrate by epitaxially growing a material having a wider bandgap than that of the InP substrate, and formed on the surface of the epitaxial layer to penetrate the epitaxial layer. And a plurality of optical semiconductor elements arranged in a row with an isolation groove reaching the InP substrate interposed therebetween.
　本願によれば、光半導体素子間に、ＩｎＰ基板よりもバンドギャップが広い材料からなるエピタキシャル層を貫通し、基板に達するアイソレーション溝を形成することにより、基板を介した漏れ電流および光の吸収損失を抑制し、アイソレーションを確保するとともに、素子を製造するに適した構造を実現できる。 According to the present application, the leakage current and the absorption of light through the substrate are formed by forming the isolation groove that penetrates the epitaxial layer made of a material having a wider band gap than the InP substrate and reaches the substrate between the optical semiconductor elements. A structure suitable for manufacturing an element can be realized while suppressing loss and ensuring isolation.
実施の形態１による半導体光集積素子の構成を示す斜視図である。1 is a perspective view showing a configuration of a semiconductor optical integrated device according to a first embodiment. 実施の形態１による半導体光集積素子の構成を示す断面図およびポテンシャル分布図である。FIG. 3 is a sectional view and a potential distribution diagram showing the configuration of the semiconductor optical integrated device according to the first embodiment. 従来の半導体光集積素子の構成を示す断面図およびポテンシャル分布図である。FIG. 9 is a cross-sectional view and a potential distribution diagram showing a configuration of a conventional semiconductor optical integrated device. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 実施の形態１による半導体光集積素子の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment. 従来の半導体光集積素子の構成を示す断面図である。It is sectional drawing which shows the structure of the conventional semiconductor optical integrated device. 実施の形態１による半導体光集積素子の構造でのアイソレーション抵抗をシミュレーションした結果の例を示す図である。FIG. 4 is a diagram showing an example of a result of simulating an isolation resistance in the structure of the semiconductor optical integrated device according to the first embodiment. 実施の形態２による半導体光集積素子の構成を示す断面図である。FIG. 9 is a cross-sectional view showing a configuration of a semiconductor optical integrated device according to a second embodiment. 実施の形態２による半導体光集積素子の製造方法を示す断面図である。FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the second embodiment. 実施の形態２による半導体光集積素子の製造方法を示す断面図である。FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the second embodiment. 実施の形態２による半導体光集積素子の製造方法を示す断面図である。FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the second embodiment.
　実施の形態１．
　図１は、実施の形態１における半導体光集積素子の構成を示す斜視図である。図２（ａ）は、図１のＡＡの矢視位置での半導体光集積素子の断面図である。 Embodiment 1.
FIG. 1 is a perspective view showing the configuration of the semiconductor optical integrated device according to the first embodiment. 2A is a cross-sectional view of the semiconductor optical integrated device at the position of arrow AA in FIG.
　図１および図２に示すように、半導体光集積素子５０３は、半絶縁半導体基板上に作成されるアレイ型光半導体素子であり、Ｆｅドープ半絶縁性ＩｎＰ基板１０１、Ｆｅドープ半絶縁性ＩｎＰ基板１０１の表面に形成されたｐ型ＡｌＩｎＡｓ層１０２、ｐ型ＡｌＩｎＡｓ層１０２の上に形成された、リッジ部１０３ａが設けられたｎ型ＩｎＰクラッド層１０３、ｎ型ＩｎＰクラッド層１０３のリッジ部１０３ａの上に形成された活性層１０４、リッジ部１０３ａと活性層１０４の両側に設けられた電流ブロック層１０５、電流ブロック層１０５で挟まれたリッジ部１０３ａ頂上部分の活性層１０４上に形成されたｐ型ＩｎＰクラッド層１０６で構成される。 As shown in FIGS. 1 and 2, the semiconductor optical integrated device 503 is an array-type optical semiconductor device formed on a semi-insulating semiconductor substrate, and includes an Fe-doped semi-insulating InP substrate 101 and an Fe-doped semi-insulating InP substrate. A p-type AlInAs layer 102 formed on the surface of 101, an n-type InP clad layer 103 provided on the p-type AlInAs layer 102 and provided with a ridge 103a, and a ridge 103a of the n-type InP clad 103. The active layer 104 formed above, the ridge portion 103a and the current blocking layer 105 provided on both sides of the active layer 104, and the p formed on the active layer 104 at the top of the ridge portion 103a sandwiched by the current blocking layers 105. The InP cladding layer 106 is formed.
　半導体光集積素子５０３は、上記のｎ型ＩｎＰクラッド層１０３、活性層１０４、電流ブロック層１０５、ｐ型ＩｎＰクラッド層で構成される半導体素子としての半導体レーザ素子１２０を複数備える。半導体レーザ素子１２０は、リッジ部１０３ａの頂上部分のｐ型ＩｎＰクラッド層の表面に、アノード電極１０８が設けられ、リッジ部１０３ａ横のｎ型ＩｎＰクラッド層１０３上に、カソード電極１０９が設けられる。半導体光集積素子５０３では、半導体レーザ素子１２０間に、底部がｐ型ＡｌＩｎＡｓ層１０２の表面に達するアイソレーション溝１１０が設けられ、アイソレーション溝１１０によって各々の半導体レーザ素子１２０が分離され電気的に絶縁される構成となっている。半導体光集積素子５０３の表面は、アノード電極１０８とカソード電極１０９が設けられた部分を除いて、絶縁膜１０７が形成されている。 The semiconductor optical integrated device 503 includes a plurality of semiconductor laser devices 120 as semiconductor devices including the n-type InP clad layer 103, the active layer 104, the current blocking layer 105, and the p-type InP clad layer. In the semiconductor laser device 120, the anode electrode 108 is provided on the surface of the p-type InP clad layer at the top of the ridge portion 103a, and the cathode electrode 109 is provided on the n-type InP clad layer 103 beside the ridge portion 103a. In the semiconductor optical integrated device 503, an isolation groove 110 whose bottom reaches the surface of the p-type AlInAs layer 102 is provided between the semiconductor laser devices 120, and each semiconductor laser device 120 is electrically separated by the isolation groove 110. It is designed to be insulated. An insulating film 107 is formed on the surface of the semiconductor optical integrated device 503 except for the portion where the anode electrode 108 and the cathode electrode 109 are provided.
　Ｆｅドープ半絶縁性ＩｎＰ基板１０１は、半絶縁半導体基板であり、Ｆｅがドーピングされた半絶縁性のＩｎＰ基板である。ｐ型ＡｌＩｎＡｓ層１０２は、Ｆｅドープ半絶縁性ＩｎＰ基板１０１の表面に形成され、半絶縁半導体基板に使用される半導体材料ＩｎＰよりもバンドギャップが広い材料からなるエピタキシャル層である。 The Fe-doped semi-insulating InP substrate 101 is a semi-insulating semiconductor substrate, and is a Fe-doped semi-insulating InP substrate. The p-type AlInAs layer 102 is an epitaxial layer formed on the surface of the Fe-doped semi-insulating InP substrate 101 and made of a material having a wider band gap than the semiconductor material InP used for the semi-insulating semiconductor substrate.
　ｎ型ＩｎＰクラッド層１０３は、ｐ型ＡｌＩｎＡｓ層１０２の上に積層され、表面にリッジ部１０３ａが設けられている。ｎ型ＩｎＰクラッド層１０３のリッジ部１０３ａ上には、活性層１０４が形成され、リッジ部１０３ａおよび活性層１０４の両側部には電流ブロック層１０５が設けられる。活性層１０４には、例えばＩｎＧａＡｓＰといった四元系混晶半導体材料が用いられる。電流ブロック層１０５は、活性層１０４の発光効率を高めるために、リッジ１０３ａ部分に電流を狭窄する。ｐ型ＩｎＰクラッド層１０６は、電流ブロック層１０５で挟まれたリッジ部１０３ａ頂上部分の活性層１０４上に形成される。 The n-type InP clad layer 103 is laminated on the p-type AlInAs layer 102, and the ridge portion 103a is provided on the surface. An active layer 104 is formed on the ridge portion 103a of the n-type InP clad layer 103, and current blocking layers 105 are provided on both sides of the ridge portion 103a and the active layer 104. For the active layer 104, a quaternary mixed crystal semiconductor material such as InGaAsP is used. The current blocking layer 105 constricts the current in the ridge 103a portion in order to increase the luminous efficiency of the active layer 104. The p-type InP clad layer 106 is formed on the active layer 104 at the top of the ridge 103 a sandwiched by the current blocking layers 105.
　図２（ｂ）は、半導体光集積素子５０３でのＦｅドープ半絶縁性ＩｎＰ基板１０１、ｐ型ＡｌＩｎＡｓ層１０２およびｎ型ＩｎＰクラッド層１０３におけるポテンシャル分布を示す図である。なお、図２（ｂ）において、ＶＢは価電子帯、ＣＢは導伝帯のエネルギーバンドである。図２（ｂ）に示すように、Ｆｅドープ半絶縁性ＩｎＰ基板１０１とｐ型ＡｌＩｎＡｓ層１０２の界面、およびｐ型ＡｌＩｎＡｓ層１０２とｎ型ＩｎＰクラッド層１０３の界面は、バンドが不連続となるだけではなく、ｐ型ＡｌＩｎＡｓ層１０２は、Ｆｅドープ半絶縁性ＩｎＰ基板１０１よりもバンドギャップが大きいため、ｎ型ＩｎＰクラッド層１０３とＦｅドープ半絶縁性ＩｎＰ基板１０１との間に電子Ｅに対するポテンシャル障壁を設けることができる。このポテンシャル障壁によって、電子ＥはＦｅドープ半絶縁性ＩｎＰ基板側に漏れにくくなり、絶縁を確保することができる。このｐ型ＡｌＩｎＡｓ層１０２が、漏れ電流を抑制するための層となる。 FIG. 2B is a diagram showing a potential distribution in the Fe-doped semi-insulating InP substrate 101, the p-type AlInAs layer 102, and the n-type InP clad layer 103 in the semiconductor optical integrated device 503. In FIG. 2B, VB is a valence band and CB is a conduction band energy band. As shown in FIG. 2B, bands are discontinuous at the interface between the Fe-doped semi-insulating InP substrate 101 and the p-type AlInAs layer 102, and the interface between the p-type AlInAs layer 102 and the n-type InP clad layer 103. Not only that, since the p-type AlInAs layer 102 has a larger bandgap than the Fe-doped semi-insulating InP substrate 101, the potential for electrons E is increased between the n-type InP clad layer 103 and the Fe-doped semi-insulating InP substrate 101. Barriers can be provided. Due to this potential barrier, the electrons E are less likely to leak to the Fe-doped semi-insulating InP substrate side, and insulation can be secured. The p-type AlInAs layer 102 serves as a layer for suppressing leakage current.
　なお、ｐ型ＡｌＩｎＡｓ層のキャリア濃度は、ｐ型であればどのようなキャリア濃度であっても構わない。ｐ型ＡｌＩｎＡｓ層は、キャリア濃度にかかわらず、電子に対するポテンシャル障壁を保つことができ、電子がＦｅドープ半絶縁性ＩｎＰ基板１０１への漏れ電流を抑制することができる。 The carrier concentration of the p-type AlInAs layer may be any carrier concentration as long as it is p-type. The p-type AlInAs layer can maintain a potential barrier for electrons regardless of the carrier concentration, and can suppress leakage current of electrons into the Fe-doped semi-insulating InP substrate 101.
　従来の半導体光集積素子においては、ｐ型ＡｌＩｎＡｓ層ではなく、ｐ型ＩｎＰ層１１１が用いられている。図３（ａ）は、従来の半導体光集積素子の構成を示す断面図であり、図３（ｂ）は、半導体光集積素子５０３でのＦｅドープ半絶縁性ＩｎＰ基板１０１、ｐ型ＩｎＰ層１１１およびｎ型ＩｎＰクラッド層１０３におけるポテンシャル分布を示す図である。なお、図３（ｂ）において、ＶＢは価電子帯、ＣＢは導伝帯のエネルギーバンドである。従来の半導体光集積素子のように、ｐ型ＩｎＰ層１１１を用いた場合には、電子に対して十分なポテンシャル障壁が得られないため、電子が基板側に漏れ、絶縁抵抗が低下する。 In the conventional semiconductor optical integrated device, the p-type InP layer 111 is used instead of the p-type AlInAs layer. 3A is a cross-sectional view showing a configuration of a conventional semiconductor optical integrated device, and FIG. 3B is a Fe-doped semi-insulating InP substrate 101 and p-type InP layer 111 in the semiconductor optical integrated device 503. 3 is a diagram showing a potential distribution in the n-type InP clad layer 103. FIG. In FIG. 3B, VB is a valence band and CB is a conduction band energy band. When the p-type InP layer 111 is used as in the conventional semiconductor optical integrated device, a sufficient potential barrier for electrons cannot be obtained, so electrons leak to the substrate side and the insulation resistance decreases.
次に、実施の形態１における半導体光集積素子５０３の製造方法について、図４から図１５に基づき説明する。図４から図１５は、実施の形態１による半導体光集積素子５０３の製造工程を示す断面図である。 Next, a method of manufacturing the semiconductor optical integrated device 503 according to the first embodiment will be described with reference to FIGS. 4 to 15 are sectional views showing the manufacturing steps of the semiconductor optical integrated device 503 according to the first embodiment.
　まず、図４に示すように、Ｆｅドープ半絶縁性ＩｎＰ基板１０１の表面に、ＡｌＩｎＡｓ１０２、ｎ型ＩｎＰクラッド層１０３、活性層１０４、ｐ型ＩｎＰクラッド層１０６をエピタキシャル成長により順次積層する。これらは、有機金属気相化学成長（Metal Organic Chemical Vapor Deposition：ＭＯＣＶＤ、以下ＭＯＣＶＤ）法により、結晶成長させる。 First, as shown in FIG. 4, AlInAs 102, n-type InP clad layer 103, active layer 104, and p-type InP clad layer 106 are sequentially laminated on the surface of Fe-doped semi-insulating InP substrate 101 by epitaxial growth. These are crystal-grown by a metal organic chemical vapor deposition (MOCVD, hereinafter MOCVD) method.
　続いて、図５に示すように、ｐ型ＩｎＰクラッド層１０６まで順次積層した後、ｐ型ＩｎＰクラッド層１０６の表面に、絶縁膜を成膜し、エッチング加工することでストライプ状の絶縁膜１１２を形成する。 Subsequently, as shown in FIG. 5, after the p-type InP clad layer 106 is sequentially laminated, an insulating film is formed on the surface of the p-type InP clad layer 106 and is etched to form a stripe-shaped insulating film 112. To form.
　次いで、図６に示すように、形成した絶縁膜１１２をマスクとして、ｐ型ＩｎＰクラッド層１０６、活性層１０４をストライプ状にエッチング加工し、さらにｎ型ＩｎＰクラッド層１０３を膜厚の半分程度の位置までストライプ状にエッチング加工をして、ｎ型ＩｎＰクラッド層１０３にリッジ部１０３ａを形成する。 Next, as shown in FIG. 6, the p-type InP clad layer 106 and the active layer 104 are etched into stripes using the formed insulating film 112 as a mask, and the n-type InP clad layer 103 is formed to a thickness of about half the film thickness. Etching is performed up to the position in a stripe shape to form a ridge portion 103a in the n-type InP clad layer 103.
　続いて、図７に示すように、リッジ部１０３ａの加工形成に用いた絶縁膜１１２をマスクとして、ｎ型ＩｎＰクラッド層１０３の上に電流ブロック層１０５をｐ型ＩｎＰクラッド層１０６の両側が埋まる位置までＭＯＣＶＤ法によりエピタキシャル成長させる。 Subsequently, as shown in FIG. 7, the insulating film 112 used for forming the ridge portion 103a is used as a mask to fill the n-type InP clad layer 103 with the current block layer 105 on both sides of the p-type InP clad layer 106. Epitaxial growth is performed up to the position by the MOCVD method.
　続いて、図８に示すように、リッジ部１０３ａの加工形成と電流ブロック層１０５の成長にマスクとして使用した絶縁膜１１２を除去する。絶縁膜１１２の除去には、フッ酸等のエッチング液を使用する。 Subsequently, as shown in FIG. 8, the insulating film 112 used as a mask for processing and forming the ridge portion 103a and growing the current blocking layer 105 is removed. To remove the insulating film 112, an etching solution such as hydrofluoric acid is used.
　続いて、図９に示すように、絶縁膜１１２を除去した後、露出するｐ型ＩｎＰクラッド層１０６および電流ブロック層１０５の上に、さらにｐ型ＩｎＰクラッド層１０６をエピタキシャル成長させる。 Subsequently, as shown in FIG. 9, after removing the insulating film 112, the p-type InP clad layer 106 is further epitaxially grown on the exposed p-type InP clad layer 106 and the current blocking layer 105.
　次いで、図１０に示すように、成長させたｐ型ＩｎＰクラッド層１０６上の全面に、絶縁膜を成膜し、活性層１０４と、その両側の電流ブロック層１０５を一部含むような幅でストライプ状にエッチング加工する。 Next, as shown in FIG. 10, an insulating film is formed on the entire surface of the grown p-type InP clad layer 106, and the active layer 104 and the current blocking layers 105 on both sides of the active layer 104 are partially included in the width. Etching is done in stripes.
　続いて、図１１に示すように、形成した絶縁膜１１４をマスクとして、ｎ型ＩｎＰクラッド層１０３のリッジ部１０３ａの根元部分まで達するようｐ型ＩｎＰクラッド層１０６および電流ブロック層１０５をエッチング加工し、メサ溝１１５ｂを設ける。エッチング加工後、フッ酸等で、絶縁膜１１４をエッチング除去する。 Subsequently, as shown in FIG. 11, the p-type InP clad layer 106 and the current block layer 105 are etched by using the formed insulating film 114 as a mask so as to reach the root portion of the ridge portion 103a of the n-type InP clad layer 103. , Mesa groove 115b is provided. After the etching process, the insulating film 114 is removed by etching with hydrofluoric acid or the like.
　次いで、図１２に示すように、メサ溝１１５ｂを設けた表面の全面に絶縁膜１１６を成膜し、メサ溝１１５ｂの底部部分でｎ型ＩｎＰクラッド層１０３を覆う絶縁膜１１６をエッチング加工し、隣のメサ部１１５ａの横でｎ型ＩｎＰクラッド層１０３を覆う絶縁膜１１６の部分にストライプ状の開口部１１６ａを形成する。 Next, as shown in FIG. 12, an insulating film 116 is formed on the entire surface provided with the mesa groove 115b, and the insulating film 116 covering the n-type InP clad layer 103 is etched at the bottom of the mesa groove 115b. A stripe-shaped opening 116a is formed in a portion of the insulating film 116 that covers the n-type InP clad layer 103 next to the adjacent mesa 115a.
　続いて、図１３に示すように、形成した絶縁膜１１６をマスクとして、開口部１１６ａを通して、ｎ型ＩｎＰクラッド層１０３、ｐ型ＡｌＩｎＡｓ層１０２を通り、Ｆｅドープ半絶縁性ＩｎＰ基板１０１の内部に達するまでエッチング加工し、アイソレーション溝１１０を形成する。エッチング加工後、絶縁膜１１６をフッ酸等でエッチング除去する。 Then, as shown in FIG. 13, using the formed insulating film 116 as a mask, through the opening 116 a, through the n-type InP clad layer 103 and the p-type AlInAs layer 102, and inside the Fe-doped semi-insulating InP substrate 101. The isolation groove 110 is formed by performing etching processing until reaching. After the etching process, the insulating film 116 is removed by etching with hydrofluoric acid or the like.
　次いで、図１４に示すように、メサ溝１１５ｂにアイソレーション溝１１０を形成した表面の全面に絶縁膜１０７を成膜する。 Next, as shown in FIG. 14, an insulating film 107 is formed on the entire surface of the mesa groove 115b in which the isolation groove 110 is formed.
　続いて、図１５に示すように、メサ部１１５ａの頂上部分でｐ型ＩｎＰクラッド層１０６の部分を覆う絶縁膜１０７と、メサ溝１１５ｂの底部部分でｎ型ＩｎＰクラッド層１０３の部分を覆う絶縁膜１０７をエッチング加工し、ｐ型ＩｎＰクラッド層１０６およびｎ型ＩｎＰクラッド層１０３を覆う絶縁膜１０７の部分にそれぞれストライプ状の開口部１０７ａ、１０７ｂを形成する。 Subsequently, as shown in FIG. 15, an insulating film 107 covering the p-type InP clad layer 106 at the top of the mesa 115a and an insulating film 107 covering the n-type InP clad layer 103 at the bottom of the mesa groove 115b. The film 107 is etched to form stripe-shaped openings 107a and 107b in the insulating film 107 portion covering the p-type InP clad layer 106 and the n-type InP clad layer 103, respectively.
　最後に、開口部１０７ａにはｐ型ＩｎＰクラッド層１０６に接続するアノード電極１０８を形成し、開口部１０７ｂにはｎ型ＩｎＰクラッド層１０３に接続するカソード電極１０９を形成することで、図２（ａ）に示すような、半導体光集積素子５０３が得られる。 Finally, an anode electrode 108 connected to the p-type InP clad layer 106 is formed in the opening 107a, and a cathode electrode 109 connected to the n-type InP clad layer 103 is formed in the opening 107b. A semiconductor optical integrated device 503 as shown in a) is obtained.
　なお、ここでは埋め込み型の導波路構造を有するレーザについて説明したが、リッジ型の導波路構造を有するレーザであっても構わない。 Although a laser having a buried waveguide structure has been described here, a laser having a ridge waveguide structure may be used.
　半導体光集積素子５０３に対応する従来の半導体光集積素子は、図１６に示すように、ｐ型ＡｌＩｎＡｓ層１０２ではなく、ｐ型ＩｎＰ層１１１が用いられている。 As shown in FIG. 16, the conventional semiconductor optical integrated device corresponding to the semiconductor optical integrated device 503 uses the p-type InP layer 111 instead of the p-type AlInAs layer 102.
　図１７は、実施の形態２における半導体光集積素子５０３の構造でのアイソレーション抵抗をシミュレーションした結果の例を示す図であり、隣接するカソード間電極に電圧を印加し、そのときのカソード間の抵抗値を示す。半導体光集積素子５０３のシミュレーションでは、Ｆｅドープ半絶縁性ＩｎＰ基板１０１はＦｅを５×１０１６ｃｍ－３ドーピングしたものとし、ｐ型ＡｌＩｎＡｓ層１０２は膜厚が１００ｎｍで、キャリア濃度が５×１０１６ｃｍ－３とし、ｎ型ＩｎＰクラッド層１０３はキャリア濃度が１×１０１８ｃｍ－３とした。比較として、従来の半導体光集積素子は、図３（ａ）および図１６の構造でシミュレーションした。従来の半導体光集積素子のシミュレーションでは、ｐ型ＩｎＰ層１１１は膜厚が１００ｎｍで、キャリア濃度が５×１０１６ｃｍ－３とした。従来の半導体光集積素子のＦｅドープ半絶縁性ＩｎＰ基板１０１およびｎ型ＩｎＰクラッド層１０３のキャリア濃度設定は、半導体光集積素子５０３のシミュレーションモデルと同じとした。 FIG. 17 is a diagram showing an example of a result of simulating the isolation resistance in the structure of the semiconductor optical integrated device 503 according to the second embodiment, in which a voltage is applied to the electrodes between adjacent cathodes and the voltage between the cathodes at that time is applied. Indicates the resistance value. In the simulation of the semiconductor optical integrated device 503, it is assumed that the Fe-doped semi-insulating InP substrate 101 is doped with Fe at 5 × 10 16 cm −3 , the p-type AlInAs layer 102 has a film thickness of 100 nm, and the carrier concentration is 5 × 10 5. and 16 cm -3, n-type InP cladding layer 103 has a carrier concentration of 1 × 10 18 cm -3. For comparison, the conventional semiconductor optical integrated device was simulated with the structures shown in FIGS. In the simulation of the conventional semiconductor optical integrated device, the p-type InP layer 111 has a film thickness of 100 nm and a carrier concentration of 5 × 10 16 cm −3 . The carrier concentration settings of the Fe-doped semi-insulating InP substrate 101 and the n-type InP cladding layer 103 of the conventional semiconductor optical integrated device were the same as those of the simulation model of the semiconductor optical integrated device 503.
　図１７に示すように、アイソレーション溝１１０の底部が、ｐ型ＡｌＩｎＡｓ層１０２を貫通し、Ｆｅドープ半絶縁性ＩｎＰ基板１０１の内部まで達する構成とする本願の半導体光集積素子５０３の曲線２０３の方が、従来の半導体光集積素子の図３（ａ）の構造に対応する曲線２０５および図１６の構造に対応する曲線２０７よりも、隣接する素子のカソード間で、ほぼ全域に渡る印加電圧で、より大きい抵抗値を実現することができる。 As shown in FIG. 17, the bottom of the isolation groove 110 penetrates the p-type AlInAs layer 102 and reaches the inside of the Fe-doped semi-insulating InP substrate 101. In comparison with the curve 205 corresponding to the structure of FIG. 3A and the curve 207 corresponding to the structure of FIG. 16 of the conventional semiconductor optical integrated device, the voltage applied across the cathodes of adjacent devices is almost the same. , A larger resistance value can be realized.
　このように、アイソレーション溝１１０をｐ型ＡｌＩｎＡｓ層１０２を貫通するようにエッチングし、除去した構成とすることで、ｎ型ＩｎＰクラッド層１０３とｐ型ＡｌＩｎＡｓ層１０２間に生じるバンド不連続部を介して流れる電流経路を遮断することができるため、さらに、Ｆｅドープ半絶縁性ＩｎＰ基板１０１とｐ型ＡｌＩｎＡｓ層１０２間の境界のバンド不連続部を介して流れる電流も遮断することができるため、より高抵抗化することができる。特に、これらの材料の境界のバンド構造では、電子が補足されやすくなっており、いわゆる二次元電子ガス層Ｓ１を形成する（図２（ｂ）参照）。よってｐ型ＡｌＩｎＡｓ層１０２を含む異なる境界部分は電流が流れやすい。したがって、エッチング深さをｎ型ＩｎＰクラッド層１０３とｐ型ＡｌＩｎＡｓ層１０２の境界を含み、より基板方向にエッチングし、ｐ型ＡｌＩｎＡｓ層１０２を含む材料の境界（二次元電子ガス層Ｓ１）を貫通するように設けることが望ましい。 In this way, the isolation groove 110 is etched so as to penetrate the p-type AlInAs layer 102 and removed, so that the band discontinuity generated between the n-type InP clad layer 103 and the p-type AlInAs layer 102 is formed. Since it is possible to cut off the current path flowing therethrough, it is also possible to cut off the current flowing through the band discontinuity at the boundary between the Fe-doped semi-insulating InP substrate 101 and the p-type AlInAs layer 102. The resistance can be further increased. In particular, in the band structure at the boundary of these materials, electrons are easily trapped, and a so-called two-dimensional electron gas layer S1 is formed (see FIG. 2B). Therefore, a current easily flows through different boundary portions including the p-type AlInAs layer 102. Therefore, the etching depth includes the boundary between the n-type InP clad layer 103 and the p-type AlInAs layer 102, and the etching is performed in the more substrate direction to penetrate the boundary (two-dimensional electron gas layer S1) of the material including the p-type AlInAs layer 102. It is desirable to provide it.
　素子間を電気的にアイソレーションする場合、ｐ型ＡｌＩｎＡｓ層１０２はわずか１００ｎｍの膜厚で、キャリア濃度も５×１０１６ｃｍ－３と、アンドープレベルに近いキャリア濃度でよいことから、本願の構造は製造の観点、およびキャリア吸収による光損失を抑制するという点でも適切である。 In the case of electrically isolating the elements, the p-type AlInAs layer 102 has a film thickness of only 100 nm and the carrier concentration is 5 × 10 16 cm −3, which is close to the undoped level. Is also appropriate from the viewpoint of manufacturing and from the viewpoint of suppressing light loss due to carrier absorption.
　以上のように、本実施の形態１にかかる半導体光集積素子５０３によれば、Ｆｅドープ半絶縁性ＩｎＰ基板１０１の表面に、二次元電子ガス層Ｓ１を介してＦｅドープ半絶縁性ＩｎＰ基板１０１よりもバンドギャップが広い材料をエピタキシャル成長させたｐ型ＡｌＩｎＡｓ層１０２と、ｐ型ＡｌＩｎＡｓ層１０２の表面に、ｐ型ＡｌＩｎＡｓ層１０２と二次元電子ガス層Ｓ１を貫通し、Ｆｅドープ半絶縁性ＩｎＰ基板１０１の内部に達するアイソレーション溝１１０を挟んで列状に配列して構成された複数の半導体レーザ素子１２０とを備えるようにしたので、基板を介した漏れ電流および光の吸収損失を抑制し、アイソレーションを確保するとともに、素子を製造するに適した構造を実現できるだけでなく、さらに高抵抗化することができる。 As described above, according to the semiconductor optical integrated device 503 of the first embodiment, the Fe-doped semi-insulating InP substrate 101 is formed on the surface of the Fe-doped semi-insulating InP substrate 101 via the two-dimensional electron gas layer S1. Fe-doped semi-insulating InP substrate that penetrates the p-type AlInAs layer 102 and the two-dimensional electron gas layer S1 on the surface of the p-type AlInAs layer 102, which is obtained by epitaxially growing a material having a wider band gap than Since a plurality of semiconductor laser elements 120 are arranged in a row with an isolation groove 110 reaching the inside of 101 interposed therebetween, leakage current through the substrate and absorption loss of light are suppressed, Not only can isolation be ensured, a structure suitable for manufacturing devices can be realized, and further higher resistance can be achieved. Kill.
　実施の形態２．
　実施の形態１では、各々の半導体レーザ素子１２０が分離し電気的に絶縁するためにアイソレーション溝１１０を設けたが、実施の形態２では、アイソレーション溝を形成する代わりにイオン注入をする場合について示す。 Embodiment 2.
In the first embodiment, the isolation groove 110 is provided to separate and electrically insulate each semiconductor laser device 120, but in the second embodiment, ion implantation is performed instead of forming the isolation groove. About.
　図１８は、実施の形態３における半導体光集積素子の構成を示す断面図である。図１８に示すように、半導体光集積素子５０４は、実施の形態１においてアイソレーション溝１１０を形成して各々の半導体レーザ素子１２０を分離する代わりに、イオン注入により、半導体レーザ素子１２０間に所定の深さまでイオンを注入し、高抵抗化させたイオン注入部１１７を設けることで各々の半導体レーザ素子１２０を分離する。これにより、実施の形態１の効果を得られるだけでなく、アイソレーション溝１１０を形成する必要が無いため、素子作製時のウエハ表面の凹凸を低減でき、製造の容易さが向上する。実施の形態３による半導体光集積素子５０４のその他の構成については、実施の形態１の半導体光集積素子５０３と同様であり、対応する部分には同符号を付してその説明を省略する。 FIG. 18 is a sectional view showing the structure of the semiconductor optical integrated device according to the third embodiment. As shown in FIG. 18, in the semiconductor optical integrated device 504, instead of forming the isolation groove 110 and separating each semiconductor laser device 120 in the first embodiment, a predetermined space is provided between the semiconductor laser devices 120 by ion implantation. Each semiconductor laser element 120 is separated by implanting ions up to the depth of 1 to provide an ion implantation section 117 having a high resistance. As a result, not only the effect of the first embodiment can be obtained, but also because it is not necessary to form the isolation groove 110, the unevenness of the wafer surface at the time of manufacturing the element can be reduced, and the ease of manufacturing is improved. The other configurations of the semiconductor optical integrated device 504 according to the third embodiment are similar to those of the semiconductor optical integrated device 503 of the first embodiment, and corresponding parts are denoted by the same reference numerals and the description thereof will be omitted.
　次に、実施の形態３における半導体光集積素子５０４の製造方法について、図２４から図２６に基づき説明する。図２４から図２６は、実施の形態３による半導体光集積素子５０４の製造工程を示す断面図である。 Next, a method of manufacturing the semiconductor optical integrated device 504 according to the third embodiment will be described with reference to FIGS. 24 to 26. 24 to 26 are cross-sectional views showing the manufacturing process of the semiconductor optical integrated device 504 according to the third embodiment.
　まず、実施の形態１での図１２までの工程が終了し、ｎ型ＩｎＰクラッド層１０３覆う絶縁膜１１６の部分にストライプ状の開口部１１６ａを形成した後、開口部１１６ａから露出したｎ型ＩｎＰクラッド層１０３にイオンを注入し、図２４に示すように、イオン注入部１１７を形成する。イオン注入部１１７を形成した後、絶縁膜１１６をフッ酸等でエッチング除去する。 First, after the steps up to FIG. 12 in the first embodiment are completed, a striped opening 116a is formed in a portion of the insulating film 116 covering the n-type InP cladding layer 103, and then the n-type InP exposed from the opening 116a is formed. Ions are implanted into the cladding layer 103 to form an ion-implanted portion 117, as shown in FIG. After forming the ion-implanted portion 117, the insulating film 116 is removed by etching with hydrofluoric acid or the like.
　続いて、図２５に示すように、メサ溝１１５ｂにイオン注入部１１７を形成した表面の全面に絶縁膜１０７を成膜する。 Subsequently, as shown in FIG. 25, an insulating film 107 is formed on the entire surface of the mesa groove 115b on which the ion implantation portion 117 is formed.
　次いで、図２６に示すように、メサ部１１５ａの頂上部分でｐ型ＩｎＰクラッド層１０６の部分を覆う絶縁膜１０７と、メサ溝１１５ｂの底部部分でｎ型ＩｎＰクラッド層１０３の部分を覆う絶縁膜１０７をエッチング加工し、ｐ型ＩｎＰクラッド層１０６およびｎ型ＩｎＰクラッド層１０３を覆う絶縁膜１０７の部分にそれぞれストライプ状の開口部１０７ａ、１０７ｂを形成する。 Then, as shown in FIG. 26, an insulating film 107 covering the p-type InP clad layer 106 at the top of the mesa 115a and an insulating film 107 covering the n-type InP clad layer 103 at the bottom of the mesa groove 115b. 107 is etched to form stripe-shaped openings 107a and 107b in portions of the insulating film 107 that cover the p-type InP clad layer 106 and the n-type InP clad layer 103, respectively.
　最後に、開口部１０７ａにはｐ型ＩｎＰクラッド層１０６に接続するアノード電極１０８を形成し、開口部１０７ｂにはｎ型ＩｎＰクラッド層１０３に接続するカソード電極１０９を形成することで、図２３に示すような、半導体光集積素子５０４が得られる。 Finally, an anode electrode 108 connected to the p-type InP clad layer 106 is formed in the opening 107a, and a cathode electrode 109 connected to the n-type InP clad layer 103 is formed in the opening 107b. A semiconductor optical integrated device 504 as shown is obtained.
　以上のように、本実施の形態２にかかる半導体光集積素子５０４によれば、アイソレーション溝１１０の代わりに、イオン注入部１１７を設けたので、実施の形態１および実施の形態２の効果を得られるだけでなく、アイソレーション溝１１０を形成する必要が無いため、素子作製時のウエハ表面の凹凸を低減でき、製造の容易さが向上する。 As described above, according to the semiconductor optical integrated device 504 according to the second embodiment, the ion implantation part 117 is provided instead of the isolation groove 110, so that the effects of the first and second embodiments can be obtained. Not only is it obtained, but since it is not necessary to form the isolation groove 110, the unevenness of the wafer surface at the time of device fabrication can be reduced, and the ease of manufacturing is improved.
　なお、実施の形態１および実施の形態２では、Ｆｅドープ半絶縁性ＩｎＰ基板１０１の表面にｐ型ＡｌＩｎＡｓ層１０２を形成したが、これに限るものではない。ｎ型またはアンドープのＡｌＩｎＡｓ層を形成してもよい。また、ｐ型ＡｌＩｎＡｓ層１０２をＩｎＰよりもバンドギャップの大きい他の材料で置き換えたものを形成してもよい。例えば、ｐ型ＡｌｙＧａｘＩｎ（１－ｘ－ｙ）Ａｓで、０＜ｘ≦０．０７１、０．４０３≦ｙ＜０．４７６の範囲であれば、ＩｎＰのバンドギャップ１．３４４ｅＶより大きくなる。この場合も、ｐ型ＡｌｙＧａｘＩｎ（１－ｘ－ｙ）Ａｓ層に限るわけではなく、ｎ型またはアンドープのＡｌｙＧａｘＩｎ（１－ｘ－ｙ）Ａｓ層を形成してもよい。ｎ型ＡｌＩｎＡｓ層またはｎ型ＡｌｙＧａｘＩｎ（１－ｘ－ｙ）Ａｓを形成する場合は、ｎ型ＩｎＰクラッド層１０３にはｐ型ＩｎＰクラッド層、ｐ型ＩｎＰクラッド層１０６にはｎ型ＩｎＰクラッド層、アノード電極１０８にはカソード電極、カソード電極１０９にはアノード電極とする。ｐ型ＡｌｙＧａｘＩｎ（１－ｘ－ｙ）Ａｓを形成する場合は、実施の形態１と同様の構成とする。アンドープのＡｌｙＧａｘＩｎ（１－ｘ－ｙ）Ａｓ層を形成する場合は、どちらの構成としてもよい。いずれの場合も、上記実施の形態と同様の効果を得ることができる。 Although the p-type AlInAs layer 102 is formed on the surface of the Fe-doped semi-insulating InP substrate 101 in the first and second embodiments, the present invention is not limited to this. An n-type or undoped AlInAs layer may be formed. Alternatively, the p-type AlInAs layer 102 may be replaced with another material having a bandgap larger than that of InP. For example, in the case of p-type Al y Ga x In (1-xy) As and 0 <x ≦ 0.071 and 0.403 ≦ y <0.476, the band gap of InP is 1.344 eV. growing. Also in this case, the layer is not limited to the p-type Al y Ga x In (1-xy) As layer, and an n-type or undoped Al y Ga x In (1-xy) As layer may be formed. Good. When the n-type AlInAs layer or the n-type Al y Ga x In (1-xy) As is formed, the n-type InP clad layer 103 is a p-type InP clad layer, and the p-type InP clad layer 106 is an n-type. The InP clad layer, the anode electrode 108 is a cathode electrode, and the cathode electrode 109 is an anode electrode. When the p-type Al y Ga x In (1-xy) As is formed, it has the same configuration as that of the first embodiment. When an undoped Al y Ga x In (1-xy) As layer is formed, either structure may be used. In any case, it is possible to obtain the same effect as that of the above embodiment.
　また、ＩｎＰ基板としてＦｅドープ半絶縁性ＩｎＰ基板１０１を用いたが、これに限るものではない。ｎ型ＩｎＰ基板またはｐ型ＩｎＰ基板を用いてもよい。例えば、ｎ型ＩｎＰ基板ではＳまたはＳｉ等をドーピングしたもの、ｐ型ＩｎＰ基板ではＺｎまたはＭｇ等をドーピングしたものが挙げられる。この場合も、上記実施の形態と同様の効果を得ることができる。基板方向の漏れ電流抑制は、基板上に形成された基板材料よりバンドギャップが広い材料によりなされるため、基板極性は問わない。ただし、ｐ型半導体基板を使用することもできるが、光吸収によるレーザ特性の観点からｎ型半導体基板のほうが好適である。ｎ型の導電性を担う電子による吸収は、ｐ型の導電性を担うホールよりも光吸収係数が小さいことが一般に知られている。 Moreover, although the Fe-doped semi-insulating InP substrate 101 is used as the InP substrate, the present invention is not limited to this. An n-type InP substrate or a p-type InP substrate may be used. For example, an n-type InP substrate may be doped with S or Si, and a p-type InP substrate may be doped with Zn, Mg or the like. Also in this case, the same effect as that of the above embodiment can be obtained. Since the leakage current in the substrate direction is suppressed by a material having a wider bandgap than the substrate material formed on the substrate, the substrate polarity does not matter. However, although a p-type semiconductor substrate can be used, an n-type semiconductor substrate is preferable from the viewpoint of laser characteristics due to light absorption. It is generally known that absorption by electrons having n-type conductivity has a smaller light absorption coefficient than holes having p-type conductivity.
　また、半導体光集積素子５０３、５０４は、光半導体素子のみを列状に配列したが、これに限るものではない。光半導体素子と光半導体素子以外の電子デバイスを配列し、光半導体素子と光半導体素子以外の電子デバイスのカソード間またはアノード間を電気的に分離する構成としてもよい。この場合も、上記実施の形態と同様の効果を得ることができる。 Moreover, in the semiconductor optical integrated devices 503 and 504, only the optical semiconductor devices are arranged in a row, but the invention is not limited to this. The optical semiconductor element and the electronic device other than the optical semiconductor element may be arranged, and the cathode or the anode of the optical semiconductor element and the electronic device other than the optical semiconductor element may be electrically separated. Also in this case, the same effect as that of the above embodiment can be obtained.
　本願は、様々な例示的な実施の形態及び実施例が記載されているが、１つ、または複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるのではなく、単独で、または様々な組み合わせで実施の形態に適用可能である。従って、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。例えば、少なくとも１つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも１つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。 Although the present application describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more of the embodiments are applicable to particular embodiments. However, the present invention is not limited to this, and can be applied to the embodiments alone or in various combinations. Therefore, innumerable variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, it is assumed that at least one component is modified, added, or omitted, and further, at least one component is extracted and combined with the components of other embodiments.
　１０１　Ｆｅドープ半絶縁性ＩｎＰ基板、１０２　ｐ型ＡｌＩｎＡｓ層、１０３　ｎ型ＩｎＰクラッド層、１０３ａ　リッジ部、１０４　活性層、１０５　電流ブロック層、１０６　ｐ型ＩｎＰクラッド層、１１０　アイソレーション溝、１１７　イオン注入部、１２０　半導体レーザ素子、５０３、５０４　半導体光集積素子。 101 Fe-doped semi-insulating InP substrate, 102 p-type AlInAs layer, 103 n-type InP clad layer, 103a ridge portion, 104 active layer, 105 current blocking layer, 106 p-type InP clad layer, 110 isolation groove, 117 ion implantation Part, 120 semiconductor laser device, 503, 504 semiconductor optical integrated device.

Claims (9)

  1. 　ＩｎＰ基板の表面に、二次元電子ガス層を介して前記ＩｎＰ基板よりもバンドギャップが広い材料をエピタキシャル成長させたエピタキシャル層と、
    　前記エピタキシャル層の表面に、前記エピタキシャル層と前記二次元電子ガス層を貫通し、前記ＩｎＰ基板の内部に達するアイソレーション溝を挟んで列状に形成された複数の光半導体素子と
    　を備えたことを特徴とする半導体光集積素子。     An epitaxial layer in which a material having a wider bandgap than that of the InP substrate is epitaxially grown on the surface of the InP substrate via a two-dimensional electron gas layer;
    A plurality of optical semiconductor elements formed in rows on the surface of the epitaxial layer, with the isolation groove penetrating the epitaxial layer and the two-dimensional electron gas layer and reaching the inside of the InP substrate. A semiconductor optical integrated device characterized by:
  2. 　前記エピタキシャル層は、ｐ型、ｎ型またはアンドープのＡｌＩｎＡｓ層であることを特徴とする請求項１に記載の半導体光集積素子。 The semiconductor optical integrated device according to claim 1, wherein the epitaxial layer is a p-type, n-type, or undoped AlInAs layer.
  3. 　前記エピタキシャル層は、ｐ型、ｎ型またはアンドープのＡｌｙＧａｘＩｎ（１－ｘ－ｙ）Ａｓ層（０＜ｘ≦０．０７１、０．４０３≦ｙ＜０．４７６）であることを特徴とする請求項１に記載の半導体光集積素子。 The epitaxial layer is a p-type, n-type, or undoped Al y Ga x In (1-xy) As layer (0 <x ≦ 0.071, 0.403 ≦ y <0.476). The semiconductor optical integrated device according to claim 1, which is characterized in that.
  4. 　前記光半導体素子は、前記エピタキシャル層がｐ型またはアンドープの場合は、前記エピタキシャル層の表面に形成され、リッジ部が設けられたｎ型ＩｎＰクラッド層と、前記リッジ部の頂上部に形成された活性層と、前記リッジ部の両側部に設けられた電流ブロック層と、前記電流ブロック層で挟まれた前記活性層の表面に形成されたｐ型ＩｎＰクラッド層とから構成されたことを特徴とする請求項２または請求項３に記載の半導体光集積素子。 When the epitaxial layer is p-type or undoped, the optical semiconductor element is formed on the surface of the epitaxial layer, and is formed on the n-type InP clad layer provided with a ridge portion and on the top of the ridge portion. An active layer, a current blocking layer provided on both sides of the ridge portion, and a p-type InP clad layer formed on the surface of the active layer sandwiched by the current blocking layers. The semiconductor optical integrated device according to claim 2 or 3.
  5. 　前記光半導体素子は、前記エピタキシャル層がｎ型またはアンドープの場合は、前記エピタキシャル層の表面に形成され、リッジ部が設けられたｐ型ＩｎＰクラッド層と、前記リッジ部の頂上部に形成された活性層と、前記リッジ部の両側部に設けられた電流ブロック層と、前記電流ブロック層で挟まれた前記活性層の表面に形成されたｎ型ＩｎＰクラッド層とから構成されたことを特徴とする請求項２または請求項３に記載の半導体光集積素子。 When the epitaxial layer is n-type or undoped, the optical semiconductor element is formed on the surface of the epitaxial layer, and is formed on the p-type InP clad layer provided with a ridge portion and on the top of the ridge portion. An active layer, a current blocking layer provided on both sides of the ridge portion, and an n-type InP clad layer formed on the surface of the active layer sandwiched by the current blocking layers. The semiconductor optical integrated device according to claim 2 or 3.
  6. 　前記アイソレーション溝の代わりに、イオン注入部を設けたことを特徴とする請求項１から請求項５のいずれか１項に記載の半導体光集積素子。 (6) The semiconductor optical integrated device according to any one of (1) to (5), wherein an ion implantation part is provided instead of the isolation groove.
  7. 　前記ＩｎＰ基板は、Ｆｅがドーピングされた半絶縁性半導体基板であることを特徴とする請求項１から請求項６のいずれか１項に記載の半導体光集積素子。 7. The semiconductor optical integrated device according to any one of claims 1 to 6, wherein the InP substrate is a semi-insulating semiconductor substrate doped with Fe.
  8. 　前記ＩｎＰ基板は、ｎ型またはｐ型の半導体基板であることを特徴とする請求項１から請求項７のいずれか１項に記載の半導体光集積素子。 The semiconductor optical integrated device according to any one of claims 1 to 7, wherein the InP substrate is an n-type or p-type semiconductor substrate.
  9. 　前記光半導体素子だけでなく、前記光半導体素子と前記光半導体素子以外の電子デバイスを配列して構成されていることを特徴とする請求項１から請求項８のいずれか１項に記載の半導体光集積素子。 9. The semiconductor according to claim 1, wherein not only the optical semiconductor element but also the optical semiconductor element and an electronic device other than the optical semiconductor element are arranged. Optical integrated device.
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