JPH07235731A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To selectively form a high-resistance areas on the surface of II-VI or III-V compound semiconductor by a simple process. CONSTITUTION:The manufacture of a compound semiconductor device has a process of demarcating a high-resistance area 3 and providing a mask 2 which absorbs group II or III elements, which form the compound semiconductor, at the time of heat treatment on the surface of semiconductor 4, and a process of heattreating the semiconductor 4 in the atmosphere that contains group If or III elements and selectively forming the high-resistance area 3 directly under the mask 2 of the semiconductor 4 by the external diffusion of such elements in the semiconductor 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a II-VI group or III-V group compound semiconductor device, and more particularly to a method for selectively forming a high resistance region on a compound semiconductor surface.

II-VI group compound semiconductors containing Zn are often used for light-emitting devices such as blue-emitting semiconductor lasers, and III-V group compound semiconductors are often used for light-emitting devices such as semiconductor lasers from visible light to infrared light. ing.

In the manufacture of these elements, in order to produce a current constriction portion that limits an element isolation region or a current path,
It is often necessary to form a high resistance region on the surface of a compound semiconductor.

Therefore, there is a demand for a method of easily forming a high resistance region on the surface of a II-VI group or III-V group compound semiconductor.

[0005]

2. Description of the Related Art Conventionally, as a method of forming a high resistance region on the surface of a compound semiconductor, a method of forming a mesa on the semiconductor surface and embedding the mesa with a high resistance layer, a groove is formed on the semiconductor surface There is known a method of burying with, and a method of implanting oxygen ions from the semiconductor surface to form a high resistance layer.

However, these methods have the problems that the process is complicated and the expensive device is required because the process and the embedding process of the semiconductor surface are required. For this reason, a method of providing an insulating layer pattern on the surface and using this as a high resistance region is often used. Hereinafter, manufacturing of a semiconductor device using the insulating layer as a current confinement layer will be described with reference to manufacturing of a stripe type II-V group DH (double hetero structure) semiconductor laser.

FIG. 3 is a cross-sectional process diagram of a conventional example, showing a manufacturing process of a stripe type DH semiconductor laser. First,
Referring to FIG. 3A, on the p-type GaAs substrate 1, a clad layer made of p-type ZnSSe 5, an active layer made of CdZnSe, and an n-type ZnSSe as an upper clad layer.
The conductive semiconductor layer 7 made of is sequentially deposited by the molecular beam epitaxial method.

Next, referring to FIG. 3B, an insulating layer 31 made of a silicon nitride film is deposited on the conductive semiconductor layer 7 by the CVD method, and subsequently, the light emitting region 6a is defined in the insulating layer 31. A striped opening 31a is opened.

Then, a conductive film is deposited on the upper surface of the substrate 1 and the lower surface of the substrate 1 to form the electrodes 8 and 9, whereby a semiconductor laser is manufactured. The current flowing from the upper electrode 8 to the lower electrode 9 of this semiconductor laser is blocked by the insulating layer 31 and flows only through the opening 31a. Therefore, the insulating layer 31 acts as the current confinement portion 10 that concentrates the current in the light emitting region 6a immediately below the opening 31.

However, in the semiconductor laser manufactured by such a method, the opening 31a of the insulating layer 31 is provided on the surface of the conductive semiconductor layer 7 deposited on the active layer 6, so that the opening 31a and the active layer 6 are separated from each other. The distance is large. Therefore, opening 3
The current confined by 1 cannot be effectively concentrated in the light emitting region 6a.

Further, it is difficult to sufficiently separate the element forming region with the insulating layer formed on the surface of the semiconductor.

[0012]

As described above, the conventional method of embedding a mesa or oxygen ion implantation for forming a high resistance region on the surface of a compound semiconductor requires complicated steps or It has the disadvantage of requiring expensive equipment.

On the other hand, the method of forming the current constriction portion on the surface of the compound semiconductor has a problem that the confined current cannot be effectively concentrated in the light emitting region. In addition, it is difficult to achieve sufficient element isolation with the surface insulating layer.

According to the present invention, a high resistance region is selectively formed in a predetermined region of a compound semiconductor by forming a mask on the surface of the compound semiconductor and performing heat treatment. An object is to provide a method for manufacturing a compound semiconductor device in which a resistance region is formed.

[0015]

FIG. 1 is a sectional process drawing of a first embodiment of the present invention, showing a forming process of a high resistance region for element isolation. FIG. 2 is a sectional process drawing of the second embodiment of the present invention, which shows a manufacturing process of a stripe type DH semiconductor laser.

The first constitution of the present invention for solving the above-mentioned problems is to refer to FIGS. 1 and 2 to the II-VI group compound diffused on the surface of the n-type II-VI group compound semiconductor 4 during the heat treatment. A step of providing a mask 2 that absorbs at least one of the group II elements in the compound semiconductor 4, and then performing a heat treatment in an atmosphere containing at least one of the group II elements, And a step of selectively forming the high resistance region 3 in the II-VI group compound semiconductor 4, and the second structure is the n-type II-VI group compound semiconductor 4
The II-VI group compound semiconductor 4 that diffuses on the surface during heat treatment
Mask 2 that absorbs at least one of the Group II elements
And then arranging the source substrate 21 containing at least one of the group II elements on the mask 2, and then performing heat treatment to form the II-V in a region under the mask 2.
And a step of selectively forming the high resistance region 3 in the group I compound semiconductor 4, and the third structure is that the n-type II-VI group compound semiconductor 4 is Zn,
A method for producing a compound semiconductor device having a first or second structure characterized by containing one or more kinds of Group II elements selected from Mg and Mn, and a fourth structure, a step of providing a mask 2 on the surface of the p-type III-V compound semiconductor 4 for absorbing at least one of the group V elements in the III-V compound semiconductor 4 that diffuses during heat treatment, and then, the group V element Heat treatment in an atmosphere containing at least one of the above, and selectively forming the high resistance region 3 in the III-V group compound semiconductor 4 in the region under the mask 2. , And the fifth configuration is p-type II
The II that diffuses on the surface of the Group IV compound semiconductor 4 during heat treatment
At least one of the group V elements in the group IV compound semiconductor 4
A step of providing a mask 2 for absorbing the seed, a step of disposing a source substrate 21 containing at least one kind of the group V element on the mask 2, and a heat treatment to form a region under the mask 2 And the step of selectively forming the high resistance region 3 in the III-V group compound semiconductor 4.

[0017]

In the first structure of the present invention, referring to FIG.
Type II-VI group compound semiconductor 4, eg Zn, Mg or Mn
The surface of the II-VI group compound semiconductor having the constituent elements is partially covered with the mask 2, and heat treatment is performed in an atmosphere containing the constituent elements of the II-VI group compound semiconductor 4, such as Zn, Mg or Mn. The mask can be directly formed on the semiconductor surface, or a separately manufactured mask can be placed on the semiconductor surface.

The mask 2 is made of a substance which diffuses and forms a solid solution with at least one group II element constituting the group II-VI compound semiconductor 4. Therefore, the heat treatment causes the group II element contained in the region directly below the mask 2 of the semiconductor 4 to diffuse outwardly to the surface of the semiconductor 4 and be absorbed in the mask 2. as a result,
Immediately below the mask 2, a semiconductor 4 region having a low concentration of a group II element such as Zn, Mg or Mn is formed.

This heat treatment is performed at a temperature at which the diffusion of the group VI element is slow and the diffusion of the group II element is sufficiently fast. This temperature can be set to 300 to 500 ° C. for Zn, for example. Further, Mg and Mn are also made in the same temperature range.

The semiconductor 4 region having a low group II element concentration is
Compensation defects are generated due to the vacancies of these group II elements, so that the n-type semiconductor 4 is compensated and converted into the high resistance region 3.

On the other hand, since the surface of the semiconductor 4 region exposed in the opening 2a of the mask 2 is exposed to the atmosphere containing the group II element, the outward diffusion to the surface is suppressed and the concentration of the group II element decreases. Does not cause For this reason, compensation defects do not occur,
It does not increase the resistance.

The above-mentioned high resistance region 3 is formed from the surface of the semiconductor 4 to a depth corresponding to the heat treatment, that is, inside the semiconductor. On the other hand, the semiconductor 4 below the opening 2a of the mask 2 does not cause any defect and its electrical characteristics are unchanged. Therefore, this high resistance region 3 can be used as an element isolation region or a mesa burying region.

Therefore, according to this structure, a high resistance region, which is formed in the semiconductor and can be used for element isolation, embedding of mesas, etc., can be easily formed. The fourth structure of the present invention is applied to a p-type III-V group compound semiconductor in place of the n-type II-VI group compound semiconductor of the first structure.
In this configuration, referring to FIG.
A substance that diffuses a solid solution of a group element, for example, SiO ₂ is used. In addition, heat treatment is performed in an atmosphere containing the Group V element.

Generally, in a III-V group compound semiconductor, a V group element diffuses at a lower temperature than a III group element. Therefore, mask 2
In the semiconductor 4 region covered with
Compensation defects are generated due to the vacancy of the group V element, and the p-type semiconductor 4 is converted into the compensated high resistance region 3.

On the other hand, in the semiconductor 4 region under the mask 2 opening 2a, outward diffusion is suppressed as in the first structure, and the original characteristics are maintained without increasing the resistance. Therefore, the same effect as the first configuration is obtained.

In the second or fifth configuration, the opening of the mask is covered with the source semiconductor and heat treatment is performed. This source semiconductor is an element that diffuses outward in the compound semiconductor during heat treatment, that is, in the case of II-VI group compound semiconductors, Zn, Mg, Mn, etc.
Group II elements are used as constituent elements in Group III-V compound semiconductors. Therefore, the mask opening covered with the source semiconductor becomes an atmosphere in which the vapor pressure of these elements diffusing outward is high. Therefore, it is not necessary to include these elements in the heat treatment atmosphere, and the heat treatment apparatus is simplified.

In the third structure of the present invention, the II-VI group compound semiconductor is a II-VI group compound semiconductor containing at least one of Zn, Mg or Mn as a constituent element. Such a semiconductor is particularly suitable for application to the active region of a blue light to ultraviolet light emitting device. Therefore, this structure is suitable for manufacturing a light emitting element for visible light of a short wavelength.

[0028]

EXAMPLES The present invention will be described with reference to examples. The first embodiment of the present invention is an application example to the step of separating the epitaxial semiconductor 4 layers into elements to form the element forming region 4a with reference to FIG.

First, a Cl-doped ZnSSe layer is deposited as the n-type II-VI group compound semiconductor 4 on the insulating or p-type GaAs substrate 1 by, for example, the molecular beam epitaxial method. Then, using the CVD method (chemical vapor deposition method),
A SiO ₂ film is deposited on the semiconductor 4, patterned,
A mask 2 having an opening 2a that defines an element formation region is formed. The mask 2 may be a silicon nitride film or an alumina film instead of SiO ₂ .

Next, heat treatment is performed at 350 ° C. in a nitrogen atmosphere containing dimethyl Zn. As a result, referring to FIG. 1B, the semiconductor 4 under the region covered with the mask 2 has a high resistance and a high resistance region 3 is formed, and the semiconductor 4 is insulated and separated. The atmosphere may be one in which a Zn vapor pressure is generated by heating a source source or solid Zn.

At this time, an outer diffusion region 11 in which Zn diffuses outward is formed in the vicinity of the interface of the substrate 1 in contact with the high resistance region 3. However, when the substrate 1 is p-type, even if Zn vacancy is generated, it is not compensated and remains p-type. When the substrate 1 is an insulating substrate which is compensated by deep level impurities, the outer diffusion region 11 is compensated by the deep level and is not inverted and remains insulative. GaA
The diffusion of As in s hardly occurs at 350 ° C,
The change in III-V compound semiconductors is not a problem.

The region under the opening 2a of the mask does not change even by the heat treatment, and the original semiconductor 4 remains the element forming region 4a. The element formation region formed by such a method is
It can be used as a formation region of a transistor, a light receiving element or a light emitting element.

The second embodiment of the present invention is applied to the formation of a current constriction portion of a stripe type DH semiconductor laser emitting blue light. First, referring to FIG. 2A, a deposition temperature of 250 is formed on a Zn-doped p ⁺ type GaAs substrate 1.
By the molecular beam epitaxial method at ℃,
Clad layer 5 composed of a p-type ZnS _0.06 Se _0.94 layer doped with Cu, and non-doped Cd _0.2 Zn _0.8 Se having a thickness of 10 nm
An active layer 6 consisting of layers and a conductive semiconductor layer 7 consisting of an n-type ZnS _0.06 Se _0.94 layer doped with Cl and having a thickness of 2 μm are sequentially deposited as an upper clad layer. In the present embodiment, this conductive semiconductor layer 7 acts as the semiconductor 4 described above. Furthermore, the conductive semiconductor layer 7 does not need to be entirely conductive, and some layers may be conductive.
For example, the surface layer can be made of a true semiconductor or a p-type semiconductor.

Hereinafter, in this embodiment, the conductive semiconductor layer 7 is Z
The case of nSSe will be described, but the conductive semiconductor layer 7
Is the same when ZnMgSSe or ZnMnSSe is.

The source substrate is manufactured in a step different from the step of depositing the semiconductor lamination shown in FIG. Figure 1
Referring to (b), the source substrate 21 is a Zn-doped p ⁺ -type GaAs substrate 1a, and the source layer 7a is a Cl-doped n-type ZnS _0.06 Se _0.94 layer having a thickness of 5 μm by the molecular beam epitaxial method. Deposit. Further, a silicon nitride film having a thickness of 50 nm, for example, is deposited on the source layer 7a by the plasma CVD method, and this silicon nitride film is patterned using, for example, a BHF-based etchant to form the mask 2. The pattern of the mask 2 has a stripe-shaped opening 2a having a width of 10 μm, for example, depending on the structure of the stripe laser.

Next, with reference to FIG. 2C, the source substrate 21 is provided with the surface of the mask 2 and the surface of the semiconductor laminate shown in FIG. Contact and place on the conductive semiconductor layer 7.

Next, heat treatment is performed at 300 ° C. for 60 minutes in a nitrogen atmosphere. At this time, the source layer 7a serves as a Zn vapor pressure generation source to increase the Zn vapor pressure in the atmosphere of the opening 2a of the mask 2 and at the same time serves as a Cl generation source to increase the Cl concentration in the atmosphere of the opening 2a. .

As a result of this heat treatment, referring to FIG. 2D, the mask 2 adjacent to both sides of the stripe-shaped opening 2a is formed.
A high resistance region 3 in which the conductive semiconductor layer 7 has a high resistance is formed below the region covered with (4) by outward diffusion of Zn. Furthermore, the active layer 6 and the cladding layer 5 immediately below the high resistance region 3
The outer diffusion regions 6b and 7b having a low Zn concentration are formed in the upper layer. The non-doped active layer 6 is usually of the n ⁻ type, and the outer diffusion region 6b has a high resistance. Further, since the cladding layer 5 is p-type, it is not compensated and the conductivity type of the outer diffusion region 7b does not change.

The high resistance region 3 can be limited to the inside of the conductive semiconductor layer 7. In such a case, there is an advantage that there is little risk of deterioration of the active layer 6. Further, the regions of the conductive semiconductor layer 7, the active layer 6 and the cladding layer 5 immediately below the opening 2a remain in a mesa shape in contact with the high resistance region 3 without the outward diffusion of Zn and without being altered. Therefore, the conductive semiconductor layer 7 in this region serves as a current path of a mesa-embedded device having the high resistance region 3 as the current constriction portion 10, and the active layer 6 in this mesa serves as the light emitting region 6a. In this structure, the active layer 6 on the side surface of the light emitting region is the highly diffused outer diffusion region 6b, so that the leak current around the light emitting region 6a is suppressed.

If necessary, the current constriction portion 10 can be limited to only a shallow region on the surface of the conductive semiconductor layer 7. By this heat treatment, the outer diffusion region 1b is also formed in the source substrate, and the diffused Zn increases the Zn concentration in the mask 2. Generally, this increase in concentration is not so large as to hinder the diffusion in the conductive semiconductor layer 7. However, in order to avoid this effect, GaA with a low Zn concentration is used as the substrate 1a.
It is also possible to use s.

Then, the source substrate 21 is removed, and FIG.
Referring to (e), after the front surface of the conductive semiconductor layer 7 and the back surface of the substrate 1 are shallowly etched, I is formed on the front surface of the conductive semiconductor layer 7.
AuZn, for example, is vacuum-deposited on the rear surface of the substrate 1 to form ohmic electrodes 8 and 9, and a semiconductor laser is manufactured.

The third embodiment of the present invention relates to the manufacture of III-V semiconductor lasers. The structure and process of the semiconductor laser according to this example are similar to those of the second example shown in FIG.

First, referring to FIG. 2A, n ⁺ type In
On the P substrate 1, for example, metal organic chemical vapor deposition (MOVPE)
Method), an n-type InP clad layer, an InGaAsP active layer, and a conductive semiconductor layer 7 made of p-type InP are sequentially deposited. The conductive semiconductor layer 7 acts as the semiconductor 4 described above, as in the second embodiment.

Further, in a separate step, the source substrate 21 is formed similarly to the embodiment. However, the substrate 1a is n ⁺ type InP, and the source layer 7 is p type InP. Also, mask 2
For example, a silicon oxide or silicon nitride film can be used.

Next, referring to FIG. 2C, the same heat treatment as in the second embodiment is performed. However, the heat treatment temperature is InP
The temperature at which P therein diffuses is set to, for example, 500 ° C. As a result, referring to FIG. 2D, a structure in which the mesa is buried in the high resistance region 3 is formed as in the second embodiment. The high resistance region is generated by the outward diffusion of P.

Further, referring to FIG. 2 (e), the electrodes 8,
9 is formed, and a stripe type DH semiconductor laser is manufactured.

[0047]

As described above, according to the present invention, a high resistance region can be formed in a semiconductor by providing a mask on the semiconductor surface and performing heat treatment. Since a compound semiconductor device manufacturing method capable of easily forming a compound semiconductor device having an isolation region or a buried structure with a simple device can be provided, it greatly contributes to the improvement of the semiconductor device manufacturing technology.

[Brief description of drawings]

FIG. 1 is a sectional process drawing of a first embodiment of the present invention.

FIG. 2 is a sectional process drawing of a second embodiment of the present invention.

FIG. 3 is a cross-sectional process diagram of a conventional example

[Explanation of symbols]

 1, 1a Substrate 1b, 6b, 7b, 11 Outer diffusion region 2 Mask 2a, 31a Opening 3 High resistance region 4 Semiconductor 4a Element forming region 5 Cladding layer 6 Active layer 6a Light emitting region 7 Conductive semiconductor layer 7a Source layer 8, 9 Electrode 10 Current constriction part 21 Source substrate 31 Insulating layer

Claims (5)

[Claims] 1. A II-VI group compound semiconductor (4) diffusing on the surface of an n-type II-VI group compound semiconductor (4) during heat treatment.
The step of providing a mask (2) that absorbs at least one of the group II elements in the inside, and then performing a heat treatment in an atmosphere containing at least one of the group II elements so that the region under the mask (2) is exposed. And a step of selectively forming a high resistance region (3) in the II-VI group compound semiconductor (4). 2. The II-VI group compound semiconductor (4) diffusing on the surface of an n-type II-VI group compound semiconductor (4) during heat treatment.
A step of providing a mask (2) for absorbing at least one of the group II elements therein, and then disposing a source substrate (21) containing at least one of the group II elements on the mask (2) And a heat treatment to selectively form a high resistance region (3) in the II-VI group compound semiconductor (4) under the mask (2). Method of manufacturing compound semiconductor device. 3. The n-type II-VI group compound semiconductor (4)
3. The method for manufacturing a compound semiconductor device according to claim 1, wherein the compound semiconductor contains one or more group II elements selected from Zn, Mg and Mn. 4. A III-V compound semiconductor (4) which diffuses on the surface of a p-type III-V compound semiconductor (4) during heat treatment.
The step of providing a mask (2) that absorbs at least one of the group V elements therein, and then performing a heat treatment in an atmosphere containing at least one of the group V elements so that the region under the mask (2) is And a step of selectively forming a high resistance region (3) in the III-V group compound semiconductor (4). 5. A III-V compound semiconductor (4) which diffuses on the surface of a p-type III-V compound semiconductor (4) during heat treatment.
A step of providing a mask (2) that absorbs at least one of the group V elements therein, and then disposing a source substrate (21) containing at least one of the group V elements on the mask (2) And a heat treatment to selectively form a high resistance region (3) in the III-V group compound semiconductor (4) under the mask (2). Method of manufacturing compound semiconductor device.