WO2020083360A1 - 栅线断路及栅线与数据线短路的修复方法、修复结构 - Google Patents

栅线断路及栅线与数据线短路的修复方法、修复结构 Download PDF

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Publication number
WO2020083360A1
WO2020083360A1 PCT/CN2019/113218 CN2019113218W WO2020083360A1 WO 2020083360 A1 WO2020083360 A1 WO 2020083360A1 CN 2019113218 W CN2019113218 W CN 2019113218W WO 2020083360 A1 WO2020083360 A1 WO 2020083360A1
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Prior art keywords
pixel
sub
common electrode
repair
coupled
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PCT/CN2019/113218
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English (en)
French (fr)
Inventor
李立雄
陈平
王贺卫
吴松
于建威
胡海涛
吴国东
季帅
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Priority to US16/768,593 priority Critical patent/US11226525B2/en
Publication of WO2020083360A1 publication Critical patent/WO2020083360A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a repair method and repair structure for a broken gate line and a short circuit between a gate line and a data line.
  • the array substrate is one of the core components in the display panel.
  • the array substrate includes multiple signal lines at different layers.
  • the signal line formed is limited by the influence of factors such as the uniformity of the deposition of the metal material, the cleanliness of the substrate, and the accuracy of the etching process. Various defects may occur.
  • the defective signal lines in the array substrate need to be repaired so that the display panel can display normally.
  • a method for repairing a broken gate line in an array substrate includes: multiple sub-pixels, multiple gate lines, multiple data lines, multiple common electrode lines, and multiple compensation structures.
  • Each sub-pixel includes: a transistor, a pixel electrode, and a common electrode; each transistor of a row of sub-pixels is coupled to the same gate line, and each transistor of a column of sub-pixels is coupled to the same data line; each common electrode of a row of sub-pixels It is coupled to the same common electrode line; each common electrode of the plurality of sub-pixels is electrically connected to the plurality of compensation structures through the plurality of common electrode lines.
  • the method for repairing the broken circuit of the grid line includes: determining the broken position of the grid line; along the extending direction of the grid line where the broken line position is located, determining the two closest to the broken line position and on both sides of the broken line position A connection element, wherein the two connection elements are each transistor coupled to the gate line where the disconnection position is located, and the common electrode of the sub-pixel coupled to the gate line through the gate line Two elements in each compensation structure of the; from each sub-pixel coupled to the gate line where the disconnection position is located, select one or two sub-pixels electrically connected to the determined two connecting elements as repair sub-pixels, It is determined that the common electrode line coupled to the common electrode of each of the repair sub-pixels is the selected common electrode line; a communication path is formed between the front and the rear at the disconnected position to use the communication path bypass In the disconnected position, the communication path includes at least a common electrode of each repair sub-pixel, and an independent line segment cut from the selected common electrode line; Breaking the other common electrode, each of said repair sub-
  • the communication path includes at least one transistor and pixel electrode of the repair sub-pixel, a common electrode of each repair sub-pixel, and an independent line segment cut from the selected common electrode line;
  • the communication path includes at least one compensation structure coupled to the common electrode of the repair sub-pixel, the common electrode of each repair sub-pixel, and an independent line segment cut from the selected common electrode line.
  • a common electrode line is provided between each adjacent two gate lines; the plurality of compensation structures are divided into multiple groups, and each group of compensation structures includes several compensation structures arranged at intervals along the column direction; Each compensation structure of the group compensation structure is alternately arranged with each common electrode of a column of sub-pixels, and each common electrode of the column of sub-pixels is connected in series.
  • the two connection elements closest to the disconnection position and respectively on both sides of the disconnection position are two transistors; or, one transistor and one compensation structure.
  • the selecting one or two sub-pixels related to the determined two connecting elements from the sub-pixels coupled to the gate line where the disconnection position is located as the repair sub-pixel includes: The two connecting elements closest to the disconnection position and respectively on both sides of the disconnection position are two transistors, and the sub-pixels to which the two transistors belong are selected as the first repair sub-pixel and the second repair sub-pixel; If the two connection elements closest to the disconnection position and on both sides of the disconnection position are a transistor and a compensation structure, and the sub-pixel to which the transistor belongs and the sub-pixel to which the common electrode coupled to the compensation structure belongs The pixels are different sub-pixels, the sub-pixel to which the common electrode coupled to the compensation structure belongs is selected as the first repair sub-pixel, and the sub-pixel to which the transistor belongs is selected as the second repair sub-pixel; The two connection elements adjacent to and respectively on both sides of the disconnection position are a transistor and a compensation structure, and the sub-image to which the transistor belongs The subpixel to which the common
  • the two connection elements closest to the disconnection position and on both sides of the disconnection position are two transistors, and the common electrode of the second repair sub-pixel is not coupled to the compensation structure
  • forming a communication path between the front and the rear at the disconnected position includes: passing the front of the broken position through the second end of the transistor of the first repair sub-pixel And the pixel electrode of the sub-pixel, which is coupled to the common electrode of the sub-pixel; passing the rear part of the broken position through the second end of the transistor of the second repair sub-pixel and the pixel of the sub-pixel The electrode is coupled to the common electrode of the sub-pixel.
  • the two connection elements closest to the disconnection position and on both sides of the disconnection position are two transistors, and the common electrode of the second repair sub-pixel is coupled to the compensation structure Situation; wherein, the compensation structure coupled to the common electrode of the second repair sub-pixel includes: a first compensation structure passing through the gate line where the disconnection is located, and a second passing through the selected common electrode line A compensation structure; the forming a communication path between the front and the rear at the disconnected position includes: passing the front of the broken position through the second end of the transistor of the first repair sub-pixel, And the pixel electrode of the sub-pixel, coupled to the common electrode of the sub-pixel; passing the rear of the broken position through the second end of the transistor of the second repair sub-pixel and the pixel electrode of the sub-pixel , Coupled to the common electrode of the sub-pixel.
  • the two connection elements closest to the disconnection position and on both sides of the disconnection position are two transistors, and the common electrode of the second repair sub-pixel is coupled to the compensation structure Situation; wherein, the compensation structure coupled to the common electrode of the second repair sub-pixel includes: a first compensation structure passing through the gate line where the disconnection is located, and a second passing through the selected common electrode line A compensation structure; the forming a communication path between the front and the rear at the disconnected position includes: passing the front of the broken position through the second end of the transistor of the first repair sub-pixel, And the pixel electrode of the sub-pixel is coupled to the common electrode of the sub-pixel; the rear part of the broken position is coupled to the first compensation structure through the common electrode of the second repair sub-pixel, and the The common electrode of the sub-pixel is coupled.
  • the disconnecting the common electrode in the communication path from other common electrodes includes: coupling the first compensation structure and the second compensation structure to the common electrode of the second repair subpixel The common electrodes other than the common electrode of the second repair sub-pixel are broken.
  • the two connection elements closest to the disconnection position and on both sides of the disconnection position are a transistor and a compensation structure
  • the sub-pixel to which the transistor belongs is coupled to the compensation structure Where the sub-pixel to which the common electrode belongs is the same sub-pixel
  • the compensation structure coupled to the common electrode of the first repair sub-pixel includes: a first compensation structure passing through the gate line where the disconnection position is located , And a second compensation structure passing through the selected common electrode line; forming a communication path between the front and the rear at the disconnected position includes: passing the front at the broken position through The second end of the transistor of the first repair sub-pixel and the pixel electrode of the sub-pixel are coupled to the common electrode of the sub-pixel; the back of the broken position is passed through the The first compensation structure coupled to the common electrode is coupled to the common electrode of the sub-pixel.
  • the disconnecting the common electrode in the communication path from other common electrodes includes: a first compensation structure and a second compensation structure coupled to the common electrode of the first repair sub-pixel and The common electrodes other than the common electrode of the first repair sub-pixel are broken.
  • the two connection elements closest to the disconnection position and on both sides of the disconnection position are a transistor and a compensation structure
  • the sub-pixel to which the transistor belongs is coupled to the compensation structure
  • the sub-pixel to which the common electrode belongs is a different sub-pixel
  • the first repair sub-pixel and the second repair sub-pixel are both coupled to the compensation structure
  • the The compensation structure coupled to the common electrode and the compensation structure coupled to the common electrode of the second repair sub-pixel both include: a first compensation structure passing through the gate line where the disconnection position is located, and passing the selected common A second compensation structure of the electrode wire
  • the forming a communication path between the front and the rear at the disconnected position includes: passing the front of the broken position through the first repair sub-pixel
  • the first compensation structure coupled to the common electrode is coupled to the common electrode of the sub-pixel; the rear portion of the broken position is coupled to the common electrode of the second repair sub-pixel A compensation structure, coupled with the common subpixel electrode.
  • the disconnecting the common electrode in the communication path from other common electrodes includes: a first compensation structure and a second compensation structure coupled to the common electrode of the first repair sub-pixel and The common electrodes other than the common electrode of the first repair sub-pixel are disconnected; the first compensation structure and the second compensation structure coupled to the common electrode of the second repair sub-pixel are removed from the second repair The common electrodes other than the common electrode of the sub-pixel are disconnected.
  • a repair structure for broken gate lines in an array substrate is provided.
  • the repair structure is repaired by the repair method according to any one of the above.
  • the repair structure includes: a broken gate line including the front and the rear at the broken position; one or two repair sub-pixels, each of the repair sub-pixels includes a transistor, a pixel electrode, and a common electrode;
  • a selected common electrode line, the selected common electrode line includes an independent line segment coupled to the common electrode of each of the repair sub-pixels, and the independent line segment is not coupled to other parts of the selected common electrode line.
  • the communication passage is configured to bypass the disconnection position; the communication passage includes at least a common electrode of each of the repair sub-pixels, and An independent line segment in the selected common electrode line; the common electrode in the communication path is not coupled with other common electrodes, and each of the repair sub-pixels is not coupled with the data line.
  • the communication path includes at least one transistor and pixel electrode of the repair sub-pixel, a common electrode of each repair sub-pixel, and an independent line segment in the selected common electrode line.
  • the repair structure includes two repair sub-pixels, respectively: a first repair sub-pixel coupled to the front of the disconnected position, and a first sub-pixel coupled to the rear of the disconnected position Two repair sub-pixels, and the common electrode of the second repair sub-pixel is not coupled to the compensation structure.
  • the front part of the fracture position is coupled to the common electrode of the sub-pixel through the second end of the transistor of the first repair sub-pixel and the pixel electrode of the sub-pixel; the rear part of the fracture position Through the second end of the transistor of the second repair sub-pixel and the pixel electrode of the sub-pixel, it is coupled to the common electrode of the sub-pixel.
  • the repair structure includes two repair sub-pixels, respectively: a first repair sub-pixel coupled to the front of the disconnected position, and a first sub-pixel coupled to the rear of the disconnected position Two repair sub-pixels, and the common electrode of the second repair sub-pixel is coupled to the compensation structure.
  • the compensation structure coupled to the common electrode of the second repair sub-pixel includes: a first compensation structure passing through the gate line where the disconnection position is located, and a second compensation structure passing through the selected common electrode line.
  • the front part of the fracture position is coupled to the common electrode of the sub-pixel through the second end of the transistor of the first repair sub-pixel and the pixel electrode of the sub-pixel; the rear part of the fracture position Through the second end of the transistor of the second repair sub-pixel and the pixel electrode of the sub-pixel, it is coupled to the common electrode of the sub-pixel.
  • the first compensation structure nor the second compensation structure is coupled to the common electrodes of sub-pixels other than the second repair sub-pixel.
  • the repair structure includes two repair sub-pixels, respectively: a first repair sub-pixel coupled to the front of the disconnected position, and a first sub-pixel coupled to the rear of the disconnected position Two repair sub-pixels, and the common electrode of the second repair sub-pixel is coupled to the compensation structure.
  • the compensation structure coupled to the common electrode of the second repair sub-pixel includes: a first compensation structure passing through the gate line where the disconnection position is located, and a second compensation structure passing through the selected common electrode line.
  • the front part of the fracture position is coupled to the common electrode of the sub-pixel through the second end of the transistor of the first repair sub-pixel and the pixel electrode of the sub-pixel; the rear part of the fracture position
  • the first compensation structure coupled to the common electrode of the second repair sub-pixel is coupled to the common electrode of the sub-pixel. Neither the first compensation structure nor the second compensation structure is coupled to the common electrodes of sub-pixels other than the second repair sub-pixel.
  • the repair structure includes a repair sub-pixel, the repair sub-pixel is coupled to the front of the disconnection position, and the repair sub-pixel is coupled to the compensation structure.
  • the compensation structure coupled to the common electrode of the repair sub-pixel includes: a first compensation structure passing through the gate line where the disconnection position is located, and a second compensation structure passing through the selected common electrode line.
  • the front part of the fracture position is coupled to the common electrode of the sub-pixel through the second end of the transistor of the repair sub-pixel and the pixel electrode of the sub-pixel; the rear part of the fracture position through the
  • the first compensation structure to which the common electrode of the repair sub-pixel is coupled is coupled to the common electrode of the sub-pixel. Neither the first compensation structure nor the second compensation structure is coupled to the common electrode of the sub-pixels other than the repair sub-pixel.
  • the repair structure includes two repair sub-pixels, respectively: a first repair sub-pixel coupled to the front of the disconnected position, and a first sub-pixel coupled to the rear of the disconnected position Two repair sub-pixels, and both the first repair sub-pixel and the second repair sub-pixel are coupled to the compensation structure.
  • the compensation structure coupled to the common electrode of the first repair sub-pixel and the compensation structure coupled to the common electrode of the second repair sub-pixel both include: first compensation through the gate line where the disconnection position is located Structure, and a second compensation structure passing through the selected common electrode line.
  • the front part at the fracture position is coupled to the common electrode of the sub-pixel through the first compensation structure coupled to the common electrode of the first repair sub-pixel; the rear part at the fracture position is passed through The first compensation structure coupled to the common electrode of the second repair sub-pixel is coupled to the common electrode of the sub-pixel.
  • the first compensation structure and the second compensation structure coupled to the common electrode of the first repair sub-pixel are not coupled to the common electrode of the sub-pixels other than the repair sub-pixel;
  • the first compensation structure and the second compensation structure to which the common electrode is coupled are not coupled to the common electrodes of sub-pixels other than the repair sub-pixel.
  • a method for repairing a short circuit between a gate line and a data line in an array substrate includes the following steps: determining a short-circuit position between the gate line and the data line; along the extending direction of the gate line The gate line is cut off on both sides immediately adjacent to the short-circuit position, so that the gate line forms an open circuit; the repair method of the grid line open circuit as described in some embodiments above is used to repair the broken grid line.
  • an array substrate includes a repair structure for broken gate lines as described in any one of the foregoing embodiments.
  • a display device including the array substrate as provided in the above aspect.
  • FIG. 1 is a schematic partial top structural view of an array substrate provided according to the related art
  • FIG. 2 is a schematic diagram of a method for repairing a short circuit between a gate line and a data line according to the related art
  • FIG. 3 is a schematic diagram of another method for repairing a short circuit between a gate line and a data line according to the related art
  • FIG. 4 is a schematic partial top structural view of an array substrate used in a method for repairing a broken gate line according to some embodiments of the present disclosure
  • FIG. 5 is a schematic flowchart of a method for repairing a broken gate line according to some embodiments of the present disclosure
  • FIG. 6 is a schematic diagram of a method for repairing a broken gate line according to some embodiments of the present disclosure
  • FIG. 7 is a schematic diagram of yet another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram of another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • FIG. 12 is a schematic diagram of another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • FIG. 13 is a schematic diagram of another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • FIG. 14 is a schematic diagram of another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • 15 is a schematic diagram of another method for repairing a broken gate line according to some embodiments of the present disclosure.
  • 16 is a schematic diagram of a method for repairing a short circuit between a gate line and a data line according to some embodiments of the present disclosure
  • 17 is a schematic diagram of yet another method for repairing a short circuit between a gate line and a data line according to some embodiments of the present disclosure
  • FIG. 18 is a schematic diagram of another method for repairing a short circuit between a gate line and a data line according to some embodiments of the present disclosure
  • 19 is a schematic diagram of another method for repairing a short circuit between a gate line and a data line according to some embodiments of the present disclosure
  • 20 is a schematic diagram of another method for repairing a short circuit between a gate line and a data line according to some embodiments of the present disclosure
  • 21 is a schematic cross-sectional structure diagram of a display device according to some embodiments of the present disclosure.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • orientation or positional relationship indicated by “up / up”, “down / down”, “row / row direction”, and “column / column direction” are based on the orientation or positional relationship shown in the drawings, only for convenience
  • the simplified description of the technical solutions of the present invention is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as limiting the present invention.
  • the signal lines of the array substrate include a gate line and a data line. Since the intersection of the gate line and the data line is only insulated by the gate insulating layer, the gate line and the data line are prone to occur. kind of bad.
  • the opening of the gate line and / or data line (Open), which will cause the broken gate line and / or data line to fail to transmit the corresponding signal normally, affecting the display effect of the display panel;
  • the intersection of the gate line and the data line A short circuit (Data Gate Short, abbreviated as DGS) occurs, which will cause the signal of the gate line and the data line to affect each other, making the display panel unable to display normally.
  • DGS Data Gate Short
  • a test process (Cell Test) is required for each display panel to determine the quality of the panel.
  • the detection process includes the detection of each signal line defect and a further repair process.
  • FIG. 1 is a schematic partial top structural view of an array substrate 01.
  • the array substrate 01 includes: a base substrate 10, a plurality of sub-pixels 20 (also referred to as sub-pixels) that are provided on the base substrate 10, and A plurality of gate lines 30, a plurality of data lines 40, a plurality of common electrode lines 50, and a plurality of compensation structures 60.
  • each sub-pixel 20 includes a transistor (for example, a thin film transistor, Thin Film Transistor, abbreviated as TFT), a pixel electrode 21 and a common electrode 22.
  • the plurality of sub-pixels 20 included in the array substrate 01 are arranged in an array of multiple rows and columns.
  • the row direction of the plurality of sub-pixels 20 is set as the first direction D1
  • the column direction is the second direction D2. It can be understood that the row direction and the column direction of the plurality of sub-pixels 20 cross each other, that is, the first direction D1 and the second direction D2 cross each other, for example, the first direction D1 and the second direction D2 are perpendicular to each other.
  • Each transistor TFT of each row of sub-pixels 20 (for example, each row of sub-pixels 20 arranged along the first direction D1) is coupled to one gate line 30, and each transistor TFT of the same row of sub-pixels 20 is coupled to the same gate line 30 Pick up.
  • Each transistor TFT of each column of sub-pixels 20 (for example, each column of sub-pixels 20 arranged along the second direction D2) is coupled to one data line 40, and each transistor TFT of the same column of sub-pixels 20 is coupled to the same data line 40.
  • Each common electrode 22 of the plurality of sub-pixels 20 is electrically connected to the plurality of compensation structures 60 through the plurality of common electrode lines 50. Wherein, each common electrode 22 of each row of sub-pixels 20 is coupled to one common electrode line 50, and each common electrode 22 of the same row of sub-pixels 20 is coupled to the same common electrode line 50.
  • FIG. 1 is a partial top view schematic diagram of the array substrate 01, only a portion of the top view of each structure side of the array substrate 01 is shown. Therefore, in FIG. 1, only the dotted frame represents the base substrate 10 And, the actual number of sub-pixels 20 included in the array substrate 01 is much larger than the number illustrated in FIG. 1, which is only an example.
  • each transistor TFT of each row of sub-pixels 20 is coupled to a gate line 30 so that the gate line 30 provides a scan signal to each transistor TFT coupled thereto.
  • the control terminal (commonly referred to as a gate) of the transistor TFT of each row of sub-pixels 20 is coupled to a gate line 30.
  • the gate of the transistor TFT may be a part protruding from the gate line 30, or the gate of the transistor TFT may also be a part on the main body of the extending direction of the gate line 30.
  • FIG. 1 shows only the latter case as an example, that is, “the gate is a part of the main body in the extending direction of the gate line 30”, that is, in FIG. 1, the gate of the transistor TFT is connected to the transistor TFT on the gate line 30 That part.
  • the patterns of the gate and the gate lines can follow various structures in the related art, which is not limited herein.
  • Each transistor TFT of each column of sub-pixels 20 is coupled to a data line 40, so that the data line 40 provides a data signal to each transistor TFT coupled thereto to control the array substrate 01 and the box-to-box substrate formed after the box-to-box The display screen of the display panel.
  • the first end of the transistor TFT of each column of sub-pixels 20 is coupled to a data line 40.
  • the first end of the transistor TFT may be an input end, which is called a source (Source); the second end of the transistor TFT, which may be an output end, is called a drain. Therefore, “the first end of the transistor TFT of each column of sub-pixels 20 is coupled to one data line 40” can be understood as the source of the transistor TFT of each column of sub-pixels 20 is coupled to one data line 40.
  • the drain of the transistor TFT of each column of sub-pixels 20 is coupled to the row of pixel electrodes 21.
  • the source electrode of the transistor TFT is coupled to the data line, and the drain electrode of the transistor TFT is coupled to the pixel electrode as an example for description, however, those skilled in the art It should be understood that due to the interchangeability in structure and composition of the source and drain of the transistor, the first end of the transistor TFT may also be referred to as the output, that is, the drain and the second end of the transistor TFT may be referred to as The output, that is, the source, belongs to the equivalent transformation of the above embodiment of the present disclosure.
  • the above array substrate 01 also includes an insulating layer for isolating different conductive layers, for example, a gate insulating layer provided for isolating the gate pattern layer from the source-drain pattern layer, wherein the gate pattern layer includes the gate of the transistor TFT,
  • the gate line 30 and the source-drain pattern layer include the source S, the drain D, and the data line 40 of the transistor TFT; for another example, a passivation layer provided to isolate the pixel electrode 21 and the common electrode 22.
  • the above-mentioned transistor TFT certainly includes structures such as an active layer.
  • the insulating layers and the active layer in the transistor TFT are not shown in FIG. 1 above, and the specifics of the insulating layers
  • the installation location, the specific structure of the transistor TFT, and the shape of each electrode structure can follow related technologies, which are not limited in the embodiments of the present disclosure.
  • the common electrode 22 of each sub-pixel 20 of the array substrate 01 is an independent block electrode instead of a whole layer of planar electrodes, and each common electrode 22 is configured to transmit The same common voltage signal, therefore, each common electrode 22 of each row of sub-pixels 20 is coupled to a corresponding common electrode line 50 in order to receive the common voltage signal.
  • the common electrode 22 is made of a transparent conductive oxide material such as ITO (Indium Tin Oxide), and the common electrode line 50 and the gate line 30 are arranged in the same layer, and the lower resistivity is used. It is made of a metal material such as Cu (copper), that is, the common electrode 22 and the common electrode line 50 are formed through different pattern processing processes, and it is difficult to form them simultaneously in the same pattern processing process. Therefore, in order to ensure good electrical communication between the two, each common electrode 22 of each row of sub-pixels 20 is electrically connected to the common electrode line 50 through a portion having an overlapping area with one common electrode line 50.
  • ITO Indium Tin Oxide
  • the common electrode 22 of each row of sub-pixels 20 corresponds to one coupled common electrode line 50
  • the coupling manner may be as follows: each common electrode 22 of each row of sub-pixels 20 overlaps with one common electrode line 50 The part of the area is in electrical communication with the common electrode line 50.
  • the coupling manner may also be: each common electrode 22 of each row of sub-pixels 20 is bridged to a common electrode line 50 through a conductive structure, so that each common electrode 22 of each row of sub-pixels 20 and the common electrode line 50 Electrically connected (ie coupled).
  • overlap area specifically refers to an area where the orthographic projections of the two structures on the base substrate 10 overlap.
  • the parts with overlapping areas of the two can be directly overlapped together to form electrical communication; when the common electrode 22 and the common electrode line 50 are located in different layers (ie When there is an insulating layer between the two, the portions of the two that have overlapping regions can be connected through vias that penetrate the insulating layer at corresponding positions to form electrical communication.
  • each common electrode 22 of the plurality of sub-pixels 20 is electrically connected to the plurality of compensation structures 60 through the plurality of common electrode lines 50.
  • each compensation structure 60 is located between two adjacent common electrodes 22 arranged in the column direction, and is coupled with the two common electrodes 22, so that by providing a column of compensation structures 60, a column of common electrodes 22 can be connected in series
  • each compensation structure 60 and each common electrode line 50 together form a grid-like electrical communication path, so that the common electrode 22 of the plurality of sub-pixels 20 passes through the plurality of common electrode lines 50 and the
  • the compensation structures 60 are electrically connected together, thereby reducing the resistance of the overall structure (ie, the Com structure) formed by each common electrode 22 and each common electrode line 50, and at the same time, the uniformity of the voltage applied to the Com structure can also be improved.
  • the manner in which the compensation structure 60 is connected to the two adjacent common electrodes 22 arranged in the column direction includes, but is not limited to: the compensation structure 60 passes through a portion having an overlapping area with the two adjacent common electrodes 22 arranged in the column direction , Electrically connected to the two adjacent common electrodes 22; or, the connection mode may also be: the compensation structure 60 bridges the two adjacent common electrodes 22 arranged in the column direction through the conductive structure, so that the phase The two adjacent common electrodes 22 are electrically connected together.
  • the compensation structure 60 is, for example, a portion having an overlapping area with two adjacent common electrodes 22 arranged in the column direction, and the two common electrodes 22 may be electrically connected together.
  • the compensation structure 60 and the corresponding common electrode 22 The graphics with overlapping areas include but are not limited to the rectangle illustrated in FIG. 1, and the middle portion of the compensation structure 60 connecting the two rectangles above and below and crossing the gate line 30 includes but is not limited to the strip shape illustrated in FIG. 1 .
  • the specific shapes of the pixel electrode 21 and the common electrode 22 are not limited, as long as the pixel electrode 21 and the common electrode 22 are arranged oppositely, that is, there is an overlapping area between the two, which can form a corresponding driving liquid crystal molecule deflection Electric field.
  • the patterns of the pixel electrode 21 and the common electrode 22 illustrated in FIG. 1 are only examples.
  • the detected defect is a short circuit (DGS) between the gate line and the data line.
  • DGS short circuit
  • One way of repairing is to convert the short circuit between the gate line and the data line into a disconnection of the data line, and repair the disconnected data line with the help of a structure such as a common electrode in the sub-pixel. As shown in Figure 2, the repair process is specifically:
  • the two common electrode lines 50 and between the common electrodes 22 of the two sub-pixels 20 and the other common electrodes 22 The compensation structure 60 cuts off, so that the data line signal loaded on the data line 40 where the disconnection occurs can be transmitted via the common electrode 22 near the disconnection position.
  • the above-mentioned repair method needs to sacrifice two sub-pixels 20, that is, two sub-pixels 20 cannot be displayed normally after the repair and become dark spots.
  • the above-mentioned repair method needs to sacrifice four sub-pixels 20. That is to say, after the data line signal loaded on the data line 40 with the disconnection is transmitted via the common electrodes 22 of the four sub-pixels 20, since the common electrodes 22 of the four sub-pixels 20 cannot be loaded with the corresponding common electrode voltage, As a result, when the display device including the above-mentioned array substrate 01 is displayed after repair, the four sub-pixels 20 cannot be displayed, which is a dark spot. Since more dark spots are formed after the repair, the product quality of the display panel is affected more Big.
  • some embodiments of the present disclosure provide a method for repairing a short circuit between a gate line and a data line in an array substrate.
  • this repair method first determine the position of the short circuit between the gate line and the data line; then, along the extension direction of the gate line, cut the two sides of the short-circuited gate line immediately adjacent to the short-circuit position to make the gate line open; then use The repair method of the broken grid line repairs the broken grid line. That is to say, regarding the short circuit problem between the gate line and the data line, in the embodiment of the present disclosure, the short circuit problem between the gate line and the data line is converted into the open circuit problem of the grid line, and then a certain repair method is used to repair the open circuit of the gate line. Therefore, the short circuit between the gate line and the data line is finally repaired.
  • the method for repairing the broken gate line in the embodiments provided below is not only applicable to the repair process of the short circuit between the gate line and the data line. It can be understood that the repair method for the broken gate line is also applicable to the simple gate Scenarios of wire breakage, and other scenes that require the application of these repair methods of wire breakage.
  • the array substrate 01 includes: multiple sub-pixels 20, multiple gate lines 30, and multiple data lines 40 , Multiple common electrode lines 50 and multiple compensation structures 60.
  • the array substrate 01 further includes a base substrate 10, the plurality of sub-pixels 20, the plurality of gate lines 30, the plurality of data lines 40, the plurality of common electrode lines 50 and the A plurality of compensation structures 60 may be provided on the base substrate 10.
  • each sub-pixel 20 includes a transistor TFT, a pixel electrode 21 and a common electrode 22.
  • Each transistor TFT of a row of sub-pixels 20 is coupled to the same gate line 30
  • each transistor TFT of a column of sub-pixels 20 is coupled to the same data line 40
  • each common electrode 22 of a row of sub-pixels 20 is connected to the same common electrode line 50 Coupling.
  • Each common electrode 22 of the plurality of sub-pixels 20 is electrically connected to the plurality of compensation structures 60 through the plurality of common electrode lines 50.
  • each transistor TFT coupled to one gate line 30 and each compensation structure 60 that crosses the gate line 30 and is coupled to the common electrode 22 of the sub-pixel 20 to which the gate line 30 is coupled are collectively referred to as the The connection element L of the strip gate line 30.
  • the gate line 300 is coupled to five transistors TFTs, and the five sub-pixels 20 across the gate line 30 and coupled to the gate line 30
  • the connection element L corresponding to the gate line 30 should not be limited to the five transistor TFTs and the two compensation structures 60, but include more transistor TFTs and compensation structures 60.
  • the gate line 30 also corresponds to a plurality of connection elements L, and the plurality of connection elements L include transistors TFT coupled to the gate line 30, And each compensation structure 60 that spans the gate line 30 and is coupled to the common electrode 22 of each sub-pixel 20 to which the gate line 30 is coupled.
  • the repair method of the broken gate line includes S1 to S3:
  • the manner of determining the disconnection position of the gate line includes, but is not limited to, the manner of manual inspection, and may also include the manner of inspection by means of corresponding inspection equipment.
  • S2 Along the extending direction of the gate line where the disconnection position is located, determine the two connection elements closest to the disconnection position and on both sides of the disconnection position; from each sub-pixel coupled to the gate line where the disconnection position is located, select the One or two sub-pixels electrically connected by the determined two connecting elements are used as repair sub-pixels; the common electrode line coupled to the common electrode of each repair sub-pixel is determined as the selected common electrode line.
  • the "extending direction of the gate line" is, for example, the row direction in which the plurality of sub-pixels 20 are arranged, and is, for example, the first direction D1.
  • connection elements are each of the transistors coupled to the gate line where the disconnection is located, and each of the compensation structures across the gate line and coupled to the common electrode of the sub-pixel to which the gate line is coupled Two components.
  • S3 forming a communication path between the front and the rear at the disconnected position to bypass the disconnected position with the communication path; the connected path includes at least the common electrode of each repaired sub-pixel and is cut out from the selected common electrode line Separate line segments; disconnect the common electrode in the communication path from other common electrodes, and disconnect each repair sub-pixel from the data line to which it is coupled.
  • a disconnection position on the gate line 30 divides the corresponding part of the gate line 30 into two segments, and the “front” F1 at the disconnection position mentioned in this article Refers to one of the two segments, and the "rear” F2 at the open position refers to the other of the two segments.
  • the disconnection position (marked as “Open” in FIG. 6 to FIG. 15 means disconnection) divides the corresponding part of the gate line 30 into two segments, that is, located on the left side of the disconnection position One section and the section located to the right of the open position.
  • the "front” F1 at the disconnected position refers to a section located to the left of the disconnected position
  • the "rear” F2 at the disconnected position refers to a section located to the right of the disconnected position.
  • the "front” F1 at the disconnected position refers to a section located to the right of the disconnected position
  • the "rear” F2 at the disconnected position refers to a section located to the left of the disconnected position.
  • the so-called “bypass” is an action that allows the gate line signal loaded on the broken gate line to pass through the above common electrode including at least each repaired sub-pixel, and cut out from the selected common electrode line
  • the connection path of the independent line segment bypasses the open position, so that the gate line signal can continue to be transmitted, so as to be loaded into the other transistor TFT connected to the gate line, so that the row of sub-pixels other than the repair sub-pixel The sub-pixels can display normally.
  • the "independent line segment" cut from the selected common electrode line is a line segment electrically isolated from the remaining part on the selected common electrode line.
  • the function of the communication path is to break the position on the bypass gate line, and the communication path includes at least the common electrode of each repair sub-pixel and an independent line segment cut from the selected common electrode line, The independent line segments cut on the common electrode line are electrically connected with the common electrode of each repair sub-pixel.
  • each common electrode of the plurality of sub-pixels passes through the plurality of common electrode lines and the plurality of compensation structures
  • the common electrical connection therefore, after the selected common electrode line is cut off, the common voltage signal loaded on the remaining part of the selected common electrode line except the independent line segment can be transmitted to the remaining part through the compensation structure at the corresponding position
  • the other common electrodes are electrically connected, so that the selected common electrode line can normally transmit a common voltage signal.
  • the bypass is bypassed
  • the position of the open circuit, so that the open circuit on the grid line can be repaired, the number of repairable grid lines is not limited, and the number of sub-pixels that form dark spots after the repair of an open circuit location is only one or two, that is, one open location is formed after repair
  • the number of sub-pixels of dark dots is at most two; with the repair method in the related art, there are at least two sub-pixels that form dark dots after repairing an open position, even as described in the related technology above, for some open In the case of location, there are four sub-pixels that form dark spots after repairing an open circuit location. Therefore, in comparison, with the repair method provided by the embodiments of the present disclosure, the number of sub-pixels that form dark dots after repairing an open circuit position is small, so that the display effect after repair is good.
  • the above-mentioned communication path includes at least one transistor TFT for repairing the sub-pixel and the pixel electrode 21, a common electrode 22 for each repairing sub-pixel, and a cut from the selected common electrode line Independent line segment.
  • the above communication path includes at least one compensation structure 60 coupled to the common electrode 22 of the repair sub-pixel, the common electrode 22 of each repair sub-pixel, and the selected common electrode line Cut out the independent line segment.
  • a common electrode line 50 is provided between each adjacent two grid lines 30; the plurality of compensation structures 60 are divided into multiple groups Compensation structure, each group of compensation structures includes several compensation structures 60 arranged at intervals along the column direction (second direction D2); each compensation structure 60 of each group of compensation structures and each common electrode 22 of a column of sub-pixels are alternately arranged, each compensation The structure 60 is coupled to two common electrodes 22 adjacent in the column direction, so that each compensation structure 60 of each group of compensation structures connects the common electrodes 22 of the column of sub-pixels 20 in series.
  • one common electrode line 50 is provided between every two adjacent gate lines 30.
  • the common electrode line 50 may be arranged closer to one of the gate lines 30 (the following one grid line 30).
  • the plurality of sets of compensation structures 60 correspond to at least two columns of the common electrodes 22 among the plurality of columns of common electrodes 22 included in the array substrate 01, and the set of compensation structures 60 correspond to one row of common electrodes 22. Since each column of common electrodes 22 is located between two adjacent data lines 40, and each compensation structure 60 of each group of compensation structures and each common electrode 22 of a corresponding row of sub-pixels 20 are alternately arranged, each group of compensation structures 60 also has Located between the two data lines 40 where the corresponding common electrode column is located. It can include the following two setting methods:
  • each set of compensation structures 60 corresponds to each row of common electrodes 22 included in the array substrate 01 in a one-to-one correspondence.
  • the plurality of sets of compensation structures 60 may be provided between a part of the data lines 40 among all the data lines 40 included in the array substrate 01. That is to say, each set of compensation structures 60 is arranged in a one-to-one correspondence with some columns of the common electrodes 22 among the columns of the common electrodes 22 included in the array substrate 01.
  • the interval between the adjacent two sets of compensation structures 60 is along the column direction (second Two columns of sub-pixels 20 in direction D2). That is, every three columns of adjacent sub-pixels 20 in the array substrate 01 share a column of compensation structures 60. That is, every third data line 40 is provided with a set of compensation structures 60.
  • Such a 3: 1 structural design can make the number of compensation structures 60 distributed throughout the substrate appropriate, which is beneficial to reduce the resistance of the entire Com structure.
  • the compensation structure 60 functions to reduce the resistance of the entire Com structure, the compensation structure 60 is usually made of a metal material with a low resistivity, and the transparency of these metal materials such as Cu is low.
  • each column of sub-pixels 20 is correspondingly provided with a column of compensation structures 60, that is, each adjacent two data lines 40 are provided with a set of compensation structures 60, which affects the entire array substrate.
  • 01 has a large influence on the light transmittance
  • the above 3: 1 structural design has a small influence on the light transmittance, which can avoid increasing the performance of the backlight module matched with the liquid crystal display panel including the array substrate 01 Consume.
  • the arrangement form of the multiple sets of compensation structures 60 in the array substrate 01 is not limited to the above example, but may be every 2, 4, 5, 6, 7, 8, 9, 10
  • An equal number of data lines 40 are provided with a set of compensation structures 60.
  • the connecting elements L that are closest to the disconnection position on the gate line 30 and respectively on both sides of the disconnection position may include at least the following two situations:
  • the two connecting elements L that are closest to the disconnection position on the gate line 30 and respectively on both sides of the disconnection position are two transistors TFT, that is, the disconnection position (FIG. 6 ⁇ FIG. Marked as "Open” in 8, means open) between two transistors TFT.
  • connection elements L that are closest to the disconnection position on the gate line 30 and are on both sides of the disconnection position, one of which is a transistor TFT and the other is a compensation structure 60, namely
  • the open position (marked as “Open” in FIGS. 9 to 15, indicating open) is between the transistor TFT and the compensation structure 60.
  • how to select the repair sub-pixel in S2 includes at least the following three ways:
  • the two connecting elements L are two transistor TFTs
  • the sub-pixel 20 serves as a first repair sub-pixel P1 and a second repair sub-pixel P2.
  • the first repair sub-pixel P1 is coupled to the front F1 at the disconnected position
  • the second repair sub-pixel P2 is coupled to the rear F2 at the disconnected position. That is, in the process of repairing the broken gate line, the two sub-pixels of the first repair sub-pixel P1 and the second repair sub-pixel P2 are sacrificed to complete the repair work.
  • the two connecting elements L one of which is a transistor TFT and the other is a compensation structure 60
  • the sub-pixel 20 to which it belongs is the same sub-pixel, and from each sub-pixel 20 coupled to the gate line 30 where the disconnection position is located, the sub-pixel 20 to which the transistor TFT belongs is selected as the first repair sub-pixel P1.
  • the first repair sub-pixel P1 is coupled to the front part F1 at the disconnected position. That is, in the process of repairing the broken gate line, one sub-pixel of the first repair sub-pixel P1 is sacrificed to complete the repair work.
  • the two connecting elements L one of which is a transistor TFT and the other is a compensation structure 60
  • the sub-pixel 20 to which the transistor TFT belongs is coupled to the compensation structure 60
  • the sub-pixels to which the common electrode 22 belongs are different sub-pixels, from the sub-pixels 20 coupled to the gate line 30 where the disconnection position is located, select the sub-pixel 20 to which the common electrode 22 to which the compensation structure 60 is coupled belongs
  • the first repair sub-pixel P1 selects the sub-pixel 20 to which the transistor TFT belongs as the second repair sub-pixel P2.
  • the first repair sub-pixel P1 is coupled to the front F1 at the disconnected position
  • the second repair sub-pixel P2 is coupled to the rear F2 at the disconnected position. That is, in the process of repairing the broken gate line, the two sub-pixels of the first repair sub-pixel P1 and the second repair sub-pixel P2 are sacrificed to complete the repair work.
  • the disconnection position on the gate line 30 includes at least the following five types:
  • the open position (marked as “Open” in FIG. 6 means open) is between two transistors TFT.
  • the sub-pixels 20 to which the two transistors TFT belong respectively are the first repair sub-pixel P1 and the second repair sub-pixel P2, wherein the common electrode 22 of the second repair sub-pixel P2 is not coupled to the compensation structure 60.
  • the open position (marked as “Open” in FIG. 7 and FIG. 8 to indicate open) is between the two transistors TFT.
  • the sub-pixels 20 to which the two transistors TFT belong respectively are the first repair sub-pixel P1 and the second repair sub-pixel P2, wherein the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure 60.
  • the compensation structure 60 coupled to the common electrode 22 of the second repair sub-pixel P2 includes a first compensation structure C1 spanning the gate line 30 where the disconnection is located, and a second compensation structure C2 passing through the selected common electrode line.
  • the open position (marked as “Open” in FIG. 9 means open) is between the transistor TFT and the compensation structure 60, and the sub-pixel 20 to which the transistor TFT belongs is coupled to the compensation structure 60
  • the subpixel 20 to which the connected common electrode 22 belongs is the same subpixel, and the subpixel is the first repair subpixel P1.
  • the compensation structure 60 coupled to the common electrode 22 of the first repair sub-pixel P1 includes: a first compensation structure C1 that spans the gate line where the disconnection position is located, and a second compensation through the selected common electrode line Structure C2.
  • the open position (marked as “Open” in FIG. 10 and FIG. 11 means open) is between the transistor TFT and the compensation structure 60, and the sub-pixel 20 to which the transistor TFT belongs is The sub-pixels 20 to which the common electrode 22 coupled to the compensation structure 60 belongs are different sub-pixels.
  • the sub-pixel 20 to which the common electrode 22 coupled to the compensation structure 60 belongs is the first repair sub-pixel P1, and the sub-pixel 20 to which the transistor TFT belongs is the second repair sub-pixel P2, wherein the common of the second repair sub-pixel P2
  • the electrode 22 is not coupled to the compensation structure 60.
  • the compensation structure 60 coupled to the common electrode 22 of the first repair sub-pixel P1 includes: a first compensation structure C1 passing through the gate line 30 where the disconnection is located, and a second compensation structure C2 passing through the selected common electrode line 50 .
  • the disconnection position (marked as "Open” in FIG. 12, FIG. 14, FIG. 14 and FIG. 15 means disconnection) is between the transistor TFT and the compensation structure 60
  • the sub-pixel 20 to which the transistor TFT belongs and the sub-pixel 20 to which the common electrode 22 to which the compensation structure 60 is coupled are different sub-pixels.
  • the sub-pixel 20 to which the common electrode 22 coupled to the compensation structure 60 belongs is a first repair sub-pixel P1
  • the sub-pixel 20 to which the transistor TFT belongs is a second repair sub-pixel P2, wherein the first repair sub-pixel P1 and the second Both repair sub-pixels P2 are coupled to the compensation structure 60.
  • the compensation structure 60 coupled to the common electrode 22 of the first repair sub-pixel P1 and the compensation structure 60 coupled to the common electrode 22 of the second repair sub-pixel P2 each include: The first compensation structure C1 and the second compensation structure C2 spanning the selected common electrode line.
  • the following provides several exemplary repair methods for the above-mentioned different disconnect locations, which are used to describe in detail the specific repair process after the gate line is disconnected.
  • an exemplary method for repairing the disconnection includes the following steps:
  • S1 Determine the breaking position of the gate line 30 (marked as “Open” in FIG. 6 to indicate breaking).
  • S2 includes the following S211 to S212.
  • S211 Determine the two connecting elements L that are closest to the disconnection position and are on both sides of the disconnection position. If the two connection elements L are two transistor TFTs, then from the sub-pixels 20 coupled to the gate line 30 where the disconnection position is located, the sub-pixel 20 to which each of the two transistors TFT belongs is selected as the first repair sub-pixel P1 and the second repair sub-pixel P2. The first repair sub-pixel P1 is coupled to the front F1 at the disconnected position, and the second repair sub-pixel P2 is coupled to the rear F2 at the disconnected position.
  • S212 Determine that one common electrode line 50 coupled to the common electrode 22 of each of the first repair sub-pixel P1 and the second repair sub-pixel P2 (e.g., having an overlapping area) is the selected common electrode line 50 '.
  • S3 includes the following S311 to S314.
  • S311 Passing the front part F1 at the broken position through the second end (for example, the drain D) of the transistor TFT of the first repair sub-pixel P1 and the pixel electrode of the sub-pixel 20 (ie, the first repair sub-pixel P1) 21, coupled to the common electrode 22 of the sub-pixel 20.
  • S312 Pass the rear part F2 at the broken position through the second end (for example, the drain D) of the transistor TFT in the second repair sub-pixel P2 and the sub-pixel 20 (that is, the pixel electrode of the second repair sub-pixel P2 21, coupled to the common electrode 22 of the sub-pixel 20.
  • S313 Disconnect the transistors TFT of the first repair sub-pixel P1 and the second repair sub-pixel P2 and the data line 40 to which they are coupled. In this way, it can be avoided that the pixel electrodes 21 of the first repair sub-pixel P1 and the second repair sub-pixel P2 are still loaded with the data line signal on the data line 40, which affects the normal repair of the gate line 30.
  • S314 The selected common electrode line 50 'is disconnected from the other common electrodes 22 except for the common electrode 22 in the first repair sub-pixel P1 and the second repair sub-pixel P2 to form the selected common electrode line 50' Cut out the independent line segment 50a.
  • the pixel electrode 21 of the first repair sub-pixel P1 through the second end of the transistor TFT of the first repair sub-pixel P1 (denoted as drain D in FIG. 6), the pixel electrode 21 of the first repair sub-pixel P1, and the common electrode of the first repair sub-pixel P1 22.
  • the independent line segment 50a, the common electrode 22 of the second repair sub-pixel P2, the pixel electrode 21 of the second repair sub-pixel P2, and the second end of the transistor TFT of the second repair sub-pixel P2 (shown as a drain in FIG. 6) D)
  • the formed communication path, bypass and open position, and the signal transmission method can be as shown by the dotted arrow in FIG. 6.
  • the transmission direction X of the gate line signal may be from left to right, from right to left, or from both sides to the middle.
  • the disclosure only takes the transmission direction X of the gate line signal from left to right as an example for illustration, that is, as shown in FIG. 6, the transmission direction X of the gate line signal and the front portion F1 at the disconnection position point to the rear at the disconnection position
  • the direction of the part F2 is the same.
  • the transmission direction X of the gate line signal is from left to right.
  • the dark dots formed are only the first repair sub-pixel P1 and the second repair sub-pixel P2, which has less impact on the entire display panel and the repair effect is better .
  • S311 includes:
  • the front part F1 at the fracture position and the second end of the transistor TFT of the first repair sub-pixel P1 are soldered on, and the first repair sub-pixel P1
  • the pixel electrode 21 and the common electrode 22 of the sub-pixel i.e., the first repair sub-pixel P1 are connected by welding, so that the front portion F1 at the broken position passes through the second end of the transistor TFT of the first repair sub-pixel P1 (FIG.
  • the drain electrode D) and the pixel electrode 21 of the sub-pixel 20 are coupled to the common electrode 22 of the sub-pixel 20.
  • S312 includes:
  • S313 includes:
  • the first end (for example, the source S) of the transistor TFT of the first repair sub-pixel P1 and the second repair sub-pixel P2 is disconnected from the data line 40 coupled thereto, so as to avoid the first repair sub
  • the pixel electrodes 21 of the pixel P1 and the second repair sub-pixel P2 are still loaded with the data line signal on the data line 40, which affects the normal repair of the gate line 30.
  • the first end of the transistor TFT is the source S, and the second end is the drain D.
  • the first end may be the drain D, and the second end may be the source S.
  • the former one is taken as an example for description, that is, the first end is the source electrode S, and the second end is the drain electrode D.
  • the process of forming the independent line segment 50a may include the following steps:
  • the first adjacent sub-pixel P1 ′ is the previous sub-pixel 20 immediately adjacent to the first repair sub-pixel P1
  • the second adjacent sub-pixel P2 ′ is The next sub-pixel 20 immediately adjacent to the second repair sub-pixel P2.
  • an independent line segment 50a is formed that is electrically connected to the common electrode 22 in the first repair sub-pixel P1 and the second repair sub-pixel P2 and is cut off from the selected common electrode line 50 '.
  • the selected common electrode line 50 ′ on both sides of the repair unit composed of the first repair sub-pixel P1 and the second repair sub-pixel P2 is cut to form an independent line segment 50 a, which is electrically connected to the common electrode 22 of the other sub-pixels 20 Isolate.
  • an exemplary method for repairing a disconnection includes the following steps:
  • S1 Determine the disconnection position of the gate line 30 (marked as “Open” in FIG. 7, indicating disconnection).
  • S2 includes the following S221 to S222.
  • S221 Determine the two connecting elements L that are closest to the disconnection position and are on both sides of the disconnection position. If the two connection elements L are two transistor TFTs, then from the sub-pixels 20 coupled to the gate line 30 where the disconnection position is located, the sub-pixel 20 to which each of the two transistors TFT belongs is selected as the first repair sub-pixel P1 and the second repair sub-pixel P2. The first repair sub-pixel P1 is coupled to the front F1 at the disconnected position, and the second repair sub-pixel P2 is coupled to the rear F2 at the disconnected position.
  • S222 Determine that one common electrode line 50 coupled to the common electrode 22 of each of the first repair sub-pixel P1 and the second repair sub-pixel P2 (e.g., having an overlapping area) is the selected common electrode line 50 '.
  • S3 includes the following S321 to S325.
  • S321 Pass the front part F1 at the broken position through the second end of the transistor TFT in the first repair sub-pixel P1 (for example, the drain D), and the pixel of the sub-pixel 20 (ie, the first repair sub-pixel P1)
  • the electrode 21 is coupled to the common electrode 22 of the sub-pixel 20.
  • S322 Pass the rear part F2 at the broken position through the second end of the transistor TFT in the second repair sub-pixel P2 (for example, the drain D), and the pixel of the sub-pixel 20 (ie, the second repair sub-pixel P2)
  • the electrode 21 is coupled to the common electrode 22 of the sub-pixel 20.
  • S323 Disconnect the transistor TFT of the first repair sub-pixel P1 and the second repair sub-pixel P2 and the data line 40 to which they are coupled. In this way, it can be avoided that the pixel electrodes 21 of the first repair sub-pixel P1 and the second repair sub-pixel P2 are still loaded with the data line signal on the data line 40, which affects the normal repair of the gate line 30.
  • S324 The selected common electrode line 50 'is disconnected from the other common electrodes 22 except for the common electrode 22 in the first repair sub-pixel P1 and the second repair sub-pixel P2 to form the selected common electrode line 50' Cut out the independent line segment 50a.
  • the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 is disconnected from the other common electrodes 22 except the common electrode 22 in the second repair sub-pixel P2; it will be disconnected from the second repair sub
  • the second compensation structure C2 to which the common electrode 22 of the pixel P2 is coupled is disconnected from other common electrodes except the common electrode 22 in the second repair sub-pixel P2. For example, to cut off the first compensation structure C1 and cut off the second compensation structure C2, so as to avoid that the common electrode 22 in the second repair sub-pixel P2 is still loaded with the common voltage signal on the common electrode line 50, affecting the gate line 30 Normal repair.
  • the dark dots formed are only the first repair sub-pixel P1 and the second repair sub-pixel P2, which has less impact on the entire display panel and the repair effect is better .
  • S321 includes:
  • the pixel electrode 21 is welded to the common electrode 22 of the sub-pixel (ie, the first repair sub-pixel P1), so that the front portion F1 at the broken position passes through the second end of the transistor TFT in the first repair sub-pixel P1 (FIG. In FIG. 7, the drain electrode D) and the pixel electrode 21 of the sub-pixel 20 are coupled to the common electrode 22 of the sub-pixel 20.
  • S322 includes:
  • S323 includes:
  • the first end (for example, the source S) of the transistor TFT of each of the first repair sub-pixel P1 and the second repair sub-pixel P2 is disconnected from the data line 40 coupled thereto, so as to avoid the first repair sub
  • the pixel electrodes 21 of the pixel P1 and the second repair sub-pixel P2 are still loaded with the data line signal on the data line 40, which affects the normal repair of the gate line 30.
  • the source S of the transistor TFT of each of the first repair sub-pixel P1 and the second repair sub-pixel P2 is cut off.
  • the process of forming the independent line segment 50a may include the following steps:
  • the first adjacent sub-pixel P1 ′ is the previous sub-pixel 20 immediately adjacent to the first repair sub-pixel P1
  • the second adjacent sub-pixel P2 ′ is The next sub-pixel 20 immediately adjacent to the second repair sub-pixel P2.
  • an independent line segment 50a is formed that is electrically connected to the common electrode 22 in the first repair sub-pixel P1 and the second repair sub-pixel P2 and is cut off from the selected common electrode line 50 '.
  • the selected common electrode line 50 ′ on both sides of the repair unit composed of the first repair sub-pixel P1 and the second repair sub-pixel P2 is cut to form an independent line segment 50 a, which is electrically connected to the common electrode 22 of the other sub-pixels 20 Isolate.
  • the way of disconnecting the first compensation structure C1 to which the common electrode 22 of the second repair sub-pixel P2 and the common electrode 22 other than the common electrode 22 of the second repair sub-pixel P2 includes:
  • the first compensation structure C1 a portion between the two common electrodes 22 to which the first compensation structure C1 is coupled is cut off.
  • the way of disconnecting the second compensation structure C2 coupled to the common electrode 22 of the second repair sub-pixel P2 and the common electrode 22 other than the common electrode 22 of the second repair sub-pixel P2 includes:
  • the method includes the following steps:
  • S1 Determine the disconnection position of the gate line 30 (marked as “Open” in FIG. 8, indicating disconnection).
  • S2 includes the following S231 to S232.
  • S231 Determine the two connecting elements L that are closest to the disconnection position and are on both sides of the disconnection position. If the two connection elements L are two transistor TFTs, then from the sub-pixels 20 coupled to the gate line 30 where the disconnection position is located, the sub-pixel 20 to which each of the two transistors TFT belongs is selected as the first repair sub-pixel P1 and the second repair sub-pixel P2. The first repair sub-pixel P1 is coupled to the front F1 at the disconnected position, and the second repair sub-pixel P2 is coupled to the rear F2 at the disconnected position.
  • S232 Determine that one common electrode line 50 coupled to the common electrode 22 of each of the first repair sub-pixel P1 and the second repair sub-pixel P2 (e.g., having an overlapping area) is the selected common electrode line 50 '.
  • S3 includes the following S331 to S335.
  • S331 Pass the front part F1 at the broken position through the second end (for example, the drain D) of the transistor TFT in the first repair subpixel P1, and the pixel of the subpixel 20 (ie, the first repair subpixel P1)
  • the electrode 21 is coupled to the common electrode 22 of the sub-pixel 20.
  • the rear part F2 at the fracture position is coupled to the common electrode 22 in the second repair sub-pixel P2 through the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2.
  • S333 Disconnect the transistor TFT of the first repair sub-pixel P1 and the second repair sub-pixel P2 and the data line 40 to which they are coupled. In this way, it can be avoided that the pixel electrodes 21 of the first repair sub-pixel P1 and the second repair sub-pixel P2 are still loaded with the data line signal on the data line 40, which affects the normal repair of the gate line 30.
  • S334 The selected common electrode line 50 'is disconnected from the other common electrodes 22 except for the common electrode 22 in the first repair sub-pixel P1 and the second repair sub-pixel P2 to form the selected common electrode line 50' Cut out the independent line segment 50a.
  • the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 is disconnected from the other common electrodes 22 except the common electrode 22 of the second repair sub-pixel P2; it will be disconnected from the second repair sub-pixel
  • the second compensation structure C2 to which the common electrode 22 of P2 is coupled is disconnected from other common electrodes 22 except for the common electrode 22 of the second repair sub-pixel P2. For example, to cut off the first compensation structure C1 and cut off the second compensation structure C2, so as to avoid that the common electrode 22 of the second repair sub-pixel P2 is still loaded with the common voltage signal on the common electrode line 50, affecting the gate line 30 Normally repaired.
  • the pixel electrode 21 of the first repair sub-pixel P1 In this way, through the second end of the transistor TFT of the first repair sub-pixel P1 (indicated as drain D in FIG. 8), the pixel electrode 21 of the first repair sub-pixel P1, and the common electrode of the first repair sub-pixel P1 22.
  • the independent line segment 50a, the common electrode 22 of the second repair sub-pixel P2, and the communication path formed by the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2, bypassing the disconnection position, signal transmission The method can be as shown by the dotted arrow in FIG. 8.
  • the dark dots formed are only the first repair sub-pixel P1 and the second repair sub-pixel P2, which has less impact on the entire display panel and the repair effect is better .
  • the difference between the two repair methods illustrated in FIG. 7 and FIG. 8 above is that in the communication path illustrated in FIG. 7, the communication path is via the first repair sub-pixel P1 and the second repair sub-pixel P2.
  • the respective transistors TFT, their respective pixel electrodes 21, their respective common electrodes 22, and the independent line segments 50a cut from the selected common electrode line 50 'bypass the broken position, and the compensation structure 60 is not used.
  • the communication path is via the transistor TFT of the first repair sub-pixel P1, its pixel electrode 21, its common electrode 22, the common electrode 22 of the second repair sub-pixel P2, and an independent line segment 50a
  • the first compensation structure C1 to which the common electrode 22 of the second repair sub-pixel P2 is coupled, bypassing the open position, does not use the transistor TFT and the pixel electrode 21 in the second repair sub-pixel P2.
  • the open position on the gate line 30 is the second type described above, that is, the open position is between the two transistors TFT, and the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure 60, the above figure may be selected Any one of the repair methods shown in Figure 7 or Figure 8.
  • S331 includes:
  • the front part F1 at the fracture position and the second end of the transistor TFT of the first repair sub-pixel P1 are soldered on, and the first repair sub-pixel P1
  • the pixel electrode 21 is welded to the common electrode 22 of the sub-pixel (ie, the first repair sub-pixel P1), so that the front portion F1 at the broken position passes through the second end of the transistor TFT of the first repair sub-pixel P1 (FIG. 7 Is shown as drain D), and the pixel electrode 21 of the sub-pixel 20 is coupled to the common electrode 22 of the sub-pixel 20.
  • S332 includes:
  • the first compensation structure C1 coupling the rear portion F2 at the rupture position and the common electrode 22 of the second repair sub-pixel P2 is soldered on.
  • first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 is electrically connected to the common electrode 22 of the second repair sub-pixel P2, when the rear portion F2 at the fracture position is connected to the first compensation When the structure C1 is turned on by welding, the rear part F2 at the fracture position is electrically connected to the common electrode 22 in the second repair sub-pixel P2.
  • welding the rear portion F2 at the fracture position to the first compensation structure C1 can be performed by welding the rear portion F2 at the fracture position to the first compensation structure C1 Welding is conducted between the parts with overlapping areas.
  • the common electrode 22 in the second repair sub-pixel P2 is loaded instead of the common voltage signal that should be loaded when the gate line 30 is not broken. Therefore, it is difficult for the second repair sub-pixel P2 to continue to display normally.
  • the electric field generated between the pixel electrode 21 in the sub-pixel and the common electrode 22 loaded with the gate line signal in the sub-pixel affects the normal deflection of the liquid crystal molecules in the vicinity of the second repair sub-pixel P2.
  • the transistor TFT is disconnected from the pixel electrode 21 in this sub-pixel.
  • the manner of disconnecting the transistor TFT of the first repair sub-pixel P1 and the data line 40 coupled thereto includes, but not limited to, the following manner:
  • the data line 40 to which the first end (for example, the source S) of the transistor TFT of the first repair sub-pixel P1 is coupled is disconnected. For example, it is to cut off the first end (for example, the source S) of the transistor TFT of the first repair sub-pixel P1.
  • the manners of disconnecting the transistor TFT of the second repair sub-pixel P2 and the data line 40 coupled thereto include, but are not limited to the following three ways:
  • the data line 40 electrically connected to the first end (for example, the source S) of the transistor TFT of the second repair sub-pixel P2. For example, it is to cut off the first end (for example, the source S) of the transistor TFT of the second repair sub-pixel P2.
  • the second electrode (for example, the drain D) of the transistor TFT in the second repair sub-pixel P2 is electrically disconnected from the pixel electrode 21 connected to the second end (for example, the drain D) of the transistor TFT.
  • the drain electrode D is electrically disconnected from the pixel electrode 40, for example, the first terminal (for example, the source S) and the second terminal (for example, the drain D) of the transistor TFT of the second repair sub-pixel P2 are cut off.
  • FIG. 8 only illustrates a way of disconnecting the “first end of the transistor TFT”.
  • the method of “the second end of the transistor TFT” please refer to FIG. 8 for understanding. No longer.
  • the process of forming the independent line segment 50a may include the following steps:
  • the first adjacent sub-pixel P1 ′ is the previous sub-pixel 20 immediately adjacent to the first repair sub-pixel P1
  • the second adjacent sub-pixel P2 ′ is The next sub-pixel 20 immediately adjacent to the second repair sub-pixel P2.
  • an independent line segment 50a is formed that is in electrical communication with the common electrode 22 of the first repair sub-pixel P1 and the second repair sub-pixel P2, and is cut off from the selected common electrode line 50 '.
  • the selected common electrode line 50 ′ on both sides of the repair unit composed of the first repair sub-pixel P1 and the second repair sub-pixel P2 is cut to form an electrical separation from other parts in the selected common electrode line 50 ′ Separate line segment 50a, so as to be electrically isolated from the common electrodes 22 of other sub-pixels 20.
  • the way of disconnecting the first compensation structure C1 to which the common electrode 22 of the second repair sub-pixel P2 and the common electrode 22 other than the common electrode 22 of the second repair sub-pixel P2 includes:
  • the first connection part is a part of the first compensation structure C1 coupled with the rear part F2 at the breaking position.
  • the first connection portion is the welding connection between the first compensation structure C1 and the rear portion F2 at the breaking position Welding part.
  • the second connection portion is a portion of the first compensation structure C1 coupled with other common electrodes 22 except the common electrode 22 of the second repair sub-pixel P2, for example, the second connection portion is the first compensation In the structure C1, the common electrode 22 other than the common electrode 22 of the second repair sub-pixel P2 has an overlapping portion of the overlapping area.
  • the way of disconnecting the second compensation structure C2 coupled to the common electrode 22 of the second repair sub-pixel P2 and the common electrode 22 other than the common electrode 22 of the second repair sub-pixel P2 includes:
  • an example of a method for repairing an open circuit is provided for the third type of open circuit.
  • the method includes the following steps:
  • Step S1 Determine the disconnection position of the gate line 30 (marked as “Open” in FIG. 9, indicating disconnection).
  • S2 includes the following S241 to S242.
  • S241 Determine the two connecting elements L that are closest to the disconnection position and are on both sides of the disconnection position. If the two connecting elements L, one of which is a transistor TFT and the other is a compensation structure 60, and the sub-pixel 20 to which the transistor TFT belongs and the sub-pixel 20 to which the common electrode 22 to which the compensation structure 60 is coupled are the same For the sub-pixel, the sub-pixel 20 to which the transistor TFT belongs is selected as the first repair sub-pixel P1 from each sub-pixel 20 coupled to the gate line 30 where the disconnection position is located. Wherein, the first repair sub-pixel P1 is coupled to the front part F1 at the disconnected position.
  • S242 Determine that one common electrode line 50 coupled to the common electrode 22 of the first repair sub-pixel P1 (e.g., having an overlapping area) is the selected common electrode line 50 '.
  • S3 includes the following S341-S345:
  • S341 Pass the front part F1 at the broken position through the second end of the transistor TFT in the first repair sub-pixel P1 (for example, the drain D), and the pixel of the sub-pixel 20 (ie, the first repair sub-pixel P1)
  • the electrode 21 is coupled to the common electrode 22 of the sub-pixel 20;
  • the rear part F2 at the fracture position is coupled to the common electrode 22 in the first repair sub-pixel P1 through the first compensation structure C1 coupled to the common electrode 22 of the first repair sub-pixel P1.
  • S343 Disconnect the transistor TFT of the first repair sub-pixel P1 and the data line 40 coupled thereto. In this way, it can be avoided that the pixel electrode 21 of the first repair sub-pixel P1 is still loaded with the data line signal on the data line 40, which affects the normal repair of the gate line 30.
  • S344 The selected common electrode line 50 'is disconnected from the other common electrodes 22 except the common electrode 22 in the first repair sub-pixel P1 to form an independent line segment 50a cut from the selected common electrode line 50'.
  • S345 Disconnect the first compensation structure C1 to which the common electrode 22 of the first repair sub-pixel P1 is connected to other common electrodes 22 except the common electrode 22 of the first repair sub-pixel P1; disconnect the first repair sub-pixel P1
  • the second compensation structure C2 to which the common electrode 22 is coupled is disconnected from the other common electrodes 22 except the common electrode 22 of the first repair sub-pixel P1. For example, to cut off the first compensation structure C1 and cut off the second compensation structure C2, so as to avoid that the common electrode 22 of the first repair sub-pixel P1 is still loaded with the common voltage signal on the common electrode line 50, affecting the gate line 30 Normally repaired.
  • the second terminal of the transistor TFT of the first repair sub-pixel P1 (denoted as drain D in FIG. 8), the pixel electrode 21 in the first repair sub-pixel P1, and the common of the first repair sub-pixel P1
  • the communication path formed by the electrode 22, the independent line segment 50a , and the first compensation structure C1 coupled to the common electrode 22 of the first repair sub-pixel P1 bypasses the open position, and the signal transmission method can be as shown by the dotted arrow in FIG. 9 .
  • the dark dots formed are only the first repair sub-pixel P1, which has less impact on the entire display panel and a better repair effect.
  • S341 includes:
  • the front part F1 at the fracture position and the second end of the transistor TFT of the first repair sub-pixel P1 are soldered on, and the first repair sub-pixel P1
  • the pixel electrode 21 is welded to the common electrode 22 of the sub-pixel (ie, the first repair sub-pixel P1), so that the front portion F1 at the broken position passes through the second end of the transistor TFT of the first repair sub-pixel P1 (FIG. 9 Is shown as drain D), and the pixel electrode 21 of the sub-pixel 20 is coupled to the common electrode 22 of the sub-pixel 20.
  • S342 includes:
  • the first compensation structure C1 that couples the rear portion F2 at the fracture position to the common electrode 22 of the first repair sub-pixel P1 is conductively connected.
  • the first compensation structure C1 coupled to the common electrode 22 of the first repair sub-pixel P1 is electrically connected to the common electrode 22 in the first repair sub-pixel P1, when the rear portion F2 at the fracture position is connected to the first When the selected compensation structure C1 is turned on by welding, the rear part F2 at the fracture position is electrically connected to the common electrode 22 in the first repair sub-pixel P1.
  • S343 includes:
  • the first end (for example, the source S) of the transistor TFT of the first repair sub-pixel P1 is disconnected from the data line 40 coupled thereto. Therefore, it is avoided that the pixel electrode 21 of the first repair sub-pixel P1 is still loaded with the data line signal on the data line 40, which affects the normal repair of the gate line 30. For example, it is to cut off the first end (for example, the source S) of the transistor TFT of the first repair sub-pixel P1.
  • the process of forming the independent line segment 50a may include the following steps:
  • the first adjacent sub-pixel P1 ′ is the previous sub-pixel 20 immediately adjacent to the first repair sub-pixel P1
  • the second adjacent sub-pixel P1 ′′ is The next sub-pixel 20 immediately adjacent to the first repair sub-pixel P1.
  • the selected common electrode lines 50 'on both sides of the first repair sub-pixel P1 are cut to form an independent line segment 50a, so as to be electrically isolated from the common electrodes 22 of other sub-pixels 20.
  • the manner of disconnecting the first compensation structure C1 to which the common electrode 22 of the first repair sub-pixel P1 is coupled to other common electrodes 22 except the common electrode 22 in the first repair sub-pixel P1 includes:
  • the first connection part is a part of the first compensation structure C1 coupled with the rear part F2 at the breaking position.
  • the first connection portion is the welding connection between the first compensation structure C1 and the rear portion F2 at the breaking position Welding part.
  • the second connection portion is a portion of the first compensation structure C1 coupled with other common electrodes 22 except the common electrode 22 of the first repair sub-pixel P1.
  • the second connection portion is the first compensation In the structure C1, the common electrode 22 other than the common electrode 22 of the first repair sub-pixel P1 has an overlapping portion of the overlapping area.
  • the manner of disconnecting the second compensation structure C2 coupled to the common electrode 22 of the first repair sub-pixel P1 and the common electrode 22 other than the common electrode 22 of the first repair sub-pixel P1 includes:
  • an exemplary disconnection repair method is provided, which is similar to the foregoing disconnection repair method provided for the above second disconnection position shown in FIG. 7, both The communication paths are all via the transistor TFT of the first repair sub-pixel P1 and the second repair sub-pixel P2, the pixel electrode 21 of the first repair sub-pixel P1 and the second repair sub-pixel P2, and the first repair sub-pixel P1
  • the common electrode 22 of each of the second repair sub-pixel P2 and the independent line segment 50a cut from the selected common electrode line 50 'bypass the open position.
  • the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure 60, and the common electrode 22 of the first repair sub-pixel P1 is not connected to the compensation structure. 60coupled.
  • the common electrode 22 of the first repair sub-pixel P1 is coupled to the compensation structure 60, and the common electrode 22 of the second repair sub-pixel P2 is not compensated. Structure 60 is coupled.
  • the broken circuit repair method provided for the fourth broken circuit position shown in FIG. 10 is equivalent to the first repaired sub-pixel P1 of the broken circuit repair method for the second broken circuit position shown in FIG. 7.
  • the position is exchanged with the second repair sub-pixel P2, that is, the original first repair sub-pixel P1 is coupled to the front portion F1 at the open position in the open-circuit repair method provided for the second open-circuit position shown in FIG. 7 ,
  • the second repair sub-pixel P2 is coupled to the rear portion F2 at the disconnected position, replaced with the second repair sub-pixel P2 coupled to the front portion F1 at the disconnected position, and the first repair sub-pixel P1 is coupled to the rear portion at the disconnected position F2 is coupled.
  • the disconnection repair method provided for the above fourth disconnection position shown in FIG. 10 wherein the processing steps related to the first repair sub-pixel P1 can be provided for the second disconnection position shown in FIG. 7
  • the specific steps of the broken circuit repair method provided for the fourth broken circuit position shown in FIG. 10 will not be repeated in text.
  • FIG. 11 for the above-mentioned fourth disconnection position, another example of the disconnection repair method is provided, which is similar to the foregoing disconnection repair method provided for the above-mentioned second disconnection position shown in FIG. 8.
  • the communication paths of the two are via the transistor TFT in a repair sub-pixel, the pixel electrode 21 of the repair sub-pixel, the common electrode 22 of the repair sub-pixel, the independent line segment 50a, the common electrode 22 of the other repair sub-pixel, and
  • the first compensation structure C1 coupled to the common electrode 22 of another repair sub-pixel bypasses the open position.
  • the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure 60, and the common electrode 22 of the first repair sub-pixel P1 is not connected to the compensation structure. 60coupled.
  • the common electrode 22 of the first repair sub-pixel P1 is coupled to the compensation structure 60, and the common electrode 22 of the second repair sub-pixel P2 is not compensated. Structure 60 is coupled.
  • the disconnection repair method provided for the fourth disconnection position shown in FIG. 11 is equivalent to the first repair subpixel P1 of the disconnection repair method provided for the second disconnection position shown in FIG. 8
  • the position is exchanged with the second repair sub-pixel P2, that is, the original first repair sub-pixel P1 in the disconnection repair method provided for the second disconnection position shown in FIG. 8 is coupled to the front part F1 at the disconnection position ,
  • the second repair sub-pixel P2 is coupled to the rear portion F2 at the disconnected position, replaced with the second repair sub-pixel P2 coupled to the front portion F1 at the disconnected position, and the first repair sub-pixel P1 is coupled to the rear portion at the disconnected position F2 is coupled.
  • the processing steps related to the second repair sub-pixel P2 in the disconnection repair method of FIG. For the processing steps related to the second repair sub-pixel P2, the processing steps related to the first repair sub-pixel P1 in the disconnection repair method provided for the foregoing second disconnection position shown in FIG. 8 can be used.
  • the corresponding circuit breaking repair method provided for the above second circuit breaking position shown in FIG. 8 can be followed step.
  • the specific steps of the broken circuit repair method provided for the fourth broken circuit position shown in FIG. 11 will not be repeated in text.
  • an exemplary disconnection repair method is provided, which is similar to the above-mentioned second disconnection location repair method shown in FIG. 7, both
  • the communication paths are all via the transistor TFT of the first repair sub-pixel P1 and the second repair sub-pixel P2, the pixel electrode 21 of the first repair sub-pixel P1 and the second repair sub-pixel P2, and the first repair sub-pixel P1
  • the common electrode 22 of each of the second repair sub-pixel P2 and the independent line segment 50a cut from the selected common electrode line 50 'bypass the open position.
  • the circuit break repair method provided for the above-mentioned fifth circuit break position shown in FIG. 12 differs from the circuit break repair method provided for the above-mentioned second circuit break position shown in FIG. 7 only in:
  • the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure 60, and the common electrode 22 of the first repair sub-pixel P1 is not connected to the compensation structure. 60coupled.
  • the common electrode 22 of the first repair sub-pixel P1 and the common electrode 22 of the second repair sub-pixel P2 are both coupled to the compensation structure 60.
  • the broken circuit repair method provided for the fourth broken circuit position shown in FIG. 12 is equivalent to the broken circuit repair method provided for the second broken circuit position shown in FIG. 7 on the original basis,
  • a compensation structure 60 coupled to the common electrode 22 of the first repair sub-pixel P1 is added, that is, the circuit repair method provided for the above second circuit-breaking location shown in FIG. 7, the second repair sub-pixel P2 remains unchanged,
  • the first repair sub-pixel P1 adds a compensation structure 60 coupled thereto.
  • the disconnection repair method provided for the fourth disconnection position shown in FIG. 12 above wherein, for the processing steps related to the first repair sub-pixel P1, except for following the second disconnection position shown in FIG. 7
  • it also includes processing for the compensation structure 60 coupled to the common electrode 22 of the first repair sub-pixel P1.
  • the circuit repair method provided for the above-mentioned second circuit break position shown in FIG. 7 can be used in connection with the second repair sub The processing method of the compensation structure 60 to which the common electrode 22 of the pixel P2 is coupled.
  • FIG. 13 for the above-mentioned fifth disconnection location, another example of the disconnection repair method is provided, which is similar to the above-mentioned second disconnection location repair method shown in FIG. 8.
  • the communication paths of the two are via the transistor TFT of the first repair subpixel P1, the pixel electrode 21 of the first repair subpixel P1, the common electrode 22 of the first repair subpixel P1, the independent line segment 50a, and the second repair subpixel P2
  • the common electrode 22 and the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 bypass the open position.
  • the circuit breaking repair method provided for the fifth circuit breaking position shown in FIG. 13 is different from the circuit breaking repair method provided for the second circuit breaking position shown in FIG. 8 above only in:
  • the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure 60, and the common electrode 22 of the first repair sub-pixel P1 is not connected to the compensation structure. 60coupled.
  • the common electrode 22 of the first repair sub-pixel P1 and the common electrode 22 of the second repair sub-pixel P2 are both coupled to the compensation structure 60.
  • the broken circuit repair method provided for the fifth broken circuit position shown in FIG. 13 is equivalent to the broken circuit repair method provided for the second broken circuit position shown in FIG. 8 on the original basis,
  • a compensation structure 60 coupled to the common electrode 22 of the first repair sub-pixel P1 is added, that is, the disconnection repair method shown in FIG. 8 provided for the above second disconnection position, the second repair sub-pixel P2 remains unchanged,
  • the first repair sub-pixel P1 adds a compensation structure 60 coupled thereto.
  • it also includes processing for the compensation structure 60 coupled to the common electrode 22 of the first repair sub-pixel P1.
  • the circuit repair method provided for the above-mentioned second circuit break position shown in FIG. 7 can be used in connection with the second repair sub The processing method of the compensation structure 60 to which the common electrode 22 of the pixel P2 is coupled.
  • another exemplary disconnection repair method is provided, which is similar to the above-mentioned second disconnection location repair method shown in FIG. 8, two The communication paths of the two are via the transistor TFT in a repair sub-pixel, the pixel electrode 21 of the repair sub-pixel, the common electrode 22 of the repair sub-pixel, the independent line segment 50a, the common electrode 22 of the other repair sub-pixel, and The first compensation structure C1 coupled to the common electrode 22 of another repair sub-pixel bypasses the open position.
  • the circuit breaking repair method provided for the fifth circuit breaking position shown in FIG. 14 is different from the circuit breaking repair method provided for the second circuit breaking position shown in FIG. 8 above only in:
  • connection paths of the disconnection repair method provided for the second disconnection position shown in FIG. 8 are all via the transistor TFT of the first repair sub-pixel P1, the pixel electrode 21 of the first repair sub-pixel P1, and the first repair sub-pixel
  • the common electrode 22 of P1, the independent line segment 50a, the common electrode 22 of the second repair sub-pixel P2 and the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 bypass the open position.
  • the communication path shown in FIG. 14 for the disconnection repair method provided for the fifth disconnection position is the first compensation structure C1 and the first repair subpixel P1 coupled to the common electrode 22 of the first repair subpixel P1
  • the common electrode 22, the independent line segment 50a, the common electrode 22 of the second repair sub-pixel P2, the pixel electrode 21 of the second repair sub-pixel P2, and the transistor TFT of the second repair sub-pixel P1 bypass the open position.
  • the disconnection repair method provided for the fifth disconnection position shown in FIG. 14 is equivalent to the first repair subpixel P1 of the disconnection repair method provided for the second disconnection position shown in FIG. 8.
  • the position is exchanged with the second repair sub-pixel P2, and on the basis of the original, a compensation structure 60 coupled to the common electrode 22 of the first repair sub-pixel P1 is added. That is, it is equivalent to coupling the original “first repair sub-pixel P1 with the front part F1 at the open position in the open-circuit repair method provided for the second open-circuit position shown in FIG.
  • the disconnection repair method provided for the above-mentioned fifth disconnection position shown in FIG. 14, wherein, for the processing steps related to the first repair sub-pixel P1, the above-mentioned second disconnection position shown in FIG. 8 can be used The processing steps related to the second repair sub-pixel P2 in the provided disconnection repair method.
  • the processing steps related to the second repair sub-pixel P2 in addition to following the processing steps related to the first complex sub-pixel P1 in the disconnection repair method provided for the above second disconnection position shown in FIG. 8, it also includes For the processing of the compensation structure 60 coupled to the common electrode 22 of the second repair sub-pixel P2.
  • the corresponding circuit breaking repair method provided for the above second circuit breaking position shown in FIG. 8 can be followed step.
  • the specific steps of the disconnection repair method provided in FIG. 14 for the above fourth disconnection position will not be repeated in text.
  • S1 Determine the position of the gate line 30 to be disconnected (marked as "Open” in FIG. 15 to indicate disconnection).
  • S2 includes the following S251 to S252.
  • S251 Determine the two connecting elements L that are closest to the disconnection position and are on both sides of the disconnection position. If the two connecting elements L, one of which is a transistor TFT and the other is a compensation structure 60, and the sub-pixel 20 to which the transistor TFT belongs and the sub-pixel 20 to which the common electrode 22 to which the compensation structure 60 is coupled are different For the sub-pixel, the sub-pixel 20 to which the common electrode 22 coupled to the compensation structure 60 belongs is selected as the first repair sub-pixel P1 from each sub-pixel 20 coupled to the gate line 30 where the disconnection position is located, and the transistor is selected The sub-pixel 20 to which the TFT belongs serves as the second repair sub-pixel P2. The first repair sub-pixel P1 is coupled to the front F1 at the disconnected position, and the second repair sub-pixel P2 is coupled to the rear F2 at the disconnected position.
  • S252 Determine that one common electrode line 50 coupled to the common electrode 22 of each of the first repair subpixel P1 and the second repair subpixel P2 (e.g., having an overlapping area) is the selected common electrode line 50 '.
  • S3 includes the following S351 to S355.
  • the front portion F1 at the fracture position is coupled to the common electrode 22 of the first repair sub-pixel P1 through the first compensation structure C1 coupled to the common electrode 22 of the first repair sub-pixel P1.
  • the rear part F2 at the fracture position is coupled to the common electrode 22 of the second repair sub-pixel P2 through the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2.
  • S353 Disconnect the transistors TFT of the first repair sub-pixel P1 and the second repair sub-pixel P2 and the data line 40 to which they are coupled. In this way, it can be avoided that the pixel electrodes 21 of the first repair sub-pixel P1 and the second repair sub-pixel P2 are still loaded with the data line signal on the data line 40, which affects the normal repair of the gate line 30.
  • S354 Disconnect the selected common electrode line 50 'from the other common electrodes 22 except for the common electrodes 22 of the first repair sub-pixel P1 and the second repair sub-pixel P2 to form a cut from the selected common electrode line 50' Out of the independent line segment 50a.
  • S355 disconnect the first compensation structure C1 and the second compensation structure C2 coupled to the common electrode 22 of the first repair sub-pixel P1 and other common electrodes except the common electrode 22 of the first repair sub-pixel P1;
  • the first compensation structure C1 and the second compensation structure C2 coupled to the common electrode 22 in the second repair sub-pixel P2 are disconnected from other common electrodes except the common electrode 22 in the second repair sub-pixel P2.
  • the common voltage signal affects the normal repair of the gate line 30.
  • the first compensation structure C1 coupled to the common electrode 22 of the first repair subpixel P1, the common electrode 22 of the first repair subpixel P1, the independent line segment 50a, and the common electrode of the second repair subpixel P2 22.
  • the communication path formed by the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 bypasses the open position, and the signal transmission method may be as shown by the dotted arrow in FIG. 15.
  • the dark dots formed are only the first repair sub-pixel P1 and the second repair sub-pixel P2, which has less impact on the entire display panel and the repair effect is better .
  • the open position on the gate line 30 is the fifth type described above, that is, the open position is between the transistor TFT and the compensation structure 60, and the sub-pixel to which the transistor TFT belongs and the sub-electrode to which the common electrode coupled to the compensation structure belongs.
  • any one of the repair methods illustrated in FIG. 12 to FIG. 15 may be selected.
  • step S351 includes:
  • the front portion F1 at the fracture position and the first compensation structure C1 coupled to the common electrode 22 of the first repair sub-pixel P1 are soldered on.
  • step S352 includes:
  • the first compensation structure C1 coupled to the common electrode 22 of the first repair sub-pixel P1 is electrically connected to the common electrode 22 of the first repair sub-pixel P1, when the front portion F1 at the break position is connected to the first When the compensation structure C1 is turned on by welding, the front portion F1 at the fracture position is electrically connected to the common electrode 22 in the first repair sub-pixel P1. Since the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 is electrically connected to the common electrode 22 of the second repair sub-pixel P2, when the rear portion F2 at the fracture position is connected to the first When the compensation structure C1 is turned on by welding, the rear part F2 at the fracture position is electrically connected to the common electrode 22 in the second repair sub-pixel P2.
  • welding the front portion F1 at the fracture position to the first compensation structure C1 can be performed by welding the front portion F1 at the fracture position to the first compensation structure C1
  • Welding is conducted between the parts with overlapping areas.
  • Welding conduction between the rear part F2 at the breaking position and the first compensation structure C1 may be welding conduction through a part having an overlapping area between the rear part F2 at the breaking position and the first compensation structure C1.
  • the common electrode 22 of the first repair sub-pixel P1 and the first The gate electrode signal is loaded on the common electrode 22 of the second repair sub-pixel P2, instead of the common voltage signal that should be loaded when the gate line 30 is not disconnected.
  • the first repair sub-pixel P1 and the second repair sub-pixel The pixel P2 is difficult to continue to display normally, in order to avoid the pixel electrode 21 of the first repair sub-pixel P1 and the pixel electrode 21 of the second repair sub-pixel P2 and the common electrode 22 loaded with the gate line signal in the sub-pixel
  • the electric field affects the normal deflection of liquid crystal molecules in the vicinity of the first repair subpixel P1 and the second repair subpixel P2. Therefore, the transistor TFT of the first repair subpixel P1 needs to be disconnected from the pixel electrode 21 in the subpixel, and the The transistor TFT in the second repair sub-pixel P2 is disconnected from the pixel electrode 21 in the sub-pixel.
  • the manners of disconnecting the transistor TFT of the first repair sub-pixel P1 and the data line 40 coupled thereto include but are not limited to the following three ways:
  • the first line (for example, the source S) of the transistor TFT of the first repair sub-pixel P1 is disconnected from the data line 40 coupled thereto. For example, it is to cut off the first end (for example, the source S) of the transistor TFT of the first repair sub-pixel P1.
  • the second end (for example, the drain D) of the transistor TFT of the first repair sub-pixel P1 is electrically disconnected from the pixel electrode 40, for example, the second end of the transistor TFT of the first repair sub-pixel P1 (for example Is the drain D).
  • the first line (for example, the source S) of the transistor TFT of the first repair sub-pixel P1 is electrically disconnected from the data line 40, and the second side of the transistor TFT of the first repair sub-pixel P1 (for example, The drain electrode D) is electrically disconnected from the pixel electrode 21, for example, to cut off the first end (for example, the source S) and the second end (for example, the drain D) of the transistor TFT of the first repair sub-pixel P1.
  • the manners of disconnecting the transistor TFT of the second repair sub-pixel P2 and the data line 40 coupled thereto include, but are not limited to the following three ways:
  • the data line 40 electrically connected to the first end (for example, the source S) of the transistor TFT in the second repair sub-pixel P2. For example, it is to cut off the first end (for example, the source S) of the transistor TFT of the second repair sub-pixel P2.
  • the second electrode (for example, the drain D) of the transistor TFT in the second repair sub-pixel P2 is electrically disconnected from the pixel electrode 21 connected to the second end (for example, the drain D) of the transistor TFT.
  • FIG. 15 only illustrates a way of disconnecting the first end of the transistor TFT.
  • the process of forming the independent line segment 50a may include the following steps:
  • the first adjacent sub-pixel P1 ′ is the previous sub-pixel 20 immediately adjacent to the first repair sub-pixel P1
  • the second adjacent sub-pixel P2 ′ is The next sub-pixel 20 immediately adjacent to the second repair sub-pixel P2.
  • an independent line segment 50a is formed that is electrically connected to the common electrode 22 of the first repair sub-pixel P1 and the second repair sub-pixel P2 and is cut off from the selected common electrode line 50 '.
  • the selected common electrode line 50 ′ on both sides of the repair unit composed of the first repair sub-pixel P1 and the second repair sub-pixel P2 is cut to form an independent line segment 50 a, which is electrically connected to the common electrode 22 of the other sub-pixels 20 Isolate.
  • the manner of disconnecting the first compensation structure C1 to which the common electrode 22 of the first repair sub-pixel P1 is coupled to other common electrodes 22 except the common electrode 22 of the first repair sub-pixel P1 includes:
  • the first connection part is a part of the first compensation structure C1 coupled with the front part F1 at the breaking position.
  • the first connection portion is the first compensation structure C1 and the front portion F1 at the fracture position by welding Welding part.
  • the second connection portion is a portion of the first compensation structure C1 coupled with other common electrodes 22 except the common electrode 22 of the first repair sub-pixel P1.
  • the second connection portion is the first compensation In the structure C1, the common electrode 22 other than the common electrode 22 of the first repair sub-pixel P1 has an overlapping portion of the overlapping area.
  • the manner of disconnecting the second compensation structure C2 coupled to the common electrode 22 of the first repair sub-pixel P1 and the common electrode 22 other than the common electrode 22 of the first repair sub-pixel P1 includes:
  • the first compensation structure C1 and the second compensation structure C2 to which the common electrode 22 of the first repair sub-pixel P1 is coupled are disconnected in the same manner as other common electrodes 22 except the common electrode 22 of the second repair sub-pixel P2 Can be understood with reference to FIG. 15 and will not be repeated here in text.
  • the first compensation structure C1 coupled to the common electrode 22 in the second repair sub-pixel P2 is disconnected from other common electrodes except the common electrode 22 in the second repair sub-pixel P2
  • the method of disconnecting the first compensation structure C1 coupled to the common electrode 22 of the first repair sub-pixel P1 and other common electrodes other than the common electrode 22 of the first repair sub-pixel P1 may be used, here No longer.
  • the welding conduction method includes, but is not limited to, a laser welding method, that is, a laser with a high energy density has an overlapping area for both parties that need to be turned on The parts are welded, so that the welded parts penetrate the insulating layer between the two and are directly connected together to achieve electrical communication.
  • the laser can be welded to the corresponding structure from the side of the base substrate (ie, the laser first penetrates the base substrate).
  • the welding conductive parts include but are not limited to the numbers shown in FIGS. 6 to 15 above, and only need to ensure that the two conductive structures fused to each other can be fully fused together, in order to It is sufficient to achieve electrical connectivity.
  • the cutting method includes but is not limited to the method of using laser cutting, that is, the corresponding structure is heated by a laser with a high energy density, so that its temperature rises rapidly, and it is achieved in a very short time.
  • the boiling point of the material of the structure so that the material vaporizes to form steam, and these steams are ejected at a fast speed, and at the same time as the ejection, a cut can be formed in the corresponding structure to cut off the corresponding structure.
  • the laser can be cut off from the base substrate side (that is, the laser first penetrates the base substrate) to cut the corresponding structure.
  • sequence numbers of each step indicated by the letter “S” in the above examples of the repair methods provided by the embodiments of the present disclosure are only for convenience of description and do not strictly represent the actual sequence of steps. Those skilled in the art have the ability to adjust the sequence of steps after learning the technical solutions of the embodiments of the present disclosure, which should fall within the scope disclosed in the embodiments of the present disclosure.
  • some embodiments of the present disclosure provide a repair method for a short circuit between a gate line and a data line in an array substrate. As shown in FIGS. 16 to 20, the gate line and the data line are shorted
  • the repair method includes the following steps:
  • the broken gate line 30 is repaired.
  • the method for repairing a short circuit between a gate line and a data line is to convert the defect of a short circuit between the gate line and the data line into a fault of the gate line disconnection, and then use the repair method of the gate line disconnection to further repair
  • the types of repairs for signal lines in array substrates have been expanded.
  • the case where the gate line 30 and the data line 40 are short-circuited includes the following four types:
  • neither the common electrode 22 of the first repair sub-pixel P1 nor the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure 60.
  • the two sides of the short-circuited gate line 30 immediately adjacent to the short-circuit position are cut to form a break of the gate line 30, and the break position of the gate line 30 is located between the two transistors TFT .
  • the common electrode 22 of the first repair sub-pixel P1 is not coupled to the compensation structure 60; the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure 60.
  • the two sides of the short-circuited gate line 30 immediately adjacent to the short-circuit position are cut to form a break of the gate line 30, and the break position of the gate line 30 is located between the two transistors TFT .
  • the common electrode 22 of the first repair sub-pixel P1 is coupled to the compensation structure 60; the common electrode 22 of the second repair sub-pixel P2 is not coupled to the compensation structure 60.
  • the two sides of the short-circuited gate line 30 immediately adjacent to the short-circuit position are cut to form a break of the gate line 30.
  • the break position of the gate line 30 is located in a compensation structure 60 and a Between transistors TFT.
  • the common electrode 22 of the first repair sub-pixel P1 and the common electrode 22 of the second repair sub-pixel P2 are both coupled to the compensation structure 60.
  • the two sides of the short-circuited gate line 30 immediately adjacent to the short-circuit position are cut to form a break of the gate line 30.
  • the break position of the gate line 30 is located in a compensation structure 60 and a Between transistors TFT.
  • the intersection of the gate line 30 and the data line 40 may refer to FIG.
  • the gate line 30 is divided into a wide area and a narrow area, and the wide area and the narrow area are arranged at intervals.
  • the laser can cut the gate line 30 from the side of the base substrate (that is, the laser first penetrates the base substrate). Therefore, in order to facilitate the cutting of the short-circuit position between the gate line 30 and the data line 40, the gate line 30 may be disposed below the data line 40, that is, the gate line 30 is closer to the array substrate 01 relative to the data line 40 Substrate substrate.
  • some embodiments of the present disclosure provide a repair structure for a broken gate line in an array substrate.
  • the repair structure is subjected to any of the repair methods for broken grid lines corresponding to FIG. 6 to FIG. 15. It can be obtained by a repair method, or the repair structure can be repaired by any one of the repair methods corresponding to the short circuit between the gate line and the data line as shown in FIGS. 16 to 20.
  • the repair structure 100 includes: a broken gate line 30, one or two repair sub-pixels, and a selected common electrode line 50 '.
  • the open gate line 30 includes a front part F1 and a rear part F2 at the open position (Open).
  • One or two repair sub-pixels are, for example, a first repair sub-pixel P1 and / or a second repair sub-pixel P2, and each repair sub-pixel includes a transistor TFT, a pixel electrode 21 and a common electrode 22.
  • the selected common electrode line 50 ' is a common electrode line coupled to the common electrode 22 of each repair sub-pixel among the plurality of common electrode lines 50 of the array substrate 01.
  • the selected common electrode line 50 ' includes an independent line segment 50a coupled to the common electrode 22 of each repair sub-pixel.
  • the independent line segment 50a is a section of the common electrode line obtained by cutting the selected common electrode line 50'.
  • the independent line segment 50a is not selected.
  • the other part of the fixed common electrode line 50 ' is coupled.
  • the communication path is formed by the repair method described in any of the above embodiments, and the communication path includes at least the common electrode 22 of each repair sub-pixel and an independent line segment 50a in the selected common electrode line 50 '. Moreover, the common electrode 22 in the communication path is not coupled with other common electrodes, and each repair sub-pixel is not coupled with the data line 40.
  • the disconnection occurring on the gate line 30 can be repaired, and the gate line 30 can be removed from the row of sub-pixels to which it is coupled.
  • the other sub-pixels outside the pixel normally transmit scan signals, so that the other sub-pixels can be normally turned on or off.
  • the communication path includes at least one transistor TFT for repairing the sub-pixel and the pixel electrode 21, the common electrode 22 for each repairing sub-pixel, and the selected common electrode line 50 ′ Independent line segment 50a.
  • the repair structure 100 includes two repair sub-pixels, respectively: a first repair sub-pixel P1 coupled to the front F1 of the disconnected position, and a rear F2 coupled to the disconnected position
  • the second repair sub-pixel P2 and the common electrode 22 of the second repair sub-pixel P2 is not coupled to the compensation structure.
  • the front portion F1 at the break position is coupled to the common electrode 22 of the sub-pixel through the second end of the transistor TFT of the first repair sub-pixel P1 and the pixel electrode 21 of the sub-pixel.
  • the rear portion F2 at the fracture position is coupled to the common electrode 22 of the sub-pixel through the second end of the transistor of the second repair sub-pixel P2 and the pixel electrode 21 of the sub-pixel.
  • the second end of the transistor TFT of the first repair subpixel P1, the pixel electrode 21 of the first repair subpixel P1, the common electrode 22 of the first repair subpixel P1, the independent line segment 50a, and the second repair subpixel P2 The common electrode 22, the pixel electrode 21 of the second repair sub-pixel P2, and the second end of the transistor TFT of the second repair sub-pixel P2 form a communication path between the front portion F1 and the rear portion F2 at the open position.
  • the repair structure includes two repair sub-pixels, which are: a first repair sub-pixel P1 coupled to the front F1 of the disconnected position and a rear F2 coupled to the disconnected position
  • the second repair sub-pixel P2 and the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure.
  • the compensation structure coupled to the common electrode 22 of the second repair sub-pixel P2 includes: a first compensation structure C1 passing through the gate line 30 where the disconnection is located, and a second compensation structure C2 passing through the selected common electrode line 50 '.
  • the front portion F1 at the break position is coupled to the common electrode 22 of the sub-pixel through the second end of the transistor TFT of the first repair sub-pixel P1 and the pixel electrode 21 of the sub-pixel.
  • the rear portion F2 at the fracture position is coupled to the common electrode 22 of the sub-pixel through the second end of the transistor TFT of the second repair sub-pixel P2 and the pixel electrode 21 of the sub-pixel.
  • Neither the first compensation structure C1 nor the second compensation structure C2 is coupled to the common electrode 22 of sub-pixels other than the second repair sub-pixel P2.
  • the second end of the transistor TFT of the first repair subpixel P1, the pixel electrode 21 of the first repair subpixel P1, the common electrode 22 of the first repair subpixel P1, the independent line segment 50a, and the second repair subpixel P2 The common electrode 22, the pixel electrode 21 of the second repair sub-pixel P2, and the second end of the transistor TFT of the second repair sub-pixel P2 form a communication path between the front portion F1 and the rear portion F2 at the open position.
  • the repair structure includes two repair sub-pixels, which are: a first repair sub-pixel P1 coupled to the front F1 of the disconnected position, and a rear sub-pixel F2 coupled to the disconnected position
  • the second repair sub-pixel P2 and the common electrode 22 of the second repair sub-pixel P2 is coupled to the compensation structure.
  • the compensation structure coupled to the common electrode 22 of the second repair sub-pixel P2 includes: a first compensation structure C1 passing through the gate line 30 where the disconnection is located, and a second compensation structure 50a passing through the selected common electrode line 50 '.
  • the front portion F1 at the break position is coupled to the common electrode 22 of the sub-pixel through the second end of the transistor TFT of the first repair sub-pixel P1 and the pixel electrode 21 of the sub-pixel.
  • the rear part F2 at the fracture position is coupled to the common electrode 22 of the sub-pixel through the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2.
  • Neither the first compensation structure C1 nor the second compensation structure C2 is coupled to the common electrode 22 of sub-pixels other than the second repair sub-pixel P2.
  • the second end of the transistor TFT of the first repair subpixel P1, the pixel electrode 21 of the first repair subpixel P1, the common electrode 22 of the first repair subpixel P1, the independent line segment 50a, and the second repair subpixel P2 The common electrode 22 and the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 form a communication path between the front portion F1 and the rear portion F2 at the open position.
  • the repair structure includes a repair sub-pixel and a first repair sub-pixel P1, the repair sub-pixel is coupled to the front part F1 of the disconnected position, and the repair sub-pixel is coupled to the compensation structure .
  • the compensation structure coupled to the common electrode 22 of the repair sub-pixel includes: a first compensation structure C1 passing through the gate line 30 where the disconnection is located, and a second compensation structure C2 passing through the selected common electrode line 50 '.
  • the front portion F1 at the fracture position is coupled to the common electrode 22 of the sub-pixel through the second end of the transistor TFT of the repair sub-pixel and the pixel electrode 21 of the sub-pixel.
  • the rear part at the fracture position is coupled to the common electrode 22 of the sub-pixel through the first compensation structure C1 coupled by the common electrode 22 of the repair sub-pixel.
  • Neither the first compensation structure C1 nor the second compensation structure C2 is coupled to the common electrode 22 of sub-pixels other than the repair sub-pixel.
  • the first compensation structure C1 to which the common electrode 22 of the pixel P1 is coupled forms a communication path between the front portion F1 and the rear portion F2 at the disconnected position.
  • the specific structure of the repair structure shown in FIG. 9 can be referred to the description about the repair method corresponding to FIG. 9 above, and will not be repeated here.
  • FIG. 10 to FIG. 14 show some other repair structures.
  • the specific structures of these repair structures refer to the description about the repair methods corresponding to FIG. 10 to FIG. 14 above, and the description will not be repeated here.
  • the communication path does not include the transistor TFT and pixel electrode of each repair sub-pixel, but the compensation structure coupled by the common electrode 22 of each repair sub-pixel and each repair sub-pixel The common electrode 22 and the independent line segment 50a in the selected common electrode line 50 'are formed.
  • the repair structure includes two repair sub-pixels, respectively: a first repair sub-pixel P1 coupled to the front F1 of the disconnected position, and a rear F2 coupled to the disconnected position
  • the second repair sub-pixel P2 and both the first repair sub-pixel P1 and the second repair sub-pixel P2 are coupled to the compensation structure.
  • the front portion F1 at the fracture position is coupled to the common electrode 22 of the sub-pixel through the first compensation structure C1 coupled to the common electrode 22 of the first repair sub-pixel P1.
  • the rear portion F2 at the fracture position is coupled to the common electrode 22 of the sub-pixel through the first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2.
  • the first compensation structure C1 and the second compensation structure C2 coupled to the common electrode 22 of the first repair sub-pixel P1 are not coupled to the common electrode 22 of other sub-pixels than the repair sub-pixel.
  • the first compensation structure C1 and the second compensation structure C2 coupled to the common electrode 22 of the second repair sub-pixel P2 are not coupled to the common electrode 22 of other sub-pixels than the repair sub-pixel.
  • the first compensation structure C1 coupled to the common electrode 22 of the first repair subpixel P1, the common electrode 22 of the first repair subpixel P1, the independent line segment 50a, the common electrode 22 of the second repair subpixel P2, and The first compensation structure C1 coupled to the common electrode 22 of the second repair sub-pixel P2 forms a communication path between the front portion F1 and the rear portion F2 at the open position.
  • some embodiments of the present disclosure provide an array substrate, as shown in FIGS. 6 to 15 and FIGS. 16 to 20, the array substrate 01 includes at least one of the above Repair the structure.
  • the number of repair structures included in the array substrate 01 is different from that of the array substrate 01
  • the sum of the number of defective gate line breaks and the short circuit faults of the gate line and the data line is equal.
  • a repair structure corresponds to a defective gate line break or a short circuit between the gate line and the data line.
  • the above array substrate 01 further includes elements or structures such as a plurality of gate lines 30, a plurality of data lines 50, a plurality of sub-pixels 60, etc.
  • elements or structures such as a plurality of gate lines 30, a plurality of data lines 50, a plurality of sub-pixels 60, etc.
  • the display device 1A includes: an array substrate 01, which is broken by the gate line as described above Repair method, or through the repair method of the gate line and the data line short circuit as described above. That is, the array substrate 01 is the array substrate 01 provided in the above embodiment.
  • the display device 1A is a liquid crystal display device.
  • the display device 1A may further include: a counter substrate 02 opposite to the array substrate 01; and, located on the array substrate 01 and the counter The liquid crystal layer 03 between the cell substrate 02.
  • the counter substrate 02 may be a color filter substrate; or, when the array substrate 01 is a COA (color filter on array) type array substrate, that is, when a color filter film is formed on the array substrate 01, the counter The substrate 02 may be a cover glass, for example, cover glass.
  • each sub-pixel includes a pixel electrode and a common electrode, and the array substrate 01 and the counter substrate 02 are packaged in a cell to form a liquid crystal display device
  • the LCD panel can be an AD-SDS (Advanced-Super Dimensional Switching) panel.
  • AD-SDS Advanced-Super Dimensional Switching
  • the fringe electric field generated between the pixel electrode and the common electrode on the array substrate side makes the The aligned liquid crystal molecules between the electrodes and above the electrodes can be deflected in a plane direction parallel to the display surface of the display panel, so that the light transmission efficiency of the liquid crystal layer can be improved while increasing the viewing angle.
  • the above-mentioned display device 1A may further include a backlight module providing a backlight, a driving circuit part, etc.
  • a backlight module providing a backlight
  • a driving circuit part etc. The specific structure will not be repeated here.
  • the display device may be any device that displays an image regardless of motion (eg, video) or fixed (eg, still image) and regardless of text or drawing. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices including, but not limited to, mobile phones, wireless devices, personal data assistants (Portable Android Devices, Abbreviated as PAD), handheld or portable computer, GPS (Global Positioning System) receiver / navigator, camera, MP4 (full name MPEG-4 Part 14) video player, video camera, game console, watch , Clock, calculator, TV monitor, flat panel display, computer monitor, car display (e.g.
  • GPS Global Positioning System
  • MP4 full name MPEG-4 Part 14
  • odometer display etc.
  • navigator e.g., navigator, cockpit controller and / or display
  • camera view display e.g. rear view in vehicle Camera display
  • electronic photos e.g. electronic billboards or signs
  • projectors e.g., architectural structures, packaging, and aesthetic structures (for example, for a display that displays an image of a piece of jewelry), etc.

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Abstract

公开一种栅线断路及栅线与数据线短路的修复方法、显示装置，涉及显示技术领域。该栅线断路的修复方法包括：确定栅线的断路位置；沿断路位置所在的栅线的延伸方向，确定与断路位置最邻近且分别处于断路位置两侧的两个连接元件；从与断路位置所在的栅线耦接的各子像素中，选择与所确定的两个连接元件电连接的一个或两个子像素作为修复子像素；确定与各修复子像素的公共电极耦接的公共电极线为选定公共电极线；在断路位置处的前部与后部之间形成连通通路，以利用连通通路旁路断路位置；将连通通路中的公共电极与其他公共电极断路，将各修复子像素与其所耦接的数据线断路。

Description

栅线断路及栅线与数据线短路的修复方法、修复结构
本申请要求于2018年10月26日提交中国专利局、申请号为201811258793.1、发明名称为“栅线断路及栅线与数据线短路的修复方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种栅线断路及栅线与数据线短路的修复方法、修复结构。
背景技术
阵列基板是显示面板中的核心组件之一，阵列基板中包括有位于不同层的多种信号线。
目前，阵列基板的制备过程中，在形成各信号线的图案处理过程中，受限于金属材料沉积的均匀性、基板的清洁程度及刻蚀工艺的精确度等因素的影响，形成的信号线可能会出现各种不良。
对于阵列基板中存在不良的信号线，需要进行修复，以使得显示面板能够正常显示。
公开内容
一方面，提供一种阵列基板中栅线断路的修复方法，所述阵列基板包括：多个子像素、多条栅线、多条数据线、多条公共电极线和多个补偿结构。其中，每个子像素包括：晶体管、像素电极和公共电极；一行子像素的各晶体管与同一条栅线耦接，一列子像素的各晶体管与同一条数据线耦接；一行子像素的各公共电极与同一条公共电极线耦接；所述多个子像素的各公共电极通过所述多条公共电极线和所述多个补偿结构电性连通。
所述栅线断路的修复方法包括：确定栅线的断路位置；沿所述断路位置所在的栅线的延伸方向，确定与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件，其中，所述两个连接元件为，所与所述断路位置所在的栅线耦接的各晶体管，及经过该栅线且与该栅线所耦接的子像素的公共电极耦接的各补偿结构中的两个元件；从与所述断路位置所在的栅线耦接的各子像素中，选择与所确定的两个连接元件电连接的一个或两个子像素作为修复子像素，确定与各所述修复子像素的公共电极耦接的公共电极线为选定公共电极线；在所述断路位置处的前部与后部之间形成连通通路，以利用所述连通通路旁路所述断路位置，所述连通通路至少包括各所述修复子像素的公共电极，及从所述选定公共电极线上切割出的独立线段；将所述连通通路中的公共电极与其他公共电极断路，将各所述修复子像素与其所耦接的数据线断路。
在一些实施例中，所述连通通路至少包括一个所述修复子像素的晶体管和像素电极，各所述修复子像素的公共电极，及从所述选定公共电极线上切割出的独立线段；或者，所述连通通路至少包括一个所述修复子像素的公共电极所耦接的补偿结构，各所述修复子像素的公共电极，及从所述选定公共电极线上切割出的独立线段。
在一些实施例中，每相邻两条栅线之间设置有一条公共电极线；所述多个补偿 结构分为多组，每组补偿结构包括沿列方向间隔设置的若干个补偿结构；每组补偿结构的各补偿结构与一列子像素的各公共电极交替设置，将该列子像素的各公共电极串接。与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管；或者，一个晶体管和一个补偿结构。
在一些实施例中，所述从与所述断路位置所在的栅线耦接的各子像素中，选择与所确定的两个连接元件相关的一个或两个子像素作为修复子像素，包括：若与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管，则选择这两个晶体管各自所属的子像素作为第一修复子像素和第二修复子像素；若与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为一个晶体管和一个补偿结构，且该晶体管所属的子像素与该补偿结构所耦接的公共电极所属的子像素为不同的子像素，则选择该补偿结构所耦接的公共电极所属的子像素作为第一修复子像素，选择该晶体管所属的子像素作为第二修复子像素；若与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为一个晶体管和一个补偿结构，且该晶体管所属的子像素与该补偿结构所耦接的公共电极所属的子像素为相同的子像素，则选择该晶体管所属的子像素作为第一修复子像素；其中，所述第一修复子像素与所述断路位置处的前部耦接，所述第二修复子像素与所述断路位置处的后部耦接。
在一些实施例中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管，且所述第二修复子像素的公共电极不与补偿结构耦接的情况下，所述在所述断路位置处的前部与后部之间形成连通通路，包括：将所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；将所述断裂位置处的后部，通过所述第二修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接。
在一些实施例中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管，且所述第二修复子像素的公共电极与补偿结构耦接的情况下；其中，与所述第二修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；所述在所述断路位置处的前部与后部之间形成连通通路，包括：将所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；将所述断裂位置处的后部，通过所述第二修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接。
在一些实施例中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管，且所述第二修复子像素的公共电极与补偿结构耦接的情况下；其中，与所述第二修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；所述在所述断路位置处的前部与后部之间形成连通通路，包括：将所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；将所述断裂位置处的后部，通过所述第二修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接。
在一些实施例中，所述将所述连通通路中的公共电极与其他公共电极断路，包 括：将所述第二修复子像素的公共电极所耦接的第一补偿结构及第二补偿结构与除所述第二修复子像素的公共电极之外的其他公共电极断路。
在一些实施例中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为一个晶体管和一个补偿结构，且该晶体管所属的子像素与该补偿结构所耦接的公共电极所属的子像素为相同的子像素的情况下；其中，与所述第一修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；所述在所述断路位置处的前部与后部之间形成连通通路，包括：将所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；将所述断裂位置处的后部，通过所述第一修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接。
在一些实施例中，所述将所述连通通路中的公共电极与其他公共电极断路，包括：将所述第一修复子像素的公共电极所耦接的第一补偿结构及第二补偿结构与除所述第一修复子像素的公共电极之外的其他公共电极断路。
在一些实施例中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为一个晶体管和一个补偿结构，且该晶体管所属的子像素与该补偿结构所耦接的公共电极所属的子像素为不同的子像素，且所述第一修复子像素和所述第二修复子像素均与补偿结构耦接的情况下；其中，与所述第一修复子像素的公共电极耦接的补偿结构，及与所述第二修复子像素的公共电极耦接的补偿结构均包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；所述在所述断路位置处的前部与后部之间形成连通通路，包括：将所述断裂位置处的前部，通过与所述第一修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接；将所述断裂位置处的后部，通过与所述第二修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接。
在一些实施例中，所述将所述连通通路中的公共电极与其他公共电极断路，包括：将所述第一修复子像素的公共电极所耦接的第一补偿结构及第二补偿结构与除所述第一修复子像素的公共电极之外的其他公共电极断路；将所述第二修复子像素的公共电极所耦接的第一补偿结构及第二补偿结构与除所述第二修复子像素的公共电极之外的其他公共电极断路。
另一方面，提供一种阵列基板中栅线断路的修复结构，所述修复结构经如上述任一项所述的修复方法进行修复得到。所述修复结构包括：断路的栅线，所述栅线包括断路位置处的前部和后部；一个或两个修复子像素，每个所述修复子像素包括晶体管、像素电极和公共电极；选定公共电极线，所述选定公共电极线包括与各所述修复子像素的公共电极耦接的独立线段，所述独立线段不与所述选定公共电极线的其它部分耦接。其中，所述断路位置处的前部与后部之间具有连通通路，所述连通通路被配置为旁路所述断路位置；所述连通通路至少包括各所述修复子像素的公共电极，及所述选定公共电极线中的独立线段；所述连通通路中的公共电极不与其他公共电极耦接，且各所述修复子像素不与数据线耦接。
在一些实施例中，所述连通通路至少包括一个所述修复子像素的晶体管和像素电极，各所述修复子像素的公共电极，及所述选定公共电极线中的独立线段。
在一些实施例中，所述修复结构包括两个修复子像素，分别为：与所述断路位置的前部耦接的第一修复子像素，和与所述断路位置的后部耦接的第二修复子像素，且所述第二修复子像素的公共电极不与补偿结构耦接。所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；所述断裂位置处的后部，通过所述第二修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接。
在一些实施例中，所述修复结构包括两个修复子像素，分别为：与所述断路位置的前部耦接的第一修复子像素，和与所述断路位置的后部耦接的第二修复子像素，且所述第二修复子像素的公共电极与补偿结构耦接。与所述第二修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构。所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；所述断裂位置处的后部，通过所述第二修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接。所述第一补偿结构和所述第二补偿结构均不与除所述第二修复子像素以外的其它子像素的公共电极耦接。
在一些实施例中，所述修复结构包括两个修复子像素，分别为：与所述断路位置的前部耦接的第一修复子像素，和与所述断路位置的后部耦接的第二修复子像素，且所述第二修复子像素的公共电极与补偿结构耦接。与所述第二修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构。所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；所述断裂位置处的后部，通过所述第二修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接。所述第一补偿结构和所述第二补偿结构均不与除所述第二修复子像素以外的其它子像素的公共电极耦接。
在一些实施例中，所述修复结构包括一个修复子像素，该修复子像素与所述断路位置的前部耦接，且该修复子像素与补偿结构耦接。与该修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构。所述断裂位置处的前部，通过该修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；所述断裂位置处的后部，通过该修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接。所述第一补偿结构和所述第二补偿结构均不与除该修复子像素以外的其它子像素的公共电极耦接。
在一些实施例中，所述修复结构包括两个修复子像素，分别为：与所述断路位置的前部耦接的第一修复子像素，和与所述断路位置的后部耦接的第二修复子像素，且所述第一修复子像素和所述第二修复子像素均与补偿结构耦接。与所述第一修复子像素的公共电极耦接的补偿结构，及与所述第二修复子像素的公共电极耦接的补偿结构均包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构。所述断裂位置处的前部，通过与所述第一修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接；所述断裂位置处的后部，通过与所述第二修复子像素的公共电极所耦接的第一补偿结构，与该子像素 的公共电极耦接。与所述第一修复子像素的公共电极耦接的第一补偿结构和第二补偿结构不与除该修复子像素以外的其它子像素的公共电极耦接；与所述第二修复子像素的公共电极耦接的第一补偿结构和第二补偿结构不与除该修复子像素以外的其它子像素的公共电极耦接。
又一方面，提供一种阵列基板中栅线与数据线短路的修复方法，包括以下步骤：确定栅线与数据线之间的短路位置；沿所述栅线的延伸方向，将发生短路的所述栅线上紧邻所述短路位置的两侧切断，以使所述栅线形成断路；采用如上面一些实施例所述的栅线断路的修复方法，对发生断路的所述栅线进行修复。
再一方面，提供一种阵列基板，所述阵列基板包括如上述任一实施例所述的栅线断路的修复结构。
再一方面，提供一种显示装置，包括如上述方面所提供的阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据相关技术提供的一种阵列基板的局部俯视结构示意图；
图2为根据相关技术提供的一种栅线与数据线短路的修复方法的示意图；
图3为根据相关技术提供的另一种栅线与数据线短路的修复方法的示意图；
图4为根据本公开一些实施例提供的栅线断路的修复方法所应用的阵列基板的局部俯视结构示意图；
图5为根据本公开一些实施例提供的一种栅线断路的修复方法的流程示意图；
图6为根据本公开一些实施例提供的一种栅线断路的修复方法的示意图；
图7为根据本公开一些实施例提供的再一种栅线断路的修复方法的示意图；
图8为根据本公开一些实施例提供的另一种栅线断路的修复方法的示意图；
图9为根据本公开一些实施例提供的又一种栅线断路的修复方法的示意图；
图10为根据本公开一些实施例提供的又一种栅线断路的修复方法的示意图；
图11为根据本公开一些实施例提供的又一种栅线断路的修复方法的示意图；
图12为根据本公开一些实施例提供的又一种栅线断路的修复方法的示意图；
图13为根据本公开一些实施例提供的又一种栅线断路的修复方法的示意图；
图14为根据本公开一些实施例提供的又一种栅线断路的修复方法的示意图；
图15为根据本公开一些实施例提供的又一种栅线断路的修复方法的示意图；
图16为根据本公开一些实施例提供的一种栅线与数据线短路的修复方法的示意图；
图17为根据本公开一些实施例提供的再一种栅线与数据线短路的修复方法的示意图；
图18为根据本公开一些实施例提供的另一种栅线与数据线短路的修复方法的示意图；
图19为根据本公开一些实施例提供的又一种栅线与数据线短路的修复方法的示意图；
图20为根据本公开一些实施例提供的又一种栅线与数据线短路的修复方法的示意图；
图21为根据本公开一些实施例提供的一种显示装置的剖面结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
需要指出的是，除非另有定义，本公开实施例中所使用的所有术语(包括技术和科学术语)具有与本公开所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
例如，本公开说明书以及权利要求书中所使用的术语“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，仅是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上/上方”、“下/下方”、“行/行方向”以及“列/列方向”等指示的方位或位置关系的术语为基于附图所示的方位或位置关系，仅是为了便于说明本发明的技术方案的简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
例如，在某些情况下，涉及“行方向”的实施例可以在“列方向”的情况下实施等等，相反亦如此。将本公开所述方案进行90°旋转或镜像后亦属本公开要求保护的权利范畴。
在显示面板的阵列基板中，受多方面因素影响，各种信号线可能会存在不良，如短路或断路。示例性的，阵列基板的信号线包括栅线(Gate Line)和数据线(Data Line)，由于栅线和数据线的交叉处仅由栅绝缘层隔开绝缘，栅线和数据线容易发生各种不良。例如，栅线和/或数据线的断路(Open)，这会导致发生断路的栅线和/或数据线无法正常传输相应的信号，影响显示面板的显示效果；栅线与数据线的交叉处发生短路(Data Gate Short，缩写为DGS)，这会导致栅线与数据线的信号相互影响，使得显示面板无法正常显示。
相关技术中，当使用阵列基板形成显示面板后，例如，当阵列基板与对向基板封装形成液晶显示面板后，需要对每个显示面板进行检测工序(Cell Test)，以对面板质量进行判定。检测工序中包括有对各信号线不良的检测及进一步的修复工序。
为便于说明，下面先对本文中所涉及的阵列基板的结构做示例性的说明。
图1为阵列基板01的局部俯视结构示意图，该阵列基板01包括：衬底基板10、 设置于衬底基板10上的多个子像素20(也可称为亚像素，即sub-pixel)、多条栅线30、多条数据线40、多条公共电极线50和多个补偿结构60。
请继续参阅图1，其中，每个子像素20包括：晶体管(例如可以为薄膜晶体管，Thin Film Transistor，缩写为TFT)、像素电极21和公共电极22。阵列基板01所包括的多个子像素20呈多行多列的阵列式排布，此处，设定所述多个子像素20排列的行方向为第一方向D1，列方向为第二方向D2。可以理解的是，所述多个子像素20排列的行方向和列方向相互交叉，即第一方向D1与第二方向D2相互交叉，例如第一方向D1与第二方向D2相互垂直。
每行子像素20(例如，沿第一方向D1排列的每行子像素20)的各晶体管TFT与一条栅线30耦接，且同一行子像素20的各晶体管TFT与同一条栅线30耦接。每列子像素20(例如，沿第二方向D2排列的每列子像素20)的各晶体管TFT与一条数据线40耦接，且同一列子像素20的各晶体管TFT与同一条数据线40耦接。
上述多个子像素20的各公共电极22通过上述多条公共电极线50和上述多个补偿结构60电性连通。其中，每行子像素20的各公共电极22与一条公共电极线50耦接，且同一行子像素20的各公共电极22与同一条公共电极线50耦接。
需要指出的是，由于图1为阵列基板01的局部俯视结构示意图，仅示意出了阵列基板01形成有各结构一侧的俯视图的局部，因此，图1中仅以虚线框代表衬底基板10，并且，该阵列基板01中包括的子像素20的实际数量远多于图1中示意出的数量，图1仅为示例。
应当理解的是，每行子像素20的各晶体管TFT与一条栅线30耦接，以使得该条栅线30向与其耦接的各晶体管TFT提供扫描信号。
具体是指，每行子像素20的晶体管TFT的控制端(通常可被称之为栅极，Gate)与一条栅线30耦接。其中，晶体管TFT的栅极可以为从该条栅线30上突出的部分，或者，晶体管TFT的栅极也可以为该条栅线30延伸方向的主体上的一部分。图1仅以后一种情况为例进行示意，即“栅极为栅线30延伸方向的主体上的一部分”，也即在图1中，晶体管TFT的栅极为栅线30上与晶体管TFT相连接的那部分。栅极与栅线的图案可沿用相关技术中各种结构，此处对此不做限定。
每列子像素20的各晶体管TFT与一条数据线40耦接，以使得该条数据线40向与其耦接的各晶体管TFT提供数据信号，以控制上述阵列基板01与对盒基板对盒后形成的显示面板的显示画面。
示例性的，每列子像素20的晶体管TFT的第一端与一条数据线40耦接。其中，晶体管TFT的第一端，可为输入端，被称为源极(Source)；晶体管TFT的第二端，可为输出端，被称为漏极(Drain)。因此“每列子像素20的晶体管TFT的第一端与一条数据线40耦接”可以理解为，每列子像素20的晶体管TFT的源极与一条数据线40耦接。在此情况下，每列子像素20的晶体管TFT的漏极与一行像素电极21相耦接。
需要指出的是，尽管在本公开提供的各实施例中，以晶体管TFT的源极与数据线耦接、晶体管TFT的漏极与像素电极相耦接为例进行说明，然而本领域的技术人员应当明白，由于晶体管的源极和漏极在结构和组成上的可互换性，因此也可以将晶体管TFT的第一端称为输出端，即漏极、将晶体管TFT的第二端称为输出端， 即源极，这属于本公开的上述实施例的等同变换。
上述阵列基板01中当然还包括有隔离不同导电层的绝缘层，例如，为隔离栅极图案层与源漏图案层而设置的栅绝缘层，其中，栅极图案层包括晶体管TFT的栅极、栅线30，源漏图案层包括晶体管TFT的源极S、漏极D、数据线40；又如，为隔离像素电极21与公共电极22而设置的钝化层。此外，上述晶体管TFT中当然还包括有源层等结构。
由于本公开实施例并未涉及对阵列基板中绝缘层以及晶体管TFT的具体结构的改进，故上述图1中未体现出各绝缘层及晶体管TFT中的有源层，并且，各绝缘层的具体设置位置、晶体管TFT的具体结构及各电极结构的形状可沿用相关技术，本公开实施例对此不作限定。
在本公开提供的各实施例中，阵列基板01的各子像素20的公共电极22为一块块独立的块状电极，而并非一整层的面状电极，而各公共电极22被配置为传输相同的公共电压信号，因此，将每行子像素20的各公共电极22与一条对应的公共电极线50相耦接，以便接收公共电压信号。
这里，在一些实施例中，公共电极22采用ITO(Indium Tin Oxide，氧化铟锡)等透明导电氧化物材料制成，而公共电极线50与栅线30同层设置，采用电阻率较低的Cu(铜)等金属材料制成，也就是说，公共电极22与公共电极线50是经过不同的图案处理工艺形成的，难以在同一次图案处理工艺中同时形成。故，为了保证二者之间的良好电性连通，每行子像素20的各公共电极22通过与一条公共电极线50具有重叠区域的部分，与该条公共电极线50电性连通。
即，每行子像素20的公共电极22对应于一条相耦接的公共电极线50，相耦接的方式可以为：每行子像素20的各公共电极22通过与一条公共电极线50具有重叠区域的部分，与该条公共电极线50电性连通。相耦接的方式还可以为：每行子像素20的各公共电极22通过导电结构搭桥至一条公共电极线50上，从而使得每行子像素20的各公共电极22与该条公共电极线50电性连通(即耦接)。
需要指出的是，本公开实施例提供的以上及下述的各实施例中，所谓“重叠区域”，具体是指两个结构各自在衬底基板10上的正投影重叠的区域。
其中，当公共电极22与公共电极线50位于同一层时，二者具有重叠区域的部分可以直接搭接在一起，以形成电性连通；当公共电极22与公共电极线50位于不同层(即二者之间具有绝缘层)时，二者具有重叠区域的部分可以通过贯穿相应位置处绝缘层的过孔相连接，以形成电性连通。
在一些实施例中，上述多个子像素20的各公共电极22通过上述多条公共电极线50和上述多个补偿结构60电性连通。其中，每个补偿结构60位于沿列方向排列的相邻两个公共电极22之间，并与这两个公共电极22相耦接，从而通过设置一列补偿结构60可以将一列公共电极22串接起来，从而各个补偿结构60与各条公共电极线50一起，形成类似于网格状的电性连通的通路，使上述多个子像素20的公共电极22通过上述多条公共电极线50和上述多个补偿结构60共同电性连通，从而减少各公共电极22与各条公共电极线50构成的整体结构(即Com结构)的电阻，同时，还可提高Com结构上加载的电压的均一性。
这里，补偿结构60与沿列方向排列的相邻两个公共电极22相连接的方式，包 括但不限于：补偿结构60通过与沿列方向排列的相邻两个公共电极22具有重叠区域的部分，与该相邻两个公共电极22电性连通；或者，相连接的方式还可以为：补偿结构60通过导电结构搭桥至沿列方向排列的相邻两个公共电极22上，从而使得该相邻两个公共电极22电性连通在一起。
补偿结构60例如是通过与沿列方向排列的相邻两个公共电极22具有重叠区域的部分，将这两个公共电极22电性连通在一起即可，补偿结构60与对应的公共电极22之间具有重叠区域的图形包括但不限于图1中示意出的矩形，补偿结构60中连接上下的两个矩形的、且跨越栅线30的中间部分包括但不限于图1中示意出的条状。
在上述阵列基板01中，不对像素电极21和公共电极22的具体形状进行限定，只要使得像素电极21与公共电极22相对设置，即二者之间有重叠区域，能够形成相应的驱动液晶分子偏转的电场即可。图1中示意出的像素电极21、公共电极22的图形仅为示例。
对于上述阵列基板01，当阵列基板01与对向基板封装形成液晶显示面板后，若对封装形成的液晶显示面板检测后，检测出的不良为栅线与数据线之间发生短路(DGS)，一种修复思路为，将栅线与数据线短路转变为数据线断路，并借助子像素中的公共电极等结构对断路的数据线进行修复。如图2所示，修复过程具体为：
(1)沿数据线40的延伸方向，将发生短路的数据线40上紧邻短路位置(即栅线30与数据线40的交叉处)的两侧切断，从而形成数据线40的断路。
(2)将数据线40断路位置的两侧分别与公共电极线50焊接导通在一起。
(3)由于靠近断路位置的子像素20的公共电极22通过补偿结构60与前一行中相邻的子像素20的公共电极22电性连通在一起，而前一行中相邻的子像素20的公共电极22又是与位于原本发生短路的栅线30相邻的一条公共电极线50电性连通的，因此，为了避免数据线40断路位置的两侧公共电极线50焊接导通在一起后，数据线40上原本加载的数据线信号被加载到其他子像素20的公共电极22上，需要对这两条公共电极线50以及这两个子像素20的公共电极22与其他公共电极22之间的补偿结构60进行切断，以使得发生断路的数据线40上加载的数据线信号能够借助靠近断路位置处的公共电极22进行传输。
上述修复方式需要牺牲两个子像素20，即修复后有两个子像素20不能进行正常显示，成为暗点。
然而，如图3所示，当栅线30与数据线40之间的短路位置(即DGS的位置)与补偿结构60在栅线方向(即行方向)上相距两个子像素20时，为避免数据线40断路位置的两侧公共电极线50焊接导通在一起后，数据线40上原本加载的数据线信号被加载到其他子像素20的公共电极22上，除了需要对断路位置两侧的两条公共电极线进行切断，还需要对四个子像素20的公共电极22与其他公共电极22之间的补偿结构60进行切断。
这样一来，上述修复方式需要牺牲四个子像素20。也就是说，发生断路的数据线40上加载的数据线信号借助这四个子像素20的公共电极22进行传输后，由于这四个子像素20的公共电极22均无法被加载相应的公共电极电压，从而会造成包括有上述阵列基板01的显示装置修复后进行显示时，这四个子像素20无法进行显 示，即为暗点，由于修复后形成的暗点较多，对显示面板的产品品质影响较大。
基于此，本公开的一些实施例提供一种阵列基板中栅线与数据线短路的修复方法。在该修复方法中，首先确定栅线与数据线之间的短路位置；然后沿栅线的延伸方向，将发生短路的栅线上紧邻短路位置的两侧切断，使栅线形成断路；之后采用栅线断路的修复方法，对发生断路的栅线进行修复。也就是说，对于栅线与数据线的短路问题，本公开实施例中通过将栅线与数据线的短路问题转化为栅线的断路问题，然后采用一定的修复方法对栅线断路进行修复，从而最终实现栅线与数据线短路的修复。
在下文中，为了清楚的描述本公开实施例所提供的栅线与数据线短路的修复方法，首先对一些栅线断路的修复方法进行介绍，这样本领域技术人员在理解栅线断路的修复方法之后，能够更加清楚的理解栅线与数据线短路的修复方法。
然而，下面所提供的各个实施例中的栅线断路的修复方法并不仅仅适用于栅线与数据线短路的修复过程，可以理解的是，这些栅线断路的修复方法还适用于单纯的栅线断路的场景，及其他一些需要应用这些栅线断路的修复方法的场景。
基于此，本公开的一些实施例提供一种阵列基板中栅线断路的修复方法，如图4所示，该阵列基板01包括：多个子像素20、多条栅线30、多条数据线40、多条公共电极线50和多个补偿结构60。
可以理解的是，该阵列基板01还包括衬底基板10，所述多个子像素20、所述多条栅线30、所述多条数据线40、所述多条公共电极线50和所述多个补偿结构60可以设置于衬底基板10上。
请继续参考图4，其中，每个子像素20包括：晶体管TFT、像素电极21和公共电极22。一行子像素20的各晶体管TFT与同一条栅线30耦接，一列子像素20的各晶体管TFT与同一条数据线40耦接，一行子像素20的各公共电极22与同一条公共电极线50耦接。所述多个子像素20的各公共电极22通过上述多条公共电极线50和多个补偿结构60电性连通。
阵列基板01的相关结构说明请参见前述说明，此处不再赘述。
请继续参阅图4，对于阵列基板01中的某条栅线30，与其耦接的晶体管TFT有多个，跨越该栅线30且与该栅线30所耦接的子像素20的公共电极22耦接的补偿结构60有至少一个。在本文中，将与一条栅线30耦接的各晶体管TFT，以及跨越该栅线30且与该栅线30所耦接的子像素20的公共电极22耦接的各补偿结构60统称为该条栅线30的连接元件L。
例如，对于图4中由上至下的第二条栅线30，该栅线300耦接了5个晶体管TFT，跨越该栅线30且与该栅线30所耦接的5个子像素20的公共电极22耦接的补偿结构60有2个，因此可以将这5个晶体管TFT和这2个补偿结构60统称为该栅线30所对应的连接元件L。可以理解的是，以上仅仅以图4中所示出的情况为例进行说明，事实上，对于一个能够正常显示图像的显示面板而言，其阵列基板可能包括成千上万个子像素，则上述栅线30所对应的连接元件L应当不仅限于这5个晶体管TFT和这2个补偿结构60，而是包括更多的晶体管TFT和补偿结构60。
不难理解，对于阵列基板01中发生短路的栅线30而言，该栅线30同样对应多个连接元件L，所述多个连接元件L包括与该栅线30耦接的各晶体管TFT，及跨越该栅线30且与该栅线30所耦接的各子像素20的公共电极22耦接的各补偿结构60。
如图5所示，在一些实施例中，栅线断路的修复方法包括S1～S3：
S1：确定栅线的断路位置。
在上述S1中，确定栅线的断路位置的方式包括但不限于通过人工检查的方式，还可以包括借助相应的检查设备进行检查的方式。
S2：沿断路位置所在的栅线的延伸方向，确定与断路位置最邻近且分别处于断路位置两侧的两个连接元件；从与断路位置所在的栅线耦接的各子像素中，选择与所确定的两个连接元件电连接的一个或两个子像素作为修复子像素；确定与各修复子像素的公共电极耦接的公共电极线为选定公共电极线。
在上述S2中，“栅线的延伸方向”例如为多个子像素20排列的行方向，例如为第一方向D1。
另外，所述两个连接元件为，与断路位置所在的栅线耦接的各晶体管，及跨越该栅线且与该栅线所耦接的子像素的公共电极耦接的各补偿结构中的两个元件。
S3：在断路位置处的前部与后部之间形成连通通路，以利用连通通路旁路断路位置；该连通通路至少包括各修复子像素的公共电极，及从选定公共电极线上切割出的独立线段；将连通通路中的公共电极与其他公共电极断路，将各修复子像素与其所耦接的数据线断路。
在上述S3中，如图6～图15所示，栅线30上的一个断路位置将该栅线30的相应部分分为两段，本文中所提及的断路位置处的“前部”F1是指该两段中的一段，断路位置处的“后部”F2是指该两段中的另一段。例如，如图6～图15所示，该断路位置(图6～图15中标记为“Open”，表示断路)将栅线30的相应部分分为两段，即位于该断路位置左侧的一段和位于该断路位置右侧的一段。
其中，断路位置处的“前部”F1是指位于该断路位置左侧的一段，断路位置处的“后部”F2是指位于该断路位置右侧的一段。当然还可以是，断路位置处的“前部”F1是指位于该断路位置右侧的一段，断路位置处的“后部”F2是指位于该断路位置左侧的一段。
本文中仅以前一种情况为例进行说明，即断路位置处的“前部”F1是指位于该断路位置左侧的一段，断路位置处的“后部”F2是指位于该断路位置右侧的一段；对于后一种情况的断路修复可参见前一种情况，本文中不再赘述。
在上述S3中，所谓“旁路”为一个动作，即使得断路的栅线上加载的栅线信号能够通过上述至少包括各修复子像素的公共电极，及从选定公共电极线上切割出的独立线段的连通通路，绕过该断路位置，以使栅线信号得以继续传输，从而加载到连接在该条栅线上的其他晶体管TFT中，使得该行子像素除修复子像素之外的其他子像素能够正常进行显示。
另外，在上述S3中，从选定公共电极线上切割出的“独立线段”即为，与选定公共电极线上的剩余部分电性隔离开的线段。并且，由于连通通路的作用是旁路栅线上的断路位置，且该连通通路至少包括各修复子像素的公共电极，及从选定公共电极线上切割出的独立线段，故，从选定公共电极线上切割出的独立线段是与各修复子像素的公共电极电性连通在一起的。
由于所述多条公共电极线与所述多个补偿结构形成类似于网格状的电性连通的通路，使得上述多个子像素的各公共电极通过上述多条公共电极线和上述多个补 偿结构共同电性连通，因此，选定公共电极线切断后，选定公共电极线中除所述独立线段外的剩余部分加载的公共电压信号能够通过相应位置处的补偿结构传输至与所述剩余部分电性连通的其他公共电极上，从而使得该条选定公共电极线能够正常传输公共电压信号。
基于此，使用本公开实施例提供的上述栅线断路的修复方法，通过借助至少包括各修复子像素的公共电极，及从选定公共电极线上切割出的独立线段的连通通路，旁路该断路位置，从而可修复栅线上发生的断路，可修复的栅线条数没有限制，且一个断路位置修复后形成暗点的子像素数量仅为1个或2个，即一个断路位置修复后形成暗点的子像素数量最多两个；而采用相关技术中的修复方式，一个断路位置修复后形成暗点的子像素的数量至少有两个，甚至如前面的相关技术所述，对于某些断路位置的情况，一个断路位置修复后形成暗点的子像素的数量有四个。因此，相比较而言，采用本公开实施例所提供的修复方法，一个断路位置修复后形成暗点的子像素数量较少，从而修复后的显示效果好。
在一些实施例中，如图6～图14所示，上述连通通路至少包括一个修复子像素的晶体管TFT和像素电极21，各修复子像素的公共电极22，及从选定公共电极线上切割出的独立线段。
在一些实施例中，如图15所示，上述连通通路至少包括一个修复子像素的公共电极22所耦接的补偿结构60，各修复子像素的公共电极22，及从选定公共电极线上切割出的独立线段。
请继续参阅图4，上述栅线的断路修复方法所适用的阵列基板01中，每相邻两条栅线30之间设置有一条公共电极线50；所述多个补偿结构60分为多组补偿结构，每组补偿结构包括沿列方向(第二方向D2)间隔设置的若干个补偿结构60；每组补偿结构的各补偿结构60与一列子像素的各公共电极22交替设置，每个补偿结构60与沿列方向相邻的两个公共电极22耦接，使得每组补偿结构的各补偿结构60将该列子像素20的各公共电极22串接起来。
这里，每相邻两条栅线30之间设置有一条公共电极线50，例如可以将该条公共电极线50设置地更靠近其中一条栅线30(如下方的一条栅线30)。
补偿结构60的作用请参阅前述说明，此处不再赘述。
此处，多组补偿结构60与阵列基板01所包括的多列公共电极22中的至少两列公共电极22分别对应设置，一组补偿结构60对应一列公共电极22。由于各列公共电极22位于相邻两条数据线40之间，且每组补偿结构的各补偿结构60与所对应的一列子像素20的各公共电极22交替设置，因此每组补偿结构60也位于其对应的公共电极列所处的两条数据线40之间。具体可以包括以下两种设置方式：
一、可以是阵列基板01所包括的全部数据线40中每相邻两条数据线40之间，设置有上述的一组补偿结构60。也就是说，各组补偿结构60与阵列基板01所包括的各列公共电极22一一对应设置。
二、可以是在阵列基板01所包括的全部数据线40中的一部分数据线40之间分别设置有上述的多组补偿结构60。也就是说，各组补偿结构60与阵列基板01所包括的各列公共电极22中的一些列公共电极22一一对应设置。
示例性的，请继续参阅图4，上述栅线的断路修复方法所适用的阵列基板01中， 所述多个补偿结构60中，相邻两组补偿结构60之间间隔沿列方向(第二方向D2)的两列子像素20。即，阵列基板01中的每三列相邻的子像素20共用一列补偿结构60。也即，每隔3条数据线40设置有一组补偿结构60。
这样3：1的结构设计，一方面，能够使得整个基板中分布的补偿结构60的数量合适，有利于降低整个Com结构的电阻。另一方面，由于补偿结构60起到降低整个Com结构电阻的作用，因此，补偿结构60通常采用电阻率较低的金属材料制成，这些金属材料如Cu的透明度较低。这样一来，若采用1：1的结构设计，即每列子像素20均对应设置有一列补偿结构60，即每相邻两条数据线40之间均设置有一组补偿结构60，对整个阵列基板01的光透过率影响较大，因此，采用上述3：1的结构设计对光透过率影响较小，可以避免增加与包括该阵列基板01的液晶显示面板相配合的背光模组的能耗。
需要说明的是，阵列基板01中多组补偿结构60的布置形式并不限于上述示例，还可以每隔2条、4条、5条、6条、7条、8条、9条、10条等条数的数据线40设置一组补偿结构60。
在上述S2中，与栅线30上的断路位置最邻近且分别处于该断路位置两侧的连接元件L可以至少包括以下两种情形：
一、如图6～图8所示，与栅线30上的断路位置最邻近且分别处于该断路位置两侧的两个连接元件L为两个晶体管TFT，即该断路位置(图6～图8中标记为“Open”，表示断路)处于两个晶体管TFT之间。
二、如图9～图15所示，与栅线30上的断路位置最邻近且分别处于该断路位置两侧的两个连接元件L，其中一个为晶体管TFT，另一个为补偿结构60，即该断路位置(图9～图15中标记为“Open”，表示断路)处于晶体管TFT和补偿结构60之间。
根据该两个连接元件L的上述不同情形，S2中关于如何选择修复子像素至少包括如下三种方式：
一、请参阅图6～图8，若该两个连接元件L为两个晶体管TFT，则从与断路位置所在的栅线耦接的各子像素20中，选择这两个晶体管TFT各自所属的子像素20作为第一修复子像素P1和第二修复子像素P2。其中，第一修复子像素P1与断路位置处的前部F1耦接，第二修复子像素P2与断路位置处的后部F2耦接。即，在进行栅线断路修复的过程中，选择牺牲第一修复子像素P1和第二修复子像素P2这两个子像素来完成修复工作。
二、如图9所示，若该两个连接元件L，其中一个为晶体管TFT，另一个为补偿结构60，且该晶体管TFT所属的子像素20与该补偿结构60所耦接的公共电极22所属的子像素20为相同的子像素，则从与断路位置所在的栅线30耦接的各子像素20中，选择该晶体管TFT所属的子像素20作为第一修复子像素P1。其中，第一修复子像素P1与断路位置处的前部F1耦接。即，在进行栅线断路修复的过程中，选择牺牲第一修复子像素P1这1个子像素来完成修复工作。
三、如图10～图15所示，若该两个连接元件L，其中一个为晶体管TFT，另一个为补偿结构60，且该晶体管TFT所属的子像素20与该补偿结构60所耦接的公共电极22所属的子像素为不同的子像素，则从与断路位置所在的栅线30耦接的各子像素20中，选择该补偿结构60所耦接的公共电极22所属的子像素20作为第一修复子像素P1，选择 该晶体管TFT所属的子像素20作为第二修复子像素P2。其中，第一修复子像素P1与断路位置处的前部F1耦接，第二修复子像素P2与断路位置处的后部F2耦接。即，在进行栅线断路修复的过程中，选择牺牲第一修复子像素P1和第二修复子像素P2这两个子像素来完成修复工作。
根据上述该两个连接元件L的不同，以及所选择的修复子像素的公共电极22是否耦接有补偿结构60，栅线30上的断路位置至少包括以下五种：
一、如图6所示，该断路位置(图6中标记为“Open”，表示断路)处于两个晶体管TFT之间。这两个晶体管TFT各自所属的子像素20分别第一修复子像素P1和第二修复子像素P2，其中，第二修复子像素P2的公共电极22不与补偿结构60耦接。
二、如图7和8所示，该断路位置(图7和图8中标记为“Open”，表示断路)处于两个晶体管TFT之间。这两个晶体管TFT各自所属的子像素20分别第一修复子像素P1和第二修复子像素P2，其中，第二修复子像素P2的公共电极22与补偿结构60耦接。
其中，与第二修复子像素P2的公共电极22耦接的补偿结构60包括跨越断路位置所在的栅线30的第一补偿结构C1，及经过选定公共电极线的第二补偿结构C2。
三、如图9所示，该断路位置(图9中标记为“Open”，表示断路)处于晶体管TFT和补偿结构60之间，且该晶体管TFT所属的子像素20与该补偿结构60所耦接的公共电极22所属的子像素20为相同的子像素，该子像素为第一修复子像素P1。其中，与第一修复子像素P1的公共电极22耦接的补偿结构60包括：跨越所述断路位置所在的栅线的第一补偿结构C1，及经过所述选定公共电极线的第二补偿结构C2。
四、如图10和图11所示，该断路位置(图10和图11中标记为“Open”，表示断路)处于晶体管TFT和补偿结构60之间，且该晶体管TFT所属的子像素20与该补偿结构60所耦接的公共电极22所属的子像素20为不同的子像素。该补偿结构60所耦接的公共电极22所属的子像素20为第一修复子像素P1，该晶体管TFT所属的子像素20为第二修复子像素P2，其中，第二修复子像素P2的公共电极22不与补偿结构60耦接。
其中，与第一修复子像素P1的公共电极22耦接的补偿结构60包括：经过断路位置所在的栅线30的第一补偿结构C1，及经过选定公共电极线50的第二补偿结构C2。
五、如图12、图13、图14或图15所示，该断路位置(图12、图13、图14和图15中标记为“Open”，表示断路)处于晶体管TFT和补偿结构60之间，且该晶体管TFT所属的子像素20与该补偿结构60所耦接的公共电极22所属的子像素20为不同的子像素。该补偿结构60所耦接的公共电极22所属的子像素20为第一修复子像素P1，该晶体管TFT所属的子像素20为第二修复子像素P2，其中，第一修复子像素P1和第二修复子像素P2均与补偿结构60耦接。
其中，与第一修复子像素P1的公共电极22耦接的补偿结构60，及与第二修复子像素P2的公共电极22耦接的补偿结构60均包括：经过断路位置所在的栅线30的第一补偿结构C1，及跨越选定公共电极线的第二补偿结构C2。
根据栅线30上的断路位置的不同，可以选择不同的栅线断路修复方式。
下面针对上述不同的断路位置，提供几种示例的修复方式，用于详细描述栅线断路后的具体修复过程。
如图6所示，针对上述第一种断路位置，提供一种示例的断路修复方法，该方法包括如下步骤：
S1：确定栅线30的断路位置(图6中标记为“Open”，表示断路)。
S2：S2包括以下S211～S212。
S211：确定与断路位置最邻近且分别处于断路位置两侧的两个连接元件L。若该两个连接元件L为两个晶体管TFT，则从与断路位置所在的栅线30耦接的各子像素20中，选择这两个晶体管TFT各自所属的子像素20作为第一修复子像素P1和第二修复子像素P2。其中，第一修复子像素P1与断路位置处的前部F1耦接，第二修复子像素P2与断路位置处的后部F2耦接。
S212：确定与第一修复子像素P1和第二修复子像素P2各自的公共电极22耦接(例如为具有重叠区域)的一条公共电极线50为选定公共电极线50’。
S3：S3包括以下S311～S314。
S311：将断裂位置处的前部F1，通过第一修复子像素P1的晶体管TFT的第二端(例如为漏极D)、及该子像素20(即第一修复子像素P1)的像素电极21，与该子像素20的公共电极22耦接。
S312：将断裂位置处的后部F2，通过第二修复子像素P2中的晶体管TFT的第二端(例如为漏极D)、及该子像素20(即第二修复子像素P2的像素电极21，与该子像素20的公共电极22耦接。
S313：将第一修复子像素P1和第二修复子像素P2各自的晶体管TFT和其所耦接的数据线40断开。这样可以避免第一修复子像素P1和第二修复子像素P2各自的像素电极21仍被加载数据线40上的数据线信号，影响该条栅线30的正常修复。
S314：将选定公共电极线50’与除第一修复子像素P1和第二修复子像素P2中的公共电极22之外的其他公共电极22断路，以形成从选定公共电极线50’上切割出的独立线段50a。
这样一来，通过由第一修复子像素P1的晶体管TFT的第二端(图6中表示为漏极D)、第一修复子像素P1的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、第二修复子像素P2的像素电极21、以及第二修复子像素P2的晶体管TFT的第二端(图6中表示为漏极D)构成的连通通路，旁路断路位置，信号传输的方式可如图6中虚线箭头所示。
需要说明的是，栅线信号的传输方向X以是从左到右，可以是从右到左，还可以是从两边向中间。本公开仅以栅线信号的传输方向X为从左到右为例进行说明，即如在图6中，栅线信号的传输方向X与从断路位置处的前部F1指向断路位置处的后部F2的方向同向。在下文中也以栅线信号的传输方向X为从左到右为例进行说明。
可以理解的是，以上S211～S212、及S311～S314并无先后顺序的限定，各步骤可以依次或同时进行，本公开实施例对此不作限定。
这样，通过以上修复方法，对发生断路的栅线进行修复后，形成的暗点仅为第一修复子像素P1和第二修复子像素P2，对整个显示面板的影响较小，修复效果较 好。
示例性的，S311包括：
请继续参阅图6，将断裂位置处的前部F1与第一修复子像素P1的晶体管TFT的第二端(图6中表示为漏极D)焊接导通，将第一修复子像素P1中的像素电极21与该子像素(即第一修复子像素P1)的公共电极22焊接导通，从而实现断裂位置处的前部F1通过第一修复子像素P1的晶体管TFT的第二端(图6中表示为漏极D)、及该子像素20的像素电极21，与该子像素20的公共电极22耦接。
示例性的，S312包括：
请继续参阅图6，将断裂位置处的后部F2与第二修复子像素P2的晶体管TFT的第二端(图6中表示为漏极D)焊接导通，将第二修复子像素P2的像素电极21与该子像素(即第二修复子像素P2)的公共电极22焊接导通，从而实现断裂位置处的后部F2通过第二修复子像素P2中的晶体管TFT的第二端(图6中表示为漏极D)、及该子像素20的像素电极21，与该子像素20的公共电极22耦接。
示例性的，S313包括：
请继续参阅图6，将第一修复子像素P1和第二修复子像素P2各自的晶体管TFT的第一端(例如为源极S)与其耦接的数据线40断路，从而避免第一修复子像素P1和第二修复子像素P2各自的像素电极21仍被加载数据线40上的数据线信号，影响该条栅线30的正常修复。例如为切断第一修复子像素P1和第二修复子像素P2各自的晶体管TFT的第一端(例如为源极S)。
需要指出的是，在本公开提供的各实施例中，晶体管TFT的第一端为源极S，第二端为漏极D。当然在本公开的其他实施例中，也可以是，第一端为漏极D，第二端为源极S。在本文中以及附图中，仅以前一种为例进行说明，即第一端为源极S，第二端为漏极D。
示例性的，请继续参阅图6，在上述S314中，形成独立线段50a的过程可包括以下步骤：
(1)在与选定公共电极线50’耦接的一行子像素20中，确定与修复子像素两侧相邻的两个子像素分别作为第一相邻子像素P1’和第二相邻子像素P2’。
具体的，如图6所示，沿栅线30的延伸方向，第一相邻子像素P1’为与第一修复子像素P1紧邻的前一个子像素20，第二相邻子像素P2’为与第二修复子像素P2紧邻的后一个子像素20。
(2)将选定公共电极线50’上位于第一修复子像素P1中的公共电极22与位于第一相邻子像素P1’中的公共电极22之间的部分切断。
(3)将选定公共电极线50’上位于第二修复子像素P2中的公共电极22与位于第二相邻子像素P2’中的公共电极22之间的部分切断。
这样，形成了与第一修复子像素P1和第二修复子像素P2中的公共电极22均电性连通的、且从选定公共电极线50’上切断出的独立线段50a。
即，将由第一修复子像素P1与第二修复子像素P2构成的修复单元两侧的选定公共电极线50’切断，以形成独立线段50a，从而与其他子像素20的公共电极22电性隔离开。
上述(1)、(2)和(3)仅为了区分描述的层次，并不限定上述各步骤的顺 序。
如图7所示，针对上述第二种断路位置，提供一种示例的断路修复方法，该方法包括如下步骤：
S1：确定栅线30的断路位置(图7中标记为“Open”，表示断路)。
S2：S2包括以下S221～S222。
S221：确定与断路位置最邻近且分别处于断路位置两侧的两个连接元件L。若该两个连接元件L为两个晶体管TFT，则从与断路位置所在的栅线30耦接的各子像素20中，选择这两个晶体管TFT各自所属的子像素20作为第一修复子像素P1和第二修复子像素P2。其中，第一修复子像素P1与断路位置处的前部F1耦接，第二修复子像素P2与断路位置处的后部F2耦接。
S222：确定与第一修复子像素P1和第二修复子像素P2各自的公共电极22耦接(例如为具有重叠区域)的一条公共电极线50为选定公共电极线50’。
S3：S3包括以下S321～S325。
S321：将断裂位置处的前部F1，通过第一修复子像素P1中的晶体管TFT的第二端(例如为漏极D)、及该子像素20(即第一修复子像素P1)的像素电极21，与该子像素20的公共电极22耦接。
S322：将断裂位置处的后部F2，通过第二修复子像素P2中的晶体管TFT的第二端(例如为漏极D)、及该子像素20(即第二修复子像素P2)的像素电极21，与该子像素20的公共电极22耦接。
S323：将第一修复子像素P1和第二修复子像素P2各自的晶体管TFT与其耦接的数据线40断路。这样可以避免第一修复子像素P1和第二修复子像素P2各自的像素电极21仍被加载数据线40上的数据线信号，影响该条栅线30的正常修复。
S324：将选定公共电极线50’与除第一修复子像素P1和第二修复子像素P2中的公共电极22之外的其他公共电极22断路，以形成从选定公共电极线50’上切割出的独立线段50a。
S325：将与第二修复子像素P2的公共电极22耦接的第一补偿结构C1与除第二修复子像素P2中的公共电极22之外的其他公共电极22断路；将与第二修复子像素P2的公共电极22耦接的第二补偿结构C2与除第二修复子像素P2中的公共电极22之外的其他公共电极断路。例如为切断该第一补偿结构C1、切断该第二补偿结构C2，以避免第二修复子像素P2中的公共电极22仍被加载公共电极线50上的公共电压信号，影响该条栅线30的正常修复。
这样一来，通过由第一修复子像素P1的晶体管TFT的第二端(图7中表示为漏极D)、第一修复子像素P1的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、第二修复子像素P2的像素电极21、以及第二修复子像素P2的晶体管TFT的第二端(图7中表示为漏极D)构成的连通通路，旁路断路位置，信号传输的方式可如图7中虚线箭头所示。
可以理解的是，以上S221～S222、及S321～S325并无先后顺序的限定，各步骤可以依次或同时进行，本发明实施例对此不作限定。
这样，通过以上修复方法，对发生断路的栅线进行修复后，形成的暗点仅为第一修复子像素P1和第二修复子像素P2，对整个显示面板的影响较小，修复效果较 好。
示例性的，S321包括：
请继续参阅图7，将断裂位置处的前部F1与第一修复子像素P1的晶体管TFT的第二端(图7中表示为漏极D)焊接导通，将第一修复子像素P1的像素电极21与该子像素(即第一修复子像素P1)的公共电极22焊接导通，从而实现断裂位置处的前部F1通过第一修复子像素P1中的晶体管TFT的第二端(图7中表示为漏极D)、及该子像素20的像素电极21，与该子像素20的公共电极22耦接。
示例性的，S322包括：
请继续参阅图7，将断裂位置处的后部F2与第二修复子像素P2的晶体管TFT的第二端(图7中表示为漏极D)焊接导通，将第二修复子像素P2的像素电极21与该子像素(即第二修复子像素P2)的公共电极22焊接导通，从而实现断裂位置处的后部F2通过第二修复子像素P2中的晶体管TFT的第二端(图7中表示为漏极D)、及该子像素20的像素电极21，与该子像素20的公共电极22耦接。
示例性的，S323包括：
请继续参阅图7，将第一修复子像素P1和第二修复子像素P2各自的晶体管TFT的第一端(例如为源极S)与其耦接的数据线40断路，从而避免第一修复子像素P1和第二修复子像素P2各自的像素电极21仍被加载数据线40上的数据线信号，影响该条栅线30的正常修复。例如为切断第一修复子像素P1和第二修复子像素P2各自的晶体管TFT的源极S。
示例性的，请继续参阅图7，在上述S324中，形成独立线段50a的过程可包括以下步骤：
(1)在与选定公共电极线50’耦接的一行子像素20中，确定与修复子像素两侧相邻的两个子像素分别作为第一相邻子像素P1’和第二相邻子像素P2’。
具体的，如图7所示，沿栅线30的延伸方向，第一相邻子像素P1’为与第一修复子像素P1紧邻的前一个子像素20，第二相邻子像素P2’为与第二修复子像素P2紧邻的后一个子像素20。
(2)将选定公共电极线50’上位于第一修复子像素P1中的公共电极22与位于第一相邻子像素P1’中的公共电极22之间的部分切断。
(3)将选定公共电极线50’上位于第二修复子像素P2中的公共电极22与位于第二相邻子像素P2’中的公共电极22之间的部分切断。
这样，形成了与第一修复子像素P1和第二修复子像素P2中的公共电极22均电性连通的、且从选定公共电极线50’上切断出的独立线段50a。
即，将由第一修复子像素P1与第二修复子像素P2构成的修复单元两侧的选定公共电极线50’切断，以形成独立线段50a，从而与其他子像素20的公共电极22电性隔离开。
上述(1)、(2)和(3)仅为了区分描述的层次，并不限定上述各步骤的顺序。
示例性的，请继续参阅图7，在上述S325中：
将第二修复子像素P2的公共电极22所耦接的第一补偿结构C1与除第二修复子像素P2的公共电极22之外的其他公共电极22断路的方式，包括：
将该第一补偿结构C1中，处于该第一补偿结构C1所耦接的两个公共电极22之间的部分切断。
将第二修复子像素P2的公共电极22所耦接的第二补偿结构C2与除第二修复子像素P2的公共电极22之外的其他公共电极22断路的方式，包括：
将该第二补偿结构C2中，处于该第二补偿结构C2所耦接的两个公共电极22之间的部分切断。
如图8所示，针对上述第二种断路位置，提供再一种示例的断路修复方法，该方法包括如下步骤：
S1：确定栅线30的断路位置(图8中标记为“Open”，表示断路)。
S2：S2包括以下S231～S232。
S231：确定与断路位置最邻近且分别处于断路位置两侧的两个连接元件L。若该两个连接元件L为两个晶体管TFT，则从与断路位置所在的栅线30耦接的各子像素20中，选择这两个晶体管TFT各自所属的子像素20作为第一修复子像素P1和第二修复子像素P2。其中，第一修复子像素P1与断路位置处的前部F1耦接，第二修复子像素P2与断路位置处的后部F2耦接。
S232：确定与第一修复子像素P1和第二修复子像素P2各自的公共电极22耦接(例如为具有重叠区域)的一条公共电极线50为选定公共电极线50’。
S3：S3包括以下S331～S335。
S331：将断裂位置处的前部F1，通过第一修复子像素P1中的晶体管TFT的第二端(例如为漏极D)、及该子像素20(即第一修复子像素P1)的像素电极21，与该子像素20的公共电极22耦接。
S332：将断裂位置处的后部F2，通过与第二修复子像素P2的公共电极22耦接的第一补偿结构C1，与第二修复子像素P2中的公共电极22耦接。
S333：将第一修复子像素P1和第二修复子像素P2各自的晶体管TFT与其耦接的数据线40断路。这样可以避免第一修复子像素P1和第二修复子像素P2各自的像素电极21仍被加载数据线40上的数据线信号，影响该条栅线30的正常修复。
S334：将选定公共电极线50’与除第一修复子像素P1和第二修复子像素P2中的公共电极22之外的其他公共电极22断路，以形成从选定公共电极线50’上切割出的独立线段50a。
S335：将与第二修复子像素P2的公共电极22耦接的第一补偿结构C1与除第二修复子像素P2的公共电极22之外的其他公共电极22断路；将与第二修复子像素P2的公共电极22耦接的第二补偿结构C2与除第二修复子像素P2的公共电极22之外的其他公共电极22断路。例如为切断该第一补偿结构C1、切断该第二补偿结构C2，以避免第二修复子像素P2的公共电极22仍被加载公共电极线50上的公共电压信号，影响该条栅线30的正常修复。
这样一来，通过由第一修复子像素P1的晶体管TFT的第二端(图8中表示为漏极D)、第一修复子像素P1的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、以及与第二修复子像素P2的公共电极22耦接的第一补偿结构C1构成的连通通路，旁路断路位置，信号传输的方式可如图8中虚线箭头所示。
可以理解的是，以上S231～S232、及S331～S335并无先后顺序的限定，各步骤可以依次或同时进行，本发明实施例对此不作限定。
这样，通过以上修复方法，对发生断路的栅线进行修复后，形成的暗点仅为第一修复子像素P1和第二修复子像素P2，对整个显示面板的影响较小，修复效果较好。
这里，上述图7与图8示意出的两种修复方法的不同之处在于，在图7示意出的连通通路中，连通通路是借道第一修复子像素P1和第二修复子像素P2其各自的晶体管TFT、其各自的像素电极21、其各自的公共电极22以及从选定公共电极线50’上切割出的独立线段50a，旁路断路位置的，并未借道补偿结构60。
而在图8示意出的连通通路中，连通通路是借道第一修复子像素P1的晶体管TFT、其像素电极21、其公共电极22、第二修复子像素P2的公共电极22、独立线段50a以及第二修复子像素P2的公共电极22耦接的第一补偿结构C1，旁路断路位置的，并未借道第二修复子像素P2中的晶体管TFT和像素电极21。
当栅线30上的断路位置为上述第二种时，即该断路位置处于两个晶体管TFT之间，且第二修复子像素P2的公共电极22与补偿结构60耦接时，可以选择上述图7或图8示意出的任一种修复方式。
示例性的，S331包括：
请继续参阅图8，将断裂位置处的前部F1与第一修复子像素P1的晶体管TFT的第二端(图8中表示为漏极D)焊接导通，将第一修复子像素P1的像素电极21与该子像素(即第一修复子像素P1)的公共电极22焊接导通，从而实现断裂位置处的前部F1通过第一修复子像素P1的晶体管TFT的第二端(图7中表示为漏极D)、及该子像素20的像素电极21，与该子像素20的公共电极22耦接。
示例性的，S332包括：
请继续参阅图8，将断裂位置处的后部F2与第二修复子像素P2的公共电极22耦接的第一补偿结构C1焊接导通。
由于与第二修复子像素P2的公共电极22耦接的第一补偿结构C1与第二修复子像素P2的公共电极22电性连通，因此，当断裂位置处的后部F2与该第一补偿结构C1焊接导通时，该断裂位置处的后部F2即与第二修复子像素P2中的公共电极22电性连通在一起了。
具体的，由前述对补偿结构60的相关说明可知，将断裂位置处的后部F2与第一补偿结构C1焊接导通，可以是通过将断裂位置处的后部F2与第一补偿结构C1之间具有重叠区域的部分焊接导通。
在图8所示的修复方法的基础上，进一步的，考虑到发生断路的栅线30上加载的栅线信号通过上述连通通路得以继续传输后，第二修复子像素P2中的公共电极22上加载的即是栅线信号，而不是该条栅线30未断路时，原本应当加载的公共电压信号，因此，第二修复子像素P2是难以继续正常显示的，为了避免第二修复子像素P2中的像素电极21与该子像素中加载了栅线信号的公共电极22之间产生的电场，影响第二修复子像素P2附近液晶分子的正常偏转，故需要将第二修复子像素P2中的晶体管TFT与该子像素中的像素电极21断路。
示例性的，在上述S333中：
将第一修复子像素P1的晶体管TFT与其耦接的数据线40断路的方式，包括但不限于下述方式：
将第一修复子像素P1的晶体管TFT的第一端(例如为源极S)与其耦接的数据线40断路。例如为切断第一修复子像素P1的晶体管TFT的第一端(例如为源极S)。
将第二修复子像素P2的晶体管TFT与其耦接的数据线40断路的方式，包括但不限于以下三种方式：
一、将第二修复子像素P2的晶体管TFT的第一端(例如为源极S)与其电连接的数据线40断路。例如为切断第二修复子像素P2的晶体管TFT的第一端(例如为源极S)。
二、将第二修复子像素P2中的晶体管TFT的第二端(例如为漏极D)与其电连接的像素电极21断路，例如为切断晶体管TFT的第二端(例如为漏极D)。
三、将第二修复子像素P2中的晶体管TFT的第一端(例如为源极S)与其电连接的数据线40断路，并且将第二修复子像素P2中的晶体管TFT的第二端(例如为漏极D)与其电连接的像素电极40断路，例如为切断第二修复子像素P2的晶体管TFT的第一端(例如为源极S)和第二端(例如为漏极D)。
需要指出的是，上述图8中仅示意出“切断晶体管TFT的第一端”这一种断路的方式，对于“切断晶体管TFT的第二端”的方式，可参考图8进行理解，此处不再赘述。
示例性的，请继续参阅图8，在上述S334中，形成独立线段50a的过程可包括以下步骤：
(1)在与选定公共电极线50’耦接的一行子像素20中，确定与修复子像素两侧相邻的两个子像素分别作为第一相邻子像素P1’和第二相邻子像素P2’。
具体的，如图8所示，沿栅线30的延伸方向，第一相邻子像素P1’为与第一修复子像素P1紧邻的前一个子像素20，第二相邻子像素P2’为与第二修复子像素P2紧邻的后一个子像素20。
(2)将选定公共电极线50’上位于第一修复子像素P1中的公共电极22与位于第一相邻子像素P1’中的公共电极22之间的部分切断。
(3)将选定公共电极线50’上位于第二修复子像素P2中的公共电极22与位于第二相邻子像素P2’中的公共电极22之间的部分切断。
这样，形成了与第一修复子像素P1和第二修复子像素P2的公共电极22均电性连通的，且从选定公共电极线50’上切断出的独立线段50a。
即，将由第一修复子像素P1与第二修复子像素P2构成的修复单元两侧的选定公共电极线50’切断，以形成与选定公共电极线50’中的其他部分电性隔开的独立线段50a，从而与其他子像素20的公共电极22电性隔离开。
上述(1)、(2)和(3)仅为了区分描述的层次，并不限定上述各步骤的顺序。
示例性的，请继续参阅图8，在上述S335中：
将第二修复子像素P2的公共电极22所耦接的第一补偿结构C1与除第二修复子像素P2的公共电极22之外的其他公共电极22断路的方式，包括：
将该第一补偿结构C1中，处于该第一补偿结构C1的第一连接部分与第二连接部分之间的部分切断。其中，第一连接部分为该第一补偿结构C1中与断裂位置处的后部F2耦接的部分。例如，当采用上述焊接的方式，将断裂位置处的后部F2与该第一补偿结构C1导通时，第一连接部分为该第一补偿结构C1与断裂位置处的后部F2焊接导通的焊接部分。其中，第二连接部分为该第一补偿结构C1中与除第二修复子像素P2的公共电极22之外的其他公共电极22耦接的部分，例如，第二连接部分为，该第一补偿结构C1中，与除第二修复子像素P2的公共电极22之外的其他公共电极22具有重叠区域的重叠部分。
将第二修复子像素P2的公共电极22所耦接的第二补偿结构C2与除第二修复子像素P2的公共电极22之外的其他公共电极22断路的方式，包括：
将该第二补偿结构C2中，处于该第二补偿结构C2所耦接的两个公共电极22之间的部分切断。
如图9所示，针对上述第三种断路位置，提供一种示例的断路修复方法，该方法包括如下步骤：
步骤S1：确定栅线30的断路位置(图9中标记为“Open”，表示断路)。
S2：S2包括以下S241～S242。
S241：确定与断路位置最邻近且分别处于断路位置两侧的两个连接元件L。若该两个连接元件L，其中一个为晶体管TFT，另一个为补偿结构60，且该晶体管TFT所属的子像素20与该补偿结构60所耦接的公共电极22所属的子像素20为相同的子像素，则从与断路位置所在的栅线30耦接的各子像素20中，选择该晶体管TFT所属的子像素20作为第一修复子像素P1。其中，第一修复子像素P1与断路位置处的前部F1耦接。
S242：确定与第一修复子像素P1的公共电极22耦接(例如为具有重叠区域)的一条公共电极线50为选定公共电极线50’。
S3：S3包括以下S341-S345：
S341：将断裂位置处的前部F1，通过第一修复子像素P1中的晶体管TFT的第二端(例如为漏极D)、及该子像素20(即第一修复子像素P1)的像素电极21，与该子像素20的公共电极22耦接；
S342：将断裂位置处的后部F2，通过与第一修复子像素P1的公共电极22耦接的第一补偿结构C1，与第一修复子像素P1中的公共电极22耦接。
S343：将第一修复子像素P1的晶体管TFT与其耦接的数据线40断路。这样可以避免第一修复子像素P1的像素电极21仍被加载数据线40上的数据线信号，影响该条栅线30的正常修复。
S344：将选定公共电极线50’与除第一修复子像素P1中的公共电极22之外的其他公共电极22断路，以形成从选定公共电极线50’上切割出的独立线段50a。
S345：将第一修复子像素P1的公共电极22所耦接的第一补偿结构C1与除第一修复子像素P1的公共电极22之外的其他公共电极22断路；将第一修复子像素P1的公共电极22所耦接的第二补偿结构C2与除第一修复子像素P1的公共电极22之外的其他公共电极22断路。例如为切断该第一补偿结构C1、切断该第二补偿结构C2，以避免第一修复子像素P1的公共电极22仍被加载公共电极线50上的公共 电压信号，影响该条栅线30的正常修复。
这样一来，通过由第一修复子像素P1的晶体管TFT的第二端(图8中表示为漏极D)、第一修复子像素P1中的像素电极21、第一修复子像素P1的公共电极22、独立线段50a 、以及与第一修复子像素P1的公共电极22耦接的第一补偿结构C1构成的连通通路，旁路断路位置，信号传输的方式可如图9中虚线箭头所示。
可以理解的是，以上S241～S242、及S341～S345并无先后顺序的限定，各步骤可以依次或同时进行，本发明实施例对此不作限定。
这样，通过以上修复方法，对发生断路的栅线进行修复后，形成的暗点仅为第一修复子像素P1，对整个显示面板的影响较小，修复效果较好。
示例性的，S341包括：
请继续参阅图9，将断裂位置处的前部F1与第一修复子像素P1的晶体管TFT的第二端(图9中表示为漏极D)焊接导通，将第一修复子像素P1的像素电极21与该子像素(即第一修复子像素P1)的公共电极22焊接导通，从而实现断裂位置处的前部F1通过第一修复子像素P1的晶体管TFT的第二端(图9中表示为漏极D)、及该子像素20的像素电极21，与该子像素20的公共电极22耦接。
示例性的，S342包括：
请继续参阅图9，将断裂位置处的后部F2与第一修复子像素P1的公共电极22耦接的第一补偿结构C1焊接导通。
由于与第一修复子像素P1的公共电极22耦接的第一补偿结构C1与第一修复子像素P1中的公共电极22电性连通，因此，当断裂位置处的后部F2与该第一选定补偿结构C1焊接导通时，该断裂位置处的后部F2即与第一修复子像素P1中的公共电极22电性连通在一起了。
具体的，由前述对补偿结构60的相关说明可知，将断裂位置处的后部F2与第一补偿结构C1焊接导通，可以是通过断裂位置处的后部F2与第一补偿结构C1之间具有重叠区域的部分焊接导通。
示例性的，S343包括：
请继续参阅图9，将第一修复子像素P1的晶体管TFT的第一端(例如为源极S)与其耦接的数据线40断路。从而避免第一修复子像素P1的像素电极21仍被加载数据线40上的数据线信号，影响该条栅线30的正常修复。例如为切断第一修复子像素P1的晶体管TFT的第一端(例如为源极S)。
示例性的，请继续参阅图9，在上述S344中，形成独立线段50a的过程可包括以下步骤：
(1)在与选定公共电极线50’耦接的一行子像素20中，确定与修复子像素两侧相邻的两个子像素分别作为第一相邻子像素P1’和第二相邻子像素P1”。
具体的，如图9所示，沿栅线30的延伸方向，第一相邻子像素P1’为与第一修复子像素P1紧邻的前一个子像素20，第二相邻子像素P1”为与第一修复子像素P1紧邻的后一个子像素20。
(2)将选定公共电极线50’上位于第一修复子像素P1的公共电极22与位于第一相邻子像素P1’的公共电极22之间的部分切断。
(3)将选定公共电极线50’上位于第一修复子像素P1的公共电极22与位于第 二相邻子像素P1”的公共电极22之间的部分切断。
这样，形成了与第一修复子像素P1中的公共电极22电性连通的、且从选定公共电极线50’上切断出的独立线段50a。
即，将第一修复子像素P1两侧的选定公共电极线50’切断，以形成独立线段50a，从而与其他子像素20的公共电极22电性隔离开。
上述(1)、(2)和(3)仅为了区分描述的层次，并不限定上述各步骤的顺序。
示例性的，请继续参阅图9，在上述S345中：
将第一修复子像素P1的公共电极22所耦接的第一补偿结构C1与除第一修复子像素P1中的公共电极22之外的其他公共电极22断路的方式，包括：
将该第一补偿结构C1中，处于该第一补偿结构C1的第一连接部分与第二连接部分之间的部分切断。其中，第一连接部分为该第一补偿结构C1中与断裂位置处的后部F2耦接的部分。例如，当采用上述焊接的方式，将断裂位置处的后部F2与该第一补偿结构C1导通时，第一连接部分为该第一补偿结构C1与断裂位置处的后部F2焊接导通的焊接部分。其中，第二连接部分为该第一补偿结构C1中与除第一修复子像素P1的公共电极22之外的其他公共电极22耦接的部分，例如，第二连接部分为，该第一补偿结构C1中，与除第一修复子像素P1的公共电极22之外的其他公共电极22具有重叠区域的重叠部分。
将第一修复子像素P1的公共电极22所耦接的第二补偿结构C2与除第一修复子像素P1的公共电极22之外的其他公共电极22断路的方式，包括：
将该第二补偿结构C2中，处于该第二补偿结构C2所耦接的两个公共电极22之间的部分切断。
如图10所示，针对上述第四种断路位置，提供一种示例的断路修复方法，该方法与前述图7所示出的针对上述第二种断路位置提供的断路修复方法相类似，两者的连通通路均是借道第一修复子像素P1和第二修复子像素P2各自的晶体管TFT、第一修复子像素P1和第二修复子像素P2各自的像素电极21、第一修复子像素P1和第二修复子像素P2各自的公共电极22以及从选定公共电极线50’上切割出的独立线段50a，旁路断路位置。
图10所示出的针对上述第四种断路位置提供的断路修复方法与上述图7所示出的针对上述第二种断路位置提供的断路修复方法的不同之处在于：
图7所示出的针对上述第二种断路位置提供的断路修复方法，第二修复子像素P2的公共电极22与补偿结构60耦接，第一修复子像素P1的公共电极22不与补偿结构60耦接。
而图10所示出的针对上述第四种断路位置提供的断路修复方法，第一修复子像素P1的公共电极22与补偿结构60耦接，第二修复子像素P2的公共电极22不与补偿结构60耦接。
也就是说，图10所示出的针对上述第四种断路位置提供的断路修复方法，相当于图7所示出的针对上述第二种断路位置提供的断路修复方法的第一修复子像素P1和第二修复子像素P2互换了位置，即将图7所示出的针对上述第二种断路位置提供的断路修复方法中原本的第一修复子像素P1与断路位置处的前部F1耦接，第二修 复子像素P2与断路位置处的后部F2耦接，换成第二修复子像素P2与断路位置处的前部F1耦接，第一修复子像素P1与断路位置处的后部F2耦接。
因此，图10所示出的针对上述第四种断路位置提供的断路修复方法，其中，对于有关第一修复子像素P1的处理步骤可沿用图7所示出的针对上述第二种断路位置提供的断路修复方法中有关第二修复子像素P2的处理步骤；其中，对于有关第二修复子像素P2的处理步骤可沿用图7所示出的针对上述第二种断路位置提供的断路修复方法中有关第一修复子像素P1的处理步骤；其中，对于除了有关第一修复子像素P1和第二修复子像素P2的处理步骤之外的其他步骤，可沿用图7所示出的针对上述第二种断路位置提供的断路修复方法中的相应步骤。此处对于图10所示出的针对上述第四种断路位置提供的断路修复方法的具体步骤，不再用文字赘述。
如图11所示，针对上述第四种断路位置，提供再一种示例的断路修复方法，该方法与前述图8所示出的针对上述第二种断路位置提供的断路修复方法相类似，两者的连通通路均是借道一个修复子像素中的晶体管TFT、该修复子像素的像素电极21、该修复子像素的公共电极22、独立线段50a、另一个修复子像素的公共电极22、以及与另一个修复子像素的公共电极22耦接的第一补偿结构C1，旁路断路位置。
图11所示出的针对上述第四种断路位置提供的断路修复方法与上述图8所示出的针对上述第二种断路位置提供的断路修复方法的不同之处仅在于：
图8所示出的针对上述第二种断路位置提供的断路修复方法，第二修复子像素P2的公共电极22与补偿结构60耦接，第一修复子像素P1的公共电极22不与补偿结构60耦接。
而图11所示出的针对上述第四种断路位置提供的断路修复方法，第一修复子像素P1的公共电极22与补偿结构60耦接，第二修复子像素P2的公共电极22不与补偿结构60耦接。
也就是说，图11所示出的针对上述第四种断路位置提供的断路修复方法，相当于图8所示出的针对上述第二种断路位置提供的断路修复方法的第一修复子像素P1和第二修复子像素P2互换了位置，即将图8所示出的针对上述第二种断路位置提供的断路修复方法中原本的第一修复子像素P1与断路位置处的前部F1耦接，第二修复子像素P2与断路位置处的后部F2耦接，换成第二修复子像素P2与断路位置处的前部F1耦接，第一修复子像素P1与断路位置处的后部F2耦接。
因此，图11所示出的针对上述第四种断路位置提供的断路修复方法，其中，对于有关第一修复子像素P1的处理步骤可沿用图8所示出的针对上述第二种断路位置提供的断路修复方法中有关第二修复子像素P2的处理步骤。其中，对于有关第二修复子像素P2的处理步骤可沿用图8所示出的针对上述第二种断路位置提供的断路修复方法中有关第一修复子像素P1的处理步骤。其中，对于除了有关第一修复子像素P1和第二修复子像素P2的处理步骤之外的其他步骤，可沿用图8所示出的针对上述第二种断路位置提供的断路修复方法中的相应步骤。此处对于图11所示出的针对上述第四种断路位置提供的断路修复方法的具体步骤，不再用文字赘述。
如图12所示，针对上述第五种断路位置，提供一种示例的断路修复方法，该方法与上述图7所示出的针对上述第二种断路位置提供的断路修复方法相类似，两者的连通通路均是借道第一修复子像素P1和第二修复子像素P2各自的晶体管TFT、第一修复子像素P1和第二修复子像素P2各自的像素电极21、第一修复子像素P1和第二修复子像素P2各自的公共电极22以及从选定公共电极线50’上切割出的独立线段50a，旁路断路位置。
图12所示出的针对上述第五种断路位置提供的断路修复方法与上述图7所示出的针对上述第二种断路位置提供的断路修复方法的不同之处仅在于：
图7所示出的针对上述第二种断路位置提供的断路修复方法，第二修复子像素P2的公共电极22与补偿结构60耦接，第一修复子像素P1的公共电极22不与补偿结构60耦接。
而图12所示出的针对上述第五种断路位置提供的断路修复方法，第一修复子像素P1的公共电极22和第二修复子像素P2的公共电极22均与补偿结构60耦接。
也就是说，图12所示出的针对上述第四种断路位置提供的断路修复方法，相当于图7所示出的针对上述第二种断路位置提供的断路修复方法，在原有的基础上，增加了与第一修复子像素P1的公共电极22耦接的补偿结构60，即图7所示出的针对上述第二种断路位置提供的断路修复方法，第二修复子像素P2保持不变，第一修复子像素P1添加与其耦接的补偿结构60。
因此，图12所示出的针对上述第四种断路位置提供的断路修复方法，其中，对于有关第一修复子像素P1的处理步骤，除了沿用图7所示出的针对上述第二种断路位置提供的断路修复方法中有关第一复子像素P1的处理步骤之外，还包括对于与第一修复子像素P1的公共电极22耦接的补偿结构60的处理。对于与第一修复子像素P1的公共电极22耦接的补偿结构60的处理的方法，可沿用图7所示出的针对上述第二种断路位置提供的断路修复方法中有关与第二修复子像素P2的公共电极22耦接的补偿结构60的处理的方法。其中，对于除了有关第一修复子像素P1的处理步骤之外的其他步骤，可沿用图7所示出的针对上述第二种断路位置提供的断路修复方法中的相应步骤。此处对于图12所示出的针对上述第四种断路位置提供的断路修复方法的具体步骤，不再用文字赘述。
如图13所示，针对上述第五种断路位置，提供再一种示例的断路修复方法，该方法与上述图8所示出的针对上述第二种断路位置提供的断路修复方法相类似，两者的连通通路均是借道第一修复子像素P1的晶体管TFT、第一修复子像素P1的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2中的公共电极22以及与第二修复子像素P2的公共电极22耦接的第一补偿结构C1，旁路断路位置。
图13所示出的针对上述第五种断路位置提供的断路修复方法与上述图8所示出的针对上述第二种断路位置提供的断路修复方法的不同之处仅在于：
图8所示出的针对上述第二种断路位置提供的断路修复方法，第二修复子像素P2的公共电极22与补偿结构60耦接，第一修复子像素P1的公共电极22不与补偿结构60耦接。
而图13所示出的针对上述第五种断路位置提供的断路修复方法，第一修复子 像素P1的公共电极22和第二修复子像素P2的公共电极22均与补偿结构60耦接。
也就是说，图13所示出的针对上述第五种断路位置提供的断路修复方法，相当于图8所示出的针对上述第二种断路位置提供的断路修复方法，在原有的基础上，增加了与第一修复子像素P1的公共电极22耦接的补偿结构60，即图8所示出的针对上述第二种断路位置提供的断路修复方法，第二修复子像素P2保持不变，第一修复子像素P1添加与其耦接的补偿结构60。
因此，图13所示出的针对上述第五种断路位置提供的断路修复方法，其中，对于有关第一修复子像素P1的处理步骤，除了沿用图8所示出的针对上述第二种断路位置提供的断路修复方法中有关第一复子像素P1的处理步骤之外，还包括对于与第一修复子像素P1的公共电极22耦接的补偿结构60的处理。对于与第一修复子像素P1的公共电极22耦接的补偿结构60的处理的方法，可沿用图7所示出的针对上述第二种断路位置提供的断路修复方法中有关与第二修复子像素P2的公共电极22耦接的补偿结构60的处理的方法。其中，对于除了有关第一修复子像素P1的处理步骤之外的其他步骤，可沿用图8所示出的针对上述第二种断路位置提供的断路修复方法中的相应步骤。此处对于图13所示出的针对上述第五种断路位置提供的断路修复方法的具体步骤，不再用文字赘述。
如图14所示，针对上述第五种断路位置，提供另一种示例的断路修复方法，该方法与上述图8所示出的对上述第二种断路位置提供的断路修复方法相类似，两者的连通通路均是借道一个修复子像素中的晶体管TFT、该修复子像素的像素电极21、该修复子像素的其公共电极22、独立线段50a、另一个修复子像素的公共电极22以及与另一个修复子像素的公共电极22耦接的第一补偿结构C1，旁路断路位置。
图14所示出的针对上述第五种断路位置提供的断路修复方法与上述图8所示出的针对上述第二种断路位置提供的断路修复方法的不同之处仅在于：
图8所示出的针对第二种断路位置提供的断路修复方法的连通通路均是借道第一修复子像素P1的晶体管TFT、第一修复子像素P1的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22以及与第二修复子像素P2的公共电极22耦接的第一补偿结构C1，旁路断路位置。
而图14所示出的针对上述第五种断路位置提供的断路修复方法的连通通路是借道第一修复子像素P1的公共电极22耦接的第一补偿结构C1、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、第二修复子像素P2的像素电极21、以及第二修复子像素P1的晶体管TFT，旁路断路位置。
也就是说，图14所示出的针对上述第五种断路位置提供的断路修复方法，相当于图8所示出的针对上述第二种断路位置提供的断路修复方法的第一修复子像素P1和第二修复子像素P2互换了位置，且在原有的基础上，增加了与第一修复子像素P1的公共电极22耦接的补偿结构60。即，相当于将图8所示出的针对上述第二种断路位置提供的断路修复方法中原本的“第一修复子像素P1与断路位置处的前部F1耦接，第二修复子像素P2与断路位置处的后部F2耦接”，换成“第二修复子像素P2与断路位置处的前部F1耦接，第一修复子像素P1与断路位置处的后部F2耦接”，并且第二修复子像素P2保持不变，第一修复子像素P1添加与其耦接的补偿结构60。
因此，图14所示出的针对上述第五种断路位置提供的断路修复方法，其中， 对于有关第一修复子像素P1的处理步骤，可沿用图8所示出的针对上述第二种断路位置提供的断路修复方法中有关第二修复子像素P2的处理步骤。其中，对于有关第二修复子像素P2的处理步骤，除了沿用图8所示出的针对上述第二种断路位置提供的断路修复方法中有关第一复子像素P1的处理步骤之外，还包括对于与第二修复子像素P2的公共电极22耦接的补偿结构60的处理。对于与与第二修复子像素P2的公共电极22耦接的补偿结构60的处理的方法，可沿用图7所示出的针对上述第二种断路位置提供的断路修复方法中有关对与第二修复子像素P2的公共电极22耦接的补偿结构60的处理的方法。其中，对于除了有关第一修复子像素P1和第二修复子像素P2的处理步骤之外的其他步骤，可沿用图8所示出的针对上述第二种断路位置提供的断路修复方法中的相应步骤。此处对于图14针对上述第四种断路位置提供的断路修复方法的具体步骤，不再用文字赘述。
如图15所示，针对上述第五种断路位置，提供又一种示例的断路修复方法，该方法包括如下步骤：
S1：确定栅线30的断路位置(图15中标记为“Open”，表示断路)。
S2：S2包括以下S251～S252。
S251：确定与断路位置最邻近且分别处于断路位置两侧的两个连接元件L。若该两个连接元件L，其中一个为晶体管TFT，另一个为补偿结构60，且该晶体管TFT所属的子像素20与该补偿结构60所耦接的公共电极22所属的子像素20为不同的子像素，则从与断路位置所在的栅线30耦接的各子像素20中，选择该补偿结构60所耦接的公共电极22所属的子像素20作为第一修复子像素P1，选择该晶体管TFT所属的子像素20作为第二修复子像素P2。其中，第一修复子像素P1与断路位置处的前部F1耦接，第二修复子像素P2与断路位置处的后部F2耦接。
S252：确定与第一修复子像素P1和第二修复子像素P2各自的公共电极22耦接(例如为具有重叠区域)的一条公共电极线50为选定公共电极线50’。
S3：S3包括以下S351～S355。
S351：将断裂位置处的前部F1，通过与第一修复子像素P1的公共电极22耦接的第一补偿结构C1，与第一修复子像素P1的公共电极22耦接。
S352：将断裂位置处的后部F2，通过与第二修复子像素P2的公共电极22耦接的第一补偿结构C1，与第二修复子像素P2的公共电极22耦接。
S353：将第一修复子像素P1和第二修复子像素P2各自的晶体管TFT与其耦接的数据线40断路。这样可以避免第一修复子像素P1和第二修复子像素P2各自的像素电极21仍被加载数据线40上的数据线信号，影响该条栅线30的正常修复。
S354：将选定公共电极线50’与除第一修复子像素P1和第二修复子像素P2的公共电极22之外的其他公共电极22断路，以形成从选定公共电极线50’上切割出的独立线段50a。
S355：将与第一修复子像素P1的公共电极22所耦接的第一补偿结构C1及第二补偿结构C2与除第一修复子像素P1的公共电极22之外的其他公共电极断路；将与第二修复子像素P2中的公共电极22所耦接的第一补偿结构C1及第二补偿结构C2与除第二修复子像素P2中的公共电极22之外的其他公共电极断路。例如为切断该第一补偿结构C1、切断该第二补偿结构C2，以避免第一修复子像素P1的公 共电极22和第二修复子像素P2的公共电极22仍被加载公共电极线50上的公共电压信号，影响该条栅线30的正常修复。
这样一来，通过由与第一修复子像素P1的公共电极22耦接的第一补偿结构C1、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、以及与第二修复子像素P2的公共电极22耦接的第一补偿结构C1构成的连通通路，旁路断路位置，信号传输的方式可如图15中虚线箭头所示。
可以理解的是，以上S251～S252、及S351～S355并无先后顺序的限定，各步骤可以依次或同时进行，本发明实施例对此不作限定。
这样，通过以上修复方法，对发生断路的栅线进行修复后，形成的暗点仅为第一修复子像素P1和第二修复子像素P2，对整个显示面板的影响较小，修复效果较好。
当栅线30上的断路位置为上述第五种时，即该断路位置处于晶体管TFT和补偿结构60之间，且该晶体管TFT所属的子像素与该补偿结构所耦接的公共电极所属的子像素为不同的子像素，且第一修复子像素和第二修复子像素均与补偿结构耦接时，可以选择上述图12～图15示意出的任一种修复方式。
示例性的，步骤S351包括：
请继续参阅图15，将断裂位置处的前部F1和与第一修复子像素P1的公共电极22耦接的第一补偿结构C1焊接导通。
示例性的，步骤S352包括：
请继续参阅图15，将断裂位置处的后部F2和与第二修复子像素P2的公共电极22耦接的第一补偿结构C1焊接导通。
由于与第一修复子像素P1的公共电极22耦接的第一补偿结构C1，与第一修复子像素P1的公共电极22电性连通，因此，当断裂位置处的前部F1与该第一补偿结构C1焊接导通时，该断裂位置处的前部F1即与第一修复子像素P1中的公共电极22电性连通在一起。由于与第二修复子像素P2的公共电极22耦接的第一补偿结构C1，与第二修复子像素P2的公共电极22电性连通，因此，当断裂位置处的后部F2与该第一补偿结构C1焊接导通时，该断裂位置处的后部F2即与第二修复子像素P2中的公共电极22电性连通在一起了。
具体的，由前述对补偿结构60的相关说明可知，将断裂位置处的前部F1与第一补偿结构C1焊接导通，可以是通过将断裂位置处的前部F1与第一补偿结构C1之间具有重叠区域的部分焊接导通。将断裂位置处的后部F2与第一补偿结构C1焊接导通，可以是通过将断裂位置处的后部F2与第一补偿结构C1之间具有重叠区域的部分焊接导通。
在图15所示的修复方法的基础上，进一步的，考虑到发生断路的栅线30上加载的栅线信号通过上述连通通路得以继续传输后，第一修复子像素P1的公共电极22和第二修复子像素P2的公共电极22上加载的即是栅线信号，而不是该条栅线30未断路时，原本应当加载的公共电压信号，因此，第一修复子像素P1和第二修复子像素P2是难以继续正常显示的，为了避免第一修复子像素P1的像素电极21和第二修复子像素P2中的像素电极21与该子像素中加载了栅线信号的公共电极22之间产生的电场，影响第一修复子像素P1和第二修复子像素P2附近液晶分子的正 常偏转，故需要将第一修复子像素P1的晶体管TFT与该子像素中的像素电极21断路，以及需要将第二修复子像素P2中的晶体管TFT与该子像素中的像素电极21断路。
示例性的，在上述S353中：
将第一修复子像素P1的晶体管TFT与其耦接的数据线40断路的方式，包括但不限于以下三种方式：
一、将第一修复子像素P1的晶体管TFT的第一端(例如为源极S)与其耦接的数据线40断路。例如为切断第一修复子像素P1的晶体管TFT的第一端(例如为源极S)。
二、将第一修复子像素P1的晶体管TFT的第二端(例如为漏极D)与其电连接的像素电极40断路，例如为切断第一修复子像素P1的晶体管TFT的第二端(例如为漏极D)。
三、将第一修复子像素P1的晶体管TFT的第一端(例如为源极S)与其电连接的数据线40断路，并且将第一修复子像素P1的晶体管TFT的第二端(例如为漏极D)与其电连接的像素电极21断路，例如为切断第一修复子像素P1的晶体管TFT的第一端(例如为源极S)和第二端(例如为漏极D)。
将第二修复子像素P2的晶体管TFT与其耦接的数据线40断路的方式，包括但不限于以下三种方式：
一、将第二修复子像素P2中的晶体管TFT的第一端(例如为源极S)与其电连接的数据线40断路。例如为切断第二修复子像素P2的晶体管TFT的第一端(例如为源极S)。
二、将第二修复子像素P2中的晶体管TFT的第二端(例如为漏极D)与其电连接的像素电极21断路，例如为切断晶体管TFT的第二端(例如为漏极D)。
三、将第二修复子像素P2中的晶体管TFT的第一端(例如为源极S)与其电连接的数据线40断路，并且将第二修复子像素P2的晶体管TFT的第二端(例如为漏极D)与其电连接的像素电极21断路，例如为切断第二修复子像素P2的晶体管TFT的第一端(例如为源极S)和第二端(例如为漏极D)。
需要指出的是，上述图15中仅示意出“切断晶体管TFT的第一端”这一种断路的方式，对于“切断晶体管TFT的第二端”的方式，可参考图15进行理解，此处不再赘述。
示例性的，请继续参阅图15，在上述S354中，形成独立线段50a的过程可包括以下步骤：
(1)在与选定公共电极线50’耦接的一行子像素20中，确定与修复子像素两侧相邻的两个子像素分别作为第一相邻子像素P1’和第二相邻子像素P2’。
具体的，如图15所示，沿栅线30的延伸方向，第一相邻子像素P1’为与第一修复子像素P1紧邻的前一个子像素20，第二相邻子像素P2’为与第二修复子像素P2紧邻的后一个子像素20。
(2)将选定公共电极线50’上位于第一修复子像素P1中的公共电极22与位于第一相邻子像素P1’中的公共电极22之间的部分切断。
(3)将选定公共电极线50’上位于第二修复子像素P2中的公共电极22与位于 第二相邻子像素P2’中的公共电极22之间的部分切断。
这样，形成了与第一修复子像素P1和第二修复子像素P2的公共电极22均电性连通的、且从选定公共电极线50’上切断出的独立线段50a。
即，将由第一修复子像素P1与第二修复子像素P2构成的修复单元两侧的选定公共电极线50’切断，以形成独立线段50a，从而与其他子像素20的公共电极22电性隔离开。
上述(1)、(2)和(3)仅为了区分描述的层次，并不限定上述各步骤的顺序。
示例性的，请继续参阅图15，在上述S355中：
将第一修复子像素P1的公共电极22所耦接的第一补偿结构C1与除第一修复子像素P1的公共电极22之外的其他公共电极22断路的方式，包括：
将该第一补偿结构C1中，处于该第一补偿结构C1的第一连接部分与第二连接部分之间的部分切断。其中，第一连接部分为该第一补偿结构C1中与断裂位置处的前部F1耦接的部分。例如，当采用上述焊接的方式，将断裂位置处的前部F1与该第一补偿结构C1导通时，第一连接部分为该第一补偿结构C1与断裂位置处的前部F1焊接导通的焊接部分。其中，第二连接部分为该第一补偿结构C1中与除第一修复子像素P1的公共电极22之外的其他公共电极22耦接的部分，例如，第二连接部分为，该第一补偿结构C1中，与除第一修复子像素P1的公共电极22之外的其他公共电极22具有重叠区域的重叠部分。
将第一修复子像素P1的公共电极22所耦接的第二补偿结构C2与除第一修复子像素P1的公共电极22之外的其他公共电极22断路的方式，包括：
将该第二补偿结构C2中，处于该第二补偿结构C2所耦接的两个公共电极22之间的部分切断。
将第二修复子像素P2的公共电极22所耦接的第一补偿结构C1和第二补偿结构C2与除第二修复子像素P2的公共电极22之外的其他公共电极22断路的方式，和，将第一修复子像素P1的公共电极22所耦接的第一补偿结构C1和第二补偿结构C2与除第二修复子像素P2的公共电极22之外的其他公共电极22断路的方式相同，可以参考图15进行理解，此处不再用文字赘述。
示例性的，在上述S355中，将第二修复子像素P2中的公共电极22所耦接的第一补偿结构C1与除第二修复子像素P2中的公共电极22之外的其他公共电极断路的方式，可以沿用上述将第一修复子像素P1的公共电极22所耦接的第一补偿结构C1与除第一修复子像素P1的公共电极22之外的其他公共电极断路的方式，此处不再赘述。
在上述图6至图15示意出的各示例的实施方式中，焊接导通的方式包括但不限于采用激光焊接的方式，即采用具有高能量密度的激光对需要进行导通的双方具有重叠区域的部分进行熔接，从而使得熔接的部分穿透二者之间的绝缘层直接连接在一起，实现电性连通。
这里，为避免具有高能量密度的激光对阵列基板01中的其他结构产生不利影响，可以使得激光从衬底基板一侧(即激光先穿透衬底基板)对相应结构进行焊接导通。
并且，焊接导通的部位(示例的可以为激光焊接点)包括但不限于以上图6至图15中示意出的数量，只需保证相互熔接的两个导电结构能够充分地熔接在一起，以实现电性连通即可。
在上述各示例的实施方式中，切断的方式包括但不限于采用激光切断的方式，即利用具有高能量密度的激光加热相应结构，使其温度迅速上升，在非常短的时间内达到制成该结构的材料的沸点，以使材料气化，形成蒸气，这些蒸气喷出的速度很快，能够在喷出的同时，在相应结构上形成切口，从而对相应结构进行切断。
同样的，为避免具有高能量密度的激光对阵列基板01中的其他结构产生不利影响，可以使得激光从衬底基板一侧(即激光先穿透衬底基板)对相应结构进行切断。
需要说明的是，本公开实施例所提供的以上各修复方法示例中的以字母“S”表示的各步骤序号，仅仅是为了方便描述进行的编号，并不严格代表实际的步骤次序。本领域技术人员在获悉了本公开实施例的技术方案之后，有能力对步骤次序进行调整，这应当属于本公开实施例所公开的范围。
在上述栅线断路的修复方法的基础上，本公开的一些实施例提供一种阵列基板中栅线与数据线短路的修复方法，如图16至图20所示，该栅线与数据线短路的修复方法包括以下步骤：
确定栅线30与数据线40之间的短路位置(图16至图20中标记为DGS)；
沿栅线30的延伸方向，将发生短路的栅线30上紧邻短路位置的两侧切断，以形成栅线30的断路；
采用上述图6至图8、图10至图15所示意的栅线断路的修复方法，对发生断路的栅线30进行修复。
即，本公开实施例提供的上述栅线与数据线短路的修复方法，通过将栅线与数据线短路的不良转变为栅线断路的不良，然后利用上述栅线断路的修复方法进行修复，进一步扩展了对阵列基板中信号线不良的修复类型。
参见前述对栅线30上断路位置的划分方式，栅线30与数据线40短路的情况包括如下四种：
一、如图16所示，第一修复子像素P1的公共电极22和第二修复子像素P2的公共电极22均不与补偿结构60耦接。这种情况下，沿栅线30的延伸方向，将发生短路的栅线30上紧邻短路位置的两侧切断，形成栅线30的断路后，栅线30的断路位置位于两个晶体管TFT之间。
二、如图17和图18所示，第一修复子像素P1的公共电极22不与补偿结构60耦接；第二修复子像素P2的公共电极22与补偿结构60耦接。这种情况下，沿栅线30的延伸方向，将发生短路的栅线30上紧邻短路位置的两侧切断，形成栅线30的断路后，栅线30的断路位置位于两个晶体管TFT之间。
三、如图19所示，第一修复子像素P1的公共电极22与补偿结构60耦接；第二修复子像素P2的公共电极22不与补偿结构60耦接。这种情况下，沿栅线30的延伸方向，将发生短路的栅线30上紧邻短路位置的两侧切断，形成栅线30的断路后，栅线30的断路位置位于一个补偿结构60和一个晶体管TFT之间。
四、如图20所示，第一修复子像素P1的公共电极22和第二修复子像素P2的 公共电极22均与补偿结构60耦接。这种情况下，沿栅线30的延伸方向，将发生短路的栅线30上紧邻短路位置的两侧切断，形成栅线30的断路后，栅线30的断路位置位于一个补偿结构60和一个晶体管TFT之间。
对于情况一，即图16示意出的栅线与数据线短路的位置，修复的过程请参见前述图6所示出的栅线断路的修复方法的相关说明；对于情况二，即图17和图18示意出的栅线与数据线短路的位置，修复的过程请参见前述图7和图8所示出的栅线断路的修复方法的相关说明；对于情况三，即图19示意出的栅线与数据线短路的位置，修复的过程请参见前述图10和图11所示出的栅线断路的修复方法的相关说明；对于情况四，即图20示意出的栅线与数据线短路的位置，修复的过程请参见前述图12～图15所示出的栅线断路的修复方法的相关说明；此处对于具体步骤均不再赘述。
可以理解的是，在本公开实施例提供的上述将栅线与数据线短路转变为栅线断路进行修复的方法中，适用的阵列基板01中，栅线30与数据线40交叉处可参考图1的设计，即如图1中栅线30与数据线40交叉处的虚线框所示，栅线30上与数据线40交叉的区域的宽度，小于栅线30上的其他区域的宽度，即栅线30被分为较宽区域和较窄区域，且较宽区域和较窄区域间隔设置。
这样，便于对栅线30与数据线40之间的短路位置进行切割，还可以减少栅线30与数据线40交叉的重叠区域面积，降低二者之间的寄生电容。
并且，为避免具有高能量密度的激光对阵列基板01中的数据线40产生不利影响，可以使得激光从衬底基板一侧(即激光先穿透衬底基板)对栅线30进行切断。由此，为便于对栅线30与数据线40之间的短路位置进行切割，可将栅线30设置在数据线40下方，即相对于数据线40，栅线30更靠近于阵列基板01的衬底基板。
在上述各实施例的基础上，本公开的一些实施例提供一种阵列基板中栅线断路的修复结构，该修复结构经如图6～图15所对应的栅线断路的修复方法中的任一修复方法进行修复得到，或者该修复结构经如图16～图20所对应的栅线与数据线短路的修复方法中的任一修复方法进行修复得到。
请参见图6，上述修复结构100包括：断路的栅线30、一个或两个修复子像素、及选定公共电极线50’。
其中，对于一个断路位置，断路的栅线30包括断路位置(Open)处的前部F1和后部F2。
一个或两个修复子像素，例如为第一修复子像素P1和/或第二修复子像素P2，每个修复子像素包括晶体管TFT、像素电极21和公共电极22。
选定公共电极线50’为，阵列基板01的多条公共电极线50中，与各修复子像素的公共电极22耦接的一条公共电极线。选定公共电极线50’包括与各修复子像素的公共电极22耦接的独立线段50a，独立线段50a为对选定公共电极线50’进行切割得到一段公共电极线，独立线段50a不与选定公共电极线50’的其它部分耦接。
在上述修复结构100中，断路位置处的前部F1与后部F2之间具有连通通路，该连通通路被配置为旁路该断路位置。该连通通路经上述任一实施例所述的修复方法形成，该连通通路至少包括各修复子像素的公共电极22，及选定公共电极线50’中的独立线段50a。且该连通通路中的公共电极22不与其他公共电极耦接，且各修 复子像素不与数据线40耦接。
这样，利用上述修复结构100中所形成的连通通路旁路栅线30的断路位置，可修复栅线30上发生的断路，保证栅线30能够向其所耦接的一行子像素中除修复子像素外的其它子像素正常传输扫描信号，从而使得其它子像素能够正常打开或关闭。
如图6～图14所示，在一些实施例中，连通通路至少包括一个修复子像素的晶体管TFT和像素电极21，各修复子像素的公共电极22，及选定公共电极线50’中的独立线段50a。
示例性的，如图6所示，修复结构100包括两个修复子像素，分别为：与断路位置的前部F1耦接的第一修复子像素P1，和与断路位置的后部F2耦接的第二修复子像素P2，且第二修复子像素P2的公共电极22不与补偿结构耦接。
断裂位置处的前部F1，通过第一修复子像素P1的晶体管TFT的第二端、及该子像素的像素电极21，与该子像素的公共电极22耦接。断裂位置处的后部F2，通过第二修复子像素P2的晶体管的第二端、及该子像素的像素电极21，与该子像素的公共电极22耦接。
这样，由第一修复子像素P1的晶体管TFT的第二端、第一修复子像素P1的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、第二修复子像素P2的像素电极21、以及第二修复子像素P2的晶体管TFT的第二端，在断路位置处的前部F1与后部F2之间形成连通通路。
图6所示出的修复结构的具体结构，可参见上面关于图6所对应的修复方法的描述，此处不再重复叙述。
示例性的，如图7所示，修复结构包括两个修复子像素，分别为：与断路位置的前部F1耦接的第一修复子像素P1，和与断路位置的后部F2耦接的第二修复子像素P2，且第二修复子像素P2的公共电极22与补偿结构耦接。
与第二修复子像素P2的公共电极22耦接的补偿结构包括：经过断路位置所在的栅线30的第一补偿结构C1，及经过选定公共电极线50’的第二补偿结构C2。
断裂位置处的前部F1，通过第一修复子像素P1的晶体管TFT的第二端、及该子像素的像素电极21，与该子像素的公共电极22耦接。断裂位置处的后部F2，通过第二修复子像素P2的晶体管TFT的第二端、及该子像素的像素电极21，与该子像素的公共电极22耦接。
第一补偿结构C1和第二补偿结构C2均不与除第二修复子像素P2以外的其它子像素的公共电极22耦接。
这样，由第一修复子像素P1的晶体管TFT的第二端、第一修复子像素P1的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、第二修复子像素P2的像素电极21、以及第二修复子像素P2的晶体管TFT的第二端，在断路位置处的前部F1与后部F2之间形成连通通路。
图7所示出的修复结构的具体结构，可参见上面关于图7所对应的修复方法的描述，此处不再重复叙述。
示例性的，如图8所示，修复结构包括两个修复子像素，分别为：与断路位置的前部F1耦接的第一修复子像素P1，和与断路位置的后部F2耦接的第二修复子像 素P2，且第二修复子像素P2的公共电极22与补偿结构耦接。
与第二修复子像素P2的公共电极22耦接的补偿结构包括：经过断路位置所在的栅线30的第一补偿结构C1，及经过选定公共电极线50’的第二补偿结构50a。
断裂位置处的前部F1，通过第一修复子像素P1的晶体管TFT的第二端、及该子像素的像素电极21，与该子像素的公共电极22耦接。断裂位置处的后部F2，通过第二修复子像素P2的公共电极22所耦接的第一补偿结构C1，与该子像素的公共电极22耦接。
第一补偿结构C1和第二补偿结构C2均不与除第二修复子像素P2以外的其它子像素的公共电极22耦接。
这样，由第一修复子像素P1的晶体管TFT的第二端、第一修复子像素P1的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、以及与第二修复子像素P2的公共电极22耦接的第一补偿结构C1，在断路位置处的前部F1与后部F2之间形成连通通路。
图8所示出的修复结构的具体结构，可参见上面关于图8所对应的修复方法的描述，此处不再重复叙述。
示例性的，如图9所示，修复结构包括一个修复子像素，及第一修复子像素P1，该修复子像素与断路位置的前部F1耦接，且该修复子像素与补偿结构耦接。
与该修复子像素的公共电极22耦接的补偿结构包括：经过断路位置所在的栅线30的第一补偿结构C1，及经过选定公共电极线50’的第二补偿结构C2。
断裂位置处的前部F1，通过该修复子像素的晶体管TFT的第二端、及该子像素的像素电极21，与该子像素的公共电极22耦接。断裂位置处的后部，通过该修复子像素的公共电极22所耦接的第一补偿结构C1，与该子像素的公共电极22耦接。
第一补偿结构C1和第二补偿结构C2均不与除该修复子像素以外的其它子像素的公共电极22耦接。
这样，由第一修复子像素P1的晶体管TFT的第二端、第一修复子像素P1中的像素电极21、第一修复子像素P1的公共电极22、独立线段50a、以及与第一修复子像素P1的公共电极22耦接的第一补偿结构C1，在断路位置处的前部F1与后部F2之间形成连通通路。
图9所示出的修复结构的具体结构，可参见上面关于图9所对应的修复方法的描述，此处不再重复叙述。
示例性的，图10～图14示出了另外的一些修复结构，这些修复结构的具体结构参见上面关于图10～图14所对应的修复方法的描述，此处不再重复叙述。
如图15所示，在另一些实施例中，连通通路中不包括各修复子像素的晶体管TFT和像素电极，而是由各修复子像素的公共电极22耦接的补偿结构、各修复子像素的公共电极22、及选定公共电极线50’中的独立线段50a形成。
示例性的，如图15所示，修复结构包括两个修复子像素，分别为：与断路位置的前部F1耦接的第一修复子像素P1，和与断路位置的后部F2耦接的第二修复子像素P2，且第一修复子像素P1和第二修复子像素P2均与补偿结构耦接。
与第一修复子像素P1的公共电极22耦接的补偿结构，及与第二修复子像素P1的公共电极22耦接的补偿结构均包括：经过断路位置所在的栅线30的第一补偿结 构C1，及经过选定公共电极线50’的第二补偿结构C2。
断裂位置处的前部F1，通过与第一修复子像素P1的公共电极22所耦接的第一补偿结构C1，与该子像素的公共电极22耦接。断裂位置处的后部F2，通过与第二修复子像素P2的公共电极22所耦接的第一补偿结构C1，与该子像素的公共电极22耦接。
与第一修复子像素P1的公共电极22耦接的第一补偿结构C1和第二补偿结构C2不与除该修复子像素以外的其它子像素的公共电极22耦接。与第二修复子像素P2的公共电极22耦接的第一补偿结构C1和第二补偿结构C2不与除该修复子像素以外的其它子像素的公共电极22耦接。
这样，由与第一修复子像素P1的公共电极22耦接的第一补偿结构C1、第一修复子像素P1的公共电极22、独立线段50a、第二修复子像素P2的公共电极22、以及与第二修复子像素P2的公共电极22耦接的第一补偿结构C1，在断路位置处的前部F1与后部F2之间形成连通通路。
如图15所示出的修复结构的具体结构，可参见上面关于图15所对应的修复方法的描述，此处不再重复叙述。
在上述各实施例所述的修复结构的基础上，本公开的一些实施例提供一种阵列基板，如图6～图15、及图16～图20所示，该阵列基板01包括至少一个上述修复结构。
例如，在该阵列基板01中的栅线断路不良及栅线与数据线短路不良均采用上述修复结构进行修复的情况下，该阵列基板01中所包括的修复结构的数量，与该阵列基板01中所存在的栅线断路不良和栅线与数据线短路不良的数量之和相等，一个修复结构对应一个栅线断路不良或者一个栅线与数据线短路不良。
上述阵列基板01还包括多条栅线30、多条数据线50、多个子像素60等元件或结构，具体结构可参阅前面关于阵列基板01的结构的描述，此处不再重复叙述。
在上述各实施例的基础上，本公开的一些实施例提供一种显示装置1A，如图21所示，显示装置1A包括：包括阵列基板01，该阵列基板01经过如上所述的栅线断路的修复方法修复，或者经过如上所述的栅线与数据线短路的修复方法修复。也即，该阵列基板01为如上述实施例所提供的阵列基板01。
请继续参阅图21，在一些实施例中，该显示装置1A为液晶显示装置，该显示装置1A还可包括：与该阵列基板01相对设置的对向基板02；以及，位于阵列基板01与对盒基板02之间的液晶层03。
示例性的，该对向基板02可以为彩膜基板；或者，当该阵列基板01为COA(color filter on array)型阵列基板时，即阵列基板01上制作有彩色滤色膜时，对向基板02可以为盖板，例如为盖板玻璃(Cover glass)。
在上述显示装置1A为液晶显示装置的情况下，在上述阵列基板01中，每个子像素均包括有像素电极和公共电极，该阵列基板01与对向基板02对盒封装形成液晶显示装置所包括的液晶显示面板后，该液晶显示面板可以为AD-SDS型(Advanced-Super Dimensional Switching，高级超维场开关)面板，通过位于阵列基板侧的像素电极与公共电极之间产生的边缘电场，使电极间以及电极上方的取向液晶分子都能在平行于显示面板显示面的平面方向内发生偏转，从而可在增大视角 的同时提高液晶层的透光效率。
上述显示装置1A还可包括提供背光的背光模组、驱动电路部分等，具体结构此处不再赘述。
本公开实施例提供的显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图画的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置包括但不限于移动电话、无线装置、个人数据助理(Portable Android Device，缩写为PAD)、手持式或便携式计算机、GPS(Global Positioning System，全球定位系统)接收器/导航器、相机、MP4(全称为MPEG-4 Part 14)视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于显示一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可想到的变化或替换，都应涵盖在本公开的保护范围之内。

Claims (20)

  1. 一种阵列基板中栅线断路的修复方法，所述阵列基板包括：多个子像素、多条栅线、多条数据线、多条公共电极线和多个补偿结构；其中，每个子像素包括：晶体管、像素电极和公共电极；一行子像素的各晶体管与同一条栅线耦接，一列子像素的各晶体管与同一条数据线耦接；一行子像素的各公共电极与同一条公共电极线耦接；所述多个子像素的各公共电极通过所述多条公共电极线和所述多个补偿结构电性连通；
    所述栅线断路的修复方法包括：
    确定栅线的断路位置；
    沿所述断路位置所在的栅线的延伸方向，确定与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件；其中，所述两个连接元件为，与所述断路位置所在的栅线耦接的各晶体管，及跨越该栅线且与该栅线所耦接的子像素的公共电极耦接的各补偿结构中的两个元件；
    从与所述断路位置所在的栅线耦接的各子像素中，选择与所确定的两个连接元件电连接的一个或两个子像素作为修复子像素；确定与各所述修复子像素的公共电极耦接的公共电极线为选定公共电极线；
    在所述断路位置处的前部与后部之间形成连通通路，以利用所述连通通路旁路所述断路位置；所述连通通路至少包括各所述修复子像素的公共电极，及从所述选定公共电极线上切割出的独立线段；
    将所述连通通路中的公共电极与其他公共电极断路，将各所述修复子像素与其所耦接的数据线断路。
  2. 根据权利要求1所述的栅线断路的修复方法，其中，所述连通通路至少包括一个所述修复子像素的晶体管和像素电极，各所述修复子像素的公共电极，及从所述选定公共电极线上切割出的独立线段；或者，
    所述连通通路至少包括一个所述修复子像素的公共电极所耦接的补偿结构，各所述修复子像素的公共电极，及从所述选定公共电极线上切割出的独立线段。
  3. 根据权利要求1所述的栅线断路的修复方法，其中，
    每相邻两条栅线之间设置有一条公共电极线；
    所述多个补偿结构分为多组，每组补偿结构包括沿列方向间隔设置的若干个补偿结构；每组补偿结构的各补偿结构与一列子像素的各公共电极交替设置，将该列子像素的各公共电极串接；
    与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管；或者，一个晶体管和一个补偿结构。
  4. 根据权利要求3所述的栅线断路的修复方法，其中，所述从与所述断路位置所在的栅线耦接的各子像素中，选择与所确定的两个连接元件相关的一个或两个子像素作为修复子像素，包括：
    若与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管，则选择这两个晶体管各自所属的子像素作为第一修复子像素和第二修复子像素；
    若与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为一个晶体管和一个补偿结构，且该晶体管所属的子像素与该补偿结构所耦接的公共电极所属的子像素为不同的子像素，则选择该补偿结构所耦接的公共电极所属的子像素作为第一修复子像素，选择该晶体管所属的子像素作为第二修复子像素；
    若与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为一个晶体管和一个补偿结构，且该晶体管所属的子像素与该补偿结构所耦接的公共电极所属的子像素为相同的子像素，则选择该晶体管所属的子像素作为第一修复子像素；
    其中，所述第一修复子像素与所述断路位置处的前部耦接，所述第二修复子像素与所述断路位置处的后部耦接。
  5. 根据权利要求4所述的栅线断路的修复方法，其中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管，且所述第二修复子像素的公共电极不与补偿结构耦接的情况下，
    所述在所述断路位置处的前部与后部之间形成连通通路，包括：
    将所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    将所述断裂位置处的后部，通过所述第二修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接。
  6. 根据权利要求4所述的栅线断路的修复方法，其中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管，且所述第二修复子像素的公共电极与补偿结构耦接的情况下，
    其中，与所述第二修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；
    所述在所述断路位置处的前部与后部之间形成连通通路，包括：
    将所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    将所述断裂位置处的后部，通过所述第二修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接。
  7. 根据权利要求4所述的栅线断路的修复方法，其中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为两个晶体管，且所述第二修复子像素的公共电极与补偿结构耦接的情况下，
    其中，与所述第二修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；
    所述在所述断路位置处的前部与后部之间形成连通通路，包括：
    将所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    将所述断裂位置处的后部，通过所述第二修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接。
  8. 根据权利要求6或7所述的栅线断路的修复方法，其中，所述将所述连通通路中的公共电极与其他公共电极断路，包括：
    将所述第二修复子像素的公共电极所耦接的第一补偿结构及第二补偿结构与除所述第二修复子像素的公共电极之外的其他公共电极断路。
  9. 根据权利要求4所述的栅线断路的修复方法，其中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为一个晶体管和一个补偿结构，且该晶体管所属的子像素与该补偿结构所耦接的公共电极所属的子像素为相同的子像素的情况下，
    其中，与所述第一修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；
    所述在所述断路位置处的前部与后部之间形成连通通路，包括：
    将所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    将所述断裂位置处的后部，通过所述第一修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接。
  10. 根据权利要求9所述的栅线断路的修复方法，其中，所述将所述连通通路中的公共电极与其他公共电极断路，包括：
    将所述第一修复子像素的公共电极所耦接的第一补偿结构及第二补偿结构与除所述第一修复子像素的公共电极之外的其他公共电极断路。
  11. 根据权利要求4所述的栅线断路的修复方法，其中，在与所述断路位置最邻近且分别处于所述断路位置两侧的两个连接元件为一个晶体管和一个补偿结构，且该晶体管所属的子像素与该补偿结构所耦接的公共电极所属的子像素为不同的子像素，且所述第一修复子像素和所述第二修复子像素均与补偿结构耦接的情况下，
    其中，与所述第一修复子像素的公共电极耦接的补偿结构，及与所述第二修复子像素的公共电极耦接的补偿结构均包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；
    所述在所述断路位置处的前部与后部之间形成连通通路，包括：
    将所述断裂位置处的前部，通过与所述第一修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接；
    将所述断裂位置处的后部，通过与所述第二修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接。
  12. 根据权利要求11所述的栅线断路的修复方法，其中，所述将所述连通通路中的公共电极与其他公共电极断路，包括：
    将所述第一修复子像素的公共电极所耦接的第一补偿结构及第二补偿结构与除所述第一修复子像素的公共电极之外的其他公共电极断路；
    将所述第二修复子像素的公共电极所耦接的第一补偿结构及第二补偿结构与除所述第二修复子像素的公共电极之外的其他公共电极断路。
  13. 一种阵列基板中栅线断路的修复结构，所述修复结构经如权利要求1～12中任一项所述的修复方法进行修复得到；所述修复结构包括：
    断路的栅线，所述栅线包括断路位置处的前部和后部；
    一个或两个修复子像素，每个所述修复子像素包括晶体管、像素电极和公共电极；
    选定公共电极线，所述选定公共电极线包括与各所述修复子像素的公共电极耦接的独立线段，所述独立线段不与所述选定公共电极线的其它部分耦接；
    其中，所述断路位置处的前部与后部之间具有连通通路，所述连通通路被配置为旁路所述断路位置；所述连通通路至少包括各所述修复子像素的公共电极，及所述选定公共电极线中的独立线段；
    所述连通通路中的公共电极不与其他公共电极耦接，且各所述修复子像素不与数据线耦接。
  14. 根据权利要求13所述的修复结构，其中，所述连通通路至少包括一个所述修复子像素的晶体管和像素电极，各所述修复子像素的公共电极，及所述选定公共电极线中的独立线段。
  15. 根据权利要求14所述的修复结构，其中，所述修复结构包括两个修复子像素，分别为：与所述断路位置的前部耦接的第一修复子像素，和与所述断路位置的后部耦接的第二修复子像素，且所述第二修复子像素的公共电极不与补偿结构耦接；
    所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    所述断裂位置处的后部，通过所述第二修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接。
  16. 根据权利要求14所述的修复结构，其中，所述修复结构包括两个修复子像素，分别为：与所述断路位置的前部耦接的第一修复子像素，和与所述断路位置的后部耦接的第二修复子像素，且所述第二修复子像素的公共电极与补偿结构耦接；
    与所述第二修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；
    所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    所述断裂位置处的后部，通过所述第二修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    所述第一补偿结构和所述第二补偿结构均不与除所述第二修复子像素以外的其它子像素的公共电极耦接。
  17. 根据权利要求14所述的修复结构，其中，所述修复结构包括两个修复子像素，分别为：与所述断路位置的前部耦接的第一修复子像素，和与所述断路位置的后部耦接的第二修复子像素，且所述第二修复子像素的公共电极与补偿结构耦接；
    与所述第二修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；
    所述断裂位置处的前部，通过所述第一修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    所述断裂位置处的后部，通过所述第二修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接；
    所述第一补偿结构和所述第二补偿结构均不与除所述第二修复子像素以外的其它子像素的公共电极耦接。
  18. 根据权利要求14所述的修复结构，其中，所述修复结构包括一个修复子像素，该修复子像素与所述断路位置的前部耦接，且该修复子像素与补偿结构耦接；
    与该修复子像素的公共电极耦接的补偿结构包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；
    所述断裂位置处的前部，通过该修复子像素的晶体管的第二端、及该子像素的像素电极，与该子像素的公共电极耦接；
    所述断裂位置处的后部，通过该修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接；
    所述第一补偿结构和所述第二补偿结构均不与除该修复子像素以外的其它子像素的公共电极耦接。
  19. 根据权利要求13所述的修复结构，其中，所述修复结构包括两个修复子像素，分别为：与所述断路位置的前部耦接的第一修复子像素，和与所述断路位置的后部耦接的第二修复子像素，且所述第一修复子像素和所述第二修复子像素均与补偿结构耦接；
    与所述第一修复子像素的公共电极耦接的补偿结构，及与所述第二修复子像素的公共电极耦接的补偿结构均包括：经过所述断路位置所在的栅线的第一补偿结构，及经过所述选定公共电极线的第二补偿结构；
    所述断裂位置处的前部，通过与所述第一修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接；
    所述断裂位置处的后部，通过与所述第二修复子像素的公共电极所耦接的第一补偿结构，与该子像素的公共电极耦接；
    与所述第一修复子像素的公共电极耦接的第一补偿结构和第二补偿结构不与除该修复子像素以外的其它子像素的公共电极耦接；与所述第二修复子像素的公共电极耦接的第一补偿结构和第二补偿结构不与除该修复子像素以外的其它子像素的公共电极耦接。
  20. 一种阵列基板中栅线与数据线短路的修复方法，包括：
    确定栅线与数据线之间的短路位置；
    沿所述栅线的延伸方向，将发生短路的所述栅线上紧邻所述短路位置的两侧切断，以使所述栅线形成断路；
    采用如权利要求1～8、11、12中任一项所述的栅线断路的修复方法，对发生断路的所述栅线进行修复。
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