WO2020082736A1 - 计数方法、计数装置以及应用其的计数系统和像素阵列 - Google Patents

计数方法、计数装置以及应用其的计数系统和像素阵列 Download PDF

Info

Publication number
WO2020082736A1
WO2020082736A1 PCT/CN2019/089764 CN2019089764W WO2020082736A1 WO 2020082736 A1 WO2020082736 A1 WO 2020082736A1 CN 2019089764 W CN2019089764 W CN 2019089764W WO 2020082736 A1 WO2020082736 A1 WO 2020082736A1
Authority
WO
WIPO (PCT)
Prior art keywords
storage units
counting
storage
module
count
Prior art date
Application number
PCT/CN2019/089764
Other languages
English (en)
French (fr)
Inventor
雷述宇
Original Assignee
宁波飞芯电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 宁波飞芯电子科技有限公司 filed Critical 宁波飞芯电子科技有限公司
Priority to CN201980050603.3A priority Critical patent/CN112955955B/zh
Publication of WO2020082736A1 publication Critical patent/WO2020082736A1/zh
Priority to US17/239,594 priority patent/US11950004B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/713—Transfer or readout registers; Split readout registers or multiple readout registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the invention relates to the field of microelectronics, in particular to a counting method, counting device, and counting system and pixel array using the same.
  • the dynamic range is one of the important indicators of the sensor pixel array.
  • the high dynamic range sensor is helpful to meet the requirements of high precision and helps to improve the response range of the sensor, especially for the image sensor.
  • the counting method used by the sensor for circuit integration directly affects the dynamic range of the sensor, which in turn affects the overall performance of the sensor.
  • the counting device used by the existing sensors for circuit integration is usually an asynchronous counter or a synchronous counter composed of D flip-flops.
  • D flip-flops usually have two states, such as 0 and 1, which enables the D flip-flop to flip from one state to another state to trigger the corresponding settings.
  • the existing counting device is also provided with two latches to cooperate with the flip operation between the two states of the D flip-flop, such as the 4-bit asynchronous counter composed of the cascade of D flip-flops shown in FIG. 1.
  • the counting device of this structure occupies a large area, and if it is set inside the pixel, it will occupy more pixel area, which causes certain difficulties in optimizing the pixel area; if it is set outside the pixel, the purpose of improving the dynamic range cannot be achieved, resulting in the sensor Small range and poor sensor performance.
  • the current counting method used by the sensor for circuit integration has the problems that the D trigger occupies a large internal area of the sensor and the dynamic range is small, which greatly reduces the performance of the sensor. Therefore, it is urgent to design a counting scheme to solve the above technical problems.
  • the embodiments of the present application provide a counting method, a counting device, a counting system and a pixel array using the same, to reduce the internal area of the sensor occupied by the counting circuit, and improve the dynamic range and performance of the sensor.
  • the present invention proposes a counting method, counting device, and counting system and pixel array using the same.
  • a counting device in a first aspect of an embodiment of the present invention, includes at least a storage module and an arithmetic module.
  • the storage module includes a plurality of cascaded storage units, wherein the plurality of storage units store a plurality of accumulated count intermediate values, the plurality of storage units are configured as at least one group of storage units, and the number of storage units in each group of storage units is greater than the corresponding The number of accumulated count intermediate values in the group of storage units;
  • the arithmetic module is connected to the first and last group of storage units in the plurality of storage units, and is used to calculate the intermediate value of the accumulated count input through the last group of storage units according to the received count value The value is calculated to obtain the current accumulated count intermediate value of the corresponding counting object and output to the first group of storage units in the cascaded storage units.
  • a plurality of accumulated count intermediate values are cyclically shifted to the calculation module and the corresponding count value for calculation, and until the end of counting, the plurality of current accumulated count intermediate values stored in the storage module are used as the plurality of accumulated count results corresponding to the counting object.
  • the counting device further includes a control module, connected to the storage module, for outputting a row selection control signal, the row selection control signal is used to control the storage in the plurality of storage units Cyclic displacement between multiple cumulative count intermediate values.
  • multiple storage units are configured as multiple sets of storage units, and the storage units at preset positions in the multiple sets of storage units are controlled by the same row selection control signal.
  • the plurality of memory cells are further configured such that each group of memory cells includes at least two memory cells, and different memory cells in the same group correspond to different row selection control signals.
  • the row selection control signal is used to control a cyclic displacement between a plurality of accumulated count intermediate values stored in the plurality of storage units, specifically: the row selection control signal is sequentially output , For gating the storage unit controlled by the output row selection control signal; and, for a gated storage unit, the current cumulative count intermediate value of the storage unit is replaced by the storage unit in the preset direction The intermediate value of the cumulative count currently stored by the connected storage unit, or replaced by the intermediate value of the current cumulative count output by the arithmetic module connected to the storage unit in a preset direction.
  • the counting device further includes an output module, connected to the arithmetic module, for outputting the plurality of cumulative counting results.
  • control unit is specifically configured to: output a plurality of row selection control signals corresponding to the plurality of storage units in a preset order, wherein one row selection control signal corresponds to at least one storage unit
  • the storage module is specifically used to: receive row selection control signals corresponding to different storage units, and cyclically output the plurality of cumulative counting results to the arithmetic module; the output module is specifically used to: receive and output the Multiple cumulative count results.
  • each memory cell is further configured with at least one latch, wherein the number of latches included in different memory cells is the same, and the latches at corresponding positions of different memory cells are cascaded in sequence.
  • the arithmetic module is configured with at least one arithmetic unit, and the number of arithmetic units configured by the arithmetic module is consistent with the number of latches included in the storage unit, each The arithmetic units are respectively cascaded with latches at corresponding positions in the first and last storage units.
  • the arithmetic unit is configured as a half adder or half subtractor.
  • a counting method is provided, which is applied to the counting device according to any one of the first aspect, the counting device includes a storage module and an arithmetic module, and the storage module includes a cascade A plurality of storage units, the arithmetic module is connected to the first and last groups of storage units in the plurality of storage units, wherein the plurality of storage units store a plurality of cumulative count intermediate values, the plurality of storage units are It is configured as at least one group of storage units, and the number of storage units in each group of storage units is greater than the number of intermediate values corresponding to the cumulative count of the group of storage units; the counting method includes:
  • Each cycle of cyclic displacement performs at least one of the following processes:
  • the output is output to the first group of storage units in the cascade for storage.
  • the method further includes: outputting a row selection control signal to the storage unit through the control unit; and controlling a plurality of accumulated count intermediate values stored in the plurality of storage units through the row selection control signal Cyclic displacement between.
  • the plurality of storage units are configured as multiple groups of storage units, and the storage units at preset positions in the multiple groups of storage units are controlled by the same row selection control signal.
  • the plurality of memory cells are further configured such that each group of memory cells includes at least two rows of memory cells, and different memory cells in the same group correspond to different row selection control signals.
  • the controlling the cyclic displacement between the multiple cumulative count intermediate values stored in the multiple storage units by the row selection control signal includes: The plurality of storage units sequentially output the row selection control signal to gate the storage unit controlled by the output row selection control signal; and for a gated storage unit, the current cumulative count of the storage unit is intermediate The value is replaced with the intermediate value of the cumulative count currently stored by the storage unit connected to the storage unit in the preset direction, or replaced by the intermediate value of the current cumulative count output by the arithmetic module connected to the storage unit in the preset direction.
  • the counting device further includes: outputting the plurality of cumulative counting results through an output module.
  • the method before outputting the plurality of accumulated count results through the output module, the method further includes: outputting a plurality of row selection control signals corresponding to the plurality of storage units in a preset order through the control unit, One of the row selection control signals corresponds to at least one storage unit; the row selection control signals corresponding to different storage units are received through the storage module, and the multiple cumulative counting results are cyclically output to the arithmetic module; Outputting the plurality of accumulated count results includes receiving and outputting the plurality of accumulated count results through the output module.
  • each memory cell is further configured with at least one latch, wherein the number of latches included in different memory cells is the same, and the latches at corresponding positions of different memory cells are cascaded in sequence.
  • the operation module is configured with at least one operation unit, and the number of operation units configured by the operation module is consistent with the number of latches included in the storage unit, each The arithmetic units are respectively cascaded with latches at corresponding positions in the first and last storage units.
  • the arithmetic unit is configured as a half adder or half subtractor.
  • the plurality of accumulated count results are used to indicate the total amount of charge collected by the charge storage units in the plurality of pixels.
  • the method further includes: comparing the integrated voltage converted by the current charge amount collected by the charge storage units in the plurality of pixels with a preset reference voltage through a comparison unit to obtain a current count value.
  • a counting system including at least one counting device as in any one of the first aspects.
  • a pixel array is provided, and a plurality of pixels in the pixel array are connected to the counting device according to any one of the first aspects to determine the plurality of pixels in the pixel array The amount of charge collected.
  • a plurality of cascaded storage units and a common arithmetic module are provided, and a plurality of corresponding counting objects obtained by the common arithmetic module are stored in the multiple storage units in a cyclic shift manner
  • the accumulated counting result enables each storage unit to replace the corresponding multiple latches of the D flip-flop in the prior art to realize the function of storing the count value, thereby greatly reducing the area of the storage module in the counting device and improving the sensor ’s Dynamic range; and, by sharing the arithmetic modules, the area required by the counting device is further reduced, which facilitates the optimization of the structure of the sensor.
  • the area of the counting device required for multiple counting objects can be effectively reduced, and the measuring range of the counting device can be increased, thereby improving the dynamic range of the sensor and the sensor
  • the performance helps to realize the circuit elements composed of multiple counting objects in small pixels.
  • FIG. 1 is a schematic diagram schematically showing a structure of a counting circuit provided in the prior art
  • FIG. 2 is a schematic structural diagram schematically showing a counting device according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram schematically illustrating another counting device according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram schematically showing a storage module according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram schematically showing a structure of a latch according to an embodiment of the present invention.
  • FIG. 6 is a timing diagram schematically showing a row selection control signal according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram illustrating a data flow of multiple sets of storage units involved in an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of a counting method according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a counting system according to an embodiment of the present invention.
  • the dynamic range is one of the important indicators of the sensor.
  • the high dynamic range sensor is helpful to meet the requirements of high-precision measurement, which helps to improve the measurement range of the sensor, especially to improve the measurement range of the image sensor.
  • the counting method used by the sensor for circuit integration limits the sensor's circuit design, area optimization, etc., which affects the sensor's area, response speed, dynamic range, and other parameters, and further affects the overall performance of the sensor.
  • the counting device used by the existing sensors for circuit integration is usually an asynchronous counter or a synchronous counter composed of D flip-flops, but this structure will occupy a large area inside the sensor, resulting in a certain optimization of the sensor area. difficult.
  • the dynamic range of the sensor is limited to the dynamic range of the D flip-flop, resulting in a small dynamic range of the sensor and poor sensor performance.
  • the present application provides a counting device, method, system and pixel array to reduce the internal area of the sensor occupied by the counting circuit and improve the dynamic range and performance of the sensor.
  • the counting device includes a storage module and an arithmetic module.
  • the storage module includes a plurality of cascaded storage units, wherein the plurality of storage units store a plurality of accumulated count intermediate values, the plurality of storage units are configured as at least one group of storage units, and the number of storage units in each group of storage units is greater than the corresponding The number of accumulated count intermediate values in the group of storage units; the arithmetic module is connected to the first and last group of storage units in the plurality of storage units, and is used for receiving the count value and the accumulated count intermediate value input through the last group of storage units Perform an operation to obtain the current accumulated count intermediate value of the corresponding counting object, and output it to the first group of storage units in the cascaded storage units.
  • a plurality of accumulated count intermediate values are cyclically shifted to the calculation module and the corresponding count value for calculation, and until the end of counting, the plurality of current accumulated count intermediate values stored in the storage module are used as the plurality of accumulated count results corresponding to the counting object.
  • the counting device provided by the present application is provided with a plurality of cascaded storage units and a common arithmetic module, and the multiple cumulative counting results corresponding to the counting object obtained by the common arithmetic module are stored in the multiple storage units in a cyclic shift manner So that each storage unit can replace the corresponding multiple latches of the D flip-flop in the prior art to realize the function of storing the count value, thereby greatly reducing the area of the storage module in the counting device and improving the dynamic range of the sensor; Moreover, by sharing the arithmetic modules, the area required by the counting device is further reduced, which facilitates the optimization of the structure of the sensor.
  • the area of the counting device required for multiple counting objects can be effectively reduced, and the counting device can be improved.
  • Measurement range which improves the sensor's dynamic range and sensor performance, and helps to implement circuit elements composed of multiple counting objects in small pixels.
  • the device, method, system and pixel array are based on the same inventive concept. Since the principles of the device, method, system and pixel array to solve the problem are similar, the implementation of the device, method, system and pixel array can refer to each other, and the overlap No longer.
  • the technical solutions provided by the embodiments of the present application are suitable for counting scenarios, especially for scenarios where multiple identical objects or multiple similar objects are counted.
  • the technical solution provided by the embodiments of the present application is applicable to a scenario that counts the amount of charge collected by pixels, a scenario where pixels are reset, or a counting scenario that is specific to other counting objects.
  • the counting device provided in this application can be applied to a frequency dividing circuit. Taking the frequency dividing circuit of a four-digit addition counter as an example, the four-digit addition counter starts counting from 0000, and when the count reaches 0011, the four-digit addition is reset by a peripheral circuit Counter, after reset, the four-digit up counter starts counting from 0000 again.
  • the number of input pulses is 4, which means that the frequency is divided by 4. This pulse is the frequency-divided pulse signal, so that the four-bit addition counter can make the oscillation source generate clock signals of different frequencies.
  • a counting circuit in a pixel array of an image sensor or a charge quantity counting circuit, or a charge quantity collection circuit.
  • An embodiment of the present invention provides a counting device.
  • the counting device includes at least a storage module and an arithmetic module. among them,
  • the storage module includes a plurality of cascaded storage units, wherein the plurality of storage units store a plurality of accumulated count intermediate values, the plurality of storage units are configured as at least one group of storage units, and the number of storage units in each group of storage units is greater than The number of intermediate values corresponding to the cumulative count of the group of storage units;
  • the calculation module is connected to the first and last groups of storage units in the plurality of storage units, and is used to perform calculation according to the received count value and the accumulated count intermediate value input through the last group of storage units to obtain the current accumulated count intermediate of the corresponding counting object Value and output to the first group of storage units in the cascaded storage units;
  • a plurality of accumulated count intermediate values are cyclically shifted to the calculation module and the corresponding count value for calculation, and until the end of counting, the plurality of current accumulated count intermediate values stored in the storage module are used as the plurality of accumulated count results corresponding to the counting object.
  • the arithmetic module is preferably connected to the storage module Between the first and last row of storage units in the.
  • the counting device shown in FIG. 2 is provided with a plurality of cascaded storage units and a common arithmetic module, and the multiple accumulated counts of the corresponding counting objects obtained by the common arithmetic module are stored in the multiple storage units in a cyclic shift manner
  • each storage unit can replace the corresponding multiple latches of the D flip-flop in the prior art to realize the function of storing the count value, thereby greatly reducing the area of the storage module in the counting device and improving the dynamic range of the sensor ; And, through the sharing of arithmetic modules to further reduce the area required by the counting device, to facilitate the optimization of the structure of the sensor.
  • the area of the counting device required for multiple counting objects can be effectively reduced, and the counting device can be improved.
  • the measurement range of the sensor thereby improving the dynamic range of the sensor and the performance of the sensor, helps to implement circuit elements composed of multiple counting objects (such as a pixel array composed of multiple pixel units and a counting circuit) in a small pixel.
  • multiple storage units are storage units of the same structure, or may be storage units of different structures; the number of storage units configured by different groups of storage units is at least two, and the storages configured by different groups of storage units The number of units may be the same or different.
  • the storage unit is configured but not limited to a latch, or other components; the connection mode of multiple groups of storage units is series connection, or group cascade connection, or other connection modes, which are not limited in the embodiments of the present invention.
  • the multiple storage units in this cascade are storage unit 1 to storage unit n, where n is a positive integer; further, the multiple storage units Divided into multiple groups, storage unit 1 is the first storage unit of the first group, and storage unit n is the last storage unit of the last group.
  • each storage unit is further configured with at least one latch, wherein the number of latches included in different storage units is the same, and the latches at corresponding positions of different storage units are cascaded in sequence.
  • each group of storage units includes multiple storage units, and the number of storage units configured in different groups of storage units is the same.
  • the counting device shown in FIG. 3 multiple storage units are divided into N groups of storage units connected in series, and each group of storage units is composed of the same number of storage units, that is, each group includes n storage units, where each The unit capacity of a storage unit is i-bit, and each storage unit can be implemented with i latches, where i is an integer greater than or equal to 1.
  • each group of storage units includes n storage units, and the n storage units of each storage unit correspond to n row selection control signals such as E1, E2, ..., En, etc., And controlled by the n line selection control signals.
  • the latch includes a switch and an inverter.
  • the switch is a MOS tube
  • the inverter is composed of an N-type MOS tube and a P-type MOS tube.
  • a storage unit composed of latches is used to store the intermediate value of the cumulative count or the cumulative count result.
  • the cascade structure of multiple latches avoids the setting of a switch and is shared by multiple latches.
  • the active area of the pre-stage output and the post-stage input makes each latch function equivalent to the two latches corresponding to the D flip-flop in the prior art, which can reduce the memory module by at least half Storage area.
  • multiple storage units store a plurality of intermediate values of the cumulative count
  • the correspondence relationship between the further storage units and the intermediate value of the cumulative count may be one-to-one correspondence or one-to-many. limited.
  • the number of storage units in each group of storage units is greater than the number corresponding to the middle of the cumulative count of the group of storage units.
  • the multiple storage units are used to store corresponding multiple intermediate count values through cyclic displacement.
  • at least one memory cell of each group of memory cells does not store the intermediate value of the cumulative count.
  • the at least one storage unit that does not store the intermediate value of the cumulative count is a common storage unit, where the common storage unit is used to store the intermediate value of the cumulative count corresponding to the same group of storage units during the cyclic displacement.
  • the intermediate value of the cumulative count stored by the common storage unit comes from other storage units adjacent to the same group of storage units.
  • the initial storage value of the shared storage unit is 0, and the count value stored in the shared storage unit is cleared after each round of counting.
  • the common storage unit may be provided at the connection between adjacent storage units, or the common storage unit may also be provided at other positions of the group of storage units, which is not limited in this embodiment.
  • multiple storage units store a cumulative count result corresponding to the cumulative count intermediate value in a storage unit corresponding to the cumulative count intermediate value And store the displacement of the accumulated count intermediate value in another storage unit according to the preset displacement relationship.
  • the counting device further includes a control module connected to the storage module, the control module is used to output a row selection control signal.
  • the row selection control signal is used to control the cyclic displacement between the multiple accumulated count intermediate values stored in the multiple storage units.
  • the output row selection control signal is output in sequence for gating one or more storage units controlled by the output row selection control signal; for a gated storage unit, the current cumulative count intermediate value of the storage unit It is replaced with the intermediate value of the accumulated count currently stored by the storage unit connected to the storage unit in the preset direction, or replaced by the intermediate value of the current accumulated count output by the arithmetic module connected to the storage unit in the preset direction.
  • the cumulative count intermediate value is transferred from the storage unit currently storing the cumulative count intermediate value to the The next storage unit displacement in the preset direction.
  • the current cumulative count intermediate value (for example, the initial value is 0) of the first storage unit in the selected first group of storage units is replaced by the current cumulative output of the arithmetic module (1-bit adder) connected in the preset direction Count the intermediate value A [i + 1].
  • the middle value of the cumulative count currently stored by the first storage unit in the second group of storage units (for example, the initial value is 0) is replaced by the middle value of the cumulative count stored by the last storage unit in the first group of storage units [i], and so on.
  • multiple storage units are configured as multiple groups of storage units, and the storage units at preset positions in the multiple groups of storage units are controlled by the same row selection control signal.
  • the six storage units in the storage module are configured as two groups A and B.
  • Each group of storage units includes three storage units.
  • the three row selection control signals E1, E2, and E3 are used to control the presets in the two groups.
  • the different storage units in the position namely the row selection control signal E1 is used to control the storage unit a1 of group A and the storage unit b1 of group B, and the row selection control signal E2 is used to control the storage unit a2 of group A and the storage unit b2 of group B
  • the row selection control signal E3 is used to control the storage unit a3 of group A and the storage unit b3 of group B.
  • multiple storage units are further configured such that each group of storage units includes at least two storage units, different storage units in the same group correspond to different row selection control signals, and storage units at preset positions in multiple groups of storage units are controlled Select the control signal in the same row.
  • the six memory cells in the memory module are configured as two groups A and B, and each group of memory cells includes three memory cells, the different memory cells a1, a2, and a3 in group A correspond to row selection control signals E1, respectively.
  • E2, E3, different memory cells b1, b2, b3 in group B correspond to row selection control signals E1, E2, E3, respectively. That is, when the row selection control signal E1 is output, the memory cells a1 and b1 are simultaneously gated.
  • the counting device is further configured with a comparison unit, which is connected to the arithmetic module; the comparison unit is used to convert the integrated voltage converted from the current charge amount collected by the charge storage units in multiple pixels and the preset The reference voltage is compared to obtain the current count value, and the current count value is output to the arithmetic unit.
  • a comparison unit which is connected to the arithmetic module; the comparison unit is used to convert the integrated voltage converted from the current charge amount collected by the charge storage units in multiple pixels and the preset The reference voltage is compared to obtain the current count value, and the current count value is output to the arithmetic unit.
  • the charge storage unit is a capacitor
  • the integration voltage is a capacitor integration voltage
  • the comparison result is a voltage comparison result
  • the operation module is based on the received count value and pass Before the calculation of the intermediate count value input by the last group of storage units, the voltage comparison result is obtained as the currently received count value.
  • the arithmetic module takes the sum of the currently received count value and the current accumulated count intermediate value as the accumulated count result corresponding to the accumulated count intermediate value. In this case, multiple cumulative count results are used to indicate the total amount of charge collected by the charge storage units in multiple pixels.
  • the charge storage units in multiple pixels include but are not limited to capacitors or other charge storage units . It should also be noted here that, in addition to the charge amounts listed above, the counting object may also be other electrical signals or other forms, and the embodiments of the present invention are not limited.
  • the connection mode between the operation module and the cascaded storage units includes multiple types, one of which is that the operation module is connected to the first and last two groups of the cascaded storage units.
  • the arithmetic module is configured with at least one arithmetic unit, the number of arithmetic units configured by the arithmetic module is the same as the number of latches included in the storage unit, and each arithmetic unit is respectively in the first and last two storage units The latches in the corresponding position are cascaded.
  • the arithmetic unit is configured as a half adder or half subtractor.
  • the counting device further includes an output module, connected to the arithmetic unit, for outputting a plurality of cumulative counting results.
  • the control unit outputs a plurality of row selection control signals corresponding to the plurality of storage units in a preset order, wherein one row selection control signal corresponds to at least one storage unit, so that the cycle selection can be performed based on the preset order
  • the memory cells at different positions are communicated so that the memory cells corresponding to the output row selection control signal can obtain the intermediate value of the cumulative count of the memory cells in the preset direction connected to each.
  • At least one storage unit controlled by the row selection control signal is gated, and the at least one storage unit obtains an intermediate value of the cumulative count of the storage unit in the preset direction to which each is connected.
  • the row selection control signals are sequentially gated to complete a control cycle, and each cycle of a control cycle, the cumulative count intermediate values stored in multiple storage units are sequentially shifted by one bit in the preset direction.
  • cyclic displacement methods can also be used, for example, in each cycle period, multiple storage units are divided into multiple groups, and the intermediate value of the cumulative count stored in each group of storage units As a whole, the preset steps are sequentially shifted in the preset direction.
  • each row selection control signal simultaneously controls N memory cells at corresponding positions of N groups of memory modules, and the n row selection control signals are sequentially gated in a control cycle to realize The sequential control of the memory cells in the N groups of memory cells, as shown in the timing diagram of the row selection control signal shown in FIG. 6, T is a control cycle, and the time for each row selection control signal to be gated is not greater than T / n.
  • the selected storage unit is the first of multiple sets of storage units, the last accumulated intermediate count value currently stored in the multiple sets of storage units and the count value of the corresponding count object The current accumulated count intermediate value obtained after the addition is used as the accumulated count intermediate value stored in the first storage unit.
  • the arithmetic module is configured as a half adder
  • the half adder is connected between the first storage unit of the first group and the last storage unit of the last group in multiple storage units, as shown in FIG. 3.
  • the arithmetic module obtains the intermediate value of the cumulative count currently stored by the storage unit from the last storage unit in the cascaded multiple storage units, and uses the intermediate value of the cumulative count and the storage The sum of the current count values of the count objects corresponding to the unit is used as the corresponding cumulative count result.
  • the output module outputs multiple sets of accumulated counting results in order for the subsequent circuit to obtain the accumulated counting results.
  • the storage module includes two sets of storage units, and each set of storage units includes three storage units, one of which is configured as a common storage unit, and the three storage units are controlled by three row selection signals respectively, and further storage units It is configured as a latch.
  • the six storage units in the two groups of storage units are cascaded in sequence.
  • the first row of storage units in each group of storage units is set as a common storage unit, and the last of the two groups of storage units is added by an adder (ie, an arithmetic module).
  • One row of storage units is connected to the first row of storage units.
  • each group of storage units stores two cumulative count intermediate values, that is, the two storage units in each group of storage units are respectively used to store the cumulative cumulative intermediate value accumulated by the count value converted by the capacitance integral voltage of the two capacitors.
  • two sets of memory cells are configured as latches that store four count values such as A [i], B [i], C [i], and D [i], respectively, and two locks as shared memory cells
  • the latches at the corresponding positions in the two sets of latches are respectively controlled by the row selection control signals E1, E2, and E3, that is, E1 is used to control the common latch in the first row of the two sets of latches
  • E2 is used to control the latches A [i] and C [i]
  • E3 is used to control the latches B [i] and D [i].
  • the arithmetic module compares the integrated voltage of the four capacitors with the comparison voltage V ref of the comparator (ie, the comparison module) to obtain the initial voltage comparison result, and outputs these initial voltage comparison results as the initial cumulative count intermediate value to 4 Stored in each latch (ie A [i], B [i], C [i], D [i]).
  • the row selection control signals E1, E2 , E3 is set to high level in order, so that the intermediate value of the cumulative count stored in the two sets of latches can be shifted once.
  • E1 is set to high level, in this case, the two shared latches in the first row of the latch group are selected, that is, the middle value of the accumulated count currently stored in C [i] in the first group of latches is shifted to The second group of shared latches is used for storage.
  • the intermediate value of the accumulated count currently stored in the second group of latches A [i] is output to the adder and added to CR [i] to obtain the accumulated count result A [i + 1 ], And the accumulated count result A [i + 1] is shifted to the common latch of the first group for storage.
  • E2 and E3 are set to high level in turn until the end of this control cycle.
  • the cumulative value of the cumulative count stored by the entire storage module changes from D [i], C [i], B [i], A [i] to A [i +1], B [i], C [i], D [i].
  • the control module triggers the start of the next control cycle, that is, starts the displacement process of the next intermediate value of the cumulative count .
  • the cumulative value of the cumulative count stored by the entire storage module changes from A [i + 1], B [i], C [i], D [i] to B [i + 1 ], A [i + 1], D [i], C [i].
  • the two sets of latches will undergo a cyclic shift of the cumulative intermediate value for many times until the counting process is completed when the capacitor is integrated.
  • the output module outputs the intermediate value of the accumulated count currently stored by the two sets of latches as the final accumulated count result to the subsequent stage circuit via the bus.
  • the counting device includes a storage module and an arithmetic module.
  • the storage module includes a plurality of cascaded storage units.
  • the module is connected to the first and last groups of storage units in a plurality of storage units, wherein the plurality of storage units store a plurality of cumulative count intermediate values, the plurality of storage units are configured as at least one group of storage units, and the storage unit in each group of storage units The number of is greater than the number corresponding to the middle value of the cumulative count of the group of storage units.
  • the counting method includes:
  • Each cycle of cyclic displacement performs at least one of the following processes:
  • the arithmetic module is used to perform an operation according to the count value of the count object and the accumulated count intermediate value currently stored in the last group of storage units to obtain the current accumulated count intermediate value of the count object;
  • the counting method provided by the embodiment of the present application is similar to the implementation principle of counting and setting, and for the similarities, refer to the description on the device side above, and no more details are provided below.
  • the counting method further includes the following steps: outputting a row selection control signal to the storage unit through the control unit.
  • the row shift control signal is used to control the cyclic displacement between the multiple accumulated count intermediate values stored in the multiple storage units.
  • multiple storage units are configured as multiple groups of storage units, and the storage units at preset positions in the multiple groups of storage units are controlled by the same row selection control signal.
  • each group of memory cells includes at least two rows of memory cells, and different memory cells in the same group correspond to different row selection control signals.
  • the row selection control signal is used to control the cyclic displacement between the multiple cumulative count intermediate values stored in the multiple storage units, including:
  • the row selection control signal is sequentially output to a plurality of storage units through the control unit to gate the storage unit controlled by the output row selection control signal; and, for a gated storage unit, the current cumulative count of the storage unit is intermediate The value is replaced with the intermediate value of the accumulated count currently stored by the storage unit connected to the storage unit in the preset direction, or replaced by the intermediate value of the current accumulated count output from the arithmetic module connected to the storage unit in the preset direction.
  • the counting method further includes the following steps: outputting multiple cumulative counting results through the output module.
  • the control unit may also output a plurality of row selection control signals corresponding to the plurality of storage units in a preset order, wherein one row selection control signal corresponds to at least one storage Unit; then receive row selection control signals corresponding to different storage units through the storage module, and cyclically output multiple cumulative count results to the arithmetic module; thus, multiple cumulative count results can be received and output through the output module.
  • each storage unit is further configured with at least one latch, wherein the number of latches included in different storage units is the same, and the latches at corresponding positions of different storage units are cascaded in sequence.
  • the arithmetic module is configured with at least one arithmetic unit, the number of arithmetic units configured by the arithmetic module is consistent with the number of latches included in the storage unit, and each arithmetic unit corresponds to the first and the last two storage units respectively The position of the latch cascade.
  • the arithmetic unit is configured as a half adder or half subtractor.
  • the counting method further includes the step of: comparing the integrated voltage converted by the current charge quantity collected by the charge storage units in the plurality of pixels with a preset reference voltage through a comparison unit to obtain a current count value.
  • each storage unit can replace the corresponding multiple latches of the D flip-flop in the prior art to realize the function of storing the count value, thereby greatly reducing the area of the storage module in the counting device and improving the dynamic range of the sensor ; And, through the sharing of arithmetic modules to further reduce the area required by the counting device, to facilitate the optimization of the structure of the sensor.
  • the area of the counting device required for multiple counting objects can be effectively reduced, and the counting device can be improved.
  • Measurement range which improves the sensor's dynamic range and sensor performance, and helps to implement circuit elements composed of multiple counting objects in a small pixel.
  • the present application also provides an exemplary implementation of a counting system.
  • the counting system includes at least one counting device, and the counting device is configured to perform any item provided in the embodiment corresponding to FIG. 2.
  • the present invention also provides an exemplary implementation of a pixel array including a plurality of pixels and a counting device common to the pixels.
  • the counting device may be the counting device of any one of the embodiments corresponding to FIG. 2 described above.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.
  • computer usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, the instructions The device implements the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Measurement Of Radiation (AREA)

Abstract

本发明的实施方式提供一种计数方法、计数装置以及应用其的计数系统和像素阵列，该计数装置包括：存储模块包括级联的多个存储单元，其中多个存储单元存储有多个累积计数中间值，多个存储单元被配置为至少一组存储单元；运算模块与多个存储单元中的首末组存储单元相连，用于根据接收的计数值和通过末组存储单元输入的累加计数中间值进行运算，获得对应计数对象的当前累加计数中间值，并输出至级联的多个存储单元中的首组存储单元中。其中，多个累积计数中间值循环位移至运算模块与相应的计数值进行运算，直至计数结束则以存储模块中存储的多个当前累加计数中间值作为计数对象对应的多个累积计数结果。

Description

计数方法、计数装置以及应用其的计数系统和像素阵列
本申请要求在 2018年10月24日提交中国专利局、申请号为 201811246784.0、发明名称为 一种计数系统、方法、装置及计数器的中国专利申请的优先权，其全部内容通过引用结合在本申请中；本申请要求在 2018年10月24日提交中国专利局、申请号为 201811246783.6、发明名称为 一种计数系统、方法、装置及计数器的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及微电子领域，尤其涉及一种计数方法、计数装置以及应用其的计数系统和像素阵列。
背景技术
动态范围是传感器像素阵列的重要指标之一，高动态范围的传感器有利于满足高精度的要求，有助于提升传感器的响应范围，尤其是针对图像传感器。为了提高图像传感器的动态范围，通常可以采用在像素中增设计数电路，在积分的过程中同时进行计数以实现部分数字化，但是像素中的面积有限，采用以下方法：改变积分电容值，改变积分时间，改变列级增益，多次曝光；但这些方法均无法同时满足高动态范围、强抗干扰等要求，难以在大背景光、高帧频、大阵列等测距场景下实现高精度测量的要求。
传感器进行电路积分时所采用的计数方式会直接影响到传感器的动态范围，进而影响传感器的整体性能。目前，现有的传感器进行电路积分时所采用的计数装置通常为由D触发器构成的异步计数器或同步计数器。D触发器通常具有两个状态，例如0和1，这使得D触发器能够从一个状态翻转为另一个状态以触发相应设置。现有计数装置中还设置有两个锁存器，用以配合D触发器的两个状态之间的翻转操作，比如图1示出的由D触发器级联组成的4位异步计数器。这种结构的计数装置占用面积较大，若设于像素内部则会占用较多像素面积，造成像素面积优化存在一定困难；若设于像素外部则无法实现提高动态范围的目的，导致传感器的动态范围小、传感性能差。
综上，目前传感器进行电路积分时所采用的计数方式存在D触发器占用传感器内部面积大，动态范围小等问题，大大降低了传感器性能。因此亟待设计一个计数方案用以解决上述技术问题。
发明内容
本申请实施例提供一种计数方法、计数装置以及应用其的计数系统和像素阵列，用以降低计数电路占用的传感器内部面积，提高传感器的动态范围和传感器性能。
为了克服现有技术存在的问题，本发明中提出了一种计数方法、计数装 置以及应用其的计数系统和像素阵列。
本发明实施方式的第一方面中，提供了一种计数装置，该计数装置至少包括存储模块和运算模块。存储模块包括级联的多个存储单元，其中多个存储单元存储有多个累积计数中间值，这多个存储单元被配置为至少一组存储单元，每组存储单元中存储单元的数量大于对应于该组存储单元的累积计数中间值的数量；运算模块，与这多个存储单元中的首末组存储单元相连，用于根据接收的计数值和通过该末组存储单元输入的累加计数中间值进行运算，获得对应计数对象的当前累加计数中间值，并输出至级联的这多个存储单元中的首组存储单元中。其中，多个累积计数中间值循环位移至运算模块与相应的计数值进行运算，直至计数结束则以存储模块中存储的多个当前累加计数中间值作为该计数对象对应的多个累积计数结果。
在本发明的一个实施例中，该计数装置还包括控制模块，连接于所述存储模块，用于输出行选控制信号，所述行选控制信号用于控制所述多个存储单元中存储的多个累积计数中间值之间的循环位移。
在本发明的一个实施例中，多个存储单元被配置为多组存储单元，所述多组存储单元中预设位置的存储单元受控于同一行选控制信号。
在本发明的一个实施例中，所述多个存储单元还被配置为每组存储单元包括至少两个存储单元，同一组中不同存储单元对应于不同行选控制信号。
在本发明的一个实施例中，所述行选控制信号用于控制所述多个存储单元中存储的多个累积计数中间值之间的循环位移，具体为：所述行选控制信号依次输出，用于选通由输出的所述行选控制信号控制的存储单元；以及，对于一个被选通的存储单元，该存储单元当前的累积计数中间值替换为该存储单元在预设方向上所连接的存储单元当前存储的累积计数中间值，或替换为该存储单元在预设方向上所连接的所述运算模块输出的当前累积计数中间值。
在本发明的一个实施例中，计数装置还包括输出模块，连接于所述运算模块，用于输出所述多个累积计数结果。
在本发明的一个实施例中，所述控制单元具体用于：依预设次序输出对应于所述多个存储单元的多个行选控制信号，其中一个行选控制信号对应于至少一个存储单元；所述存储模块具体用于：接收对应于不同存储单元的行选控制信号，并向所述运算模块循环输出所述多个累积计数结果；所述输出模块具体用于：接收并输出所述多个累积计数结果。
在本发明的一个实施例中，每个存储单元还被配置有至少一个锁存器，其中不同存储单元包括的锁存器的数量一致，且不同存储单元相应位置的锁存器依次级联。
在本发明的一个实施例中，所述运算模块被配置有至少一个运算单元，所述运算模块所被配置的运算单元的数量与所述存储单元所包括的锁存器的数量一致，每个所述运算单元分别与首尾两个存储单元中相应位置的锁存器级联。
在本发明的一个实施例中，所述运算单元被配置为半加器或半减器。
在本发明实施方式的第二方面中，提供了一种计数方法，应用于如第一方面任一项的计数装置中，所述计数装置包括存储模块和运算模块，所述存储模块包括级联的多个存储单元，所述运算模块与所述多个存储单元中的首末组存储单元相连，其中，所述多个存储单元存储有多个累积计数中间值，所述多个存储单元被配置为至少一组存储单元，每组存储单元中存储单元的数量大于对应于该组存储单元的累积计数中间值的数量；所述计数方法包括：
将所述多个累积计数中间值循环位移至所述运算模块与相应的所述计数值进行运算，直到计数结束则以所述存储模块中存储的多个当前累加计数中间值作为所述计数对象对应的多个累积计数结果；
其中每一周期循环位移执行至少一次以下过程：
采用所述运算模块根据计数对象的计数值和所述末组存储单元当前存储的累加计数中间值进行运算，获得所述计数对象的当前累加计数中间值；并
输出至级联的所述多个存储单元中的首组存储单元中进行存储。
在本发明的一个实施例中，还包括：通过控制单元向所述存储单元输出行选控制信号；通过所述行选控制信号来控制所述多个存储单元中存储的多个累积计数中间值之间的循环位移。
在本发明的一个实施例中，所述多个存储单元被配置为多组存储单元，所述多组存储单元中预设位置的存储单元受控于同一行选控制信号。
在本发明的一个实施例中，所述多个存储单元还被配置为每组存储单元包括至少两行存储单元，同一组中不同存储单元对应于不同行选控制信号。
在本发明的一个实施例中，所述通过所述行选控制信号来控制所述多个存储单元中存储的多个累积计数中间值之间的循环位移，包括：通过所述控制单元向所述多个存储单元依次输出所述行选控制信号，以选通由输出的所述行选控制信号控制的存储单元；并对于一个被选通的存储单元，将该存储单元当前的累积计数中间值替换为该存储单元在预设方向上所连接的存储单元当前存储的累积计数中间值，或替换为该存储单元在预设方向上所连接的所述运算模块输出的当前累积计数中间值。
在本发明的一个实施例中，计数装置还包括：通过输出模块来输出所述多个累积计数结果。
在本发明的一个实施例中，通过输出模块来输出所述多个累积计数结果之前，还包括：通过控制单元依预设次序输出对应于所述多个存储单元的多个行选控制信号，其中一个行选控制信号对应于至少一个存储单元；通过所述存储模块接收对应于不同存储单元的行选控制信号，并向所述运算模块循环输出所述多个累积计数结果；通过输出模块来输出所述多个累积计数结果，包括：通过所述输出模块来接收并输出所述多个累积计数结果。
在本发明的一个实施例中，每个存储单元还被配置有至少一个锁存器，其中不同存储单元包括的锁存器的数量一致，且不同存储单元相应位置的锁存器依次级联。
在本发明的一个实施例中，所述运算模块被配置有至少一个运算单元， 所述运算模块所被配置的运算单元的数量与所述存储单元所包括的锁存器的数量一致，每个所述运算单元分别与首尾两个存储单元中相应位置的锁存器级联。
在本发明的一个实施例中，所述运算单元被配置为半加器或半减器。
在本发明的一个实施例中，所述多个累积计数结果用于指示多个像素内的电荷存储单元采集的总电荷量。所述方法还包括：通过比较单元将所述多个像素内的电荷存储单元采集的当前电荷量所转化的积分电压与预设参考电压进行比较得到当前计数值。
在本发明实施方式的第三方面中，提供了一种计数系统，包括至少一个如第一方面任一项的计数装置。
在本发明实施方式的第四方面中，提供了一种像素阵列，该像素阵列中多个像素与如第一方面任一所述的计数装置相连，以确定所述像素阵列中的多个像素采集的电荷量。
本申请实施例提供的技术方案中，通过设置级联的多个存储单元以及共用的运算模块，并在这多个存储单元中采用循环位移的方式存储共用运算模块得到的对应计数对象的多个累积计数结果，使每一存储单元均可替代现有技术中D触发器的所对应的多个锁存器以实现存储计数值的功能，从而大大减少计数装置中存储模块的面积，提升传感器的动态范围；并且，通过对运算模块的共用进一步减少了计数装置所需的面积，便于传感器的结构优化。尤其是，在多个计数对象对运算模块、多个存储单元进行共用时，可以有效减少多个计数对象所需的计数装置的面积，提高计数装置的测量范围，从而提高传感器的动态范围和传感器性能，有助于在小象元中实现多个计数对象组成的电路元件。
附图说明
图1为示意性地示出了现有技术提供的一种计数电路的结构示意图；
图2为示意性地示出了本发明实施例涉及的一种计数装置的结构示意图；
图3为示意性地示出了本发明实施例涉及的另一种计数装置的结构示意图；
图4为示意性地示出了本发明实施例涉及的一种存储模块的结构示意图；
图5为示意性地示出了本发明实施例涉及的一种锁存器的结构示意图；
图6为示意性地示出了本发明实施例涉及的一种行选控制信号的时序示意图；
图7为示意性地示出了本发明实施例涉及的一种多组存储单元的数据流示意图；
图8为示意性地示出了本发明实施例涉及的一种计数方法的流程示意图；
图9为示意性地示出了本发明实施例涉及的一种计数系统的结构示意图。
具体实施方式
下面将参考若干示例性实施方式来描述本发明的原理和精神。应当理解，给出这些实施方式仅仅是为了使本领域技术人员能够更好地理解进而实现本发明，而并非以任何方式限制本发明的范围。相反，提供这些实施方式是为了使本公开更加透彻和完整，并且能够将本公开的范围完整地传达给本领域的技术人员。
应当理解的是，当单元/模块间被描述为“相连”时，其可以直接连接到另一单元/模块，或者可以存在中间单元/模块。与此相对，当单元/模块间被称为“直接相连”时，则不存在中间单元/模块。
动态范围是传感器的重要指标之一，高动态范围的传感器有利于满足高精度的测量要求，有助于提升传感器的测量范围，尤其是有助于提升图像传感器的测量范围。传感器进行电路积分时所采用的计数方式限制传感器的电路设计、面积优化等从而影响传感器的面积、响应速度、动态范围等参数，进一步的还会影响传感器的整体性能。
发明人发现，现有的传感器进行电路积分时所采用的计数装置通常为由D触发器构成的异步计数器或同步计数器，但这种结构会占用传感器内部较大面积，造成传感器的面积优化存在一定困难。此外，在这种计数方式中传感器的动态范围受限于D触发器的动态范围，从而导致传感器的动态范围小，传感器性能差。
为了解决上述技术问题，本申请提供一种计数装置、方法、系统以及像素阵列，用以降低计数电路占用的传感器内部面积，提高传感器的动态范围和传感器性能。该计数装置包括存储模块和运算模块。存储模块包括级联的多个存储单元，其中多个存储单元存储有多个累积计数中间值，这多个存储单元被配置为至少一组存储单元，每组存储单元中存储单元的数量大于对应于该组存储单元的累积计数中间值的数量；运算模块与这多个存储单元中的首末组存储单元相连，用于根据接收的计数值和通过该末组存储单元输入的累加计数中间值进行运算，获得对应计数对象的当前累加计数中间值，并输出至级联的这多个存储单元中的首组存储单元中。其中，多个累积计数中间值循环位移至运算模块与相应的计数值进行运算，直至计数结束则以存储模块中存储的多个当前累加计数中间值作为该计数对象对应的多个累积计数结果。
本申请提供的计数装置，通过设置级联的多个存储单元以及共用的运算模块，并在这多个存储单元中采用循环位移的方式存储共用运算模块得到的对应计数对象的多个累积计数结果，使每一存储单元均可替代现有技术中D触发器的所对应的多个锁存器以实现存储计数值的功能，从而大大减少计数装置中存储模块的面积，提升传感器的动态范围；并且，通过对运算模块的共用进一步减少了计数装置所需的面积，便于传感器的结构优化。尤其是，在多个计数对象对运算模块、多个存储单元以及相关模块(如输出模块、比较模块等)进行共用时，可以有效减少多个计数对象所需的计数装置的面积，提高计数装置的测量范围，从而提高传感器的动态范围和传感器性能，有助于在小象元中实现多个计数对象组成的电路元件。
其中，装置、方法、系统以及像素阵列是基于同一发明构思的，由于装置、方法、系统以及像素阵列解决问题的原理相似，因此装置、方法、系统以及像素阵列的实施可以相互参见，重复之处不再赘述。
本申请实施例提供的技术方案适用于计数场景，尤其是对多个相同对象或多个相似对象进行计数的场景。具体而言，本申请实施例提供的技术方案适用于对像素采集的电荷量进行计数的场景，像素复位的场景，或者针对于其他计数对象的计数场景。例如，本申请提供的计数装置可以应用于分频电路，以四位加法计数器的频分电路为例，该四位加法计数器从0000开始计数，当计数到0011时通过外围电路复位该四位加法计数器，复位后该四位加法计数器重新从0000开始计数。此情况下输入脉冲的数量为4，即实现4分频，此脉冲即为分频后的脉冲信号，从而通过该四位加法计数器可以使振荡源产生不同频率的时钟信号。
本申请实施例提供的技术方案适用于各种计量系统或计量电路，尤其是小型传感器或微型传感器中的计量电路。例如图像传感器的像素阵列中的计数电路，或电荷量计数电路，或电荷量采集电路。
本发明实施例提供了一种计数装置，如图2所示，该计数装置至少包括存储模块和运算模块。其中，
存储模块，包括级联的多个存储单元，其中多个存储单元存储有多个累积计数中间值，这多个存储单元被配置为至少一组存储单元，每组存储单元中存储单元的数量大于对应于该组存储单元的累积计数中间值的数量；
运算模块，与这多个存储单元中的首末组存储单元相连，用于根据接收的计数值和通过该末组存储单元输入的累加计数中间值进行运算，获得对应计数对象的当前累加计数中间值，并输出至级联的这多个存储单元中的首组存储单元中；
其中，多个累积计数中间值循环位移至运算模块与相应的计数值进行运算，直至计数结束则以存储模块中存储的多个当前累加计数中间值作为该计数对象对应的多个累积计数结果。
需要说明的是，若每组存储单元中存储单元的数量与该组存储单元的累积计数中间值的数量之差大于或等于设定值(例如1)，则该运算模块优选为连接于存储模块中的首末行存储单元之间。
图2示出的计数装置，通过设置级联的多个存储单元以及共用的运算模块，并在这多个存储单元中采用循环位移的方式存储共用运算模块得到的对应计数对象的多个累积计数结果，使每一存储单元均可替代现有技术中D触发器的所对应的多个锁存器以实现存储计数值的功能，从而大大减少计数装置中存储模块的面积，提升传感器的动态范围；并且，通过对运算模块的共用进一步减少了计数装置所需的面积，便于传感器的结构优化。尤其是，在多个计数对象对运算模块、多个存储单元以及相关模块(如输出模块、比较模块等)进行共用时，可以有效减少多个计数对象所需的计数装置的面积，提高计数装置的测量范围，从而提高传感器的动态范围和传感器性能，有助于在小象元中实现多个计数对象组成的电路元件(例如多个像素单元组成的 像素阵列以及计数电路)。
本申请实施例中，多个存储单元为相同结构的存储单元，也可以为不同结构的存储单元；不同组存储单元所配置的存储单元的数量为至少两个，不同组存储单元所配置的存储单元的数量可以相同也可以不同。存储单元被配置但不限于锁存器，或其他元件；多组存储单元的连接方式为串联，或分组级联，或其他连接方式，本发明实施例均不限定。
以存储单元的数量是n个为例，如图2所示，这级联的多个存储单元分别为存储单元1至存储单元n，其中n为正整数；进一步的，将这多个存储单元划分为多组，存储单元1为首组首个存储单元，存储单元n为末组末个存储单元。
一种可能的实现方式中，每个存储单元还被配置有至少一个锁存器，其中不同存储单元包括的锁存器的数量一致，且不同存储单元相应位置的锁存器依次级联。可选的，每组存储单元包括多个存储单元，并且不同组存储单元所配置的存储单元的数量一致。举例来说，图3示出的计数装置中，多个存储单元被划分为串联的N组存储单元，每组存储单元由相同数量的存储单元构成，即每组包括n个存储单元，其中每一存储单元的单位容量为i-bit，每一存储单元可采用i个锁存器实现，其中i为大于等于1的整数。进一步的，图4示出的存储模块中，每组存储单元包括n个存储单元，每组存储单元的n个存储单元分别对应于E1、E2、……、En等n个行选控制信号，并由这n个行选控制信号进行控制。较佳的，锁存器包括开关和反相器。图5所示的锁存器中，开关为MOS管，反相器由N型MOS管和P型MOS管组成。这一实现方式中采用由锁存器组成的存储单元来存储累积计数中间值或累积计数结果，既通过多个锁存器的级联结构避免了设置切换开关，又以多个锁存器共用前级输出和后级输入的有源区，使得每一锁存器的功能均可相当于现有技术中D触发器所对应的两个锁存器的功能，这样既可减少存储模块至少一半的存储面积。
本申请实施例中，多个存储单元存储有多个累积计数中间值，进一步的存储单元与累积计数中间值的对应关系可以是一一对应，也可以是一对多，本申请实施例并不限定。每组存储单元中存储单元的数量大于对应于该组存储单元的累积计数中间的数量。
多个存储单元用于通过循环位移来存储对应的多个累积计数中间值。一种可能的实施例中，在循环位移过程开始之前，每组存储单元有至少一个存储单元未存储累积计数中间值。该未存储累积计数中间值的至少一个存储单元即为共用存储单元，其中共用存储单元用于在循环位移时存储同组存储单元对应累积计数中间值。当该组存储单元所包含存储单元的数量为多个时，该共用存储单元所存储的累积计数中间值来自于同组存储单元中相邻的其他存储单元。进一步的，该共用存储单元的初始存储值为0，并且每一轮计数结束后该共用存储单元所存储的计数值清零。可选的，该共用存储单元可以设置于相邻存储单元之间的连接处，或该共用存储单元可以也可设置于该组存储单元的其他位置，本实施例并不限定。
多个累积计数中间值在多个存储单元之间的循环位移的实现方式有多种，本申请实施例并不限定。具体而言，一种实现方式中，对于多个累积计数中间值中的一个，多个存储单元将该累积计数中间值对应的一个累积计数结果存储于与该累积计数中间值对应的一个存储单元中，并根据预设位移关系将该累积计数中间值位移存储于另一个存储单元中。
为了实现多个累积计数中间值在多个存储单元之间的循环位移，计数装置还包括控制模块，连接于存储模块，该控制模块用于输出行选控制信号。其中，行选控制信号用于控制多个存储单元中存储的多个累积计数中间值之间的循环位移。具体而言，输出行选控制信号依次输出，用于选通由输出的行选控制信号控制的一个或多个存储单元；对于一个被选通的存储单元，该存储单元当前的累积计数中间值替换为该存储单元在预设方向上所连接的存储单元当前存储的累积计数中间值，或替换为该存储单元在预设方向上所连接的运算模块输出的当前累积计数中间值。
一种可能的实施例中，以级联的首组首个存储单元向末组末个存储单元的方向为预设方向，则累积计数中间值由当前存储该累积计数中间值的存储单元向该预设方向上的下一个存储单元位移。
以图3所示的计数装置为例，行选控制信号信号E 1用于选通第一组存储单元(Group1)中的首个存储单元至第N组存储单元(GroupN)中的首个存储单元，假设这些存储单元均为共用存储单元，并且以级联的首组首个存储单元向末组末个存储单元的方向为预设方向，则当控制模块输出行选控制信号信号E 1时，被选通的第一组存储单元中的首个存储单元当前的累积计数中间值(例如初值为0)替换为预设方向上所连接的运算模块(1-bit adder)输出的当前累积计数中间值A[i+1]。同时，第二组存储单元(Group2)中的首个存储单元当前存储的累积计数中间值(例如初值为0)替换为第一组存储单元中的末个存储单元存储的累积计数中间值N[i]，以此类推。
可选的，多个存储单元被配置为多组存储单元，多组存储单元中预设位置的存储单元受控于同一行选控制信号。比如，存储模块中的6个存储单元被配置为A、B两组，每组存储单元包括3个存储单元，则3个行选控制信号E1、E2、E3分别用于控制两组中预设位置的不同存储单元，即行选控制信号E1用于控制A组的存储单元a1和B组的存储单元b1，行选控制信号E2用于控制A组的存储单元a2和B组的存储单元b2，行选控制信号E3用于控制A组的存储单元a3和B组的存储单元b3。
可选的，多个存储单元还被配置为每组存储单元包括至少两个存储单元，同一组中不同存储单元对应于不同行选控制信号，多组存储单元中预设位置的存储单元受控于同一行选控制信号。例如，存储模块中的6个存储单元被配置为A、B两组，每组存储单元包括3个存储单元，则A组中不同存储单元a1、a2、a3分别对应于行选控制信号E1、E2、E3，B组中不同存储单元b1、b2、b3分别对应于行选控制信号E1、E2、E3。即当行选控制信号E1输出时，存储单元a1和b1同时被选通。
本申请实施例中，计数对象有多种，而运算模块接收计数值的方式也有 多种。一种实现方式中，计数装置还被配置有比较单元，该比较单元与运算模块相连；该比较单元用于将多个像素内的电荷存储单元采集的当前电荷量所转化的积分电压与预设参考电压进行比较得到当前计数值，并将该当前计数值输出至运算单元。一种可能的实现方式中，以图3示出的比较单元为例，电荷存储单元为电容，积分电压为电容积分电压，比较结果为电压比较结果，则运算模块在根据接收的计数值和通过末组存储单元输入的累加计数中间值进行运算之前，获取电压比较结果作为当前接收的计数值；在根据接收的计数值和通过末组存储单元输入的累加计数中间值进行运算时，对于多个存储单元当前存储的多个累积计数中间值中的一个，运算模块以该当前接收的计数值与当前累积计数中间值之和作为该累积计数中间值对应的累积计数结果。此情况下，多个累积计数结果用于指示多个像素内的电荷存储单元采集的总电荷量，可以理解的是，多个像素内的电荷存储单元包括但不限于电容、或其他电荷存储单元。此处还需要说明的是，除了上述列举的电荷量之外，计数对象还可以是其他电信号或其他形式，本发明实施例并不限定。
本申请实施例中，运算模块与级联的多个存储单元之间的连接方式包括多种，其中一种连接方式为，运算模块与级联的多个存储单元中首末两组相连。可选的，运算模块被配置有至少一个运算单元，该运算模块所被配置的运算单元的数量与存储单元所包括的锁存器的数量一致，每个运算单元分别与首尾两个存储单元中相应位置的锁存器级联。进一步的，运算单元被配置为半加器或半减器。
进一步的，计数装置还包括输出模块，连接于运算单元，用于输出多个累积计数结果。一种可能的实现方式中，控制单元依预设次序输出对应于多个存储单元的多个行选控制信号，其中一个行选控制信号对应于至少一个存储单元，使得可以基于预设顺序循环选通不同位置的存储单元，以便输出的行选控制信号所对应的存储单元得到各自所连接的预设方向上的存储单元的累积计数中间值。对于任一行选控制信号，受控于该行选控制信号的至少一个存储单元被选通，该至少一个存储单元得到各自所连接的预设方向上的存储单元的累积计数中间值。以此类推，依次选通行选控制信号后完成一个控制周期，而每循环一个控制周期，则多个存储单元所存储的累积计数中间值依次向预设方向位移一位。可以理解的是，除了上述循环位移方式以外，还可以采用其他循环位移方式，例如在每一循环周期中，将多个存储单元分为多组，而每组存储单元所存储的累积计数中间值作为整体依次向预设方向位移预设步长。
仍以图4示出的存储模块为例，每一行选控制信号同时控制N组存储模块相应位置的N个存储单元，n个行选控制信号在一个控制周期内依次被选通，用以实现N组存储单元中各个存储单元的依次控制，如图6示出的行选控制信号的时序图中，T为一个控制周期，每个行选控制信号被选通的时间不大于T/n。特别的，在一个控制周期内，若被选通的存储单元为多组存储单元中的首个，则将多组存储单元中的末个当前存储的累积计数中间值与对应计数对象的计数值相加后得到的当前累加计数中间值，作为首个存储单元存储 的累加计数中间值。
举例来说，运算模块被配置为半加器，则该半加器连接于多个存储单元中首组首个存储单元与末组末个存储单元之间，如图3所示。在这种连接方式下，单个循环位移周期中，运算模块从级联的多个存储单元中的最后一个存储单元获取该存储单元当前存储的累积计数中间值，以该累积计数中间值和该存储单元对应的计数对象当前的计数值之和作为对应的累积计数结果。进一步的，若该累积计数结果小于阈值，则说明该计数对象的计数过程未达到停止条件或未达到预设的计数门限，将该累积计数结果输出至串联的多个存储单元的首个存储单元中进行存储。若累积计数结果不小于阈值，则说明计数过程达到停止条件或达到预设计数门限，此情况下输出模块依次输出多组累积计数结果，以便后级电路获取累积计数结果。
举例来说，上述控制周期中多组存储单元内的数据流可参见图7示出的数据流示意图。假设存储模块包括两组存储单元，每组存储单元包括3个存储单元，其中1个存储单元被配置为共用存储单元，这3个存储单元分别通过3个行选信号进行控制，进一步的存储单元被配置为锁存器。这两组存储单元中的6个存储单元之间依次级联，每组存储单元中第一行存储单元设置为共用存储单元，并通过加法器(即运算模块)将这两组存储单元中最后一行存储单元和第一行存储单元相连。进一步的，每组存储单元存储两个累积计数中间值，即每组存储单元中的两个存储单元分别用于存储两个电容的电容积分电压转化的计数值所累加的累积计数中间值。例如，两组存储单元分别被配置为分别存储有A[i]、B[i]、C[i]、D[i]等四个计数值的锁存器以及两个作为共用存储单元的锁存器；并且，这两组锁存器中对应位置上的锁存器分别受行选控制信号E1、E2、E3所控制，即E1用于控制处于两组锁存器首行的共用锁存器、E2用于控制锁存器A[i]和C[i]、E3用于控制锁存器B[i]和D[i]。结合上文描述可知，这两组锁存器中累积计数中间值的循环位移过程如图7所示，具体为：
(1)运算模块将4个电容的电容积分电压与比较器(即比较模块)的比较电压V ref进行比较得到初始电压比较结果，将这些初始电压比较结果作为初始的累积计数中间值输出至4个锁存器(即A[i]、B[i]、C[i]、D[i])中进行存储。
(2)当运算模块向两组锁存器输出比较器得到的下一电压比较结果CR[i]时，在本次控制周期内，对于其中一组锁存器，行选控制信号E1、E2、E3依次设置为高电平，以使两组锁存器中存储的累积计数中间值完成一次位移。当E1设置为高电平时，此情况下两个位于锁存器组首行的共用锁存器被选通，即第一组锁存器中C[i]当前存储的累积计数中间值位移到第二组的共用锁存器中进行存储，第二组锁存器中A[i]当前存储的累积计数中间值输出至加法器与CR[i]相加得到累积计数结果A[i+1]，并该累积计数结果A[i+1]位移到第一组的共用锁存器中进行存储。以此类推，E2、E3依次设置为高电平，直到本次控制周期结束。通过本次累积计数中间值的位移过程，整个存储模块存储的累积计数中间值由上到下依次由D[i]、C[i]、B[i]、A[i]变为A[i+1]、B[i]、 C[i]、D[i]。
(3)当运算模块向两组锁存器输出比较器得到的下一电压比较结果CR[i+1]时，控制模块触发下一控制周期启动，即开始下一个累积计数中间值的位移过程。经过这一控制周期后，整个存储模块存储的累积计数中间值由上到下依次由A[i+1]、B[i]、C[i]、D[i]变为B[i+1]、A[i+1]、D[i]、C[i]。
(4)两组锁存器会经过多次累积计数中间值的循环位移，直至电容积分时计数过程完成。输出模块将两组锁存器当前存储的累积计数中间值作为最终的累积计数结果经由总线输出至后级电路。
本申请实施例提供一种计数方法，如图8所示，应用于图2或图3所示的计数装置，计数装置包括存储模块和运算模块，存储模块包括级联的多个存储单元，运算模块与多个存储单元中的首末组存储单元相连，其中，多个存储单元存储有多个累积计数中间值，多个存储单元被配置为至少一组存储单元，每组存储单元中存储单元的数量大于对应于该组存储单元的累积计数中间值的数量。该计数方法包括：
将多个累积计数中间值循环位移至运算模块与相应的计数值进行运算，直到计数结束则以存储模块中存储的多个当前累加计数中间值作为计数对象对应的多个累积计数结果；
其中每一周期循环位移执行至少一次以下过程：
S801、采用运算模块根据计数对象的计数值和末组存储单元当前存储的累加计数中间值进行运算，获得计数对象的当前累加计数中间值；并
S802、输出至级联的多个存储单元中的首组存储单元中进行存储。
本申请实施例提供的计数方法与计数置装的实现原理相似，相似之处参见上文装置侧的描述，下文不再赘述。
可选的，该计数方法还包括以下步骤：通过控制单元向存储单元输出行选控制信号。通过行选控制信号来控制多个存储单元中存储的多个累积计数中间值之间的循环位移。
进一步的，多个存储单元被配置为多组存储单元，多组存储单元中预设位置的存储单元受控于同一行选控制信号。
进一步的，多个存储单元还被配置为每组存储单元包括至少两行存储单元，同一组中不同存储单元对应于不同行选控制信号。
可选的，通过行选控制信号来控制多个存储单元中存储的多个累积计数中间值之间的循环位移，包括：
通过控制单元向多个存储单元依次输出行选控制信号，以选通由输出的行选控制信号控制的存储单元；并且，对于一个被选通的存储单元，将该存储单元当前的累积计数中间值替换为该存储单元在预设方向上所连接的存储单元当前存储的累积计数中间值，或替换为该存储单元在预设方向上所连接的运算模块输出的当前累积计数中间值。
可选的，该计数方法还包括以下步骤：通过输出模块来输出多个累积计数结果。
进一步的，通过输出模块来输出多个累积计数结果之前，还可以通过控制单元依预设次序输出对应于多个存储单元的多个行选控制信号，其中一个行选控制信号对应于至少一个存储单元；再通过存储模块接收对应于不同存储单元的行选控制信号，并向运算模块循环输出多个累积计数结果；从而可以通过输出模块来接收并输出多个累积计数结果。
可选的，每个存储单元还被配置有至少一个锁存器，其中不同存储单元包括的锁存器的数量一致，且不同存储单元相应位置的锁存器依次级联。
相应的，述运算模块被配置有至少一个运算单元，运算模块所被配置的运算单元的数量与存储单元所包括的锁存器的数量一致，每个运算单元分别与首尾两个存储单元中相应位置的锁存器级联。
具体的，运算单元被配置为半加器或半减器。
上述计数方法的一种实现方式中，多个累积计数结果用于指示多个像素内的电荷存储单元采集的总电荷量。该计数方法还包括以下步骤：通过比较单元将多个像素内的电荷存储单元采集的当前电荷量所转化的积分电压与预设参考电压进行比较得到当前计数值。
图8提供的计数方法中，通过设置级联的多个存储单元以及共用的运算模块，并在这多个存储单元中采用循环位移的方式存储共用运算模块得到的对应计数对象的多个累积计数结果，使每一存储单元均可替代现有技术中D触发器的所对应的多个锁存器以实现存储计数值的功能，从而大大减少计数装置中存储模块的面积，提升传感器的动态范围；并且，通过对运算模块的共用进一步减少了计数装置所需的面积，便于传感器的结构优化。尤其是，在多个计数对象对运算模块、多个存储单元以及相关模块(如输出模块、比较模块等)进行共用时，可以有效减少多个计数对象所需的计数装置的面积，提高计数装置的测量范围，从而提高传感器的动态范围和传感器性能，有助于在小像元中实现多个计数对象组成的电路元件。
本申请还提供了示例性实施的一种计数系统，参见图9，该计数系统包括至少一个计数装置，该计数装置用于执行图2对应的实施例提供的任一项。
本发明还提供了示例性实施的一种像素阵列，该像素阵列包括多个像素以及这多个像素共用的计数装置，这计数装置可以是上述图2对应的实施例任一项的计数装置。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或 方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (22)

  1. 一种计数装置，其特征在于，包括：
    存储模块，包括级联的多个存储单元，其中所述多个存储单元存储有多个累积计数中间值，所述多个存储单元被配置为至少一组存储单元，每组存储单元中存储单元的数量大于对应于该组存储单元的累积计数中间值的数量；
    所述运算模块，与所述多个存储单元中的首末组存储单元相连，用于根据接收的计数值和通过末组存储单元输入的累加计数中间值进行运算，获得对应计数对象的当前累加计数中间值，并输出至级联的所述多个存储单元中的首组存储单元中；
    其中，所述多个累积计数中间值循环位移至所述运算模块与相应的所述计数值进行运算，直至计数结束则以所述存储模块中存储的多个当前累加计数中间值作为所述计数对象对应的多个累积计数结果。
  2. 如权利要求1所述的计数装置，其特征在于，还包括控制模块，连接于所述存储模块，用于输出行选控制信号，所述行选控制信号用于控制所述多个存储单元中存储的多个累积计数中间值之间的循环位移。
  3. 如权利要求2所述的计数装置，其特征在于，所述多个存储单元被配置为多组存储单元，所述多组存储单元中预设位置的存储单元受控于同一行选控制信号。
  4. 如权利要求3所述的计数装置，其特征在于，所述多个存储单元还被配置为每组存储单元包括至少两个存储单元，同一组中不同存储单元对应于不同行选控制信号。
  5. 如权利要求2至4任一所述的计数装置，其特征在于，所述行选控制信号用于控制所述多个存储单元中存储的多个累积计数中间值之间的循环位移，具体为：
    所述行选控制信号依次输出，用于选通由输出的所述行选控制信号控制的存储单元；以及
    对于一个被选通的存储单元，该存储单元当前的累积计数中间值替换为该存储单元在预设方向上所连接的存储单元当前存储的累积计数中间值，或替换为该存储单元在预设方向上所连接的所述运算模块输出的当前累积计数中间值。
  6. 如权利要求2至5任一所述的计数装置，其特征在于，还包括输出模块，连接于所述运算模块，用于输出所述多个累积计数结果。
  7. 如权利要求6所述的计数装置，其特征在于，所述控制单元具体用于：
    依预设次序输出对应于所述多个存储单元的多个行选控制信号，其中一 个行选控制信号对应于至少一个存储单元；
    所述存储模块具体用于：接收对应于不同存储单元的行选控制信号，并向所述运算模块循环输出所述多个累积计数结果；
    所述输出模块具体用于：接收并输出所述多个累积计数结果。
  8. 如权利要求1至7任一所述的计数装置，其特征在于，每个存储单元还被配置有至少一个锁存器，其中不同存储单元包括的锁存器的数量一致，且不同存储单元相应位置的锁存器依次级联。
  9. 如权利要求8所述的计数装置，其特征在于，所述运算模块被配置有至少一个运算单元，所述运算模块所被配置的运算单元的数量与所述存储单元所包括的锁存器的数量一致，每个所述运算单元分别与首尾两个存储单元中相应位置的锁存器级联。
  10. 如权利要求9所述的计数装置，其特征在于，所述运算单元被配置为半加器或半减器。
  11. 一种计数方法，其特征在于，应用于如权利要求1至10任一所述的计数装置，所述计数装置包括存储模块和运算模块，所述存储模块包括级联的多个存储单元，所述运算模块与所述多个存储单元中的首末组存储单元相连，其中，所述多个存储单元存储有多个累积计数中间值，所述多个存储单元被配置为至少一组存储单元，每组存储单元中存储单元的数量大于对应于该组存储单元的累积计数中间值的数量；所述计数方法包括：
    将所述多个累积计数中间值循环位移至所述运算模块与相应的所述计数值进行运算，直到计数结束则以所述存储模块中存储的多个当前累加计数中间值作为所述计数对象对应的多个累积计数结果；
    其中每一周期循环位移执行至少一次以下过程：
    采用所述运算模块根据计数对象的计数值和所述末组存储单元当前存储的累加计数中间值进行运算，获得所述计数对象的当前累加计数中间值；并输出至级联的所述多个存储单元中的首组存储单元中进行存储。
  12. 如权利要求11所述的计数方法，其特征在于，还包括：
    通过控制单元向所述存储单元输出行选控制信号；
    通过所述行选控制信号来控制所述多个存储单元中存储的多个累积计数中间值之间的循环位移。
  13. 如权利要求12所述的计数方法，其特征在于，所述多个存储单元被配置为多组存储单元，所述多组存储单元中预设位置的存储单元受控于同一行选控制信号。
  14. 如权利要求13所述的计数方法，其特征在于，所述多个存储单元还被配置为每组存储单元包括至少两行存储单元，同一组中不同存储单元对应于不同行选控制信号。
  15. 如权利要求12至14任一所述的计数方法，其特征在于，所述通过所述行选控制信号来控制所述多个存储单元中存储的多个累积计数中间值之间的循环位移，包括：
    通过所述控制单元向所述多个存储单元依次输出所述行选控制信号，以选通由输出的所述行选控制信号控制的存储单元；并
    对于一个被选通的存储单元，将该存储单元当前的累积计数中间值替换为该存储单元在预设方向上所连接的存储单元当前存储的累积计数中间值，或替换为该存储单元在预设方向上所连接的所述运算模块输出的当前累积计数中间值。
  16. 如权利要求12至15任一所述的计数方法，其特征在于，还包括：
    通过输出模块来输出所述多个累积计数结果。
  17. 如权利要求16所述的计数方法，其特征在于，通过输出模块来输出所述多个累积计数结果之前，还包括：
    通过控制单元依预设次序输出对应于所述多个存储单元的多个行选控制信号，其中一个行选控制信号对应于至少一个存储单元；
    通过所述存储模块接收对应于不同存储单元的行选控制信号，并向所述运算模块循环输出所述多个累积计数结果；
    通过输出模块来输出所述多个累积计数结果，包括：通过所述输出模块来接收并输出所述多个累积计数结果。
  18. 如权利要求11至17任一所述的计数方法，其特征在于，每个存储单元还被配置有至少一个锁存器，其中不同存储单元包括的锁存器的数量一致，且不同存储单元相应位置的锁存器依次级联。
  19. 如权利要求18所述的计数方法，其特征在于，所述运算模块被配置有至少一个运算单元，所述运算模块所被配置的运算单元的数量与所述存储单元所包括的锁存器的数量一致，每个所述运算单元分别与首尾两个存储单元中相应位置的锁存器级联。
  20. 如权利要求19所述的计数方法，其特征在于，所述运算单元被配置为半加器或半减器。
  21. 一种计数系统，其特征在于，包括至少一个如权利要求1至10任一所述的计数装置，用以执行权利要求11至20任一所述的计数方法。
  22. 一种像素阵列，其特征在于，所述像素阵列中的多个像素与如权利要求1至10任一所述的计数装置相连，以确定所述像素阵列中的多个像素采集的电荷量。
PCT/CN2019/089764 2018-10-24 2019-06-03 计数方法、计数装置以及应用其的计数系统和像素阵列 WO2020082736A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201980050603.3A CN112955955B (zh) 2018-10-24 2019-06-03 计数方法、计数装置以及应用其的计数系统和像素阵列
US17/239,594 US11950004B2 (en) 2018-10-24 2021-04-24 Counting method, a counting device and a counting system and a pixel array using the counting device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201811246784.0 2018-10-24
CN201811246783 2018-10-24
CN201811246783.6 2018-10-24
CN201811246784 2018-10-24

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/239,594 Continuation US11950004B2 (en) 2018-10-24 2021-04-24 Counting method, a counting device and a counting system and a pixel array using the counting device

Publications (1)

Publication Number Publication Date
WO2020082736A1 true WO2020082736A1 (zh) 2020-04-30

Family

ID=70331236

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/089764 WO2020082736A1 (zh) 2018-10-24 2019-06-03 计数方法、计数装置以及应用其的计数系统和像素阵列

Country Status (3)

Country Link
US (1) US11950004B2 (zh)
CN (1) CN112955955B (zh)
WO (1) WO2020082736A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1858855A (zh) * 2006-02-17 2006-11-08 华为技术有限公司 一种延长非易失存储器寿命的计数方法和装置
CN101488749A (zh) * 2009-01-13 2009-07-22 上海应用技术学院 一种高速动态伪随机计数装置
US20110119321A1 (en) * 2004-06-11 2011-05-19 Canon Kabushiki Kaisha Random number generating method and random number generating apparatus
CN103731610A (zh) * 2012-10-12 2014-04-16 索尼公司 数据传送电路、成像器件和成像设备
CN104378559A (zh) * 2013-08-14 2015-02-25 三星电子株式会社 图像传感器和模数转换器及其模数转换方法
CN106303313A (zh) * 2016-08-12 2017-01-04 中国科学院上海高等研究院 压缩感知cmos图像传感器的量化求和电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906304B2 (en) * 2002-11-27 2005-06-14 Microsoft Corporation Photo-sensor array for motion detection
JP4272967B2 (ja) * 2003-10-16 2009-06-03 キヤノン株式会社 演算回路およびその動作制御方法
US8660234B2 (en) * 2008-07-31 2014-02-25 International Business Machines Corporation RAM based implementation for scalable, reliable high speed event counters
US8618974B2 (en) * 2010-12-20 2013-12-31 Samsung Electronics Co., Ltd. Counter circuits, analog to digital converters, image sensors and digital imaging systems including the same
CN102595068B (zh) * 2012-03-15 2013-05-22 天津大学 数字域累加cmos-tdi图像传感器
CN104375802B (zh) * 2014-09-23 2018-05-08 上海晟矽微电子股份有限公司 一种乘除法器及运算方法
US9735787B2 (en) * 2015-03-18 2017-08-15 Analog Devices, Inc. Frequency synthesizer with dynamic phase and pulse-width control
CN107247269B (zh) * 2017-06-11 2020-02-18 宁波飞芯电子科技有限公司 用于采集处理激光信号的探测装置、像素单元及阵列
US11070211B2 (en) * 2019-05-31 2021-07-20 Syzexion, Inc. Event counter circuits using partitioned moving average determinations and related methods

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110119321A1 (en) * 2004-06-11 2011-05-19 Canon Kabushiki Kaisha Random number generating method and random number generating apparatus
CN1858855A (zh) * 2006-02-17 2006-11-08 华为技术有限公司 一种延长非易失存储器寿命的计数方法和装置
CN101488749A (zh) * 2009-01-13 2009-07-22 上海应用技术学院 一种高速动态伪随机计数装置
CN103731610A (zh) * 2012-10-12 2014-04-16 索尼公司 数据传送电路、成像器件和成像设备
CN104378559A (zh) * 2013-08-14 2015-02-25 三星电子株式会社 图像传感器和模数转换器及其模数转换方法
CN106303313A (zh) * 2016-08-12 2017-01-04 中国科学院上海高等研究院 压缩感知cmos图像传感器的量化求和电路

Also Published As

Publication number Publication date
US20210243391A1 (en) 2021-08-05
CN112955955A (zh) 2021-06-11
CN112955955B (zh) 2023-01-31
US11950004B2 (en) 2024-04-02

Similar Documents

Publication Publication Date Title
US7952510B2 (en) Solid-state imaging device, driving method thereof, and camera
CN102263910B (zh) 数据选择电路、传送电路、斜波生成电路和固体摄像装置
CN103686004A (zh) 列并行模数转换器、像素感光值输出方法及cmos图像传感器
CN103208994A (zh) 一种两段式时间数字转换电路
KR20120053556A (ko) 이미지 센싱장치 및 그 구동방법
CN105763196A (zh) 一种延迟内插型时间数字转换器
CN108871596B (zh) 成像装置和包括该成像装置的成像系统
US11953629B2 (en) Light sensor and ranging method
US20240152097A1 (en) Time to digital conversion
WO2020082736A1 (zh) 计数方法、计数装置以及应用其的计数系统和像素阵列
WO2020124469A1 (zh) 模数转换电路、图像传感器和模数转换方法
CN111246136B (zh) Cmos图像传感器像素读出加速电路
US8907835B2 (en) A/D conversion circuit and solid-state image pickup device
WO2020083028A1 (zh) 一种辐射接收系统及方法、传感阵列
JP2021069061A5 (zh)
CN105282463B (zh) 能够抵抗单粒子效应的数字像素图像传感器
CN111030697B (zh) 一种高速低功耗逐次逼近型模数转换器
CN111093043B (zh) 一种辐射接收系统及方法、传感阵列
CN109151345B (zh) 成像装置的数据读出方法
CN113162609B (zh) 一种异步计数器
CN220383165U (zh) 图像传感器中的像素单元、图像传感器和电子设备
CN111669182B (zh) 信号采样装置、系统及方法
Fu et al. A SPAD readout circuit based on column-level event-driven time-to-digital converter
Lee A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS
CN117169858A (zh) 飞行时间传感器像素单元、飞行时间传感器以及电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19876140

Country of ref document: EP

Kind code of ref document: A1

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19876140

Country of ref document: EP

Kind code of ref document: A1