WO2020082450A1 - 一种纠正码中规律交错器低延迟平行化架构位址绕线机制 - Google Patents

一种纠正码中规律交错器低延迟平行化架构位址绕线机制 Download PDF

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WO2020082450A1
WO2020082450A1 PCT/CN2018/115511 CN2018115511W WO2020082450A1 WO 2020082450 A1 WO2020082450 A1 WO 2020082450A1 CN 2018115511 W CN2018115511 W CN 2018115511W WO 2020082450 A1 WO2020082450 A1 WO 2020082450A1
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address
memory
architecture
parallelization
selector
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PCT/CN2018/115511
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French (fr)
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郭书玮
李庭育
陈育鸣
魏智汎
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江苏华存电子科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems

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  • the invention relates to the technical field of high parallelization architecture supporting regularized address interleaver in error correction code, in particular to an address winding mechanism of low delay parallelization architecture of regular interleaver in correction code.
  • Today's bit correction codes are supplemented by bit-scrambling systems to increase their bit-correction capabilities, and corresponding to today's throughput, the architecture is mostly parallelized by encoding data in most decoding processors.
  • the number of address generators of the chaotic system increases with the increase of the processor. This means that under the highly parallel architecture of the bit correction code system, the complexity of address interleaving and winding also increases, and the data processing delay time also increases. Increase.
  • An encoder is a device that compiles and converts signals (such as bit streams) or data into signals that can be used for communication, transmission, and storage.
  • the encoder converts the angular displacement or linear displacement into an electrical signal.
  • the former is called a code disk, and the latter is called a code ruler.
  • the encoder can be divided into contact type and non-contact type; according to the working principle, the encoder can be divided into incremental type and absolute type.
  • the incremental encoder converts the displacement into a periodic electrical signal, and then converts this electrical signal into a count pulse, and the number of pulses represents the magnitude of the displacement.
  • Each position of the absolute encoder corresponds to a certain digital code, so its indication is only related to the start and end positions of the measurement, and not to the intermediate process of the measurement.
  • a decoder is a device that restores information from its encoded form to its original form. When the encoded data is lost, the staff can use the decoder to restore the initial settings, and it is also easy to be used by criminals.
  • criminals install their own "decoder" on the access control card swiping system, and the depositors swipe Upon entering, the bank card information is stored on their decoder. At the same time, they installed a camera on the ATM machine to shoot the depositor's bank card password. Once they had stolen bank card information and passwords, they passed them to their associates through the Internet, deciphered them and then "cloned” them, and then used the duplicated "cloned cards” to withdraw money in other places.
  • the object of the present invention is to provide a parallel delay adder and selector architecture that provides a fixed delay parallel architecture interleaving winding mechanism, which avoids the delay time caused by the parallel architecture.
  • a low-latency parallel architecture address winding mechanism to solve the problems raised in the above background art.
  • An address winding mechanism for correcting the regular interleaver low delay parallelization architecture in the code including the following steps:
  • the step A decoding processor includes a relay, a communication chip, a fuse, and a transformer.
  • the parallelized architecture of the step B includes parallelized initial addresses, folded memory addresses, interleaved addresses, selectors, differentiators, and the folded memory addresses on the parallelized architecture are respectively connected to the selector, and all The folding memory addresses are connected in series.
  • the C first calculates the initial address of the parallelized architecture, then passes through the adder and the selector at the same time, and uses a classifier to sort the data.
  • the fixed delay time of the parallelized architecture in step C is three cycles.
  • the memory a, the memory b, the memory c, the memory d are sorted into the memory b, the memory a, the memory according to the interleaved address produced by the address generator Body c, memory d.
  • the delay time is fixed at three cycles , Does not increase the delay time as the decoding processor increases;
  • the present invention uses a parallelized adder and selector architecture to provide a fixed delay parallel architecture staggered winding mechanism to avoid the delay time caused by the parallelized architecture.
  • FIG. 1 is a schematic diagram of the structure of the cutting machine body of the present invention.
  • FIG. 2 is a schematic structural view of the cutting mechanism of the present invention
  • Fig. 3 is a schematic diagram of the blade disk of the present invention.
  • the invention provides a technical solution: an address winding mechanism for a low-latency parallelization architecture of a regular interleaver in a correction code, which is characterized by the following steps:
  • the decoding processor includes relays, communication chips, fuses, and transformers.
  • the parallel architecture includes the parallel initial address, the folded memory address, the interleaved address, the selector, the classifier, and the folded memory address on the parallel architecture.
  • Device, and all the folding memory addresses are connected in series.
  • the fixed delay time of the parallelized architecture is three cycles.
  • memory a, memory b, memory c, memory d are sorted into memory b, memory a, memory c, memory d.
  • a parallelized architecture is four-data interleaved processing, and the amount of processed data is 6144 bits.
  • the parallelized architecture is provided with an address generator 1, an address generator 2, and an address generator 3.
  • Address generator 4 minimum selector, memory 1, memory 2, memory 3, memory 4, parallel interleaved winding, processor 1, processor 2, processor 3, processor 4, all
  • the address generator 1, the address generator 2, the address generator 3, and the address generator 4 are respectively connected to the minimum selector, and the minimum selector is respectively connected to the memory 1, the memory 2, the memory 3, the memory 4 connection, the memory 1, the memory 2, the memory 3, and the memory 4 are all connected with parallel interleaved windings, and the parallel interleaved windings are respectively connected with the processor 1, the processor 2, the processor 3, and the processor 4
  • the address generator 4 is connected to the node connection between the memory 4 and the parallel interleaved winding
  • the address generator 3 is connected to the node connection between the memory 3 and the parallel interlaced winding
  • the address generator, 2 is connected
  • Embodiment 2 The old parallel interleaved winding structure, according to the memory depth address and the folded address, the corresponding address can be obtained in order and compared with the interleaved address.
  • the 4Bit signal indicates the interleaved sorting, the old There is a selector a, a selector b, a selector c, a selector d, a selector a, a selector b, a selector c, one end of the selector are connected to the interleaved address on the parallel interlaced winding structure a, the selector b, the selector c, the other end of the selector d are all connected to the differentiator, the selector a, the selector b, the selector c, the third connection terminal on the selector d are all connected to the folding memory address Connect, input data a, data b, data c, data d at the discriminator, after sorting by the discriminator, the output order is data
  • Embodiment 3 provides a fixed delay parallel interleaved winding architecture with parallelized initial address, folded memory address, interleaved address, selector, differentiator, and selection on parallelized architecture
  • the device is connected to the parallelized initial address, and the selector is connected to the classifier.
  • the data a, data b, data c, and data d of the classifier are input, and the output order is data b, data a, and data c after the classifier is sorted.
  • Data d the present invention provides a fixed delay parallel interleaved winding architecture, the initial address of the parallelized architecture is calculated first, then through the adder and selector, and finally sorted by the distinguisher, the fixed delay time of this architecture is three Cycle time.
  • the corresponding initial address is derived, and the address of the folding memory is added in parallel, and then sorted and differentiated by the selector.
  • the delay time is fixed at three cycles, and does not follow the decoding.
  • the increase in the processor increases the delay time.
  • the present invention uses the parallel adder and selector architecture to provide a fixed delay parallel architecture interleaved winding mechanism to avoid the delay time caused by the parallel architecture.
  • the delay time is fixed at three cycles , Does not increase the delay time as the decoding processor increases;
  • the present invention uses a parallelized adder and selector architecture to provide a fixed delay parallel architecture staggered winding mechanism to avoid the delay time caused by the parallelized architecture.

Abstract

一种纠正码中规律交错器低延迟平行化架构位址绕线机制，包括以下步骤：A、根据解码处理器的数量与进入的资料量，推导出相对应的初始位址；B、在平行化架构上加上折叠记忆体位址；C、对折叠记忆体位址选择器排序区分；D、根据位址产生器所产出的交错位址，将资料排序，根据解码处理器的数量与进入的资料量，推导出相对应的初始位址，在平行化架构上加上折叠记忆体位址，再同时经过选择器排序区分，其延迟时间固定在三个循环周期，不随解码处理器增加而提升延迟时间，利用平行化加法器与选择器架构，提供了一种固定延迟平行架构交错绕线机制，避免了平行化架构带来的延迟时间。

Description

一种纠正码中规律交错器低延迟平行化架构位址绕线机制 技术领域
本发明涉及支援错误纠正码中规律化地址交错器的高平行化架构技术领域，具体为一种纠正码中规律交错器低延迟平行化架构位址绕线机制。
背景技术
现今的位元修正码,多辅以位元打乱系统增加其位元修证能力,对应到现今的吞吐量,架构多以平行化多数颗解码处理器处里编码资料.而适应位元打乱系统的位址产生器数量随着处理器增加而增加,这代表在高度平行化架构的位元修正码系统下,位址交错绕线的复杂度也随着提高,资料处理延迟时间也随之提高。
编码器(encoder)是将信号(如比特流)或数据进行编制、转换为可用以通讯、传输和存储的信号形式的设备。编码器把角位移或直线位移转换成电信号，前者称为码盘，后者称为码尺。按照读出方式编码器可以分为接触式和非接触式两种；按照工作原理编码器可分为增量式和绝对式两类。增量式编码器是将位移转换成周期性的电信号，再把这个电信号转变成计数脉冲，用脉冲的个数表示位移的大小。绝对式编码器的每一个位置对应一个确定的数字码，因此它的示值只与测量的起始和终止位置有关，而与测量的中间过程无关。
解码器是一种将信息从编码的形式恢复到其原来形式的器件。在丢失编码数据的时候，工作人员可以利用解码器恢复初始设置，也容易被不法分子利用，在一些无人看管的银行，犯罪分子在门禁刷卡系统上面装上自己的“解码器”，储户刷卡进门，银行卡信息便 存在他们的解码器上。同时，他们在ATM机上安装了摄像头，用来拍摄储户的银行卡密码。他们一旦窃取了银行卡信息和密码，便通过互联网传给同伙，破译后进行“克隆”，随后用复制的“克隆卡”在异地取款。
发明内容
本发明的目的在于提供一种利用平行化加法器与选择器架构,提供了一种固定延迟平行架构交错绕线机制,避免了平行化架构带来的延迟时间的一种纠正码中规律交错器低延迟平行化架构位址绕线机制，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种纠正码中规律交错器低延迟平行化架构位址绕线机制,包括以下步骤：
A、根据解码处理器的数量与进入的资料量,推导出相对应的初始位址；
B、在平行化架构上加上折叠记忆体位址；
C、对折叠记忆体位址选择器排序区分；
D、根据位址产生器所产出的交错位址,将资料排序。
优选的，所述步骤A解码处理器上包括继电器，通信芯片，保险丝，变压器。
优选的，所述步骤B平行化架构上包括平行化初始位址，折叠记忆位址，交错位址，选择器，区分器，平行化架构上的折叠记忆位址分别与选择器连接，同时所有的折叠记忆位址相互串联。
优选的，所述C先行计算平行化架构的初始位址再同时经过加法器与选择器，并采用区分器将资料进行排序。
优选的，所述步骤C平行化架构的固定延迟时间为三个循环周 期。
优选的，所述步骤D根据位址产生器所产出的交错位址,将记忆体a，记忆体b，记忆体c，记忆体d，经过排序后为记忆体b，记忆体a，记忆体c，记忆体d。
与现有技术相比，本发明的有益效果是：
(1)根据解码处理器的数量与进入的资料量,推导出相对应的初始位址,在平行加上折叠记忆体位址,再同时经过选择器排序区分，其延迟时间固定在三个循环周期,不随解码处理器增加而提升延迟时间；
(2)本发明利用平行化加法器与选择器架构,提供了一种固定延迟平行架构交错绕线机制,避免了平行化架构带来的延迟时间。
附图说明
图1为本发明切割机本体结构示意图；
图2为本发明切割机构结构示意图；
图3为本发明刀片盘示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明提供一种技术方案：一种纠正码中规律交错器低延迟平行化架构位址绕线机制,其特征在于：包括以下步骤：
A、根据解码处理器的数量与进入的资料量,推导出相对应的初 始位址；
B、在平行化架构上加上折叠记忆体位址；
C、对折叠记忆体位址选择器排序区分；
D、根据位址产生器所产出的交错位址,将资料排序。
根据解码处理器的数量与进入的资料量,推导出相对应的初始位址，解码处理器上包括继电器，通信芯片，保险丝，变压器。
在平行化架构上加上折叠记忆体位址，平行化架构上包括平行化初始位址，折叠记忆位址，交错位址，选择器，区分器，平行化架构上的折叠记忆位址分别与选择器连接，同时所有的折叠记忆位址相互串联。
对折叠记忆体位址选择器排序区分，先行计算平行化架构的初始位址再同时经过加法器与选择器，并采用区分器将资料进行排序，平行化架构的固定延迟时间为三个循环周期。
根据位址产生器所产出的交错位址,将记忆体a，记忆体b，记忆体c，记忆体d，经过排序后为记忆体b，记忆体a，记忆体c，记忆体d。
请参阅图1，实施例1：一个平行化架构为四得资料交错处理，处理资料量为6144位元，平行化架构上设有位址产生器1，位址产生器2，位址产生器3，位址产生器4，最小选择器，记忆体1，记忆体2，记忆体3，记忆体4，平行交错绕线，处理器1，处理器2，处理器3，处理器4，所述位址产生器1，位址产生器2，位址产生器3，位址产生器4分别与最小选择器连接，最小选择器分别与记忆体1，记忆体2，记忆体3，记忆体4连接，所述记忆体1，记忆体2，记忆体3，记忆体4均与平行交错绕线连接，平行交错绕线分别与处理器1，处理器2，处理器3，处理器4连接，所述 位址产生器4连接记忆体4与平行交错绕线之间的节点连接，位址产生器3连接记忆体3与平行交错绕线之间的节点连接，位址产生器,2连接记忆体2与平行交错绕线之间的节点连接，位址产生器,1连接记忆体1与平行交错绕线之间的节点连接。
请参阅图2，实施例2：旧有平行交错绕线架构,根据记忆体深度位址与折叠位址可以按照顺序求出对应位址并与交错位址比较,以4Bit讯号表示交错排序，旧有平行交错绕线架构上设有选择器a，选择器b,选择器c,选择器d,选择器a，选择器b,选择器c,选择器的一端均与交错位址连接，选择器a，选择器b,选择器c,选择器d的另一端均与区分器连接，选择器a，选择器b,选择器c,选择器d上的第三连接端头均与折叠记忆体位址连接，区分器处输入资料a,资料b,资料c，资料d,经过区分器排序后输出顺序为资料b，资料a,资料c,资料d。
请参阅图3，实施例3：本发明提供固定延迟的平行交错绕线架构上设有平行化初始位址，折叠记忆体位址，交错位址，选择器，区分器，平行化架构上的选择器分别与平行化初始位址连接，选择器均与区分器连接，输入区分器的资料a,资料b,资料c，资料d,经过区分器排序后输出顺序为资料b，资料a,资料c,资料d，本发明提供固定延迟的平行交错绕线架构,先行计算平行化架构的初始位址再同时经过加法器与选择器,最后再由区分器进行排序，此架构固定延迟时间为三个循环周期。
根据解码处理器的数量与进入的资料量,推导出相对应的初始位址,在平行加上折叠记忆体位址,再同时经过选择器排序区分，其延迟时间固定在三个循环周期,不随解码处理器增加而提升延迟时间，本发明利用平行化加法器与选择器架构,提供了一种固定延迟平行架构交错绕线机制,避免了平行化架构带来的延迟时间。
本发明的有益效果是：
(1)根据解码处理器的数量与进入的资料量,推导出相对应的初始位址,在平行加上折叠记忆体位址,再同时经过选择器排序区分，其延迟时间固定在三个循环周期,不随解码处理器增加而提升延迟时间；
(2)本发明利用平行化加法器与选择器架构,提供了一种固定延迟平行架构交错绕线机制,避免了平行化架构带来的延迟时间。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (6)

  1. 一种纠正码中规律交错器低延迟平行化架构位址绕线机制,其特征在于：包括以下步骤：
    A、根据解码处理器的数量与进入的资料量,推导出相对应的初始位址；
    B、在平行化架构上加上折叠记忆体位址；
    C、对折叠记忆体位址选择器排序区分；
    D、根据位址产生器所产出的交错位址,将资料排序。
  2. 根据权利要求1所述的一种纠正码中规律交错器低延迟平行化架构位址绕线机制,其特征在于：所述步骤A解码处理器上包括继电器，通信芯片，保险丝，变压器。
  3. 根据权利要求1所述的一种纠正码中规律交错器低延迟平行化架构位址绕线机制,其特征在于：所述步骤B平行化架构上包括平行化初始位址，折叠记忆位址，交错位址，选择器，区分器，平行化架构上的折叠记忆位址分别与选择器连接，同时所有的折叠记忆位址相互串联。
  4. 根据权利要求1所述的一种纠正码中规律交错器低延迟平行化架构位址绕线机制,其特征在于：所述C先行计算平行化架构的初始位址再同时经过加法器与选择器，并采用区分器将资料进行排序。
  5. 根据权利要求1所述的一种纠正码中规律交错器低延迟平行化架构位址绕线机制,其特征在于：所述步骤C平行化架构的固定延迟时间为三个循环周期。
  6. 根据权利要求1所述的一种纠正码中规律交错器低延迟平行化架构位址绕线机制,其特征在于：所述步骤D根据位址产生器 所产出的交错位址,将记忆体a，记忆体b，记忆体c，记忆体d，经过排序后为记忆体b，记忆体a，记忆体c，记忆体d。
PCT/CN2018/115511 2018-10-25 2018-11-14 一种纠正码中规律交错器低延迟平行化架构位址绕线机制 WO2020082450A1 (zh)

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