WO2020077931A1 - 导线及其制作方法及阵列基板 - Google Patents

导线及其制作方法及阵列基板 Download PDF

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WO2020077931A1
WO2020077931A1 PCT/CN2019/076106 CN2019076106W WO2020077931A1 WO 2020077931 A1 WO2020077931 A1 WO 2020077931A1 CN 2019076106 W CN2019076106 W CN 2019076106W WO 2020077931 A1 WO2020077931 A1 WO 2020077931A1
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conductive
layer
conductive layer
wire
adjacent
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PCT/CN2019/076106
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English (en)
French (fr)
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杨婷慧
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昆山工研院新型平板显示技术中心有限公司
昆山国显光电有限公司
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Publication of WO2020077931A1 publication Critical patent/WO2020077931A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display technology, for example, to a wire, a manufacturing method thereof, and an array substrate.
  • the flexible array substrate is a main component of a flexible OLED display panel, and includes a plurality of gate lines and a plurality of data lines arranged on the flexible substrate in a cross arrangement, and the gate lines and the data lines surround pixel units arranged in a matrix.
  • the wires may be arranged in a specific shape such as an S shape, a square wave shape, or a sawtooth shape in the plane of the array substrate.
  • this method will inevitably increase the area of the array substrate occupied by the wires, and it cannot guarantee that the wires have better tensile properties and occupy a smaller area.
  • the present application provides a wire and its manufacturing method, array substrate, display panel, and electronic equipment.
  • a conductive wire includes a first conductive layer, an intermediate conductive layer, and a second conductive layer stacked in sequence, and a plurality of isolation portions formed of a first elastic material;
  • the first conductive layer includes spaces along the extending direction of the conductive wire A plurality of first conductive portions arranged;
  • the intermediate conductive layer includes a plurality of intermediate conductive portions arranged at intervals along the extending direction of the wire;
  • the second conductive layer includes a plurality of second conductive layers arranged at intervals along the extending direction of the wire Conductive portion;
  • the isolation portion includes at least one first isolation portion and at least one second isolation portion; wherein, two adjacent first conductive portions, two adjacent middle conductive portions, and two adjacent second The conductive parts are separated by the corresponding separation parts; the adjacent two first conductive parts are separated by the first separation part; the adjacent two second conductive parts are separated by the second separation part;
  • the plurality of first conductive parts and the plurality of second conductive parts are arranged in a misaligned
  • the first conductive portion, the intermediate conductive portion, and the second conductive portion have the same material.
  • the first elastic material includes at least one of polyimide, polydimethylsiloxane, and polyurethane.
  • each first conductive portion is correspondingly connected to two adjacent second conductive portions through two adjacent middle conductive portions.
  • the thickness of the first conductive layer and the second conductive layer are equal.
  • the thickness of the first conductive layer and the second conductive layer ranges from 100 nm to 1 ⁇ m.
  • it further includes a first elastic protective layer on the side of the first conductive layer away from the middle conductive layer, and a second on the side of the second conductive layer away from the middle conductive layer Elastic protective layer.
  • the first elastic protective layer is separated by the first isolation portion into a plurality of first protective portions arranged at intervals along the extending direction of the wire.
  • the second elastic protective layer is separated by the second isolation portion into a plurality of second protective portions arranged at intervals along the extending direction of the wire.
  • the elastic modulus of the first elastic protective layer and the second elastic protective layer are both greater than the elastic modulus of the isolation portion.
  • the elastic modulus of the first elastic protective layer and the second elastic protective layer are equal.
  • the materials of the first elastic protective layer and the second elastic protective layer are second elastic materials
  • the second elastic materials are polyimide, polydimethylsiloxane, At least one of polyurethane.
  • the thickness of the first elastic protective layer and the second elastic protective layer ranges from 100 nm to 1 ⁇ m.
  • the first conductive layer, the second conductive layer and the intermediate conductive layer are multiple layers, and the first conductive layer and the second conductive layer are alternately stacked and arranged, and An intermediate conductive layer is provided between the adjacent first conductive layer and the second conductive layer.
  • An array substrate includes a flexible substrate having a plurality of pixel island regions arranged in sequence, and a flexible region located between adjacent pixel island regions, the pixel island regions being provided with an active layer , A gate insulating layer, a gate electrode, and an interlayer insulating layer; and a wire provided in the present application, the wire is provided in the flexible region and is used to connect two adjacent gate electrodes.
  • it further includes an elastic layer provided between the flexible substrate and the wire.
  • a buffer layer formed between the flexible substrate and the active layer may be further included.
  • a method of manufacturing a wire including steps:
  • first conductive layer Forming a first conductive layer on the carrier substrate, the first conductive layer including a plurality of first conductive portions spaced apart along the first direction;
  • a plurality of first isolation portions arranged at intervals in the first direction are formed on the side of the carrier substrate having the first conductive layer, and two adjacent first conductive portions are separated by one of the first isolation portions ,
  • the first isolation portion is formed of a first elastic material
  • An intermediate conductive layer and a second conductive layer are sequentially formed on the first conductive layer;
  • the intermediate conductive layer includes a plurality of intermediate conductive portions spaced apart along the first direction, each of the intermediate conductive portions is located adjacent to Between the two first isolating parts, the second conductive layer is located on the side of the first isolating part away from the bearing base, and includes a plurality of second conductive parts spaced apart along the first direction, a plurality of The second conductive portion and the plurality of first conductive portions are arranged in a misaligned manner along the first direction;
  • FIG. 1 is a schematic cross-sectional structure diagram of an array substrate in an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of the wires of the array substrate shown in FIG. 1.
  • FIG. 3 is a top view of the wire shown in FIG. 2 with the isolation portion and the second protective layer removed.
  • FIG. 4 is a flowchart of a method for manufacturing an array substrate in an embodiment of the application.
  • the array substrate is a thin-film transistor (TFT) array substrate.
  • TFT thin-film transistor
  • the array substrate must be flexible.
  • a plurality of conductive lines such as grid lines and data lines are arranged on the array substrate, and these conductive lines are arranged around the pixel units arranged in a matrix. In the process of bending or stretching, in order to prevent the wire from being broken, the wire must also be stretchable.
  • the wire can be designed to be S-shaped, so that the wire has a certain stretchability.
  • the tensile performance of the S-shaped wire is proportional to the radius of curvature, that is, the larger the radius of curvature, the better the tensile performance of the wire.
  • the larger the radius of curvature the greater the space occupied by the wire.
  • the larger the radius of curvature the larger the space occupied, and the spacing between each pixel unit will increase, thereby reducing the pixel density of the display panel and affecting the display effect.
  • an array substrate 1 includes a wire 100.
  • the wire 100 includes a first conductive layer 10, an intermediate conductive layer 20, a second conductive layer 30, and a plurality of isolation portions 40 formed of a first elastic material.
  • the first conductive layer 10 includes a plurality of first conductive portions 12 arranged at intervals along the extending direction of the wire 100.
  • the intermediate conductive layer 20 includes a plurality of intermediate conductive portions 22 arranged at intervals along the extending direction of the wire 100.
  • the second conductive layer 30 includes a plurality of second conductive portions 32 arranged at intervals along the extending direction of the wire 100.
  • the two adjacent first conductive portions 12, the two adjacent middle conductive portions 22, and the two adjacent second conductive portions 32 are all separated by corresponding isolation portions 40.
  • the partition 40 includes at least one first partition 41 and at least one second partition 42.
  • the first partition 41 and the second partition 42 are alternately provided.
  • the two adjacent first conductive portions 12 are separated by a first partition 41.
  • the two adjacent second conductive portions 32 are separated by a second partition 42.
  • the two adjacent middle conductive portions 22 are alternately spaced by the first isolation portion 41 and the second isolation portion 42.
  • the plurality of first conductive portions 12 and the plurality of second conductive portions 32 are arranged in a misaligned manner along the extending direction of the wire 100, and the adjacent first conductive portion 12 and second conductive portion 32 are connected by the intermediate conductive portion 22.
  • Two adjacent first conductive portions 12 are connected to one second conductive portion 32 through corresponding intermediate conductive portions 22, and each first conductive portion 12 is adjacent to two adjacent through two adjacent intermediate conductive portions 22
  • the second conductive portion 32 is correspondingly connected.
  • the spacing between the plurality of first conductive portions 12 of the first conductive layer 10 of the wire 100 increases, and the plurality of second conductive layers 30 The distance between the conductive portions 32 increases. Therefore, the disposition and the adjacent first conductive portion 12 and the second conductive portion 32 exert opposite forces on the opposite ends of the corresponding intermediate conductive portion 22, and the intermediate conductive portion 22 presses the isolation portion adjacent to the intermediate conductive portion 22 40.
  • the isolating portion 40 undergoes major tensile stress and undergoes elastic deformation, thereby making the wire 100 have good tensile properties.
  • the two adjacent first conductive portions 12, the two adjacent middle conductive portions 22, and the two adjacent second conductive portions 32 are all separated by the corresponding isolation portion 40, when the external force disappears, the wire Can be restored to the state before being stretched or bent.
  • the above-mentioned wire 100 has good tensile properties.
  • the wire 100 of the present application can be linear, without increasing the occupied area . Therefore, the wire 100 of the present application has better tensile properties while occupying a smaller area.
  • the wire 100 is used as a gate line or a data line on the array substrate 1, since the wire 100 occupies a small area, it is helpful to reduce the spacing between each pixel unit, thereby increasing the pixel density of the display panel and enhancing the display effect .
  • the first elastic material may be at least one of polyimide (PI), polydimethylsiloxane (PDMS), polyurethane (TPU), etc., so that the partition 40 has better elasticity Deformability.
  • PI polyimide
  • PDMS polydimethylsiloxane
  • TPU polyurethane
  • the isolation portion 40 undergoes the main tensile stress and elastically deforms, thereby reducing the tensile stress experienced by the first conductive layer, the middle conductive layer, and the second conductive layer.
  • the tensile performance of the wire is further improved, thereby improving the tensile performance of the array substrate 1.
  • the materials of the first conductive portion 12, the intermediate conductive portion 22, and the second conductive portion 32 may be the same.
  • conductive metals such as copper, gold, and silver are used.
  • the materials of the first conductive portion 12, the intermediate conductive portion 22, and the second conductive portion 32 may also be different.
  • the thickness of the first conductive layer 10 and the second conductive layer 30 are equal. In this way, during stretching, the deformation of the first conductive layer 10 and the second conductive layer 30 are consistent, which is beneficial to improve the tensile performance of the wire 100.
  • the thicknesses of the first conductive layer 10 and the second conductive layer 30 are between 100 nm and 1 ⁇ m, for example, 500 nm.
  • the thickness of the first conductive layer 10 and the second conductive layer 30 is designed to be 500 nm, so that the first conductive layer 10 and the second conductive layer 30 ensure that they have a certain tensile strength and Lower resistance. In other embodiments, the thicknesses of the first conductive layer 10 and the second conductive layer 20 may also be different.
  • each first conductive portion 12 is correspondingly connected to two adjacent second conductive portions 32 through two adjacent middle conductive portions 22. In this way, the two adjacent first conductive portions 12 and the two adjacent second conductive portions 32 are both conductive, thereby ensuring that the conducting wire 100 is in a conductive state.
  • the wire 100 further includes a first elastic protective layer 50 on the side of the first conductive layer 10 away from the middle conductive layer 20, and a second on the side of the second conductive layer 30 away from the middle conductive layer 20 Elastic protection layer 60.
  • the first elastic protective layer 50 and the second elastic protective layer 60 respectively protect the first conductive layer 10 and the second conductive layer 30 from short circuit and direct contact with the external environment, and the wire 100 is stretched When bending, it undergoes a certain tensile stress and undergoes elastic deformation, which further improves the tensile performance of the wire 100 and further improves the tensile performance of the array substrate 1.
  • the first elastic protection layer 50 is divided by the corresponding isolation portion 40 into a plurality of first protection portions 52 arranged at intervals along the extending direction of the wire 100.
  • the second elastic protective layer 60 is divided into a plurality of second protective portions 62 arranged at intervals along the extending direction of the wire 100 by the corresponding isolation portion 40.
  • the first elastic protection layer 50 is divided by the first isolation portion 41 into a plurality of first protection portions 52 that are arranged at intervals along the extending direction of the wire 100.
  • the second elastic protective layer 60 is partitioned by the second separating portion 42 into a plurality of second protective portions 62 arranged at intervals in the extending direction of the conductive wire 100.
  • the elastic modulus of the first elastic protective layer 50 and the second elastic protective layer 60 are both greater than the elastic modulus of the partition 40.
  • the isolation portion 40 extends between two adjacent first protection portions 50 and between two adjacent second protection portions 60.
  • the elastic modulus of the first protection portion 52 and the second protection portion 62 are both greater than that of the isolation portion 40, the elastic deformation of the first protection portion 52 and the second protection portion 62 is small, and the elastic deformation of the isolation portion 40 is Large, thereby reducing the amount of deformation of the first conductive portion 12 and the second conductive portion 32 that are in contact with the first protective portion 52 and the second protective portion 62, respectively, to avoid the first conductive portion 12 and the second conductive portion 32 being pulled Break, thereby enhancing the tensile performance of the wire 100, thereby increasing the tensile performance of the array substrate 1.
  • the materials of the first elastic protective layer 50 and the second elastic protective layer 60 are second elastic materials, which may be polyimide (PI), polydimethylsiloxane (PDMS), polyurethane (TPU) At least one of them.
  • the first elastic protective layer and the second elastic protective layer have a certain tensile property, and the first conductive layer 10 and the second conductive layer 30 can be better played when the wire 100 is stretched or bent To protection.
  • the thicknesses of the first elastic protective layer 50 and the second elastic protective layer 60 are between 100 nm and 1 ⁇ m, for example, 500 nm.
  • the thickness of the first elastic protective layer 50 and the second elastic protective layer 60 is designed to be 500 nm, which can reduce the thickness of the wire 100 as much as possible while satisfying the protection and tensile properties.
  • the elastic modulus of the first elastic protective layer 50 and the second elastic protective layer 60 are equal. In this way, during the process of the wire 100 being stretched, the deformation amounts of the first elastic protective layer 50 and the second elastic protective layer 60 are the same, so that the shear deformation amounts of the respective intermediate conductive portions 22 are also the same to avoid local deformation of the wire 100 If the amount is too large, the corresponding intermediate conductive portion 22 is pulled off, which further improves the tensile performance of the wire 100 and further improves the tensile performance of the array substrate 1.
  • the wire 100 may include multiple first conductive layers, multiple intermediate conductive layers, and multiple second conductive layers. Wherein, the first conductive layer and the second conductive layer are alternately stacked and arranged, and an intermediate conductive layer is provided between each adjacent first conductive layer and the second conductive layer. In this way, even if a certain conductive layer is broken, the wire 100 can be ensured to be conductive, and the tensile performance of the wire 100 is further improved.
  • the array substrate 1 further includes a flexible substrate 200 having a plurality of pixel island regions 202 arranged in sequence and between adjacent pixel island regions 202 'S flexible area 204.
  • Each pixel island region 202 includes at least two pixel columns as effective display areas, each pixel column includes a plurality of pixel units defined by gate lines and data lines, and each pixel unit includes a thin film transistor and an organic light emitting unit.
  • the thin film transistor of the pixel island region 202 includes an active layer 400, a gate insulating layer 500, a gate electrode 600, and an interlayer insulating layer 700 provided on the flexible substrate 200.
  • the wire 100 is provided in the flexible region and is used to electrically connect the gate electrode 600 of the adjacent pixel island region.
  • an elastic layer 800 may be provided between the flexible substrate 200 and the wire 100, and the elastic layer 800 is used to support the wire 100.
  • the array substrate 1 may further include a buffer layer 300, which is formed between the flexible substrate 200 and the active layer 400.
  • the wire 100 of the array substrate 1 can be applied to the gate line electrically connecting the gate electrode 600, but it is not limited thereto, and can also be applied to other connection lines, such as data lines, scan lines, edge traces, and the like.
  • the present application also provides a manufacturing method of the wires of the array substrate.
  • a manufacturing method of a wire in an embodiment of the present application includes:
  • Step S110 forming a first conductive layer 10 on the carrier substrate.
  • the first conductive layer 10 includes a plurality of first conductive portions 12 spaced apart along the first direction;
  • a layer of conductive material is formed on the carrier substrate, and the layer of conductive material is patterned by an etching process to form the first conductive layer 10.
  • a layer of second elastic material is formed on the carrier substrate, and a layer of conductive material is formed on the layer of second elastic material. Then, the conductive material and the second elastic material are patterned by an etching process to form the first conductive layer 10 and the first elastic protective layer 50, respectively.
  • the first elastic protective layer 50 includes a plurality of first protective portions 52 arranged along the first direction.
  • Step S120 forming a plurality of first isolation portions 41 spaced along the first direction on the side of the carrier substrate having the first conductive layer 10. Two adjacent first conductive portions 12 are separated by a first isolation portion 41, and the first isolation portion 41 is formed of a first elastic material;
  • a layer of first elastic material is coated on the side of the carrier substrate having the first conductive layer 10, and the layer of first elastic material is patterned to form a plurality of first isolation portions 41 spaced apart along the first direction , And two adjacent first conductive portions 12 are separated by a first isolation portion 41. Further, the first elastic material may be patterned to form a plurality of first isolation parts 41 by using laser laser, plasma bombardment and other processes.
  • Step S130 an intermediate conductive layer 20 and a second conductive layer 30 are sequentially formed on the first conductive layer 10; the intermediate conductive layer 20 includes a plurality of intermediate conductive portions 22 spaced apart along the first direction, and each intermediate conductive portion 22 is located in the phase Between two adjacent first isolation portions 41, the second conductive layer 30 is located on the side of the first isolation portion 41 away from the load-bearing base, and includes a plurality of second conductive portions 32 spaced apart along the first direction, and a plurality of second conductive portions The portion 32 and the plurality of first conductive portions 12 are arranged offset in the first direction.
  • a layer of conductive material is formed on the first conductive layer 10, and the portion of the conductive material filled between adjacent two isolation portions 40 forms an intermediate conductive portion 22, which is located on each first isolation portion 41 away from the carrier substrate The portion on one side is patterned using an etching process to form the second conductive layer 30.
  • a layer of conductive material is formed on the first conductive layer 10, and the layer of conductive material is filled between two adjacent first isolation portions 41 and covers the plane where the surface of the first isolation portion 41 away from the carrier substrate is located.
  • the conductive material is patterned by an etching process so that the conductive material is filled between adjacent two first isolation portions 41 to form an intermediate conductive layer 20 including a plurality of intermediate conductive portions 22, and the conductive material is located in each first
  • the portion of the side of the partition 41 away from the carrier substrate forms a second conductive layer 30 including a plurality of second conductive portions 32.
  • the method further includes using a mechanical chemical polishing process (CMP) to grind the conductive material on the side of each first isolation portion 41 away from the carrier substrate to achieve a desired thickness.
  • CMP mechanical chemical polishing process
  • a coating process may also be used to form a layer of second elastic material on the conductive material.
  • the second elastic material and the conductive material are simultaneously patterned to form a second conductive layer 30 and a second elastic protective layer 60.
  • the second elastic protective layer 60 includes spaced along the first direction Multiple second protection parts 62.
  • Step S140 forming a second isolation portion 42 between two adjacent second conductive portions 32, so that the adjacent two second conductive portions 32 are separated by a second isolation portion 42, and the second isolation portion 42 is formed by the first The elastic material is formed.
  • a first elastic material is filled between two adjacent second conductive portions 32 and two adjacent middle conductive portions 22 respectively corresponding to the two adjacent second conductive portions 32 to form a second isolation
  • the portion 42 is such that two adjacent second conductive portions 32 are separated by one second isolation portion 42, and the intermediate conductive portions 22 are alternately spaced by the first isolation portion 41 and the second isolation portion 42.
  • step 140 specifically includes: between two adjacent second conductive portions 32 and between two adjacent second protective portions 62 The first elastic material is filled therebetween to form a second partition 42 with a gap between two adjacent second conductive portions 32 and a gap between two adjacent second protection portions 62.
  • Step S150 Remove the carrier substrate.
  • CMP mechanical chemical polishing process
  • dry etching dry etching
  • wet etching etc.
  • the present application also provides a manufacturing method of an array substrate, which includes the manufacturing method of the above-mentioned wire.
  • step S110 there are further steps: forming a flexible substrate 200 on the carrier substrate; forming functional films such as an active layer 400, a gate insulating layer 500, a gate electrode 600, and a layer insulating layer 700 on the flexible substrate 200 Floor.
  • first direction is the extending direction of the wire 100 of the array substrate.
  • first direction is the horizontal direction shown.
  • the present application also provides a display panel.
  • the display panel includes the array substrate as described in any of the above embodiments.
  • the display panel may be a display terminal, such as a tablet computer.
  • the display panel may also be a mobile communication terminal, such as a mobile phone terminal.
  • the present application also provides an electronic device.
  • the electronic device includes the display panel as in any of the above embodiments.
  • the electronic device may be a wearable device, a sensor skin of a robot, a biological device in which a body may be embedded or attachable, a stretchable display device, an Internet of Things device, an artificial intelligence device, or the like.

Abstract

本申请涉及一种导线及其制作方法及阵列基板。本申请的导线(100)包括依次层叠设置的第一导电层(10)、中间导电层(20)、第二导电层(30)，以及由第一弹性材料形成的多个隔离部(40)。第一导电层(10)包括多个沿导线(100)延伸方向间隔布设的第一导电部(12)。中间导电层(20)包括多个沿导线(100)延伸方向间隔布设的中间导电部(22)。第二导电层(30)包括多个沿导线(100)延伸方向间隔布设的第二导电部(32)。隔离部(40)包括至少一个第一隔离部(41)和至少一个第二隔离部(42)。相邻的两个第一导电部(12)、相邻的两个中间导电部(22)及相邻的两个第二导电部(32)均通过隔离部(40)间隔。多个第一导电部(12)与多个第二导电部(32)沿导线(100)延伸方向错位排布，且相邻的所述第一导电部(12)和所述第二导电部(32)由所述中间导电部(22)连接。

Description

导线及其制作方法及阵列基板
相关申请的交叉引用
本申请要求于2018年10月17日提交中国专利局、申请号为201811208780.3、发明名称为“阵列基板及其制作方法、显示面板、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种导线及其制作方法及阵列基板。
背景技术
随着显示技术的不断发展，OLED(Organic Light-Emitting Display)技术越来越多的应用于柔性显示面板中。柔性阵列基板是柔性OLED显示面板的主要部件，包括设置在柔性基板上的交叉排布的多条栅线和多条数据线，栅线和数据线围呈矩阵排列的像素单元。为了提高导线(可包括栅线、数据线等)的拉伸性能，可以将导线在阵列基板的平面内布设呈S形、方波形、锯齿形等特定形状。但是，该方式势必会增加导线所占用的阵列基板的面积，无法保证导线具有较佳的拉伸性能的同时所占用的面积较小。
发明内容
本申请提供一种导线及其制作方法、阵列基板、显示面板、电子设备。
一种导线，包括依次层叠设置的第一导电层、中间导电层和第二导电层，以及由第一弹性材料形成的多个隔离部；所述第一导电层包括沿所述导线延 伸方向间隔布设的多个第一导电部；所述中间导电层包括沿所述导线延伸方向间隔布设的多个中间导电部；所述第二导电层包括沿所述导线延伸方向间隔布设的多个第二导电部；所述隔离部包括至少一个第一隔离部和至少一个第二隔离部；其中，相邻的两个第一导电部、相邻的两个中间导电部及相邻的两个第二导电部均通过对应的所述隔离部间隔；相邻的两个第一导电部由所述第一隔离部间隔；相邻的两个第二导电部由所述第二隔离部间隔；所述多个第一导电部与所述多个第二导电部沿所述导线延伸方向错位排布，且相邻的所述第一导电部和所述第二导电部由所述中间导电部连接。
在其中一个实施例中，所述第一导电部、所述中间导电部及所述第二导电部的材料相同。
在其中一个实施例中，所述第一弹性材料包括聚酰亚胺、聚二甲基硅氧烷、聚氨酯中的至少一种。
在其中一个实施例中，每个第一导电部通过相邻的两个中间导电部对应连接于相邻的两个第二导电部。
在其中一个实施例中，所述第一导电层与所述第二导电层的厚度相等。
在其中一个实施例中，所述第一导电层及所述第二导电层的厚度范围为100nm至1μm。
在其中一个实施例中，还包括位于所述第一导电层远离所述中间导电层一侧的第一弹性保护层，以及位于所述第二导电层远离所述中间导电层一侧的第二弹性保护层。
在其中一个实施例中，所述第一弹性保护层被所述第一隔离部分隔成沿所述导线延伸方向间隔布设的多个第一保护部。
在其中一个实施例中，所述第二弹性保护层被所述第二隔离部分隔成沿所述导线延伸方向间隔布设的多个第二保护部。
在其中一个实施例中，所述第一弹性保护层和所述第二弹性保护层的弹性模量均大于所述隔离部的弹性模量。
在其中一个实施例中，所述第一弹性保护层和所述第二弹性保护层的弹性模量相等。
在其中一个实施例中，所述第一弹性保护层和所述第二弹性保护层的材料为第二弹性材料，所述第二弹性材料为聚酰亚胺、聚二甲基硅氧烷、聚氨酯中的至少一种。
在其中一个实施例中，所述第一弹性保护层和所述第二弹性保护层的厚度范围为100nm至1μm。
在其中一个实施例中，所述第一导电层，所述第二导电层及所述中间导电层均为多层，所述第一导电层与所述第二导电层交替层叠排布，且相邻的所述第一导电层与所述第二导电层之间设有一层中间导电层。
一种阵列基板包括柔性衬底，所述柔性衬底具有多个依次排列的像素岛区域，以及位于相邻的所述像素岛区域之间的柔性区域，所述像素岛区域设有有源层、栅极绝缘层、栅电极和层间绝缘层；及本申请提供的导线，所述导线设于所述柔性区域，用于连接相邻的两个栅电极。
在其中一个实施例中，还包括设于所述柔性衬底与所述导线之间的弹性层。
在其中一个实施例中，还可包括形成于所述柔性衬底与所述有源层之间的缓冲层。
一种导线的制作方法，包括步骤：
在承载基板上形成第一导电层，所述第一导电层包括沿第一方向间隔布设的多个第一导电部；
在所述承载基板具有所述第一导电层的一侧形成沿所述第一方向间隔排布的多个第一隔离部，相邻两个第一导电部由一个所述第一隔离部间隔，所述第一隔离部由第一弹性材料形成；
在所述第一导电层上依次形成中间导电层和第二导电层；所述中间导电层包括沿所述第一方向间隔布设的多个中间导电部，每个所述中间导电部位于相邻两个第一隔离部之间，所述第二导电层位于所述第一隔离部远离所述承载基本的一侧，包括沿所述第一方向间隔布设的多个第二导电部，多个所述第二导电部与多个所述第一导电部沿所述第一方向错位排布；
在相邻两个第二导电部之间形成第二隔离部，使得相邻两个所述第二导电部由一个所述第二隔离部间隔，所述第二隔离部由第一弹性材料形成；
去除所述承载基板。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将根据说明书、附图以及权利要求书的描述变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请一些实施例的附图，对于本领域普通技术人员来讲，在不付出创造性劳 动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为本申请一实施方式中阵列基板的剖面结构示意图。
图2为图1所示的阵列基板的导线的剖面示意图。
图3为图2所示的导线去除了隔离部和第二保护层的俯视图。
图4为本申请一实施方式中阵列基板的制作方法的流程图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
在对本申请进行详细说明之前，首先对本申请中的一些内容进行解释，以便于更清楚地理解本申请的技术方案。
本实施例中，阵列基板为薄膜晶体管(Thin-film transistor，TFT)阵列基板。
相较于传统的TFT-LCD技术，OLED技术的一大优势在于其具有良好的柔韧性，可用于制作可折叠或可卷曲的显示产品。对于柔性OLED显示面板，阵列基板必须为柔性。阵列基板上排布有若干栅线、数据线等导线，这些导线围绕呈矩阵排列的像素单元设置。在弯折或拉伸的过程中，为了避免导线被拉断，就必须使得导线也具有可拉伸性。
因此，可以将导线设计为呈S形，以使导线具有一定的可拉伸性能。呈S形的导线的拉伸性能与曲率半径呈正比，即曲率半径越大，导线的拉伸性 能越好。然而，曲率半径越大，导线所占的空间也就越大。例如，对于呈S形的栅线和数据线，曲率半径越大，所占空间越大，各个像素单元之间的间距会增加，从而降低了显示面板的像素密度，影响显示效果。
因此，有必要提供一种导线拉伸性能好且占用空间小的阵列基板。
下面，将参照附图详细描述本申请实施例中的阵列基板。
请参阅图1，本申请一实施例提供的阵列基板1，包括导线100。请一并参阅图2及图3，该导线100包括依次层叠设置的第一导电层10、中间导电层20、第二导电层30，以及多个由第一弹性材料形成的隔离部40。
第一导电层10包括多个沿导线100延伸方向间隔布设的第一导电部12。中间导电层20包括多个沿导线100延伸方向间隔布设的中间导电部22。第二导电层30包括多个沿导线100延伸方向间隔布设的第二导电部32。
相邻的两个第一导电部12、相邻的两个中间导电部22及相邻的两个第二导电部32均通过对应的隔离部40间隔。如图3所示，可选地，隔离部40包括至少一个第一隔离部41和至少一个第二隔离部42。第一隔离部41和第二隔离部42交替设置。相邻的两个第一导电部12通过第一隔离部41间隔。相邻的两个第二导电部32通过第二隔离部42间隔。相邻的两个中间导电部22通过第一隔离部41和第二隔离部42交替间隔。
其中，多个第一导电部12与多个第二导电部32沿导线100延伸方向错位排布，相邻的第一导电部12和第二导电部32由中间导电部22连接。，两个相邻的第一导电部12均通过对应的中间导电部22与一个第二导电部32连接，每个第一导电部12通过两个相邻的中间导电部22与两个相邻的第二导电部32对应连接。
当上述导线100在外力的作用下被拉伸或弯折时，导线100的第一导电层10的多个第一导电部12之间的间距增大，第二导电层30的多个第二导电部32之间的间距增大。因此，错位布置且相邻的第一导电部12和第二导电部32施加给对应的中间导电部22两端的作用力相反，中间导电部22挤压与该中间导电部22相邻的隔离部40，隔离部40承受主要的拉伸应力而发生弹性变形，进而使得导线100具有良好的拉伸性能。并且，由于相邻的两个第一导电部12、相邻的两个中间导电部22及相邻的两个第二导电部32均通过对应的隔离部40间隔开来，当外力消失，导线能够恢复至被拉伸或折弯之前的状态。
如此，上述导线100具有良好的拉伸性能，与将导线设计为呈S形、方波形、锯齿形等特定形状的方式相比，本申请的导线100可呈直线形，不增加所占用的面积。故，本申请的导线100具有较佳的拉伸性能的同时所占用的面积较小。例如，当导线100用作阵列基板1上的栅线、数据线等时，由于导线100占用面积小，有利于缩小各个像素单元之间的间距，进而增大显示面板的像素密度，增强显示效果。
可选地，上述第一弹性材料可以是聚酰亚胺(PI)、聚二甲基硅氧烷(PDMS)、聚氨酯(TPU)等中的至少一种，使得隔离部40具有较好的弹性变形性能。在导线100被拉伸或弯折的过程中，隔离部40承受主要的拉伸应力而发生弹性变形，从而减小第一导电层、中间导电层及第二导电层所承受的拉伸应力，进一步提升了导线的拉伸性能，进而提升了阵列基板1的拉伸性能。
在一个实施例中，第一导电部12、中间导电部22及第二导电部32的材 料可以相同，例如采用铜、金、银等导电金属。在其他实施例中，第一导电部12、中间导电部22及第二导电部32的材料也可以不同。
在一个实施例中，第一导电层10与第二导电层30的厚度相等。如此，在拉伸时，第一导电层10与第二导电层30的变形情况一致，有利于提升导线100的拉伸性能。可选地，第一导电层10及第二导电层30的厚度在100nm至1μm之间，例如为500nm。将第一导电层10及第二导电层30的厚度设计为500nm，使得第一导电层10及第二导电层30在不大幅增加导线100厚度的情况下，保证其具有一定的抗拉强度和较低的电阻。在其它实施例中，第一导电层10与第二导电层20的厚度也可以不等。
在一个实施例中，每个第一导电部12通过相邻的两个中间导电部22对应连接于相邻的两个第二导电部32。如此，相邻两个第一导电部12及相邻两个第二导电部32均导通，从而保证导线100的处于导通状态。
在一个实施例中，导线100还包括位于第一导电层10远离中间导电层20一侧的第一弹性保护层50，以及位于第二导电层30远离所述中间导电层20一侧的第二弹性保护层60。如此，第一弹性保护层50及第二弹性保护层60分别对第一导电层10及第二导电层30起到保护作用，避免其短路以及直接与外部环境接触，并且在导线100被拉伸或弯折时，承受一定的拉伸应力而发生弹性变形，进一步提升导线100的拉伸性能，进而进一步提升阵列基板1的拉伸性能。
在一些实施例中，第一弹性保护层50被对应的隔离部40分隔成沿导线100延伸方向间隔布设的多个第一保护部52。第二弹性保护层60被对应的隔离部40分隔成沿导线100延伸方向间隔布设的多个第二保护部62。本实施 例中，第一弹性保护层50被第一隔离部41分隔成沿导线100延伸方向间隔布设的多个第一保护部52。第二弹性保护层60被第二隔离部42分隔成沿导线100延伸方向间隔布设的多个第二保护部62。
其中，第一弹性保护层50和第二弹性保护层60的弹性模量均大于隔离部40的弹性模量。如此，隔离部40延伸至相邻的两个第一保护部50之间以及相邻的两个第二保护部60之间。在阵列基板1被拉伸或弯折的过程中，第一弹性保护层50通过第一保护部52以及相应的隔离部40的弹性变形而沿导线100的延伸方向伸长，第二弹性保护层60通过第二保护部62以及相应地隔离部40的弹性变形而沿导线100的延伸方向伸长。由于第一保护部52和第二保护部62的弹性模量均大于隔离部40的弹性模量，第一保护部52与第二保护部62的弹性变形较小，隔离部40的弹性变形较大，从而减小了分别与第一保护部52和第二保护部62接触的第一导电部12和第二导电部32的变形量，避免第一导电部12和第二导电部32被拉断，从而增强了导线100的拉伸性能，进而增加了阵列基板1的拉伸性能。
可选地，第一弹性保护层50和第二弹性保护层60的材料为第二弹性材料，可以是聚酰亚胺(PI)、聚二甲基硅氧烷(PDMS)、聚氨酯(TPU)等中的至少一种。如此，第一弹性保护层和第二弹性保护层具有一定的拉伸性能，在导线100被拉伸或弯折的过程中，能够更好地对第一导电层10和第二导电层30起到保护作用。第一弹性保护层50和第二弹性保护层60的厚度在100nm至1μm之间，例如为500nm。将第一弹性保护层50和第二弹性保护层60的厚度设计为500nm，可在满足保护和拉伸性能的同时尽可能地减小导线100的厚度。
进一步地，第一弹性保护层50和第二弹性保护层60的弹性模量相等。如此，在导线100被拉伸的过程中，第一弹性保护层50与第二弹性保护层60的变形量一致，使得各个中间导电部22的剪切变形量也一致，避免导线100的局部变形量过大而导致对应的中间导电部22被拉断，进一步提升了导线100的拉伸性能，进而进一步提升了阵列基板1的拉伸性能。
本申请的实施例中，导线100可包括多层第一导电层、多层中间导电层及多层第二导电层。其中，第一导电层与第二导电层交替层叠排布，且每一相邻的第一导电层与第二导电层之间设有一中间导电层。如此，即使是某一导电层被拉断，也能保证导线100能够导通，进一步提升了导线100的拉伸性能。
请再次参阅图1，在本申请一个实施例中，阵列基板1还包括柔性衬底200，该柔性衬底200具有多个依次排列的像素岛区域202以及位于相邻的像素岛区域202之间的柔性区域204。其中，每个像素岛区域202包括至少两个作为有效显示区的像素列，每个像素列包括多个由栅线和数据线限定的像素单元，每个像素单元包括薄膜晶体管和有机发光单元。像素岛区域202的薄膜晶体管包括设于柔性衬底200上的有源层400、栅极绝缘层500、栅电极600和层间绝缘层700。导线100设于柔性区域，用于电连接相邻像素岛区域的栅电极600。
进一步地，柔性衬底200与导线100之间可设置弹性层800，该弹性层800用于支撑导线100。
需要说明的是，阵列基板1还可包括缓冲层300，缓冲层300形成于柔性衬底200与有源层400之间。
需要说明的是，阵列基板1的导线100可应用于电连接栅电极600的栅线，但不仅限于此，还可应用于其它连接线，例如数据线、扫描线、边缘走线等。
为了进一步理解本申请的技术方案，本申请还提供了一种阵列基板的导线的制作方法。
请参阅图4，本申请一实施例中的导线的制作方法，包括：
步骤S110：在承载基板上形成第一导电层10。第一导电层10包括沿第一方向间隔布设的多个第一导电部12；
具体地，在一个实施例中，在承载基板上形成一层导电材料，通过刻蚀工艺对该层导电材料层进行图案化，形成第一导电层10。
具体地，在另一个实施例中，在承载基板上形成一层第二弹性材料，在该层第二弹性材料上形成一层导电材料。然后，通过蚀刻工艺对该导电材料及第二弹性材料进行图案化，从而分别形成第一导电层10和第一弹性保护层50。第一弹性保护层50包括沿第一方向布设的多个第一保护部52。
步骤S120：在承载基板具有第一导电层10的一侧形成沿第一方向间隔排布的多个第一隔离部41。相邻两个第一导电部12由一个第一隔离部41间隔，第一隔离部41由第一弹性材料形成；
具体地，在承载基板具有第一导电层10的一侧涂布一层第一弹性材料，对该层第一弹性材料进行图案化，形成沿第一方向间隔布设的多个第一隔离部41，且相邻两个第一导电部12由一个第一隔离部41间隔。进一步地，可采用激光镭射、plasma轰击等工艺将第一弹性材料图案化以形成多个第一隔离部41。
步骤S130：在第一导电层10上依次形成中间导电层20和第二导电层30；中间导电层20包括沿第一方向间隔布设的多个中间导电部22，每个中间导电部22位于相邻两个第一隔离部41之间，第二导电层30位于第一隔离部41远离承载基本的一侧，包括沿第一方向间隔布设的多个第二导电部32，多个第二导电部32与多个第一导电部12沿第一方向错位排布。
具体地，在第一导电层10上形成一层导电材料，该层导电材料填充于相邻两个隔离部40之间的部分形成中间导电部22，位于各个第一隔离部41远离承载基板的一侧的部分采用蚀刻工艺进行图案化，形成第二导电层30。具体地，在第一导电层10上形成一层导电材料，该层导电材料填充于相邻两个第一隔离部41之间并覆盖第一隔离部41远离承载基板的表面所在的平面。对导电材料采用蚀刻工艺进行图案化，以使导电材料填充于相邻两个第一隔离部41之间的部分形成包括多个中间导电部22的中间导电层20，而导电材料位于各个第一隔离部41远离承载基板的一侧的部分形成包括多个第二导电部32的第二导电层30。
进一步地，进行图案化之前，还包括采用机械化学抛光工艺(CMP)对位于各个第一隔离部41远离承载基板的一侧的导电材料进行研磨，以达到所需的厚度。
进一步地，进行研磨之后，还可采用涂布工艺在导电材料上形成一层第二弹性材料。在进行图案化时，同时对该层第二弹性材料和导电材料进行图案化，以形成第二导电层30和第二弹性保护层60，第二弹性保护层60包括沿第一方向间隔布设的多个第二保护部62。
步骤S140：在相邻两个第二导电部32之间形成第二隔离部42，以使相 邻两个第二导电部32由一个第二隔离部42间隔，第二隔离部42由第一弹性材料形成。
具体地，在相邻两个第二导电部32及分别与该相邻两个第二导电部32对应连接的两个相邻中间导电部22之间填充第一弹性材料，以形成第二隔离部42，使得相邻两个第二导电部32由一个第二隔离部42间隔，中间导电部22由第一隔离部41和第二隔离部42交替间隔。
当阵列基板的导线100包括第二保护层60时，本申请的一个实施例中，步骤140具体包括：在相邻两个第二导电部32之间和相邻两个第二保护部62之间填充第一弹性材料，以相邻两个第二导电部32之间的间隙和相邻两个第二保护部62之间的间隙形成第二隔离部42。步骤S150：去除承载基板。
具体地，可采用机械化学抛光工艺(CMP)、干法蚀刻、湿法蚀刻等去除承载基板。
本申请还提供一种阵列基板的制作方法，该制作方法包括上述导线的制作方法。另外，在步骤S110之前还包括步骤：在承载基板上成形柔性衬底200；在柔性衬底200上形成有源层400、栅极绝缘层500、栅电极600及层件绝缘层700等功能膜层。
需要说明的是，上述第一方向即为阵列基板的导线100的延伸方向。在图2所示的实施例中，第一方向即为图示的水平方向。
基于上述阵列基板，本申请还提供一种显示面板。该显示面板包括如上任一实施例中所述的阵列基板。在一些实施例中，该显示面板可为显示终端，例如平板电脑。在另一些实施例中，该显示面板亦可为移动通信终端，例如手机终端。
基于上述显示面板，本申请还提供一种电子设备。该电子设备包括如上任一实施例中的显示面板。一些实施例中，该电子设备可以是可穿戴设备、机器人的传感器皮肤、身体可嵌入或可附接生物设备、可拉伸显示装置、物联网设备、人工智能设备等。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种导线，包括依次层叠设置的第一导电层、中间导电层和第二导电层，以及由第一弹性材料形成的多个隔离部；
    所述第一导电层包括沿所述导线延伸方向间隔布设的多个第一导电部；
    所述中间导电层包括沿所述导线延伸方向间隔布设的多个中间导电部；
    所述第二导电层包括沿所述导线延伸方向间隔布设的多个第二导电部；
    所述隔离部包括至少一个第一隔离部和至少一个第二隔离部；
    其中，相邻的两个第一导电部、相邻的两个中间导电部及相邻的两个第二导电部均通过对应的所述隔离部间隔；相邻的两个第一导电部由所述第一隔离部间隔；相邻的两个第二导电部由所述第二隔离部间隔；
    所述多个第一导电部与所述多个第二导电部沿所述导线延伸方向错位排布，且相邻的所述第一导电部和所述第二导电部由所述中间导电部连接。
  2. 根据权利要求1所述的导线，其中，所述第一导电部、所述中间导电部及所述第二导电部的材料相同。
  3. 根据权利要求1所述的导线，其中，所述第一弹性材料包括聚酰亚胺、聚二甲基硅氧烷、聚氨酯中的至少一种。
  4. 根据权利要求1所述的导线，其中，每个第一导电部通过相邻的两个中间导电部对应连接于相邻的两个第二导电部。
  5. 根据权利要求1所述的导线，其中，所述第一导电层与所述第二导电层的厚度相等。
  6. 根据权利要求1所述的导线，其中，所述第一导电层与所述第二导电层的厚度范围为100nm至1μm。
  7. 根据权利要求1所述的导线，还包括位于所述第一导电层远离所述中间导电层一侧的第一弹性保护层，以及位于所述第二导电层远离所述中间导电层一侧的第二弹性保护层。
  8. 根据权利要求7所述的导线，其中，所述第一弹性保护层被第一隔离 部分隔成沿所述导线延伸方向间隔布设的多个第一保护部。
  9. 根据权利要求7所述的导线，其中，所述第二弹性保护层被第二隔离部分隔成沿所述导线延伸方向间隔布设的多个第二保护部。
  10. 根据权利要求7所述的导线，其中，所述第一弹性保护层和所述第二弹性保护层的弹性模量均大于所述隔离部的弹性模量。
  11. 根据权利要求7所述的导线，其中，所述第一弹性保护层和所述第二弹性保护层的弹性模量相等。
  12. 根据权利要求7所述的导线，其中，所述第一弹性保护层和所述第二弹性保护层的材料为第二弹性材料，所述第二弹性材料为聚酰亚胺、聚二甲基硅氧烷、聚氨酯中的至少一种。
  13. 根据权利要求7所述的导线，其中，所述第一弹性保护层和所述第二弹性保护层的厚度范围为100nm至1μm。
  14. 根据权利要求1所述的导线，其中，所述第一导电层，所述第二导电层及所述中间导电层均为多层，所述第一导电层与所述第二导电层交替层叠排布，且相邻的所述第一导电层与所述第二导电层之间设有一层中间导电层。
  15. 一种阵列基板，包括：
    柔性衬底，所述柔性衬底具有多个依次排列的像素岛区域，以及位于相邻的所述像素岛区域之间的柔性区域；所述像素岛区域设有有源层、栅极绝缘层、栅电极和层间绝缘层；及
    如权利要求1所述的导线，所述导线设于所述柔性区域，用于连接相邻的两个栅电极。
  16. 根据权利要求15所述的阵列基板，还包括设于所述柔性衬底与所述导线之间的弹性层。
  17. 根据权利要求15所述的阵列基板，还包括形成于所述柔性衬底与所述有源层之间的缓冲层。
  18. 一种导线的制作方法，包括：
    在承载基板上形成第一导电层，所述第一导电层包括沿第一方向间隔布设的多个第一导电部；
    在所述承载基板具有所述第一导电层的一侧形成沿所述第一方向间隔排布的多个第一隔离部，相邻两个第一导电部由一个所述第一隔离部间隔，所述第一隔离部由第一弹性材料形成；
    在所述第一导电层上依次形成中间导电层和第二导电层；所述中间导电层包括沿所述第一方向间隔布设的多个中间导电部，每个所述中间导电部位于相邻两个第一隔离部之间；所述第二导电层位于所述第一隔离部远离所述承载基板的一侧，包括沿所述第一方向间隔布设的多个第二导电部，多个所述第二导电部与多个所述第一导电部沿所述第一方向错位排布；
    在相邻两个第二导电部之间形成第二隔离部，使得相邻两个第二导电部通过一个第二隔离部间隔，所述第二隔离部由第一弹性材料形成；及
    去除所述承载基板。
PCT/CN2019/076106 2018-10-17 2019-02-26 导线及其制作方法及阵列基板 WO2020077931A1 (zh)

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