WO2020073567A1 - 阵列基板及其显示面板和制作方法 - Google Patents

阵列基板及其显示面板和制作方法 Download PDF

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Publication number
WO2020073567A1
WO2020073567A1 PCT/CN2019/073184 CN2019073184W WO2020073567A1 WO 2020073567 A1 WO2020073567 A1 WO 2020073567A1 CN 2019073184 W CN2019073184 W CN 2019073184W WO 2020073567 A1 WO2020073567 A1 WO 2020073567A1
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Prior art keywords
layer
substrate
metal layer
gate
active
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English (en)
French (fr)
Inventor
吴川
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display, and in particular to an array substrate and its display panel and manufacturing method.
  • the flat panel display device has many advantages such as wide color gamut and power saving, and is widely used in various fields.
  • the existing flat panel display devices mainly include liquid crystal display devices (Liquid Crystal Display, LCD), organic light emitting diode (Organic Light Emitting Diodes, OLED) display devices and quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display devices.
  • a thin film transistor Thin Film Transistor, TFT
  • TFT Thin Film Transistor
  • the object of the present application is to provide an array substrate, a display panel and a manufacturing method thereof, which increase the absorption and release path of electrostatic charges by increasing the floating metal layer of the driving circuit to improve the resistance of the display panel Electrostatic capacity.
  • An array substrate includes: a substrate including a display area configured with a plurality of active switches and a plurality of pixel electrodes, the plurality of pixel electrodes being electrically coupled to the plurality of active switches; A plurality of driving line segments are provided on the substrate and are electrically coupled to the plurality of active switches.
  • Each driving line segment includes: an insulating layer provided on the substrate; a protective layer provided on the substrate, The protective layer covers the insulating layer; a metal layer is disposed within the coverage of the driving line segment, and the metal layer is floating (also referred to as floating); wherein, the metal layer is disposed on At least one part between the substrate and the insulating layer, and between the insulating layer and the protective layer.
  • a display panel comprising: an array substrate, an opposite substrate, the opposite substrate being arranged opposite to the array substrate; wherein, the array substrate comprises: a substrate, including a display area, the The display area is configured with a plurality of active switches and a plurality of pixel electrodes.
  • the plurality of pixel electrodes are electrically coupled to the plurality of active switches; a plurality of driving line segments are provided on the substrate and electrically coupled to the plurality Active switches, each driving line segment includes: an insulating layer disposed on the substrate; a protective layer disposed on the substrate, the protective layer covering the insulating layer; a metal layer disposed on the driving line segment Within the coverage, and the metal layer is floating; wherein, the metal layer is disposed between the substrate and the insulating layer, and at least a part of the insulating layer and the protective layer.
  • Still another object of the present application is a method for manufacturing an array substrate, including: providing a substrate; forming a first metal layer and a gate layer on the substrate, the first metal layer being located within a predetermined setting range of the source line , And there is a separation distance between the first metal layer and the gate layer, and the first metal layer is floating; forming an insulating layer, the insulating layer to cover the first metal layer and the The gate layer is provided on the substrate; a second metal layer and an active layer are formed on the insulating layer, and the position of the active layer relative to the first metal layer, the second metal layer and There is a separation distance between the active layers, and the second metal layer is floating; a protective layer is formed, the protective layer is disposed on the insulation to cover the second metal layer and the active layer On the floor.
  • FIG. 1a is a schematic structural diagram of an exemplary display device
  • FIG. 1b is a schematic structural diagram of an exemplary pixel unit
  • 1c is a schematic diagram of pixel unit configuration of an exemplary array substrate
  • FIG. 1d is a cross-sectional view of A1 in FIG. 1c;
  • Figure 1e is a cross-sectional view of A2 in Figure 1c;
  • 2a is a schematic diagram showing a pixel area of an array substrate according to an embodiment of the method of the present application
  • FIG. 2b is a schematic cross-sectional view of the source line in FIG. 2a along the S1 line;
  • FIG. 2c is a schematic cross-sectional view of the source line in FIG. 2a along the S2 line;
  • FIG. 2d is a schematic cross-sectional view of the source line in FIG. 2a along the line G1;
  • FIG. 2e is a schematic cross-sectional view of the source line in FIG. 2a taken along the line G2;
  • FIG. 3 is a schematic diagram showing a display panel according to an embodiment of the method of the present application.
  • FIG. 4 is a schematic diagram showing an embodiment of an array substrate manufacturing process according to the method of the present application.
  • FIG. 5 is a schematic diagram showing an embodiment of an array substrate manufacturing process according to the method of the present application.
  • FIG. 6 is a schematic diagram showing an embodiment of an array substrate manufacturing process according to the method of the present application.
  • FIG. 1a is a schematic structural diagram of an exemplary display device.
  • a display device 200 includes: a control board 100 including a timing module (Timing Controller, TCON) 101; a printed circuit board 103 and a flexible flat cable passing between the control board 100 (Flexible Flat Cable, FFC) 102 is connected; the source driving unit 104 and the gate driving unit 105 are disposed in the wiring area 109, and are respectively connected to the source line 104a and the gate line 105a in the display area 106.
  • the gate driving unit 105 and the source driving unit 104 include, but are not limited to, flip-chip films.
  • the driving method of the display device 200 includes: the system motherboard provides color (for example: R / G / B) compressed signals, control signals, and power transmission to the control board 100.
  • the Timing Controller (TCON) 101 on the control board 100 after processing these signals, together with the power processed by the driving circuit, is transmitted to the printed circuit board through a flexible flat cable (Flexible Flat Cable, FFC) 102 103, the gate driving unit 105 and the source driving unit 104, the gate driving unit 105 and the source driving unit 104 transmit the necessary data and power to the display area 106, so that the display device 200 can obtain the power required to display the picture, signal.
  • FFC Flexible Flat Cable
  • FIG. 1b is a partial schematic diagram of an exemplary equivalent circuit of a pixel unit.
  • FIG. 1c is a schematic diagram of pixel unit configuration of an exemplary array substrate
  • FIG. 1d is a cross-sectional view of A1 in FIG. 1c
  • FIG. 1e is a cross-sectional view of A2 in FIG. 1c.
  • the array substrate 300 includes a substrate 310 including an active switch T, a gate line 105a, a source line 104a, and a pixel electrode P.
  • the active switch T is electrically coupled to the intersection of the gate line 105a and the source line 104a
  • the pixel electrode P is electrically coupled to the active switch T and the shared line (Com) C.
  • the gate line 105 a includes a gate layer 320, an insulating layer 330 and a protective layer 350 from the substrate 310.
  • the source line 104 a includes an insulating layer 330, an active layer 340 and a protective layer 350 from the substrate 310.
  • FIG. 2a is a schematic diagram showing a pixel area of an array substrate according to an embodiment of the method of the present application.
  • FIG. 2b is a schematic cross-sectional view of the source line in FIG. 2a along the S1 line.
  • 2c is a schematic cross-sectional view of the source line in FIG. 2a along the S2 line.
  • FIG. 2d is a schematic cross-sectional view of the source line in FIG. 2a taken along the line G1.
  • FIG. 2e is a schematic cross-sectional view of the source line in FIG. 2a taken along the line G2.
  • FIGS. 1a to 1e for the device architecture and components of the prior art, please refer to FIGS. 1a to 1e to facilitate understanding.
  • the array substrate 300 includes: a substrate 310 including a display area 106, the display area 106 is configured with a plurality of active switches T and a plurality of pixel electrodes P, so The plurality of pixel electrodes P are electrically coupled to the plurality of active switches T; a plurality of driving line segments are disposed on the substrate 310 and are electrically coupled to the plurality of active switches T.
  • Each driving line segment includes: insulation Layer 330 is disposed on the substrate 310; protective layer 350 is disposed on the substrate 310, the protective layer 350 covers the insulating layer 330; metal layers 360a and 360b are disposed on the coverage of the driving line segment And the metal layers 360a and 360b are floating; wherein, the metal layer is disposed between the substrate 310 and the insulating layer 330, and the insulating layer 330 and the protective layer 350 At least one part of it.
  • the driving line segment includes a source line 104a, and an active layer 340 is provided between the insulating layer 330 and the protective layer 350.
  • the metal layer 360a is disposed between the insulating layer 330 and the substrate 310.
  • the metal layer 360a is a floating gate layer (Floating Gate) or a floating electrode layer (Floating ITO).
  • the driving line segment includes a gate line 105a, a gate layer 320 is provided at the intersection of the source line 104a and the gate line 105a, and the gate layer 320 is disposed on the substrate 310 and Between the insulating layers 330, the metal layer 360a is disposed adjacent to the gate layer 320.
  • the metal layer 360a is separated from the two adjacent gate layers 320 by a separation distance x.
  • the separation distance x is between 3 microns and 20 microns.
  • the active layer 340 includes a source layer and a drain layer.
  • the driving line segment includes a gate line 105a, and a gate layer 320 is provided between the insulating layer 330 and the substrate 310.
  • the metal layer is disposed between the insulating layer 330 and the protective layer 350.
  • the metal layer 360b is a floating active layer (Floating SD) or a floating electrode layer (Floating ITO).
  • the driving line segment includes a source line 104a, an active layer 340 is provided at the intersection of the gate line 105a and the source line 104a, and the active layer 340 is disposed on the insulating layer 330 Between the protective layer 350, the metal layer 360b is disposed between two adjacent active layers 340.
  • the metal layer 360b is separated from the two adjacent active layers 340 by a separation distance x.
  • the separation distance x is between 3 microns and 20 microns.
  • FIG. 3 is a schematic diagram of a display panel according to an embodiment of the method of the present application. Please refer to FIGS. 2a to 2e to facilitate understanding. Please refer to FIG. 1a to FIG. 1e for current display device components.
  • a display panel includes: an array substrate 300; a counter substrate 400, which is disposed opposite to the array substrate 300, and the counter substrate 400 may be a color filter substrate, or, a color The optical filter is disposed on the array substrate 300, and the counter substrate 400 is a matching substrate configured with necessary components; wherein, the array substrate 300 includes: a substrate 310, including a display area 106, and the display area 106 is configured with multiple An active switch T and a plurality of pixel electrodes P, the plurality of pixel electrodes P are electrically coupled to the plurality of active switches T; a plurality of driving line segments are provided on the substrate 310 and electrically coupled to the A plurality of active switches T, each driving line segment includes: an insulating layer 330 disposed on
  • the array substrate 300 further includes various implementation methods described above.
  • an array substrate 300 includes: a substrate 310 including a display area configured with a plurality of active switches T and a plurality of pixel electrodes P, The plurality of pixel electrodes P are electrically coupled to the plurality of active switches T; a plurality of source lines 104a are disposed on the substrate 310 and electrically coupled to the plurality of active switches T, each source
  • the pole line 104a includes: an insulating layer 330 disposed on the substrate 310; an active layer 340 disposed between the insulating layer 330 and the protective layer 350; a protective layer 350 disposed on the substrate 310, The protective layer 350 covers the insulating layer 330 and the active layer 340; a plurality of gate lines 105a are disposed on the substrate 310, and are electrically coupled to the plurality of active switches T, each gate The line 105a includes: a gate layer 320 disposed on the substrate 310; an insulating layer 330 disposed on
  • a method for manufacturing an array substrate includes:
  • step S410 a substrate 310 is provided.
  • a metal layer 360a is formed on the substrate 310, the metal layer 360a is located within a predetermined setting range of the source line 104a, and the metal layer 360a is floating.
  • step S430 an insulating layer 330 is formed.
  • the insulating layer 330 covers the metal layer 360a and is disposed on the substrate 310.
  • Step S440 an active layer 340 is formed on the insulating layer 330, and the position of the active layer 340 is relative to the metal layer 360a.
  • Step S450 a protective layer 350 is formed, and the protective layer 350 is disposed on the insulating layer 330 to cover the active layer 340.
  • the metal layer 360a and the gate layer 320 are formed in the same step, and there is a separation distance x between the metal layer 360a and the gate layer 320.
  • FIG. 5 is a schematic diagram showing an embodiment of an array substrate manufacturing process according to the method of the present application. Please cooperate with Figure 2a, Figure 2d and Figure 2e at the same time to facilitate understanding.
  • a method for manufacturing an array substrate includes:
  • step S510 a substrate 310 is provided.
  • step S520 a gate layer 320 is formed on the substrate 310.
  • step S530 an insulating layer 330 is formed, and the insulating layer 330 is disposed on the substrate 310 to cover the gate layer 320.
  • step S540 a metal layer 360b is formed on the insulating layer 330, the metal layer 360b is located within the setting range of the gate layer 320, and the metal layer 360b is floating.
  • step S550 a protective layer 350 is formed, and the protective layer 350 is disposed on the insulating layer 330 to cover the metal layer 360b.
  • the metal layer 360b and the active layer 340 are formed in the same step, and there is a separation distance x between the metal layer 360b and the active layer 340.
  • FIG. 6 is a schematic diagram showing an embodiment of an array substrate manufacturing process according to the method of the present application. Please cooperate with Figures 2a to 2c at the same time to facilitate understanding.
  • the metal layer 360a (considered as the first metal layer) is disposed in the range of the source line 104a
  • the metal layer 360b (considered as the second metal layer) is disposed in the range of the gate line 105a
  • An array substrate manufacturing method including:
  • step S610 a substrate 310 is provided.
  • Step S620 forming a first metal layer 360a and a gate layer 320 on the substrate 310, the first metal layer 360a is located within a predetermined setting range of the source line 104a, and the first metal layer 360a and the There is a separation distance x between the gate layers 320, and the first metal layer 360a is floating.
  • step S630 an insulating layer 330 is formed, and the insulating layer 330 is disposed on the substrate 310 to cover the first metal layer 360a and the gate layer 320.
  • Step S640 forming a second metal layer 360b and an active layer 340 on the insulating layer 330, and the position of the active layer 340 relative to the first metal layer 360a, the second metal layer 360b and the There is a separation distance x between the active layers 340, and the second metal layer 360b is floating.
  • a protective layer 350 is formed.
  • the protective layer 350 is disposed on the insulating layer 330 to cover the second metal layer 360b and the active layer 340.
  • the display panel of the present application may be, for example, a liquid crystal display panel, but it is not limited thereto, it may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, a curved display panel Or other types of display panels.
  • the electrostatic charge generated in the manufacturing process can be more dispersed and the potential difference can be reduced, even if static electricity occurs in the floating metal layer, causing floating If the metal layer is burned, it will not affect the display quality, which can improve the product yield.
  • This application does not need to increase the number of photomasks, but only needs to draw the required layers accordingly during design. Therefore, it is possible to maintain the original process requirements and product costs without significantly changing the existing production process. Because there is no need to adjust the production process, there are no special process requirements and difficulties, so it will not increase costs and is extremely competitive in the market. Moreover, it does not need to increase the area of the array wiring, and is suitable for a variety of display panel designs today, and of course is also suitable for the design of the narrow border of the panel, which is in line with market and technical trends and has industrial applicability.

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Abstract

本申请提供一种阵列基板及其显示面板和制作方法，其中所述阵列基板包括：基板，基板包括显示区，显示区配置多个主动开关与多个像素电极，多个像素电极电性耦接多个主动开关；多条驱动线段，设置于基板上，并电性耦接多个主动开关，每一驱动线段包括：绝缘层，设置于基板上；保护层，设置于基板上，保护层覆盖绝缘层；以及金属层，设置于驱动线段的涵盖范围内，且金属层为浮接。

Description

阵列基板及其显示面板和制作方法 技术领域
本申请涉及显示领域，特别是涉及一种阵列基板及其显示面板和制作方法。
背景技术
平板显示装置，其具有色域广、省电等众多优点，在各领域得到广泛应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)，有机发光二极管(Organic Light Emitting Diodes，OLED)显示装置和量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示装置。其中，薄膜晶体管(Thin Film Transistor，TFT)，可形成在玻璃基板或塑料基板上，通常作为主动开关，是平板显示装置的重要组成部分之一。而随着发展，也对显示面板及显示装置提出了更多、更高的要求，如抗静电性能，部分产品由于灵敏度高，因而对主动开关等组件的抗静电性能的要求特别高。
在TFT的生产和制造过程中，会在阵列基板中镀上多个具有不同功能作用的膜层，而不同的膜层是在不同的机械设备和反应室中完成。一般而言，在镀膜和基板搬运的过程中，基板与其他媒介的接触会产生大量的静电荷，该些静电荷堆积于阵列基板上，当与传送设备接触时，会形成较大的电势差，进而将接触点附近的膜层击穿，严重影响平板显示面板或平板显示装置的质量。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种阵列基板及其显示面板和制作方法，其通过增加驱动线路的浮接金属层，增加静电电荷的吸附释放路径，以提升显示面板的抗静电能力。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种阵列基板，包括：基板，包括显示区，所述显示区配置多个主动开关与多个像素电极，所述多个像素电极电性耦接所述多个主动开关；多条驱动线段，设置于所述基板上，并电性耦接所述多个主动开关，每一驱动线段包括：绝缘层，设置于所述基板上；保护层，设置于所述基板上，所述保护层覆盖所述绝缘层；金属层，设置于所述驱动线段的涵盖范围内，且所述金属层为浮接(floating，也可称浮置)；其中，所述金属层设置于所述基板与所述绝缘层之间，以及所述绝缘层与所述保护层之间的至少其一部位。
本申请解决其技术问题还可采用以下技术措施进一步实现。
本申请的另一目的为一种显示面板，包括：阵列基板，对向基板，所述对向基板与所述 阵列基板相对设置；其中，所述阵列基板包括：基板，包括显示区，所述显示区配置多个主动开关与多个像素电极，所述多个像素电极电性耦接所述多个主动开关；多条驱动线段，设置于所述基板上，并电性耦接所述多个主动开关，每一驱动线段包括：绝缘层，设置于所述基板上；保护层，设置于所述基板上，所述保护层覆盖所述绝缘层；金属层，设置于所述驱动线段的涵盖范围内，且所述金属层为浮接；其中，所述金属层设置于所述基板与所述绝缘层之间，以及所述绝缘层与所述保护层之间的至少其一部位。
本申请的再一目的为一种阵列基板制作方法，包括：提供一基板；形成第一金属层与栅极层于所述基板上，所述第一金属层位于源极线的预定设置范围内，且所述第一金属层与所述栅极层之间具有间隔距离，且所述第一金属层为浮接；形成绝缘层，所述绝缘层以涵盖所述第一金属层与所述栅极层而设置于所述基板上；形成第二金属层与有源层在所述绝缘层上，且所述有源层位置相对于所述第一金属层，所述第二金属层与所述有源层之间具有间隔距离，且所述第二金属层为浮接；形成保护层，所述保护层以涵盖所述第二金属层及所述有源层而设置于所述绝缘层上。
本申请通过增加驱动线路的浮接金属层，增加静电电荷的吸附释放路径，可以使得制造过程中产生的静电荷得以更分散，减小电势差，即便有静电发生在浮接金属层，造成浮接金属层有烧毁的情形，也不会影响显示品质，较能提高产品良率。本申请不用增加光罩数量，只需在设计时，将所需层别相应画出即可，故可以不大幅改变现有生产流程，以维持原制程需求和产品成本。因不需调整生产流程，故没有特别的制程要求与难度，故不会提升成本，极具备市场竞争性。而且，不用增加阵列走线面积，适用于现今多种的显示面板设计，当然也适用于面板窄边框设计，符合市场及技术趋势。
附图说明
图1a为范例性的显示装置的架构示意图；
图1b为范例性的像素单元结构示意图；
图1c为范例性的阵列基板的像素单元配置示意图；
图1d为图1c的A1剖面图；
图1e为图1c的A2剖面图；
图2a为显示依据本申请的方法，一实施例阵列基板的像素区域示意图；
图2b为图2a中源极线就S1剖线的剖面示意图；
图2c为图2a中源极线就S2剖线的剖面示意图；
图2d为图2a中源极线就G1剖线的剖面示意图；
图2e为图2a中源极线就G2剖线的剖面示意图；
图3为显示依据本申请的方法，一实施例显示面板示意图；
图4为显示依据本申请的方法，一实施例阵列基板制作流程示意图；
图5为显示依据本申请的方法，一实施例阵列基板制作流程示意图；
图6为显示依据本申请的方法，一实施例阵列基板制作流程示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体的实施例，对依据本申请提出的一种阵列基板及其显示面板和制作方法，其具体实施方式、结构、特征及其功效，详细说明如后。
图1a为范例性的显示装置的架构示意图。请参照图1a，一种显示装置200，包括：控制板100，所述控制板100包括时序模块(Timing Controller，TCON)101；印刷电路板103，与所述控制板100之间通过柔性扁平电缆(Flexible Flat Cable，FFC)102相连接；源极驱动单元104与栅极驱动单元105配置于布线区109，分别与显示区106内的源极线104a及栅极线105a连接。在一些实施例中，栅极驱动单元105及源极驱动单元104包括但不限制为覆晶薄膜形式。
显示装置200的驱动方式包括：系统主板提供颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板100。控制板100上的时序控制器(Timing Controller，TCON)101于处理此等信号后，连同被驱动电路处理的电源，通过柔性扁平电缆(Flexible Flat Cable，FFC)102， 一并传输至印刷电路板103的栅极驱动单元105及源极驱动单元104，栅极驱动单元105及源极驱动单元104将必要性的数据与电源传输于显示区106，从而使得显示装置200获得呈现画面需求的电源、信号。
图1b为范例性的像素单元等效电路局部示意图。图1c为范例性的阵列基板的像素单元配置示意图，图1d为图1c的A1剖面图，图1e为图1c的A2剖面图。请同时配合图1a及图1b以利于了解。阵列基板300包括基板310，其上包括主动开关T、栅极线105a、源极线104a与像素电极P，主动开关T电性耦接所述栅极线105a与所述源极线104a的交集处，所述像素电极P电性耦接所述主动开关T与共享线路(Com)C。所述栅极线105a自基板310起包括栅极层320、绝缘层330与保护层350。所述源极线104a自基板310起包括绝缘层330、有源层340与保护层350。
然而，在显示面板生产制造的过程中，由于基板310与其他媒介的接触会产生大量的静电荷，而这些感应电荷会经金属层吸附后，传输至膜层较薄弱的地方释放，比如栅极层320与有源层340交叠处，有源层340的沟道处。当与传送设备接触时，会形成较大的电势差，进而将接触点附近的膜层击穿，较会影响显示面板、显示装置的质量。
图2a为显示依据本申请的方法，一实施例阵列基板的像素区域示意图。图2b为图2a中源极线就S1剖线的剖面示意图。图2c为图2a中源极线就S2剖线的剖面示意图。图2d为图2a中源极线就G1剖线的剖面示意图。图2e为图2a中源极线就G2剖线的剖面示意图。现有技术的装置架构及组件，请参考图1a至图1e以利于了解。请参照图2a，在本申请一实施例中，所述一种阵列基板300，包括：基板310，包括显示区106，所述显示区106配置多个主动开关T与多个像素电极P，所述多个像素电极P电性耦接所述多个主动开关T；多条驱动线段，设置于所述基板310上，电性耦接所述多个主动开关T，每一驱动线段包括：绝缘层330，设置于所述基板310上；保护层350，设置于所述基板310上，所述保护层350覆盖所述绝缘层330；金属层360a、360b，设置于所述驱动线段的涵盖范围内，且所述金属层360a、360b为浮接(floating)；其中，所述金属层设置于所述基板310与所述绝缘层330之间，以及所述绝缘层330与所述保护层350之间的至少其一部位。
如图2a、图2b与图2c所绘示，在一些实施例中，所述驱动线段包括源极线104a，所述绝缘层330与所述保护层350之间设置有有源层340，所述金属层360a设置于所述绝缘层330与所述基板310之间。
在一些实施例中，所述金属层360a为浮接栅极层(Floating Gate)或浮接电极层(Floating ITO)。
在一些实施例中，所述驱动线段包括栅极线105a，所述源极线104a与所述栅极线105a 交集处具有栅极层320，所述栅极层320设置于所述基板310与所述绝缘层330之间，所述金属层360a设置于邻近所述栅极层320。
在一些实施例中，所述金属层360a与相邻的两个所述栅极层320之间分别相隔一间隔距离x。
在一些实施例中，所述间隔距离x为3微米至20微米之间。
在一些实施例中，所述有源层340包括源极层与漏极层。
如图2a、图2d与图2e所绘示，在一些实施例中，所述驱动线段包括栅极线105a，所述绝缘层330与所述基板310之间设置有栅极层320，所述金属层设置于所述绝缘层330与所述保护层350之间。
在一些实施例中，所述金属层360b为浮接有源层(Floating SD)或浮接电极层(Floating ITO)。
在一些实施例中，所述驱动线段包括源极线104a，所述栅极线105a与所述源极线104a交集处具有有源层340，所述有源层340设置于所述绝缘层330与所述保护层350之间，所述金属层360b设置于相邻的两个所述有源层340之间。
在一些实施例中，所述金属层360b与相邻的两个所述有源层340之间分别相隔一间隔距离x。
在一些实施例中，所述间隔距离x为3微米至20微米之间。
图3为显示依据本申请的方法，一实施例显示面板示意图，请配合图2a至图2e以利于理解。现行显示装置组件请同时参阅图1a至图1e。在本申请一实施例中，一种显示面板，包括：阵列基板300；对向基板400，与所述阵列基板300相对设置，所述对向基板400可为彩色滤光片基板，或者，彩色滤光片设置于所述阵列基板300上，所述对向基板400为配置必要组件的配套基板；其中，所述阵列基板300包括：基板310，包括显示区106，所述显示区106配置多个主动开关T与多个像素电极P，所述多个像素电极P电性耦接所述多个主动开关T；多条驱动线段，设置于所述基板310上，并电性耦接所述多个主动开关T，每一驱动线段包括：绝缘层330，设置于所述基板310上；保护层350，设置于所述基板310上，所述保护层350覆盖所述绝缘层330；金属层360a、360b，设置于所述驱动线段的涵盖范围内，且所述金属层360a、360b为浮接；其中，所述金属层360a、360b设置于所述基板310与所述绝缘层330之间，以及所述绝缘层330与所述保护层350之间的至少其一部位。
在一些实施例中，所述阵列基板300还包括先前所述的各种施行方式。
请参阅如图2a至图2e，在本申请一实施例中，一种阵列基板300，其包括：基板310，包括显示区，所述显示区配置多个主动开关T与多个像素电极P，所述多个像素电极P电性 耦接所述多个主动开关T；多条源极线104a，设置于所述基板310上，并电性耦接所述多个主动开关T，每一源极线104a包括：绝缘层330，设置于所述基板310上；有源层340，设置于所述绝缘层330与所述保护层350之间；保护层350，设置于所述基板310上，所述保护层350覆盖所述绝缘层330及所述有源层340；多条栅极线105a，设置于所述基板310上，电性耦接所述多个主动开关T，每一栅极线105a包括：栅极层320，设置于所述基板310上；绝缘层330，设置于所述栅极层320上；保护层350，设置于所述基板310上，所述保护层350覆盖所述绝缘层330；金属层360a、360b，设置于所述驱动线段的涵盖范围内，且所述金属层360a、360b为浮接；其中，所述金属层360a、360b包括浮接栅极层与浮接有源层；所述浮接栅极层(金属层360a)设置于所述源极线104a范围的所述基板310与所述绝缘层330之间，且邻近所述栅极层320；所述浮接有源层(金属层360b)设置于所述栅极线105a范围的所述保护层350与所述绝缘层330之间，且相邻的两个所述有源层340之间；所述有源层340包括源极层与漏极层至少其一；所述金属层360a与相邻的所述栅极层320之间间隔3微米至20微米；所述金属层360b与相邻的所述有源层340之间间隔3微米至20微米。
图4为显示依据本申请的方法，一实施例阵列基板制作流程示意图。请同时配合图2a至图2c以利于理解。本申请的一实施例，以所述金属层360a设置于源极线104a范围为例，一种阵列基板制作方法，其包括：
步骤S410，提供一基板310。
步骤S420，形成金属层360a于所述基板310上，所述金属层360a位于源极线104a的预定设置范围内，且所述金属层360a为浮接。
步骤S430，形成绝缘层330，所述绝缘层330涵盖所述金属层360a而设置于所述基板310上。
步骤S440，形成有源层340在所述绝缘层330上，且所述有源层340位置相对于所述金属层360a。
步骤S450，形成保护层350，所述保护层350以涵盖所述有源层340而设置于所述绝缘层330上。
在一些实施例中，所述金属层360a与栅极层320于同步骤形成，且所述金属层360a与所述栅极层320之间具有间隔距离x。
图5为显示依据本申请的方法，一实施例阵列基板制作流程示意图。请同时配合图2a、图2d与图2e以利于理解。本申请的一实施例，以所述金属层360b设置于栅极线105a范围为例，一种阵列基板制作方法，其包括：
步骤S510，提供一基板310。
步骤S520，形成栅极层320于所述基板310上。
步骤S530，形成绝缘层330，所述绝缘层330以涵盖所述栅极层320而设置于所述基板310上。
步骤S540，形成金属层360b于所述绝缘层330上，所述金属层360b位于所述栅极层320的设置范围内，且所述金属层360b为浮接。
步骤S550，形成保护层350，所述保护层350以涵盖所述金属层360b而设置于所述绝缘层330上。
在一些实施例中，所述金属层360b与有源层340于同步骤形成，且所述金属层360b与所述有源层340之间具有间隔距离x。
图6为显示依据本申请的方法，一实施例阵列基板制作流程示意图。请同时配合图2a至图2c以利于理解。本申请的一实施例，以所述金属层360a(视为第一金属层)设置于源极线104a范围，及所述金属层360b(视为第二金属层)设置于栅极线105a范围为例。一种阵列基板制作方法，其包括：
步骤S610，提供一基板310。
步骤S620，形成第一金属层360a与栅极层320于所述基板310上，所述第一金属层360a位于源极线104a的预定设置范围内，且所述第一金属层360a与所述栅极层320之间具有间隔距离x，且所述第一金属层360a为浮接。
步骤S630，形成绝缘层330，所述绝缘层330以涵盖所述第一金属层360a与所述栅极层320而设置于所述基板310上。
步骤S640，形成第二金属层360b与有源层340在所述绝缘层330上，且所述有源层340位置相对于所述第一金属层360a，所述第二金属层360b与所述有源层340之间具有间隔距离x，且所述第二金属层360b为浮接。
步骤S650，形成保护层350，所述保护层350以涵盖所述第二金属层360b及所述有源层340而设置于所述绝缘层330上。
在一些实施例中，本申请的显示面板可例如为液晶显示面板，然不限于此，其也可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
本申请通过增加驱动线路的浮接金属层，增加静电电荷的吸附释放路径，可以使得制造过程中产生的静电荷得以更分散，减小电势差，即便有静电发生在浮接金属层，造成浮接金属层有烧毁的情形，也不会影响显示品质，较能提高产品良率。本申请不用增加光罩数量，只需在设计时，将所需层别相应画出即可，故可以不大幅改变现有生产流程，以维持原制程 需求和产品成本。因不需调整生产流程，故没有特别的制程要求与难度，故不会提升成本，极具备市场竞争性。而且，不用增加阵列走线面积，适用于现今多种的显示面板设计，当然也适用于面板窄边框设计，符合市场及技术趋势，并具有工业实用性。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的实施例，并非对本申请作任何形式上的限制，虽然本申请已以具体的实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种阵列基板，其中，包括：
    基板，包括显示区，所述显示区配置多个主动开关与多个像素电极，所述多个像素电极电性耦接所述多个主动开关；
    多条驱动线段，设置于所述基板上，并电性耦接所述多个主动开关，每一驱动线段包括：
    绝缘层，设置于所述基板上；
    保护层，设置于所述基板上，所述保护层覆盖所述绝缘层；以及
    金属层，设置于所述驱动线段的涵盖范围内，且所述金属层为浮接；
    其中，所述金属层设置于所述基板与所述绝缘层之间，以及所述绝缘层与所述保护层之间的至少其一部位。
  2. 如权利要求1所述的阵列基板，其中，所述驱动线段包括源极线，所述绝缘层与所述保护层之间设置有有源层，所述金属层设置于所述绝缘层与所述基板之间。
  3. 如权利要求2所述的阵列基板，其中，所述金属层为浮接栅极层。
  4. 如权利要求2所述的阵列基板，其中，所述金属层为浮接电极层。
  5. 如权利要求2所述的阵列基板，其中，所述驱动线段包括栅极线，所述源极线与所述栅极线交集处具有栅极层，所述栅极层设置于所述绝缘层与所述基板之间，所述金属层设置于邻近所述栅极层。
  6. 如权利要求5所述的阵列基板，其中，所述金属层与相邻的所述栅极层之间间隔3微米至20微米。
  7. 如权利要求2所述的阵列基板，其中，所述有源层包括源极层与漏极层至少其一。
  8. 如权利要求1所述的阵列基板，其中，所述驱动线段包括栅极线，所述绝缘层与所述基板之间设置有栅极层，所述金属层设置于所述绝缘层与所述保护层之间。
  9. 如权利要求8所述的阵列基板，其中，所述金属层为浮接有源层。
  10. 如权利要求8所述的阵列基板，其中，所述金属层为浮接电极层。
  11. 如权利要求8所述的阵列基板，其中，所述驱动线段包括源极线，所述栅极线与所述源极线交集处具有有源层，所述有源层设置于所述绝缘层与所述保护层之间，所述金属层设置于相邻的两个所述有源层之间。
  12. 如权利要求11所述的阵列基板，其中，所述金属层与相邻的所述有源层之间间隔3微米至20微米。
  13. 一种显示面板，其中，包括：
    阵列基板；以及
    对向基板，与所述阵列基板相对设置；
    其中，所述阵列基板包括：
    基板，包括显示区，所述显示区配置多个主动开关与多个像素电极，所述多个像素电极电性耦接所述多个主动开关；
    多条驱动线段，设置于所述基板上，并电性耦接所述多个主动开关，每一驱动线段包括：
    绝缘层，设置于所述基板上；
    保护层，设置于所述基板上，所述保护层覆盖所述绝缘层；以及
    金属层，设置于所述驱动线段的涵盖范围内，且所述金属层为浮接；
    其中，所述金属层设置于所述基板与所述绝缘层之间，以及所述绝缘层与所述保护层之间的至少其一部位。
  14. 如权利要求13所述的显示面板，其中，所述驱动线段包括源极线，所述绝缘层与所述保护层之间设置有有源层，所述金属层设置于所述绝缘层与所述基板之间。
  15. 如权利要求14所述的显示面板，其中，所述金属层为浮接栅极层或浮接电极层。
  16. 如权利要求14所述的显示面板，其中，所述驱动线段包括栅极线，所述源极线与所述栅极线交集处具有栅极层，所述栅极层设置于所述绝缘层与所述基板之间，所述金属层设置于邻近所述栅极层。
  17. 如权利要求13所述的显示面板，其中，所述驱动线段包括栅极线，所述绝缘层与所述基板之间设置有栅极层，所述金属层设置于所述绝缘层与所述保护层之间。
  18. 如权利要求17所述的显示面板，其中，所述金属层为浮接有源层或浮接电极层。
  19. 如权利要求17所述的显示面板，其中，所述驱动线段包括源极线，所述栅极线与所述源极线交集处具有有源层，所述有源层设置于所述绝缘层与所述保护层之间，所述金属层设置于相邻的两个所述有源层之间。
  20. 一种阵列基板制作方法，其中，包括：
    提供一基板；
    形成第一金属层与栅极层于所述基板上，所述第一金属层位于源极线的预定设置范围内，且所述第一金属层与所述栅极层之间具有间隔距离，且所述第一金属层为浮接；
    形成绝缘层，所述绝缘层以涵盖所述第一金属层与所述栅极层而设置于所述基板上；
    形成第二金属层与有源层在所述绝缘层上，且所述有源层位置相对于所述第一金属层，所述第二金属层与所述有源层之间具有间隔距离，且所述第二金属层为浮接；以及
    形成保护层，所述保护层以涵盖所述第二金属层及所述有源层而设置于所述绝缘层上。
PCT/CN2019/073184 2018-10-10 2019-01-25 阵列基板及其显示面板和制作方法 Ceased WO2020073567A1 (zh)

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