WO2020073371A1 - 一种影像芯片的封装结构和制作方法 - Google Patents

一种影像芯片的封装结构和制作方法 Download PDF

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Publication number
WO2020073371A1
WO2020073371A1 PCT/CN2018/112618 CN2018112618W WO2020073371A1 WO 2020073371 A1 WO2020073371 A1 WO 2020073371A1 CN 2018112618 W CN2018112618 W CN 2018112618W WO 2020073371 A1 WO2020073371 A1 WO 2020073371A1
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Prior art keywords
functional surface
image chip
absorbing layer
wafer
layer
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PCT/CN2018/112618
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English (en)
French (fr)
Inventor
秦飞
赵帅
张理想
陈沛
安彤
代岩伟
肖智轶
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Beijing University of Technology
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Beijing University of Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/024—Manufacture or treatment of image sensors covered by group H10F39/12 of coatings or optical elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/805—Coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Definitions

  • the invention relates to a semiconductor chip packaging structure and manufacturing method, in particular to an image chip packaging structure and manufacturing method, which belongs to the field of semiconductor packaging.
  • the wafer-level packaging solution for image chips is currently mainstreamed by the bonding of the glass cover plate and the photoresist cofferdam on its surface to the wafer functional surface of the image chip, each cofferdam corresponding to each image sensor chip, making the photosensitive area
  • the location forms a sealed cavity.
  • the TSV process is performed on the non-functional side of the wafer, and metal lines are made to lead the pads on the functional side to the non-functional side of the wafer through the TSV opening. After the bumps are made on the non-functional surface, they are cut to form a single chip.
  • the current packaging solutions are mainly aimed at low- and medium-pixel imagers.
  • the glare and ghost caused by light entering the photodiode of the chip device layer through the non-functional surface and the side wall The interference of phenomena such as shadow on the shooting quality cannot be ignored.
  • the present invention proposes a packaging structure and manufacturing method of an image chip, which can effectively suppress the light from entering the photodiode of the device layer through the non-functional surface and the side wall of the chip, and reduce the interference light incident on the device layer To improve imaging quality.
  • An image chip packaging structure which is characterized by comprising:
  • the image chip is a hexahedron.
  • the image chip includes a functional surface, a non-functional surface corresponding thereto, and four side walls.
  • the functional surface contains a photosensitive area and several pads.
  • a cofferdam protecting the photosensitive area is adhered on the functional surface of the image chip, and a light-transmissive glass cover plate is adhered on the cofferdam to cover the photosensitive area.
  • the position of the photosensitive area of the non-functional surface of the image chip directly facing the functional surface is covered with a first light-absorbing layer, and the side wall is covered with a second light-absorbing layer.
  • Each non-functional surface of the image chip directly facing the functional surface is provided with a first opening, and an insulating layer is sequentially formed on the first opening and the surface of the non-functional surface to lead out the functional surface of the pad Circuit layer, and protective layer and conductive bumps.
  • the image chip packaging structure is characterized in that the first light absorbing layer and the second light absorbing layer are black materials such as black glue, brown coating, etc. that absorb all light. And the thickness of the first light absorbing layer and the second light absorbing layer is greater than 4 ⁇ m and less than 10 ⁇ m.
  • the image chip packaging structure is characterized in that the position of the photosensitive region on the non-functional surface of the image chip directly facing the functional surface covers the first light-absorbing layer, and the light-absorbing layer covers the insulating layer Below, the area of the first light absorbing layer is larger than the area of the photosensitive area.
  • the image chip packaging structure is characterized in that the included angle between the outer normal of the side wall of the image chip and the outer normal of the non-functional surface is an acute angle, and the acute angle Not more than 80 °.
  • the image chip packaging structure is characterized in that the side wall of the image chip covers the second light absorption layer, and the second light absorption layer covers the underside of the protective layer. And the light absorption layer and the protective layer encapsulate the side wall of the image chip.
  • Step 1 Provide an image chip wafer, the wafer containing a functional surface and a non-functional surface opposite thereto.
  • the functional surface of the wafer contains a number of photosensitive regions of image chips and a number of chip pads;
  • Step 2 The glass cover plate includes a first surface and a second surface opposite thereto, the first surface is covered with a layer of cofferdam;
  • Step 3 Bond the functional surface of the wafer and the cofferdam on the first surface of the glass cover plate
  • Step 4 thin the non-functional surface of the wafer
  • Step 5 Manufacture a first light absorption layer on the non-functional surface of the wafer, the first light absorption layer directly facing the photosensitive area of the functional surface of the wafer;
  • Step 6 making a first opening in the non-functional surface of the wafer that exposes each pad of the functional surface of the wafer;
  • Step 7 forming an insulating layer on the inner wall of the first opening and the non-functional surface of the wafer;
  • Step 8 making a patterned metal wiring layer on the insulating layer
  • Step 9 making a groove at the position where the non-functional surface of the wafer directly faces the scribe line, and the bottom of the groove exposes the cofferdam;
  • Step 10 making a second light-absorbing layer in the groove
  • Step 11 forming a protective layer and a second opening on the metal wiring layer
  • Step 12 forming conductive bumps on the second opening
  • Step 13 cutting the wafer and the glass cover plate along the cutting path to form a single image chip package
  • the implementation process of the image chip packaging structure described above is characterized in that the manufacturing method of the first light absorbing layer in step 5 is spin coating or spray coating, and then exposure and development.
  • the manufacturing method of the second light absorbing layer in step 10 is spray coating or printing.
  • the implementation process of the image chip packaging structure described above is characterized in that the manufacturing method of the first opening is dry etching, wet etching, cutting, and laser ablation.
  • the manufacturing method of the groove is etching or cutting.
  • the invention discloses a packaging structure and a manufacturing method of an image chip.
  • the invention can effectively prevent light from entering the photodiode of the chip device layer through the non-functional surface and the side wall of the image chip by making the light absorption layer on the non-functional surface of the image chip directly opposite the photosensitive area and the side wall of the chip Disturbing light in the photosensitive area improves the quality of imaging.
  • FIG. 1 is a schematic diagram of an image chip packaging structure drawn according to an embodiment of the present invention.
  • step 1 is a schematic cross-sectional view of the package structure after step 1.
  • step 2 is a schematic cross-sectional view of the packaging structure after step 2.
  • step 3 is a schematic cross-sectional view of the package structure after step 3.
  • 5 is a schematic cross-sectional view of the package structure after step 4.
  • FIG. 6 is a schematic cross-sectional view of the package structure after step 5.
  • FIG. 7 is a schematic cross-sectional view of the packaging structure after step 6.
  • step 9 is a schematic cross-sectional view of the packaging structure after step 8.
  • FIG. 10 is a schematic cross-sectional view of the package structure after step 9.
  • 11 is a schematic cross-sectional view of the package structure after step 10.
  • step 12 is a schematic cross-sectional view of the packaging structure after step 11.
  • step 12 is a schematic cross-sectional view of the package structure after step 12.
  • step 14 is a schematic cross-sectional view of the package structure after step 13.
  • the schematic diagram is an image chip packaging structure according to an embodiment of the present invention, including:
  • the image chip (1) is a hexahedron, the image chip (1) includes a functional surface (101), a non-functional surface (102) corresponding thereto, and four side walls (105) ).
  • the functional surface includes a photosensitive area (103) and a plurality of solder pads (104).
  • a cofferdam (2) protecting the photosensitive area (103) is adhered on the functional surface (101) of the image chip (1), and a transparent glass cover plate (3) is adhered on the cofferdam (2) ) Cover the photosensitive area (103).
  • the position of the non-functional surface (102) of the image chip (1) directly facing the photosensitive area (103) of the functional surface (101) is covered with a first light-absorbing layer (106a), and the side wall (105) is covered with a second Light absorbing layer (106b).
  • Each non-functional surface (102) of the image chip (1) directly opposite the functional surface (101) is provided with a first opening (107), the first opening (107) and the non-functional surface
  • An insulating layer (4) is sequentially formed on the surface of (102), a circuit layer (5) of the pad (104) leading out of the functional surface, a protective layer (6) and conductive bumps (7).
  • the packaging structure of the image chip is characterized in that the first light absorbing layer (106a) and the second light absorbing layer (106b) are black materials such as black glue, brown coating, etc. that absorb all light.
  • the thickness of the first light absorbing layer (106a) and the second light absorbing layer (106b) is greater than 4 ⁇ m and less than 10 ⁇ m.
  • the packaging structure of the image chip is characterized in that the position of the non-functional surface (102) of the image chip (1) directly facing the photosensitive area (103) of the functional surface (101) covers the first light-absorbing layer (106a), the light absorbing layer (106a) is covered under the insulating layer (4), and the area of the first light absorbing layer (106a) is larger than the area of the photosensitive region (103).
  • the packaging structure of the image chip is characterized in that the angle between the outer normal of the side wall (105) of the image chip (1) and the outer normal of the non-functional surface (102) Is an acute angle, and the acute angle is not greater than 80 °.
  • the packaging structure of the image chip is characterized in that the side wall (105) of the image chip (1) covers the second light absorbing layer (106b), and the second light absorbing layer (106b) covers the Below the protective layer (6). And the light absorption layer (106b) and the protective layer (6) encapsulate the side wall (105) of the image chip (1).
  • FIGS. 2 to 14 are schematic diagrams of a method for manufacturing an image chip packaging structure according to an embodiment of the present invention.
  • the manufacturing method of the image chip packaging structure of the present invention is as follows:
  • an image chip wafer (1) is provided.
  • the wafer (1) includes a functional surface (101) and a non-functional surface (102) opposite thereto.
  • the functional surface (101) of the wafer contains a number of photosensitive regions (103) of image chips and a number of chip pads (104);
  • the glass cover (3) includes a first surface (301) and a second surface (302) opposite thereto, the first surface (301) is covered with a layer of cofferdam (2 );
  • Step 3 as shown in FIG. 4, bonding the functional surface (101) of the wafer (1) and the cofferdam (2) of the first surface (301) of the glass cover (3);
  • Step 4 as shown in FIG. 5, thin the non-functional surface (102) of the wafer (1);
  • Step 5 as shown in FIG. 6, a first light absorbing layer (106a) is formed on the non-functional surface (102) of the wafer (1), the first light absorbing layer (106a) is directly opposite to the wafer (1 ) The photosensitive area (103) of the functional surface (102);
  • Step 6 as shown in FIG. 7, a first opening is formed in the non-functional surface (102) of the wafer (1) exposing each pad (104) of the functional surface (101) of the wafer (1) (107);
  • Step 7 as shown in FIG. 8, forming an insulating layer (4) on the inner wall of the first opening (107) and the non-functional surface (102) of the wafer (1);
  • Step 8 as shown in FIG. 9, forming a patterned metal wiring layer (5) on the insulating layer (4);
  • Step 9 as shown in FIG. 10, a groove (108) is formed at the position of the non-functional surface (102) of the wafer (1) directly facing the scribe line, and the bottom of the groove (108) exposes the cofferdam ( 2);
  • Step 10 as shown in FIG. 11, forming a second light absorbing layer (106b) in the groove (108);
  • Step 11 as shown in FIG. 12, forming a protective layer (6) and a second opening (601) on the metal wiring layer (5);
  • Step 12 as shown in FIG. 13, forming conductive bumps (7) on the second opening (601);
  • Step 13 as shown in FIG. 14, the wafer (1) and the glass cover (3) are cut along the scribe line to form a single image chip package;
  • the manufacturing method of the packaging structure of the image chip is characterized in that, the manufacturing method of the first light absorbing layer (106a) in step 5 is spin coating or spray coating, exposure, and development.
  • the manufacturing method of the second light absorbing layer (106b) in step 10 is spray coating or printing.
  • the method for manufacturing the packaging structure of the image chip is characterized in that the method for manufacturing the first opening (107) is one of dry etching, wet etching, cutting, and laser ablation Or a combination of several, the manufacturing method of the groove (108) is etching or cutting.

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Abstract

本发明公开了一种影像芯片的封装结构和制作方法，属于半导体封装领域。本发明通过在影像芯片的非功能面正对感光区的位置和芯片侧壁分别制作吸光层，可以有效抑制光线通过影像芯片非功能面和侧壁射入芯片器件层的光电二极管，减少入射到感光区的干扰光线，提高了成像的质量。

Description

一种影像芯片的封装结构和制作方法 技术领域
本发明涉及一种半导体芯片封装结构和制作方法，尤其涉及一种影像芯片的封装结构和制作方法，属于半导体封装领域。
背景技术
影像芯片的晶圆级封装方案，目前主流的是由玻璃盖板及其表面的光刻胶围堰与影像芯片的晶圆功能面键合，各围堰分别对应各图像传感器芯片，使得感光区位置形成密封空腔。在晶圆非功能面进行TSV制程，并制作金属线路将功能面的焊垫通过TSV开口，引到晶圆非功能面。在非功能面上制作凸点后，切割形成单颗芯片。
但是，目前的封装方案主要是针对中低像素的影像器，随着像素及拍摄质量要求的提高，光线透过非功能面和侧壁摄入芯片器件层的光电二极管而导致的炫光，鬼影等现象对拍摄质量的干扰不容忽视了。
发明内容
为了解决上述技术问题，本发明提出了一种影像芯片的封装结构和制作方法，可有效抑制光线透过芯片非功能面和侧壁射入器件层的光电二极管，减少入射到器件层的干扰光线，提高成像质量。
本发明的技术方案是这样实现的：
一种影像芯片封装结构，其特征在于，包括：
至少一影像芯片，所述影像芯片为六面体，所述影像芯片含有功能面，与其相对应的非功能面，以及四个侧壁。所述功能面含有感光区及若干焊垫。所述影像芯片的功能面上粘合一保护所述感光区的围堰，所述围堰上粘结一透光玻璃盖板覆盖所述感光区。所述影像芯片的非功能面正对功能面的感光区的位置覆盖有第一吸光层，所述侧壁覆盖有第二吸光层。所述影像芯片的非功能面正对功能面的各个焊垫位置均设有第一开口，所述第一开口和所述非功能面的表面依次制作有绝缘层，引出功能面的焊垫的线路层，和保护层及导电凸点。
作为本发明的进一步改进，所述的影像芯片封装结构，其特征在于，所述第一吸光层和第二吸光层为黑胶，褐色镀膜等吸收所有光线的黑色材料。且所述第一吸光层和所述第二吸光层的厚度大于4μm， 小于10μm。
作为本发明的进一步改进，所述的影像芯片封装结构，其特征在于，所述影像芯片的非功能面正对功能面的感光区的位置覆盖第一吸光层，所述吸光层覆盖于绝缘层的下面，所述第一吸光层的面积大于感光区的面积。
作为本发明的进一步改进，所述的影像芯片封装结构，其特征在于，所述影像芯片的侧壁的外法线和所述非功能面的外法线间的夹角为锐角，且该锐角不大于80°。
作为本发明的进一步改进，所述的影像芯片封装结构，其特征在于，所述的影像芯片的侧壁覆盖第二吸光层，所述第二吸光层覆盖于所述保护层的下面。且所述吸光层和保护层将影像芯片的侧壁包封。
一种影像芯片的封装结构的实现工艺，其特征在于，包括以下步骤：
步骤1，提供一影像芯片晶圆，所述晶圆含有功能面和与其相对的非功能面。所述晶圆的功能面含有若干影像芯片的感光区及若干芯片焊盘；
步骤2，所述玻璃盖板含有第一表面和与其相对的第二表面，所述第一表面覆盖有一层围堰；
步骤3，将所述晶圆的功能面和所述玻璃盖板的第一表面的围堰粘结；
步骤4，将所述晶圆的非功能面减薄；
步骤5，于所述晶圆的非功能面制作第一吸光层，所述第一吸光层正对所述晶圆的功能面的感光区；
步骤6，于所述晶圆的非功能面制作暴露所述晶圆功能面的各个焊垫的第一开口；
步骤7，于所述第一开口的内壁和所述晶圆的非功能面制作绝缘层；
步骤8，于所述绝缘层上制作图形化的金属布线层；
步骤9，于所述晶圆的非功能面正对切割道的位置制作凹槽，凹槽的底部暴露所述围堰；
步骤10，于所述凹槽内制作第二吸光层；
步骤11，于所述金属布线层上形成保护层和第二开口；
步骤12，于所述第二开口上形成导电凸点；
步骤13，将晶圆和玻璃盖板沿着切割道切割，形成单颗影像芯片封装体；
作为本发明的进一步改进，所述的一种影像芯片封装结构的实现工艺，其特征在于，步骤5所述第一吸光层的制作方法为旋涂或喷涂，然后曝光显影。步骤10所述第二吸光层的制作方法为喷涂或印刷。
作为本发明的进一步改进，所述的一种影像芯片封装结构的实现工艺，其特征在于，所述第一开口的制作方法为干法刻蚀，湿法刻蚀，切割，激光烧蚀中的一种或几种的组合，所述凹槽的制作方法为刻蚀或切割。
本发明的有益效果是：
本发明公开了一种影像芯片的封装结构和制作方法。本发明通过在影像芯片的非功能面正对感光区的位置和芯片侧壁分别制作吸光层，可以有效抑制光线通过影像芯片非功能面和侧壁摄入芯片器件层的光电二极管，减少如何到感光区的干扰光线，提高了成像的质量。
附图说明
图1为根据本发明实施例绘制的影像芯片封装结构示意图。
图2为步骤1后的封装结构剖面示意图。
图3为步骤2后的封装结构剖面示意图。
图4为步骤3后的封装结构剖面示意图。
图5为步骤4后的封装结构剖面示意图。
图6为步骤5后的封装结构剖面示意图。
图7为步骤6后的封装结构剖面示意图。
图8为步骤7后的封装结构剖面示意图。
图9为步骤8后的封装结构剖面示意图。
图10为步骤9后的封装结构剖面示意图。
图11为步骤10后的封装结构剖面示意图。
图12为步骤11后的封装结构剖面示意图。
图13为步骤12后的封装结构剖面示意图。
图14为步骤13后的封装结构剖面示意图。
结合附图，作以下说明：
1-影像芯片/晶圆           101-影像芯片的功能面
102-影像芯片的非功能面    103-感光区
1004-焊垫                 105-影像芯片的侧壁
106a-吸光层               106b-吸光层
107-第一开口              108-凹槽
2-围堰        3-玻璃盖板
301-玻璃盖板的第一表面    302-玻璃盖板的第二表面
4-绝缘层                  5-金属线路层
6-保护层                  601-第二开口
7-导电凸点
具体实施方式
为了能够更清楚地理解本发明的技术内容，特举以下实施例详细说明，并配合附图对本发明的上述特征和优点做详细说明。其目的仅在于更好理解本发明的内容而非限制本发明的保护范围。本发明实施例的半导体封装结构可以用于微凸点的制备，但其应用并不限于此。
参照图1，该示意图为本发明实施方式的影像芯片封装结构，包括：
至少一影像芯片(1)，所述影像芯片(1)为六面体，所述影像芯片(1)含有功能面(101)，与其相对应的非功能面(102)，以及四个侧壁(105)。所述功能面含有感光区(103)及若干焊垫(104)。所述影像芯片(1)的功能面(101)上粘合一保护所述感光区(103)的围堰(2)，所述围堰(2)上粘结一透光玻璃盖板(3)覆盖所述感光区(103)。所述影像芯片(1)的非功能面(102)正对功能面(101)的感光区(103)的位置覆盖有第一吸光层(106a)，所述侧壁(105)覆盖有第二吸光层(106b)。所述影像芯片(1)的非功能面(102)正对功能面(101)的各个焊垫位置均设有第一开口(107)，所述第一开口(107)和所述非功能面(102)的表面依次制作有绝缘层(4)，引出功能面的焊垫(104)的线路层(5)，和保护层(6)及导电凸点(7)。
可选的，所述影像芯片的封装结构，其特征在于，所述第一吸光 层(106a)和第二吸光层(106b)为黑胶，褐色镀膜等吸收所有光线的黑色材料。且所述第一吸光层(106a)和所述第二吸光层(106b)的厚度大于4μm，小于10μm。
可选的，所述影像芯片的封装结构，其特征在于，所述影像芯片(1)的非功能面(102)正对功能面(101)的感光区(103)的位置覆盖第一吸光层(106a)，所述吸光层(106a)覆盖于绝缘层(4)的下面，所述第一吸光层(106a)的面积大于感光区(103)的面积。
可选的，所述影像芯片的封装结构，其特征在于，所述影像芯片(1)的侧壁(105)的外法线和所述非功能面(102)的外法线间的夹角为锐角，且该锐角不大于80°。
可选的，所述影像芯片的封装结构，其特征在于，所述的影像芯片(1)的侧壁(105)覆盖第二吸光层(106b)，所述第二吸光层(106b)覆盖于所述保护层(6)的下面。且所述吸光层(106b)和保护层(6)将影像芯片(1)的侧壁(105)包封。
图2～图14为根据本发明实施例绘制的影像芯片封装结构制作方法的示意图。
参见图2至图14，本发明的影像芯片封装结构的制作方法如下：
步骤1，如图2所示，提供一影像芯片晶圆(1)，所述晶圆(1)含有功能面(101)和与其相对的非功能面(102)。所述晶圆的功能面(101)含有若干影像芯片的感光区(103)及若干芯片焊盘(104)；
步骤2，如图3所示，所述玻璃盖板(3)含有第一表面(301)和与其相对的第二表面(302)，所述第一表面(301)覆盖有一层围堰(2)；
步骤3，如图4所示，将所述晶圆(1)的功能面(101)和所述玻璃盖板(3)的第一表面(301)的围堰(2)粘结；
步骤4，如图5所示，将所述晶圆(1)的非功能面(102)减薄；
步骤5，如图6所示，于所述晶圆(1)的非功能面(102)制作第一吸光层(106a)，所述第一吸光层(106a)正对所述晶圆(1)功能面(102)的感光区(103)；
步骤6，如图7所示，于所述晶圆(1)的非功能面(102)制作暴露所述晶圆(1)的功能面(101)的各个焊垫(104)的第一开口 (107)；
步骤7，如图8所示，于所述第一开口(107)的内壁和所述晶圆(1)的非功能面(102)制作绝缘层(4)；
步骤8，如图9所示，于所述绝缘层(4)上制作图形化的金属布线层(5)；
步骤9，如图10所示，于所述晶圆(1)的非功能面(102)正对切割道的位置制作凹槽(108)，凹槽(108)的底部暴露所述围堰(2)；
步骤10，如图11所示，于所述凹槽(108)内制作第二吸光层(106b)；
步骤11，如图12所示，于所述金属布线层(5)上形成保护层(6)和第二开口(601)；
步骤12，如图13所示，于所述第二开口(601)上形成导电凸点(7)；
步骤13，如图14所示，将晶圆(1)和玻璃盖板(3)沿着切割道切割，形成单颗影像芯片封装体；
可选的，所述影像芯片的封装结构的制作方法，其特征在于，步骤5所述第一吸光层(106a)的制作方法为旋涂或喷涂，曝光，显影。步骤10所述第二吸光层(106b)的制作方法为喷涂或印刷。
可选的，所述影像芯片的封装结构的制作方法，其特征在于，所述第一开口(107)的制作方法为干法刻蚀，湿法刻蚀，切割，激光烧蚀中的一种或几种的组合，所述凹槽(108)的制作方法为刻蚀或切割。
虽然本发明实施例披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (8)

  1. 一种影像芯片的封装结构，其特征在于，包括至少一影像芯片(1)，所述影像芯片(1)为六面体，所述影像芯片(1)含有功能面(101)，与其相对应的非功能面(102)，以及四个侧壁(105)；所述功能面含有感光区(103)及若干焊垫(104)；所述影像芯片(1)的功能面(101)上粘合一保护所述感光区(103)的围堰(2)，所述围堰(2)上粘结一透光玻璃盖板(3)覆盖所述感光区(103)；所述影像芯片(1)的非功能面(102)正对功能面(101)的感光区(103)的位置覆盖有第一吸光层(106a)，所述侧壁(105)覆盖有第二吸光层(106b)；所述影像芯片(1)的非功能面(102)正对功能面(101)的各个焊垫位置均设有第一开口(107)，所述第一开口(107)和所述非功能面(102)的表面依次制作有绝缘层(4)，引出功能面的焊垫(104)的线路层(5)，和保护层(6)及导电凸点(7)。
  2. 根据权利要求1所述的影像芯片封装结构，其特征在于，所述第一吸光层(106a)和第二吸光层(106b)为能吸收所有光线的黑色材料；且所述第一吸光层(106a)和所述第二吸光层(106b)的厚度大于4μm，小于10μm。
  3. 根据权利要求1所述的影像芯片封装结构，其特征在于，所述影像芯片(1)的非功能面(102)正对功能面(101)的感光区(103)的位置覆盖第一吸光层(106a)，所述吸光层(106a)覆盖于绝缘层(4)的下面，所述第一吸光层(106a)的面积大于感光区(103)的面积。
  4. 根据权利要求1所述的影像芯片的封装结构，其特征在于，所述影像芯片(1)的侧壁(105)的外法线和所述非功能面(102)的外法线间的夹角为锐角，且该锐角不大于80°。
  5. 根据权利要求1所述的影像芯片封装结构，其特征在于，所述的影像芯片(1)的侧壁(105)覆盖第二吸光层(106b)，所述第二吸光层(106b)覆盖于所述保护层(6)的下面；且所述吸光层(106b)和保护层(6)将影像芯片(1)的侧壁(105)包封。
  6. 一种影像芯片的封装结构的制作方法，其特征在于，包括以下步骤：
    步骤1，提供一影像芯片晶圆(1)，所述晶圆(1)含有功能面(101)和与其相对的非功能面(102)；所述晶圆的功能面(101)含有若干影像芯片的感光区(103)及若干芯片焊盘(104)；
    步骤2，所述玻璃盖板(3)含有第一表面(301)和与其相对的第二表面(302)，所述第一表面(301)覆盖有一层围堰(2)；
    步骤3，将所述晶圆(1)的功能面(101)和所述玻璃盖板(3)的第一表面(301)的围堰(2)粘结；
    步骤4，将所述晶圆(1)的非功能面(102)减薄；
    步骤5，于所述晶圆(1)的非功能面(102)制作第一吸光层(106a)，所述第一吸光层(106a)正对所述晶圆(1)功能面(102)的感光区(103)；
    步骤6，于所述晶圆(1)的非功能面(102)制作暴露所述晶圆(1)的功能面(101)的各个焊垫(104)的第一开口(107)；
    步骤7，于所述第一开口(107)的内壁和所述晶圆(1)的非功能面(102)制作绝缘层(4)；
    步骤8，于所述绝缘层(4)上制作图形化的金属布线层(5)；
    步骤9，于所述晶圆(1)的非功能面(102)正对切割道的位置制作凹槽(108)，凹槽(108)的底部暴露所述围堰(2)；
    步骤10，于所述凹槽(108)内制作第二吸光层(106b)；
    步骤11，于所述金属布线层(5)上形成保护层(6)和第二开口(601)；
    步骤12，于所述第二开口(601)上形成导电凸点(7)；
    步骤13，将晶圆(1)和玻璃盖板(3)沿着切割道切割，形成单颗影像芯片封装体。
  7. 根据权利要求6所述的一种影像芯片的封装结构的制作方法，其特征在于，步骤5所述第一吸光层(106a)的制作方法为旋涂或喷涂，然后曝光显影；步骤10所述第二吸光层(106b)的制作方法为喷涂或印刷。
  8. 根据权利要求6所述的一种影像芯片的封装结构的制作方法，其特征在于，所述第一开口(107)的制作方法为干法刻蚀，湿法刻 蚀，切割，激光烧蚀中的一种或几种的组合，所述凹槽(108)的制作方法为刻蚀或切割。
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