WO2020073231A1 - 一种goa电路及显示装置 - Google Patents

一种goa电路及显示装置 Download PDF

Info

Publication number
WO2020073231A1
WO2020073231A1 PCT/CN2018/109648 CN2018109648W WO2020073231A1 WO 2020073231 A1 WO2020073231 A1 WO 2020073231A1 CN 2018109648 W CN2018109648 W CN 2018109648W WO 2020073231 A1 WO2020073231 A1 WO 2020073231A1
Authority
WO
WIPO (PCT)
Prior art keywords
type transistor
module
electrode
enable
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/109648
Other languages
English (en)
French (fr)
Inventor
管曦萌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Royole Technologies Co Ltd
Original Assignee
Shenzhen Royole Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Royole Technologies Co Ltd filed Critical Shenzhen Royole Technologies Co Ltd
Priority to CN201880096064.2A priority Critical patent/CN112703552A/zh
Priority to PCT/CN2018/109648 priority patent/WO2020073231A1/zh
Priority to CN201880095926.XA priority patent/CN112639954A/zh
Priority to CN201880095933.XA priority patent/CN112639955A/zh
Priority to PCT/CN2018/120046 priority patent/WO2020073471A1/zh
Priority to PCT/CN2018/120050 priority patent/WO2020073472A1/zh
Publication of WO2020073231A1 publication Critical patent/WO2020073231A1/zh
Priority to US17/226,714 priority patent/US11355046B2/en
Priority to US17/226,846 priority patent/US20220114968A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the technical field of display panels, and more specifically, to a GOA circuit and a display device.
  • Gate driver on The array (GOA) circuit is widely used in electronic displays such as LCD and AMOLED. It is a key part of the display panel and is used to provide scan pulse signals to the pixel matrix.
  • the traditional GOA circuit is designed based on the basic idea that the pre-stage triggers the post-stage, and generally consists of a bootstrap capacitor and a unipolar transistor. Based on this design, the scanning of the pixel array can only be performed sequentially, not randomly.
  • C gon is the load contribution of the GOA in the active state to the clock line
  • C ov is the load contribution of the remaining N-1 level GOA in the inactive state to the clock line
  • C pixel is the contribution of all pixels on the clock line to the clock line Load contribution.
  • each row of pixels is reduced, and the available area of the GOA circuit used with it is continuously reduced.
  • the size of the transistor that makes the GOA circuit is further restricted, and the driving ability is reduced.
  • the technical problem to be solved by the present invention is to provide a GOA circuit and a display device in view of the above-mentioned defects of the prior art.
  • the technical solution adopted by the present invention to solve its technical problem is to construct a GOA circuit, including a plurality of mutually independent GOA units, each of the GOA units includes an enabling module and a drive corresponding to the enabling module Module
  • the enable module includes an input terminal for receiving a row address signal of a row address signal, and an enable signal output terminal for outputting an enable signal according to the row address signal;
  • the driving module includes an enable signal input terminal connected to an enable signal output terminal of the enable module, an enable signal input terminal for receiving an enable signal output by the enable signal output terminal, and a power signal according to the enable signal
  • a drive signal output terminal that outputs a drive signal, the drive signal output terminal is connected to a gate line of a row corresponding to the drive module, so as to send the drive signal to the gate line of the corresponding row, and gate the corresponding Row.
  • the enabling module is a row decoder based on Gray code encoding.
  • the decoder of each row includes a plurality of transistors connected in series, and two transistors in the adjacent row and the same column are combined into one transistor when the preset conditions are satisfied.
  • the two transistors in the adjacent row and the same column satisfying the preset condition include:
  • the gates of the two transistors are shorted together, and each is the most significant transistor of the decoder in the row or the gates of the two transistors are shorted together, and the transistors immediately before the previous high position are merged together.
  • each of the GOA units further includes an enable signal output terminal connected to the enable module, for outputting a drive signal from the drive module and gating the corresponding row, Reset module capable of module reset.
  • the reset module includes a P-type reset transistor and an inverter
  • the first electrode of the P-type reset transistor is connected to a high-level signal (VDD)
  • the second electrode of the P-type reset transistor is connected to an enable signal output terminal of the enable module
  • the P-type reset The gate of the transistor is connected to the output of the inverter, and the input of the inverter is connected to the clock signal (CLKR).
  • the reset module includes an N-type reset transistor, a first electrode of the N-type reset transistor is connected to an enable signal output terminal of the enable module, and a second electrode of the N-type reset transistor Connect the ground signal (GND).
  • N-type reset transistor a first electrode of the N-type reset transistor is connected to an enable signal output terminal of the enable module, and a second electrode of the N-type reset transistor Connect the ground signal (GND).
  • the driving module includes: a pull-up P-type transistor and a pull-down N-type transistor;
  • the first electrode of the pull-up P-type transistor is connected to a pull-up clock signal (CLK)
  • the second electrode of the pull-up P-type transistor is connected to the first electrode of the pull-down N-type transistor
  • the pull-up P-type transistor The gate of the drive module as the enable signal input terminal of the drive module is connected to the enable output terminal of the enable module;
  • the second electrode of the pull-down N-type transistor is connected to a constant voltage low potential (VGL), and the gate of the pull-down N-type transistor is connected to a clock signal (CLKR);
  • the second electrode of the pull-up P-type transistor also serves as a drive signal output terminal of the drive module to connect the gate line of the row corresponding to the drive module.
  • the driving module includes: driving an inverter and a T flip-flop;
  • the input terminal of the drive inverter is used as the enable signal input terminal of the drive module to be connected to the enable output terminal of the enable module, and the output terminal of the drive inverter is connected to the input signal of the T flip-flop At the input end, the clock signal input end of the T flip-flop is connected to a pull-up clock signal (CLK), and the output end of the T flip-flop drives the signal.
  • CLK pull-up clock signal
  • the driving module further includes: a second P-type transistor connected in series between the second electrode of the pull-up P-type transistor and the first electrode of the pull-down N-type transistor;
  • the first electrode of the second P-type transistor is connected to the second electrode of the pull-up P-type transistor, and the second electrode of the second P-type transistor is connected to the first electrode of the pull-down N-type transistor.
  • the gate of the second P-type transistor is short-circuited with the gate of the pull-down N-type transistor.
  • the driving module further includes: a voltage domain conversion amplifier and a buffer inverter;
  • the input terminal of the voltage domain conversion amplifier is connected to the connection node of the second electrode of the second P-type transistor and the first electrode of the pull-down N-type transistor, and the output terminal of the voltage domain conversion amplifier is connected to the buffer
  • the input terminal of the inverter, and the output terminal of the buffer inverter as the drive signal output terminal of the drive module are connected to the gate line of the row corresponding to the drive module.
  • the voltage domain conversion amplifier includes a first N-type transistor and a second N-type transistor;
  • the first electrode and the gate of the first N-type transistor are connected to a constant voltage high potential (VGH), and the second electrode of the first N-type transistor is connected to the first electrode of the second N-type transistor.
  • the second electrode of the second N-type transistor is connected to a constant voltage low potential (VGL), and the gate of the second N-type transistor is connected to the second of the second P-type transistor as the input terminal of the voltage domain conversion amplifier A connection node between the electrode and the first electrode of the pull-down N-type transistor;
  • a connection node between the second electrode of the first N-type transistor and the first electrode of the second N-type transistor is the output terminal of the voltage domain conversion amplifier.
  • the buffered inverter includes M serially connected inverter modules; M is a natural number greater than 1;
  • Each inverter module includes a first P-type transistor and a third N-type transistor, the first electrode of the first P-type transistor is connected to a constant voltage high potential (VGH), and the second electrode of the first P-type transistor is The first electrode of the third N-type transistor is connected, and the second electrode of the third N-type transistor is connected to a constant voltage low potential (VGL);
  • the node where the gate of the first P-type transistor and the gate of the third N-type transistor in each inverter module is short-circuited is the input terminal of the inverter module, and the first P-type transistor in each inverter module
  • the node where the two electrodes and the first electrode of the third N-type transistor are connected is the output terminal of the inverter module;
  • the input terminal of the first inverter module is used as the input terminal of the buffer inverter and connected to the output terminal of the voltage domain conversion amplifier; the output terminal of the Mth inverter module is the output terminal of the buffer inverter .
  • the GOA unit further includes a voltage stabilizing module, and the voltage stabilizing module includes an enabling node and a voltage stabilizing capacitor;
  • the enable node is respectively connected to the enable signal output terminal of the enable module and the enable signal input terminal of the drive module, and the first end of the voltage stabilizing capacitor is connected to the enable node, the voltage regulator
  • the second end of the capacitor is connected to any one of constant voltage high potential (VGH), constant voltage low potential (VGL) and constant low voltage (VGLL).
  • the P-type transistor in each GOA unit is a low-temperature polysilicon, amorphous silicon, or a thin-film transistor in which a channel is made of materials in which carbon, silicon, and germanium are mixed in any ratio.
  • each of the N-type transistors in the GOA unit is a thin-film transistor whose channel is based on metal oxide.
  • the invention also provides a display device including the GOA circuit described above.
  • the invention provides a GOA circuit that supports random addressing.
  • the GOA circuit allows data to be written to the screen not in line order. When most areas of the screen are static images and only a small number of areas are constantly changing, only the portion The area is programmed, and because the row with the same image is not gated, the dynamic power consumption is effectively reduced, and the time left for each row of the image change can be increased, making it possible to achieve between display size and display power, and display refresh rate. The possibility of real-time and dynamic adjustment.
  • the post-stage trigger in the GOA circuit of the present invention does not depend on the pre-stage trigger, so when a defect occurs in the isolated first-level GOA unit, the functions of the remaining GOA units will not be affected, so that the screen and rating are improved, providing The possibility to dynamically repair the screen.
  • the GOA circuit of the present invention does not use the traditional bootstrap structure.
  • the clock line does not need to directly drive the output transistor in the GOA unit. Therefore, the dynamic response of the (N-1) level inactive GOA unit can be greatly reduced Impact of power consumption.
  • the GOA circuit of the present invention is suitable for high-resolution, large-size screens.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a single GOA unit in a GOA circuit of the present invention
  • FIG. 2 is a schematic structural diagram of a second embodiment of a single GOA unit in a GOA circuit of the present invention
  • Fig. 3 is a circuit schematic diagram of a decoder for a sequential codec
  • FIG. 4 is a circuit schematic diagram of a row decoder implemented with N-type transistors of the present invention.
  • FIG. 5 is a circuit schematic diagram of a row decoder implemented with P-type transistors of the present invention.
  • FIG. 6a is a layout design diagram of a row decoder implemented with N-type transistors (transistors are not merged),
  • FIG. 6b is a layout design diagram of the row decoder after merging transistors according to the preset conditions of the present invention, and
  • FIG. 6c is a diagram 6b circuit schematic;
  • FIG. 7a is a schematic diagram of the current flow direction of a row decoder (transistors not combined) implemented with N-type transistors
  • FIG. 7b is a schematic diagram of the current flow direction of a row decoder after merging transistors according to the preset conditions of the present invention
  • FIG. 8 is a circuit schematic diagram of the first embodiment of the reset module of the present invention.
  • FIG. 9 is a circuit schematic diagram of the second embodiment of the reset module of the present invention.
  • FIG. 10 is a schematic structural diagram of a third embodiment of a GOA circuit of the present invention.
  • FIG. 11 is a circuit schematic diagram of the first embodiment of the drive module of the present invention.
  • FIG. 12 is a schematic diagram of the timing waveforms in the operating mode of FIG. 11;
  • FIG. 13 is a timing waveform diagram of another operation mode of FIG. 11;
  • FIG. 14 is a schematic diagram and timing waveform diagram of multiple GOA units of FIG. 11 used in the present invention.
  • 15 is a circuit schematic diagram of a second embodiment of the driving module of the present invention.
  • FIG. 16 is a timing waveform diagram of FIG. 15;
  • FIG. 17 is a schematic diagram and timing waveform diagram of using multiple GOA units of FIG. 15 in the present invention.
  • FIG. 19 is a timing waveform diagram of FIG. 18.
  • FIG. 20 is a schematic diagram and timing waveform diagram of using multiple GOA units of FIG. 18 in the present invention.
  • FIG. 1 it is a schematic structural diagram of a first embodiment of a GOA circuit of the present invention.
  • the GOA circuit of this embodiment includes a plurality of mutually independent GOA units 10, and each GOA unit 10 includes an enabling module 11 and a driving module 12 corresponding to the enabling module 11.
  • the GOA circuit of the present invention is based on transistors of complementary polarity, that is, there are both N-type and P-type transistors on the panel.
  • the enable module 11 includes an input terminal for receiving a row address signal of a row address signal, and an enable signal output terminal for outputting an enable signal according to the row address signal.
  • the present invention does not limit the source of the row address signal.
  • the row address signal may be generated by an external driver IC, but in other embodiments, the row address signal may also be generated by the display screen itself.
  • the display screen can provide two transistors with complementary polarities, a dedicated circuit is designed on the display screen. The dedicated circuit can directly generate the aforementioned row address signal without the need of an external driver IC.
  • the enabling module 11 of the embodiment of the present invention is a row decoder based on Gray code encoding.
  • each row of decoders may include multiple transistors connected in series, and two transistors in adjacent rows and in the same column are combined into one transistor when the preset conditions are satisfied.
  • Gray code-encoded row decoder By using the Gray code-encoded row decoder, random addressing can be achieved, allowing data not to be written to the screen in line order, and the subsequent stage trigger does not depend on the previous stage trigger, effectively improving the screen yield and rating, giving The dynamic repair screen provides the possibility, and by using the Gray code row decoder can reduce the horizontal cross-over in the layout, allowing more transistors to merge, reducing the dynamic power of the decoder during the most commonly used sequential scanning process Consume.
  • FIG. 3 it is the circuit schematic diagram of the sequential encoding decoder.
  • This row of decoders uses 4-bit 16-level GOA as an example. If the decoder is designed with sequential encoding, the level 0 encoding is 0000, The level 2 code is 0002, ..., and the level 15 code is 1111, as shown in Table 1.
  • the decoder implemented in sequential encoding has many horizontal cross-lines, and the number of horizontal cross-lines required for each row is different.
  • N the required horizontal crossover reaches (N-1).
  • PPI pixel density
  • the row decoder based on the Gray code encoding of the present invention can be known from the nature of the Gray code. There is only 1 bit difference between adjacent codes, so each row decoder of the present invention only needs one horizontal cross line. This property has nothing to do with the size of the screen resolution, that is, whether it is FHD or 4K UHD, when using the GOA row decoder of the present invention, only one horizontal cross-line for each row is required.
  • the circuit schematic diagram of a specific embodiment of the row decoder based on Gray code encoding of the present invention is shown in FIG. 4.
  • the row decoder of this embodiment takes 4-bit 16-level GOA as an example, then the level 0 encoding is 0000, the level 1 encoding is 0001, the level 2 encoding is 0011, the level 3 encoding is 0010, ..., the The 15-level code is 1000, as shown in Table 2.
  • the transistors in the schematic diagrams of FIG. 3 and FIG. 4 that need to be explained here are N-type transistors and only have 16 levels and 4 address bits. However, the scope of application of the present invention should include N-type and P-type transistors and any multi-level case.
  • the transistor symbols in FIG. 3 and FIG. 4 only represent the transistors needed here, not the number of transistors here.
  • the schematic diagram of FIG. 4 if two transistors in adjacent rows and in the same column satisfy the preset condition, they can be merged into one transistor. That is, two transistors in adjacent rows and the same column can be merged into a transistor with a larger size and a higher driving capacity when the preset conditions are satisfied.
  • the two transistors in the adjacent row and the same column satisfy the preset conditions including: the gates of the two transistors are shorted together, and each is the most significant transistor of the decoder of the row, or the gates of the two transistors The transistors shorted together and the transistors immediately before the previous one are merged together.
  • the row decoder of the present invention can also be implemented using P-type transistors, where the implementation of P-type transistors is similar to that of N-type transistors, with the difference that code 0 corresponds to the inverse signal, code 1 corresponds to the original signal, and the voltage Polarity is symmetrical with N-type.
  • the circuit schematic diagram realized by the P-type transistor is shown in FIG. 5, and the specific coding is shown in Table 3.
  • the merging conditions of the transistors in the row decoder implemented by the P-type transistors are the same as the merging conditions of the N-type transistors, and will not be repeated here.
  • FIG. 6b it is a layout design diagram of a row decoder implemented by an N-type transistor of the present invention.
  • the layout of the row decoder can achieve the effects of being very compact, saving area, and optimizing delay.
  • the transistors in the same row are connected in series with each other, so the source and drain of adjacent transistors in the same row can be shared, and there is no need to use metal and contact holes to achieve the connection.
  • This design method can save The lateral area can effectively avoid the influence of the contact resistance and load capacitance brought by the metal wiring on the delay of the row decoder.
  • FIG. 6a is a schematic diagram of the transistors not merged
  • FIG. 6b is a schematic diagram of the transistors merged.
  • the transistors (n11 ⁇ n14) in the leftmost first column (a1) can be merged.
  • the merged layout is shown in the first column (a1 ') on the left in Figure 6b.
  • the gates of transistor n31 and transistor n32 are shorted, and the gates of transistor n33 and transistor n34 are short Connected, but the gates of transistor n32 and transistor n33 are not short-circuited), so the four transistors (n31 ⁇ n34) in this column (a3) cannot be combined; however, the two transistors in the upper half (transistor n31 and transistor n32) The gates of the two transistors (transistor n33 and transistor n34) in the lower half are shorted together, and they are adjacent to the previous high-order transistor (ie, the transistors (n21 ⁇ n24) in the second column from the left (a2)) Merged together, so according to the preset conditions, the two transistors in the upper half (transistor n31 and transistor n32) and the two transistors in the lower half (transistor n33 and transistor n34) can be merged in pairs, and the merged layout is shown in Figure 6b Is shown in the third column
  • merging refers to the active areas of transistors that originally belong to different rows of transistors on the layout (the gray area (AA) in Figure 6 can be fused.
  • the width of the active area can be increased, that is, the transistor's
  • a higher drive current can be obtained (or equivalently, the on-resistance can be lower)
  • the edges of the active regions that are separated from each other must meet the design rules for the minimum separation requirements of the process, and after fusion No need to consider this rule, the requirements for mask making and lithography can be reduced, and the yield of the process is greatly improved.
  • the merging technology enables the row decoding design of the present invention to support a high-resolution screen, so that the decoding speed is basically independent of the increased address line.
  • the driving module 12 includes an enable signal input terminal connected to the enable signal output terminal of the enable module 11, an enable signal input terminal for receiving the enable signal output by the enable signal output terminal, and A driving signal output terminal capable of outputting a driving signal, and the driving signal output terminal is connected to a gate line of a row corresponding to the driving module 12 to send the driving signal to the gate line of the corresponding row, gated The corresponding line.
  • the driving signal output by the driving module 12 is a pulse signal.
  • the driving module 12 is a pulse generator.
  • the solution of the embodiment of the present invention provides a GOA circuit that supports random addressing.
  • the GOA circuit allows data to be written to the screen out of line order. When most areas of the screen are static images and only a few areas are constantly changing, Only this part of the area needs to be programmed, and since the row with the unchanged image is not gated, the dynamic power consumption is effectively reduced, and at the same time, the time left for each row of the image change can be increased, so that the display size and display power, display refresh The real-time and dynamic adjustment is possible between rates.
  • the GOA circuit of the present invention does not depend on the trigger of the previous stage, so when the isolated GOA unit 10 has a defect, the functions of the remaining GOA units 10 will not be affected, and the screen and rating will be improved. Provides the possibility to dynamically repair the screen.
  • the GOA circuit of the present invention does not use the traditional bootstrap structure, and the clock line does not need to directly drive the output transistor in the GOA unit 10, therefore, the impact of the (N-1) -level inactive GOA unit 10 on dynamic power consumption can be greatly reduced .
  • the GOA circuit of the present invention is suitable for high-resolution, large-size screens.
  • FIG. 2 is a schematic structural diagram of a second embodiment of a GOA circuit of the present invention.
  • each GOA unit 10 further includes an enable signal output terminal connected to the enable module 11, and is used to output a drive signal after the drive module 12 outputs After the corresponding row is selected, the reset module 13 resets the enable module 11.
  • the reset module 13 may include one or more.
  • each reset module 13 is set corresponding to each row of decoders.
  • the reset module 13 of the row is reset.
  • the output terminals of the decoders of all rows are reset by the reset module 13 of all rows, and the result of the previous decoding output can be erased. So that when the next row address signal arrives, the row to output the drive signal is reselected.
  • FIG. 8 it is a circuit schematic diagram of the first embodiment of the reset module 13 of the present invention.
  • it is an embodiment of a row decoder composed of N-type transistors and a correspondingly provided reset module 13.
  • the reset module 13 may include a P-type reset transistor and an inverter.
  • the first electrode of the P-type reset transistor is connected to a high-level signal (VDD)
  • the second electrode of the P-type reset transistor is connected to an enable signal output terminal of the enable module 11
  • the P-type reset transistor The gate of the setting transistor is connected to the output terminal of the inverter, and the input terminal of the inverter is connected to the clock signal (CLKR).
  • the P-type reset transistor is turned on to charge the output terminal of the row decoder, and the output terminal of the row decoder is reset.
  • FIG. 9 it is a circuit schematic diagram of the second embodiment of the reset module 13 of the present invention.
  • it is an embodiment of a row decoder composed of P-type transistors and a correspondingly provided reset module 13.
  • the reset module 13 includes an N-type reset transistor, a first electrode of the N-type reset transistor is connected to an enable signal output terminal of the enable module 11, and the N-type reset transistor The second electrode is connected to the ground signal (GND).
  • the N-type reset transistor is turned on to discharge the output terminal of the row decoder, and the output terminal of the row decoder is reset.
  • both the high-level signal (VDD) and the clock signal (CLKR) can be provided by the driver IC.
  • FIG. 10 is a schematic structural diagram of a third embodiment of a GOA circuit of the present invention.
  • each GOA unit 10 further includes a voltage stabilizing module 14, the voltage stabilizing module 14 includes an enabling node and a voltage stabilizing capacitor;
  • the enable node is connected to the enable signal output end of the enable module 11 and the enable signal input end of the drive module 12, respectively, and the first end of the voltage stabilizing capacitor is connected to the enable node.
  • the second end of the voltage stabilizing capacitor is connected to any one of constant voltage high potential (VGH), constant voltage low potential (VGL) or constant low voltage (VGLL).
  • the constant voltage high potential (VGH) is a DC high voltage signal
  • the constant voltage low potential (VGL) is a DC low voltage signal
  • the constant low voltage (VGLL) is a DC low voltage signal lower than VGL.
  • FIG. 11 it is a circuit schematic diagram of the first embodiment of the driving module 12 of the present invention.
  • the driving module 12 of this embodiment includes a pull-up P-type transistor and a pull-down N-type transistor.
  • the first electrode of the pull-up P-type transistor is connected to a pull-up clock signal (CLK), the second electrode of the pull-up P-type transistor is connected to the first electrode of the pull-down N-type transistor, and the pull-up P-type transistor
  • CLK pull-up clock signal
  • the enable signal input terminal of the drive module 12 is connected to the enable output terminal of the enable module 11
  • the second electrode of the pull-down N-type transistor is connected to a constant voltage low potential (VGL)
  • the gate of the N-type transistor is connected to a clock signal (CLKR)
  • the second electrode of the pull-up P-type transistor is also used as a drive signal output of the drive module 12 to connect to the gate line of the row corresponding to the drive module 12 .
  • the pull-up P-type transistor is a transistor with a large mobility and a large size
  • the pull-down N-type transistor is a transistor with a small size
  • the number of transistors in the driving module 12 of this embodiment is relatively small, only one pull-up P-type transistor needs to occupy a large area, and no transistor can withstand DC high voltage for a long time, which can effectively extend the life of the GOA circuit.
  • FIG. 11 The working principle of FIG. 11 will be described below with reference to FIG. 12.
  • CLK1 ⁇ CLK4 can be provided by the driver IC, and will continue to be provided after the screen is turned on and displayed.
  • S [0: N] represents the row address signal input to the row decoder.
  • the row decoder in the GOA unit 10 of a certain stage corresponding to the row address signal Dn is selected, and the row decoder enable signal output terminal (EN) output is enabled
  • the signal is a low-level signal, and the pull-up P-type transistor is turned on.
  • the pull-up P-type transistor of the selected row introduces the positive pulse to the output terminal (OUT), and a positive pulse is generated at the output terminal (OUT)
  • the output terminal of the pull-up P-type transistor corresponds to the scan pulse required for the connected row.
  • the enable signal output terminal (EN) is still at a low voltage
  • the pull-up P-type transistor is still turned on, and the pull-up clock signal (CLK) voltage drops, driving the output terminal (OUT) voltage to drop.
  • FIG. 13 is a timing waveform diagram of another operation mode of FIG. 10.
  • the row decoder in the GOA unit 10 of a certain stage is selected, the row decoder enable signal output terminal (EN) of the row is discharged to VGLL, and the pull-up P-type transistor is turned on.
  • the upper P-type transistor introduces the positive pulse to the output terminal (OUT), and generates a positive pulse at the output terminal (OUT).
  • the positive pulse of the pull-up clock signal (CLK) disappears, the output terminal (OUT) falls to a low potential, the positive pulse of the clock signal (CLKR) arrives, the enable signal output terminal (EN) is reset to a high voltage, and the P Type transistor is off.
  • the operation mode of FIG. 13 is compared with the operation mode of FIG. 12.
  • the row decoder and the driving module 12 work in the same time period, and the row decoder continues to be turned on during the driving module 12 generation stage.
  • the voltage at the enable output (EN) is kept at a low potential, so the role of the voltage stabilizing capacitor C is reduced, and the area can be omitted or reduced.
  • FIG. 14 a schematic diagram of using multiple driving modules 12 shown in FIG. 11 is shown in FIG. 14. It can be seen from FIG. 14 that the driving module 12 is included in each stage of the GOA unit 10. Unlike the conventional GOA circuit, the output of each stage of the GOA unit 10 only enters the pixel array, and does not enter any stage of the GOA after or before Unit 10. That is, the operation of the GOA unit 10 of any stage of the present invention does not depend on the enable signal provided by the GOA of the previous stage or the latter stage, but the enable signal is generated by the row decoder within the stage.
  • the driving module 12 of this embodiment may further include: a second P-type transistor connected in series between the second electrode of the pull-up P-type transistor and the first electrode of the pull-down N-type transistor.
  • the first electrode of the second P-type transistor is connected to the second electrode of the pull-up P-type transistor, and the second electrode of the second P-type transistor is connected to the first electrode of the pull-down N-type transistor.
  • the gate of the second P-type transistor is short-circuited with the gate of the pull-down N-type transistor.
  • FIG. 15 it is a circuit schematic diagram of the second embodiment of the driving module 12 of the present invention.
  • the driving module 12 may further include: a voltage domain conversion amplifier 121 and a buffer inverter 122.
  • the input terminal of the voltage domain conversion amplifier 121 is connected to the connection node of the second electrode of the second P-type transistor and the first electrode of the pull-down N-type transistor, and the output terminal of the voltage domain conversion amplifier 121 is connected to the The input terminal of the buffer inverter 122, and the output terminal of the buffer inverter 122 as the drive signal output terminal of the drive module 12 are connected to the gate line of the row corresponding to the drive module 12.
  • the voltage domain conversion amplifier 121 can realize the amplification process of the connected driving signal, and the buffer inverter 122 can be used to shape the connected driving signal while increasing the driving capacity.
  • the voltage domain conversion amplifier 121 includes a first N-type transistor and a second N-type transistor.
  • the first electrode and the gate of the first N-type transistor are connected to a constant voltage high potential (VGH), and the second electrode of the first N-type transistor is connected to the first electrode of the second N-type transistor.
  • the second electrode of the second N-type transistor is connected to a constant voltage low potential (VGL), and the gate of the second N-type transistor is connected to the second P-type transistor as the input terminal of the voltage domain conversion amplifier 121
  • a connection node between the two electrodes and the first electrode of the pull-down N-type transistor; the connection node between the second electrode of the first N-type transistor and the first electrode of the second N-type transistor is the voltage domain conversion amplifier 121 output.
  • the buffer inverter 122 may include M series inverter modules; M is a natural number greater than 1.
  • Each inverter module includes a first P-type transistor and a third N-type transistor, a first electrode of the first P-type transistor is connected to a constant voltage high potential (VGH), and a second electrode of the upper P-type transistor and The first electrode of the third N-type transistor is connected, and the second electrode of the third N-type transistor is connected to a constant voltage low potential (VGL); the gate of the first P-type transistor and the first The node where the gate of the two N-type transistors is short-circuited is the input terminal of the inverter module, and the node connected to the second electrode of the first P-type transistor and the first electrode of the third N-type transistor in each inverter module is the opposite The output of the phase module.
  • VGH constant voltage high potential
  • VGL constant voltage low potential
  • the input terminal of the first inverting module is used as the input terminal of the buffer inverter 122 to be connected to the output terminal of the voltage domain conversion amplifier 121; the output terminal of the Mth inverting module is the buffer inverter 122 Output.
  • the M of the inverting module can be increased step by step according to the actual design requirements, so as to achieve the purpose of optimizing the delay and driving capability.
  • FIG. 16 it is a schematic diagram of a timing waveform using the circuit of FIG.
  • the row decoder performs address decoding, and the EN of the selected row decreases.
  • the negative pulse of the pull-up clock signal (CLK) arrives, the positive pulse is generated at the voltage at the N1 point, the buffer inverter 122 turns over successively, and the positive pulse is generated at the output terminal (OUT).
  • the reset module 13 is turned on, and the EN point recovers the high voltage.
  • FIG. 17 a schematic diagram of using multiple driving modules 12 shown in FIG. 15 is shown in FIG. 17. It can be seen from FIG. 17 that the driving module 12 is included in each stage of the GOA unit 10. Unlike the conventional GOA circuit, the output of each stage of the GOA unit 10 only enters the pixel array, and does not enter any level of GOA after or before Unit 10. That is, the operation of the GOA unit 10 of any stage of the present invention does not depend on the enable signal provided by the GOA of the previous stage or the latter stage, but the enable signal is generated by the row decoder within the stage.
  • FIG. 18 it is a circuit schematic diagram of the third embodiment of the driving module 12 of the present invention.
  • this embodiment differs from the second embodiment in that in the driving module 12 of this embodiment, the driving signal is generated by changing to a T flip-flop 123.
  • the driving module 12 of this embodiment includes: driving an inverter and a T flip-flop 123.
  • the input terminal of the drive inverter is used as the enable signal input terminal of the drive module 12 to be connected to the enable output terminal of the enable module 11, and the output terminal of the drive inverter is connected to the T flip-flop 123
  • the input terminal of the input signal, the clock signal input terminal of the T flip-flop 123 is connected to a pull-up clock signal (CLK), and the output terminal of the T flip-flop 123 outputs a driving signal.
  • CLK pull-up clock signal
  • the output terminal of the T flip-flop 123 outputs a driving signal.
  • the output terminal of the T flip-flop 123 is connected to the input terminal of the voltage domain conversion amplifier 121 (ie, the gate of the second N-type transistor).
  • the signal at its output terminal (Q) is inverted at the rising edge of each CLK. If the signal of Q turns out to be low, it goes high; if the signal of Q turns out to be high, it goes low. When the input voltage at T is low, the output of Q remains unchanged.
  • the dynamic function can be effectively saved, and the influence of the CLK noise and the output glitch of the decoder on the output terminal (OUT) can be effectively suppressed.
  • FIG. 19 is a schematic diagram of a single-stage timing waveform using the circuit of FIG. 18.
  • the row decoder performs address decoding, the EN of the selected row is lowered, and the T flip-flop 123 is turned on.
  • the Q terminal of the T flip-flop 123 each toggles once, generating a positive pulse.
  • the positive pulse passes through the buffer inverter 122 and is output to the pixel array in the screen.
  • FIG. 20 is a schematic diagram and timing waveform diagram of a plurality of GOA units 10 using the circuit of FIG. 18.
  • the solution of the embodiment of the present invention provides a GOA circuit that supports random addressing.
  • the GOA circuit allows data to be written to the screen out of line order. When most areas of the screen are static images and only a few areas are constantly changing, Only this part of the area needs to be programmed, and since the row with the unchanged image is not gated, the dynamic power consumption is effectively reduced, and at the same time, the time left for each row of the image change can be increased, so that the display size and display power, display refresh The real-time and dynamic adjustment is possible between rates.
  • the GOA circuit of the present invention does not depend on the trigger of the previous stage, so when the isolated GOA unit 10 has a defect, the functions of the remaining GOA units 10 will not be affected, and the screen and rating will be improved. Provides the possibility to dynamically repair the screen.
  • the GOA circuit of the present invention does not use the traditional bootstrap structure, and the clock line does not need to directly drive the output transistor in the GOA unit 10, therefore, the impact of the (N-1) -level inactive GOA unit 10 on dynamic power consumption can be greatly reduced .
  • the GOA circuit of the present invention is suitable for high-resolution, large-size screens.
  • the present invention also provides a display device including the GOA circuit of the foregoing embodiment.
  • the display device includes but is not limited to an LTPS display device and an AMOLED display device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路及显示装置，GOA电路包括多个相互独立的GOA单元（10），每一个GOA单元（10）包括一个使能模块（11）以及与使能模块（11）对应设置的驱动模块（12）；使能模块（11）包括用于接收行地址信号的行地址信号的输入端，以及用于根据行地址信号输出使能信号的使能信号输出端；驱动模块（12）包括与使能模块（11）的使能信号输出端连接、用于接收使能信号输出端输出的使能信号的使能信号输入端，以及用于根据使能信号输出驱动信号的驱动信号输出端，驱动信号输出端连接与驱动模块（12）对应设置的行的栅线，以将驱动信号发送至对应行的栅线，选通对应行。支持随机寻址，允许数据不按照行的顺序写入屏幕，后级触发不依赖于前级的触发，产品良率高，功耗低，适合于高分辨率、大尺寸屏幕。

Description

一种GOA电路及显示装置 技术领域
本发明涉及显示面板的技术领域，更具体地说，涉及一种GOA电路及显示装置。
 背景技术
Gate driver on array（GOA）电路广泛应用于LCD和AMOLED等电子显示器中，它是显示面板的关键部分，用于向像素矩阵提供扫描脉冲信号。
传统的GOA电路基于前级触发后级的基本思想设计，一般由自举电容和单一极性的晶体管组成。基于该设计，像素阵列的扫描只能顺序进行，无法随机进行。
当屏幕有N行，采用逐行扫描，刷新率是60Hz，留给每一行的时间是1/60/N。驱动GOA的时钟线的电容负载正比于：C gon+C ov*（N-1）+C pixel。C gon是处于激活状态的GOA对时钟线的负载贡献，C ov是处于非激活状态的其余N-1级GOA对时钟线的负载贡献，C pixel是正在扫描的行上所有像素对时钟线的负载贡献。当GOA输出晶体管尺寸增加时，Cgon和Cov都会按比例增加。
当屏幕尺寸不断增加、分辨率不断增高、像素密度不断增加时，对GOA电路的挑战会不断增加，这表现在：
每一行像素数量增加，GOA电路的负载增加(Cpixel)。
每一行像素的尺寸减小，与之配合的GOA电路可以使用的面积不断减小，制作GOA电路的晶体管尺寸受到进一步限制，驱动能力下降。
绝对行数的增加使得每一行的扫描时间不断减小（1/60/N），为了满足更为苛刻的时序要求， GOA输出晶体管的尺寸需要增加。这个要求不仅和前述面积减小矛盾，而且导致Cgon和Cov不断增加。
绝对行数的增加使得处于关闭状态的GOA的级数(N-1)不断增加，时钟线的负载相应增加，无用功增加。
绝对行数的增加使得GOA出现缺陷的可能增加。一旦某一级GOA出现失误，就会导致后面所有GOA失误，造成屏幕报废。
以上一切因素导致传统GOA的电路结构在用于尺寸不断增大、分辨率不断增加、像素密度不断提高的屏幕中时，面临的根本困难越来越严重，时序难以满足，功耗不断增加，且良率不断下降。
 技术问题
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种GOA电路及显示装置。
 技术解决方案
本发明解决其技术问题所采用的技术方案是：构造一种GOA电路，包括多个相互独立的GOA单元，每一个所述GOA单元包括一个使能模块以及与所述使能模块对应设置的驱动模块；
所述使能模块包括用于接收行地址信号的行地址信号的输入端，以及用于根据所述行地址信号输出使能信号的使能信号输出端；
所述驱动模块包括与所述使能模块的使能信号输出端连接、用于接收所述使能信号输出端输出的使能信号的使能信号输入端，以及用于根据所述使能信号输出驱动信号的驱动信号输出端，所述驱动信号输出端连接与所述驱动模块对应设置的行的栅线，以将所述驱动信号发送至所述对应行的栅线，选通所述对应行。
优选地，所述使能模块为基于格雷码编码的行译码器。
优选地，所述每一行译码器包括多个串联的晶体管，且相邻行、同一列的两个晶体管在满足预设条件时合并为一个晶体管。
优选地，所述相邻行、同一列的两个晶体管满足预设条件包括：
两个晶体管的栅极短接在一起，且各自是本行译码器的最高位的晶体管或者两个晶体管的栅极短接在一起，且紧邻前一高位的晶体管合并在一起。
优选地，每一个所述GOA单元还包括与所述使能模块的使能信号输出端连接、用于在所述驱动模块输出驱动信号后并将所述对应行选通后、将所述使能模块重置的重置模块。
优选地，所述重置模块包括P型重置晶体管和反相器；
所述P型重置晶体管的第一电极连接高电平信号（VDD），所述P型重置晶体管的第二电极连接所述使能模块的使能信号输出端，所述P型重置晶体管的栅极连接所述反相器的输出端，所述反相器的输入端连接时钟信号（CLKR）。
优选地，所述重置模块包括N型重置晶体管，所述N型重置晶体管的第一电极连接所述使能模块的使能信号输出端，所述N型重置晶体管的第二电极连接地信号（GND）。
优选地，所述驱动模块包括：上拉P型晶体管和下拉N型晶体管；
所述上拉P型晶体管的第一电极连接上拉时钟信号（CLK），所述上拉P型晶体管的第二电极连接所述下拉N型晶体管的第一电极，所述上拉P型晶体管的栅极作为所述驱动模块的使能信号输入端连接所述使能模块的使能输出端；
所述下拉N型晶体管的第二电极连接恒压低电位（VGL），所述下拉N型晶体管的栅极连接时钟信号（CLKR）；
所述上拉P型晶体管的第二电极还作为所述驱动模块的驱动信号输出端连接与所述驱动模块对应设置的行的栅线。
优选地，所述驱动模块包括：驱动反相器和T触发器；
所述驱动反相器的输入端作为所述驱动模块的使能信号输入端连接所述使能模块的使能输出端，所述驱动反相器的输出端连接所述T触发器的输入信号输入端，所述T触发器的时钟信号输入端连接上拉时钟信号（CLK），所述T触发器的输出端驱动信号。
优选地，所述驱动模块还包括：串联在所述上拉P型晶体管的第二电极与所述下拉N型晶体管的第一电极之间的第二P型晶体管；
所述第二P型晶体管的第一电极与所述上拉P型晶体管的第二电极连接，所述第二P型晶体管的第二电极与所述下拉N型晶体管的第一电极连接，所述第二P型晶体管的栅极与所述下拉N型晶体管的栅极短接。
优选地，所述驱动模块还包括：电压域转换放大器和缓冲反相器；
所述电压域转换放大器的输入端与所述第二P型晶体管的第二电极和所述下拉N型晶体管的第一电极的连接节点连接，所述电压域转换放大器的输出端连接所述缓冲反相器的输入端，所述缓冲反相器的输出端作为所述驱动模块的驱动信号输出端连接与所述驱动模块对应设置的行的栅线。
优选地，所述电压域转换放大器包括第一N型晶体管和第二N型晶体管；
所述第一N型晶体管的第一电极和栅极一并连接恒压高电位（VGH），所述第一N型晶体管的第二电极连接所述第二N型晶体管的第一电极，所述第二N型晶体管的第二电极连接恒压低电位（VGL），所述第二N型晶体管的栅极作为所述电压域转换放大器的输入端连接所述第二P型晶体管的第二电极和所述下拉N型晶体管的第一电极的连接节点；
所述第一N型晶体管的第二电极与所述第二N型晶体管的第一电极的连接节点为所述电压域转换放大器的输出端。
优选地，所述缓冲反相器包括M个串联的反相模块；M为大于1的自然数；
每一个反相模块包括第一P型晶体管和第三N型晶体管，所述第一P型晶体管的第一电极连接恒压高电位（VGH），所述第一P型晶体管的第二电极和所述第三N型晶体管的第一电极连接，所述第三N型晶体管的第二电极连接恒压低电位（VGL）；
每一个反相模块中的第一P型晶体管的栅极和第三N型晶体管的栅极短接的节点为反相模块的输入端，每一个反相模块中的第一P型晶体管的第二电极和第三N型晶体管的第一电极连接的节点为反相模块的输出端；
其中，第一个反相模块的输入端作为缓冲反相器的输入端连接至所述电压域转换放大器的输出端；第M个反相模块的输出端为所述缓冲反相器的输出端。
优选地，所述GOA单元还包括稳压模块，所述稳压模块包括使能节点和稳压电容；
所述使能节点分别连接所述使能模块的使能信号输出端和所述驱动模块的使能信号输入端，所述稳压电容的第一端连接所述使能节点，所述稳压电容的第二端连接恒压高电位（VGH）、恒压低电位（VGL）和恒低电压（VGLL）中的任意一种。
优选地，每一个所述GOA单元中的P型晶体管是低温多晶硅、无定型硅、或者是由碳、硅、锗三种元素按任意比例混合的材料制作沟道的薄膜晶体管。
优选地，每一个所述GOA单元中的N型晶体管是基于金属氧化物制作沟道的薄膜晶体管。
本发明还提供一种显示装置，包括以上所述的GOA电路。
 有益效果
本发明提供了一种支持随机寻址的GOA电路，该GOA电路允许数据不按照行的顺序写入屏幕，在屏幕大部分区域是静态图像，只有少部分区域不断变化时，只需要对该部分区域进行编程，且由于图像不变的行未选通，所以动态功耗有效降低，同时可以增加留给图像改变的每一行的时间，使得在显示尺寸和显示功率、显示刷新率之间可以实现实时、动态调整的可能。
另外，本发明的GOA电路中后级触发不依赖于前级的触发，所以当孤立一级GOA单元出现缺陷时，其余GOA单元的功能不会受到影响，使屏幕的和评级得到提升，提供了动态修理屏幕的可能。而且本发明的GOA电路不使用传统的自举结构，在某些实施例中时钟线不需要直接驱动GOA单元中的输出晶体管，因此，可以大大减少（N-1）级非活跃GOA单元对动态功耗的影响。
本发明的GOA电路适用于高分辨率、大尺寸屏幕。
 附图说明
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1是本发明一种GOA电路中单个GOA单元第一实施例的结构示意图；
图2是本发明一种GOA电路中单个GOA单元第二实施例的结构示意图；
图3是为顺序编码译码器的译码器的电路原理图；
图4是本发明以N型晶体管实现的行译码器的电路原理图；
图5是本发明以P型晶体管实现的行译码器的电路原理图；
图6a是以N型晶体管实现的行译码器的版图设计图（晶体管未合并）、图6b是根据本发明的预设条件合并晶体管后的行译码器的版图设计图，图6c是图6b的电路原理图；
图7a是以N型晶体管实现的行译码器（晶体管未合并）的电流流向示意图，图7b是根据本发明的预设条件合并晶体管后的行译码器的电流流向示意图；
图8是本发明重置模块第一实施例的电路原理图；
图9是本发明重置模块第二实施例的电路原理图；
图10本发明一种GOA电路第三实施例的结构示意图；
图11为本发明驱动模块第一实施例的电路原理图；
图12为图11的一运行方式的时序波形示意图；
图13为图11的另一运行方式的时序波形示意图；
图14为本发明采用图11的多个GOA单元的示意图和时序波形示意图；
图15为本发明驱动模块第二实施例的电路原理图；
图16为图15的时序波形示意图；
图17为本发明采用图15的多个GOA单元的示意图和时序波形示意图；
图18是本发明驱动模块第三实施例的电路原理图；
图19为图18的时序波形示意图；
图20为本发明采用图18的多个GOA单元的示意图和时序波形示意图。
 本发明的最佳实施方式
为了对本发明的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本发明的具体实施方式。
参考图1，为本发明一种GOA电路第一实施例的结构示意图。
如图1所示，该实施例的GOA电路包括多个相互独立的GOA单元10，每一个GOA单元10包括一个使能模块11以及与该使能模块11对应设置的驱动模块12。本发明的GOA电路基于互补极性的晶体管，即在面板上同时存在N型和P型晶体管。
使能模块11，包括用于接收行地址信号的行地址信号的输入端，以及用于根据所述行地址信号输出使能信号的使能信号输出端。
这里，需要说明的是，本发明并不限定行地址信号的来源。在一些具体实施例中，该行地址信号可以由外部的驱动IC产生，但在另一些实施例中，行地址信号也可以由显示屏自身产生。例如，当显示屏可以提供两种互补极性晶体管时，在显示屏上设计专用电路，该专用电路可直接产生前述行地址信号，而不需要外部的驱动IC提供。
可选的，本发明实施例的使能模块11为基于格雷码编码的行译码器。其中，每一行译码器可以包括多个串联的晶体管，且相邻行、同一列的两个晶体管在满足预设条件时合并为一个晶体管。
通过使用该格雷码编码的行译码器，可以实现随机寻址，允许数据不按照行的顺序写入屏幕，且后级触发不依赖于前级的触发，有效提升屏幕良率和评级，给动态修理屏幕提供了可能，而且通过采用格雷码编码的行译码器可以减少版图中的横向跨线，允许更多的晶体管合并，在最常使用的顺序扫描过程中减少译码器的动态功耗。
以下以顺序编码译码器与本发明的行译码器设计进行对比说明：
如图3所示，为顺序编码译码器的电路原理图，该行译码器以4位16级的GOA为例，如果以顺序编码来设计译码器，则第0级编码是0000、第2级编码是0002、……、第15级编码是1111，具体如表1所示。
Figure 193691dest_path_image001
表1
由图3可以看出，以顺序编码实施的译码器存在很多横向跨线，并且每一行需要的横向跨线数目不一。对于2 N级译码器，最坏情况下，在第2 N-1 -1和2 N-1级之间，需要的横向跨线达到（N-1）条。而由于横向跨线过多，必然对屏幕带来一定影响。如：占用行高，限制像素密度（PPI）的增加；增加连线之间的互感，造成信号串扰、增加连线负载，引起动态功耗和延时上升；不利于修理、不利于良率提升。
而采用本发明的基于格雷码编码的行译码器，由格雷码的性质可以知道，相邻编码之间只有1位不同，所以本发明的每一行译码器只需要一根横向跨线，这个性质与屏幕分辨率的大小无关，即无论是FHD或者4K UHD，在使用本发明的GOA行译码器时每一行的横向跨线都只需要一条。其中，本发明基于格雷码编码的行译码器的一个具体实施例的电路原理图如图4所示。该实施例的行译码器以4位16级GOA为例，则第0级编码是0000、第1级编码是0001、第2级编码是0011、第3级编码是0010、……、第15级编码是1000，具体如表2所示。
Figure 539222dest_path_image002
表2
这里需要说明的图3、图4的原理图中晶体管为N型晶体管且只有16级、4个地址位。但本发明适用范围应包括N型和P型晶体管以及任意多级的情况。另外，图3、图4中的晶体管符号仅代表此处需要晶体管，并不代表此处晶体管的数量。特别的，在图4的原理图中，如果相邻行、同一列的两个晶体管满足预设条件时可以合并为一个晶体管。即相邻行、同一列的两个晶体管在满足预设条件时可以合并为一个尺寸更大、驱动能力更高的晶体管。
其中，相邻行、同一列的两个晶体管满足预设条件包括：两个晶体管的栅极短接在一起，且各自是本行译码器的最高位的晶体管，或者两个晶体管的栅极短接在一起，且紧邻前一高位的晶体管合并在一起。
当然，本发明的行译码器也可以采用P型晶体管实现，其中，P型晶体管的实现和N型晶体管的实现类似，区别点在于：编码0对应反信号，编码1对应原信号，且电压极性与N型对称。具体的，以P型晶体管实现的电路原理图如图5所示，具体编码如表3所示。
Figure 299368dest_path_image003
表3
同样地，P型晶体管实现的行译码器中的晶体管的合并条件与N型晶体管的合并条件相同，在此不再赘述。
进一步地，如图6b所示，为本发明以N型晶体管实现的行译码器的版图设计图。本发明通过采用前述的以晶体管串联实现的行译码器，可以使得行译码器的版图可以实现十分紧凑、节省面积和优化延时的效果。
具体的，如图6b所示，同一行的晶体管相互间是串联的，所以同一行的相邻晶体管的源漏极可以共用，不需要使用金属和接触孔来实现连接，该设计方式既可以节省横向的面积，又可以有效避免金属连线带来的接触电阻和负载电容对行译码器延时的影响。
其中，图6a的版图为晶体管未合并的示意图，图6b为晶体管合并后的示意图。
如图6a所示，其最左边第一列（a1）的晶体管（n11~n14），根据预设条件，由于它们的栅极短接在一起，并且各自是本行最高位的晶体管，所以，左边第一列（a1）的晶体管（n11~n14）可以合并，合并后的版图如图6b的左边第一列（a1'）所示。接着考虑图6a左数第二列（a2），由于它们的栅极短接在一起，并且它们紧邻前一高位的晶体管（即左数第一列（a1）的晶体管（n11~n14））已经合并在一起，所以，根据预设条件，左数第二列（a2）的晶体管（n21~n24）也可以合并在一起，合并后的版图如图6b的左数第二列（a2'）所示。接着考虑图6a左数第三列（a3），由于栅极并不全部短接在一起（如图6c所示，晶体管n31与晶体管n32的栅极短接，晶体管n33与晶体管n34的栅极短接，但是晶体管n32与晶体管n33的栅极不短接），所以这一列（a3）的4个晶体管（n31~n34）不能全部合并；但是，上半部分两个晶体管（晶体管n31与晶体管n32）和下半部分两个晶体管（晶体管n33与晶体管n34）的栅极分别短接在一起，并且它们紧邻前一高位的晶体管（即左数第二列（a2）的晶体管（n21~n24））已经合并在一起，所以根据预设条件，上半部分两个晶体管（晶体管n31与晶体管n32）和下半部分两个晶体管（晶体管n33与晶体管n34）可以分别两两合并，合并后的版图如图6b的左数第三列（a3'）所示。最后考虑最低列（a4），这四个晶体管（n41~n44）只有中间两个晶体管（晶体管n42和晶体管n43）的栅极短接在一起，然而中间这两个晶体管（晶体管n42和晶体管n43）的紧邻前一高位的晶体管（晶体管n32和晶体管n33）并没有合并，所以这四个晶体管（n41~n44）不满足预设条件，不能合并，因此，最低列（a4）的四个晶体管（n41~n44）没有任何两个晶体管可以合并，所以最后行译码器合并后的版图如图6b所示。其中，图6b的电路原理图如图6c所示，在图6c中虚线框内的晶体管合并在一起。
这里需要说明的是，合并是指晶体管在版图上原属于不同行的晶体管的有源区（如图6中的灰色区域（AA）可以融合。经过融合，可以使有源区宽度增加，即晶体管的宽度增加，可以获得更高的驱动电流（或等效来看，可以使导通电阻更低）；且相互分离的有源区的边缘之间必须满足制程最小间隔要求的设计规则，而融合之后不需要考虑此规则，对掩膜版制作和光刻的要求都可以得到降低，对制程良率有很大的改善。
以下以图7a和图7b对合并后的行译码器的优势作进一步说明。
如图7a所示，考虑0001行被选中的情形。在没有合并的情况下，电流只能从本行的4个串联的TFT流过。在合并的情况下，电流向高位流动时可迅速分散到更宽的路径中（如图7b所示）。由于电阻和电流路径宽度成反比，越到高位，电阻越小，所以对使能端放电的总电阻比不合并的小，即译码速度加快。
假设，不合并情况下单个晶体管开启后的有效电阻是R，两个晶体管合并后有效电阻降为R/2。所以不合并情况下，每一行的放电总电阻为4*R；合并情况下的放电总电阻为R*（1+1/2+1/4+1/8）<2*R（等比级数）。考虑一个4096行的屏幕，需要14位地址，14个晶体管串联。不合并情况下总电阻为14*R，合并后总电阻是R*（1+1/2+1/4+1/8+ …… + 1/4096）<2*R。根据等比级数的特性可以看出合并后的总放电电阻不会随着分辨率行数的增加而等比例增加，而是存在一个上限，因此放电时间即译码时间在合并后即不受分辨率增加的影响。所以合并技术使得本发明的行译码设计可以支持高分辨率屏幕，使得译码速度基本和增加的地址线无关。
驱动模块12，其包括与所述使能模块11的使能信号输出端连接、用于接收所述使能信号输出端输出的使能信号的使能信号输入端，以及用于根据所述使能信号输出驱动信号的驱动信号输出端，所述驱动信号输出端连接与所述驱动模块12对应设置的行的栅线，以将所述驱动信号发送至所述对应行的栅线，选通所述对应行。
可选的，该驱动模块12所输出的驱动信号为脉冲信号。其中，该驱动模块12为脉冲发生器。
本发明实施例的方案，提供了一种支持随机寻址的GOA电路，该GOA电路允许数据不按照行的顺序写入屏幕，在屏幕大部分区域是静态图像，只有少部分区域不断变化时，只需要对该部分区域进行编程，且由于图像不变的行未选通，所以动态功耗有效降低，同时可以增加留给图像改变的每一行的时间，使得在显示尺寸和显示功率、显示刷新率之间可以实现实时、动态调整的可能。
另外，本发明的GOA电路中后级触发不依赖于前级的触发，所以当孤立一级GOA单元10出现缺陷时，其余GOA单元10的功能不会受到影响，使屏幕的和评级得到提升，提供了动态修理屏幕的可能。而且本发明的GOA电路不使用传统的自举结构，时钟线不需要直接驱动GOA单元10中的输出晶体管，因此，可以大大减少（N-1）级非活跃GOA单元10对动态功耗的影响。
本发明的GOA电路适用于高分辨率、大尺寸屏幕。
参考图2，为本发明一种GOA电路第二实施例的结构示意图。
该实施例在实施例一的基础上，进一步地，每一个GOA单元10还包括与所述使能模块11的使能信号输出端连接、用于在所述驱动模块12输出驱动信号后并将所述对应行选通后、将所述使能模块11重置的重置模块13。
可选的，该重置模块13可以包括一个或者多个。当该重置模块13包括多个时，每一个重置模块13与每一行译码器对应设置。
其中，在行译码器中的任意一行译码器完成一次使能信号输出，并使驱动模块12输出驱动信号后，该行的重置模块13都进行重置。在行译码器每一次完成使能信号输出后，通过所有行的重置模块13将所有行的译码器的输出端进行重置，可以将前一次译码输出的结果都会被抹去，以使在下一个行地址信号到来时重新选择输出驱动信号的行。
如图8所示，为本发明以重置模块13第一实施例的电路原理图。在该实施例中，是以N型晶体管组成的某一行译码器与对应设置的重置模块13的一个实施例。
如图8所示，该重置模块13可以包括P型重置晶体管和反相器。
所述P型重置晶体管的第一电极连接高电平信号（VDD），所述P型重置晶体管的第二电极连接所述使能模块11的使能信号输出端，所述P型重置晶体管的栅极连接所述反相器的输出端，所述反相器的输入端连接时钟信号（CLKR）。
如图8所示，当时钟信号（CLKR）的高脉冲到来时，P型重置晶体管打开，对该行译码器的输出端充电，该行译码器的输出端被重置。
如图9所示，为本发明以重置模块13第二实施例的电路原理图。在该实施例中，是以P型晶体管组成的某一行译码器与对应设置的重置模块13的一个实施例。
如图9所示，该重置模块13包括N型重置晶体管，所述N型重置晶体管的第一电极连接所述使能模块11的使能信号输出端，所述N型重置晶体管的第二电极连接地信号（GND）。
如图9所示，当时钟信号（CLKR）的高脉冲到来时，N型重置晶体管打开，对该行译码器的输出端放电，该行译码器的输出端被重置。
这里，高电平信号（VDD）和时钟信号（CLKR）均可以由驱动IC提供。
参考图10，为本发明一种GOA电路第三实施例的结构示意图。
该实施例在实施例二的基础上，进一步地，每一个GOA单元10还包括稳压模块14，所述稳压模块14包括使能节点和稳压电容；
所述使能节点分别连接所述使能模块11的使能信号输出端和所述驱动模块12的使能信号输入端，所述稳压电容的第一端连接所述使能节点，所述稳压电容的第二端连接恒压高电位（VGH）、恒压低电位（VGL）或恒低电压（VGLL）中的任意一种。
这里恒压高电位（VGH）为直流高压信号，恒压低电位（VGL）为直流低压信号，而恒低电压（VGLL）为比VGL低一些的直流低压信号。
参考图11，为本发明驱动模块12第一实施例的电路原理图。
如图11所示，该实施例的驱动模块12包括：上拉P型晶体管和下拉N型晶体管。
所述上拉P型晶体管的第一电极连接上拉时钟信号（CLK），所述上拉P型晶体管的第二电极连接所述下拉N型晶体管的第一电极，所述上拉P型晶体管的栅极作为所述驱动模块12的使能信号输入端连接所述使能模块11的使能输出端；所述下拉N型晶体管的第二电极连接恒压低电位（VGL），所述下拉N型晶体管的栅极连接时钟信号（CLKR）；所述上拉P型晶体管的第二电极还作为所述驱动模块12的驱动信号输出端连接与所述驱动模块12对应设置的行的栅线。
其中，上拉P型晶体管为大迁移率大尺寸的晶体管，下拉N型晶体管为小尺寸的晶体管。
采用该实施例的驱动模块12晶体管数目较少，只有一个上拉P型晶体管需要占用大面积，且没有晶体管长期承受直流高压，可以有效延长GOA电路的寿命。
以下以图12对图11的工作原理进行说明。
如图12所示，CLK1~CLK4均可以由驱动IC提供，在屏幕开启显示后持续提供。S[0:N]表示输入行译码器的行地址信号。
具体的：
在时段t1：为地址译码阶段，行地址信号Dn对应的某一级GOA单元10中的行译码器被选中，该行的行译码器使能信号输出端（EN）输出的使能信号为低电平信号，该上拉P型晶体管打开。
在时段t2：上拉时钟信号（CLK）正脉冲到来，被选中行的上拉P型晶体管将该正脉冲导入输出端（OUT），在输出端（OUT）产生一个正脉冲，即屏幕中与该上拉P型晶体管的输出端对应连接的行所需要的扫描脉冲。
在时段t3：使能信号输出端（EN）仍为低电压，上拉P型晶体管仍处于打开状态，上拉时钟信号（CLK）电压回落，带动输出端（OUT）电压回落。
在时段t4：时钟信号（CLKR）的正脉冲到来，重置模块13开启，P型重置晶体管打开，将EN充电到VGH，使上拉P型晶体管关闭，此时上拉时钟信号（CLK）的后续脉冲无法馈通到输出端（OUT），下拉N型晶体管开启，将输出端（OUT）持续钳制在VGL低电压。
图13为图10的另一运行方式的时序波形示意图。
如图13所示，某一级GOA单元10中的行译码器被选中，该行的行译码器使能信号输出端（EN）放电到VGLL，该上拉P型晶体管打开。上拉时钟信号（CLK）的正脉冲到来时，上位P型晶体管将该正脉冲导入输出端（OUT），在输出端（OUT）产生一个正脉冲。上拉时钟信号（CLK）的正脉冲褪去，输出端（OUT）下降到低电位，时钟信号（CLKR）的正脉冲到来，将使能信号输出端（EN）重置为高电压，上拉P型晶体管关闭。
图13的运行方式与图12的运行方式相比，图13的运行方式中的行译码器和驱动模块12在同一个时间段内工作，行译码器在驱动模块12发生阶段持续开启，将使能输出端（EN）的电压保持在低电位，所以，稳压电容C的作用减少，可省略或减小面积。
其中，采用图11所示的多个驱动模块12的示意图如图14所示。由图14可以看出，驱动模块12包含在每一级GOA单元10中，和传统的GOA电路不同，每一级GOA单元10的输出只进入像素阵列，不进入之后或之前的任何一级GOA单元10。即本发明的任一级GOA单元10的工作都不依赖于前级或后级的GOA提供使能信号，而是由本级内部的行译码器来产生使能信号。
进一步地，该实施例的驱动模块12还可以包括：串联在所述上拉P型晶体管的第二电极与所述下拉N型晶体管的第一电极之间的第二P型晶体管。
其中，第二P型晶体管的第一电极与所述上拉P型晶体管的第二电极连接，所述第二P型晶体管的第二电极与所述下拉N型晶体管的第一电极连接，所述第二P型晶体管的栅极与所述下拉N型晶体管的栅极短接。
参考图15，为本发明驱动模块12第二实施例的电路原理图。
如图15所示，该实施例在第一实施例的基础上，进一步地，驱动模块12还可以包括：电压域转换放大器121和缓冲反相器122。
所述电压域转换放大器121的输入端与所述第二P型晶体管的第二电极和所述下拉N型晶体管的第一电极的连接节点连接，所述电压域转换放大器121的输出端连接所述缓冲反相器122的输入端，所述缓冲反相器122的输出端作为所述驱动模块12的驱动信号输出端连接与所述驱动模块12对应设置的行的栅线。
其中，电压域转换放大器121可以实现所接入的驱动信号进行放大处理，缓冲反相器122可以用于对所接入的驱动信号进行整形、同时增加驱动能力。
通过在驱动模块12中增加电压域转换放大器121和缓冲反相器122可以有效节省动态功耗。由于时钟和译码器都工作在低压域（VDD，VSS），时钟不需要驱动像素。高压域是直流输入，假设有N级GOA单元10，则非激活的（N-1）级GOA单元10的输出端不贡献动态负载，因此，可以有效节省动态功耗。
具体的，如图15所示，在该实施例中，电压域转换放大器121包括第一N型晶体管和第二N型晶体管。
所述第一N型晶体管的第一电极和栅极一并连接恒压高电位（VGH），所述第一N型晶体管的第二电极连接所述第二N型晶体管的第一电极，所述第二N型晶体管的第二电极连接恒压低电位（VGL），所述第二N型晶体管的栅极作为所述电压域转换放大器121的输入端连接所述第二P型晶体管的第二电极和所述下拉N型晶体管的第一电极的连接节点；所述第一N型晶体管的第二电极与所述第二N型晶体管的第一电极的连接节点为所述电压域转换放大器121的输出端。
缓冲反相器122，可以包括M个串联的反相模块；M为大于1的自然数。
每一个反相模块包括第一P型晶体管和第三N型晶体管，所述第一P型晶体管的第一电极连接恒压高电位（VGH），所述第上P型晶体管的第二电极和所述第三N型晶体管的第一电极连接，所述第三N型晶体管的第二电极连接恒压低电位（VGL）；每一个反相模块中的第一P型晶体管的栅极和第二N型晶体管的栅极短接的节点为反相模块的输入端，每一个反相模块中的第一P型晶体管的第二电极和第三N型晶体管的第一电极连接的节点为反相模块的输出端。
其中，第一个反相模块的输入端作为缓冲反相器122的输入端连接至所述电压域转换放大器121的输出端；第M个反相模块的输出端为所述缓冲反相器122的输出端。
可以理解地，反相模块的M可以根据实际设计需要逐级增加，以达到优化延时和驱动能力的目的。
如图16所示，为采用图15的电路的时序波形示意图。
在t1时段：行译码器进行地址译码，被选中行的EN降低。
在t2时段：上拉时钟信号（CLK）负脉冲到来，N1点电压产生正脉冲，缓冲反相器122陆续翻转，输出端（OUT）产生正脉冲。
在t3时段：空闲。
在t4时段：时钟信号（CLKR）负脉冲到来，重置模块13开启，EN点恢复高电压。
其中，采用图15所示的多个驱动模块12的示意图如图17所示。由图17可以看出，驱动模块12包含在每一级GOA单元10中，和传统的GOA电路不同，每一级GOA单元10的输出只进入像素阵列，不进入之后或之前的任何一级GOA单元10。即本发明的任一级GOA单元10的工作都不依赖于前级或后级的GOA提供使能信号，而是由本级内部的行译码器来产生使能信号。
参考图18，为本发明驱动模块12第三实施例的电路原理图。
如图18所示，该实施例与第二实施例区别在于，该实施例的驱动模块12中，驱动信号改为T触发器123产生。
具体的，如图18所示，该实施例的驱动模块12包括：驱动反相器和T触发器123。
所述驱动反相器的输入端作为所述驱动模块12的使能信号输入端连接所述使能模块11的使能输出端，所述驱动反相器的输出端连接所述T触发器123的输入信号输入端，所述T触发器123的时钟信号输入端连接上拉时钟信号（CLK），所述T触发器123的输出端输出驱动信号。如图18所示，T触发器123的输出端连接电压域转换放大器121的输入端（即第二N型晶体管的栅极）。
其中，T触发器123的输入信号输入端（T）输入的电压为高电压时，在每个CLK的上升沿将其输出端（Q）的信号翻转。如果Q的信号原来是低，则变为高；如果Q的信号原来是高，则变为低。当T端输入电压是低时，保持Q的输出不变。
通过采用该实施例可以有效节省动态功能，且能够有效遏制CLK噪声和译码器的输出毛刺对输出端（OUT）的影响。
图19是采用图18的电路的单级时序波形示意图。
如图19所示：
在t1时段：行译码器执行地址译码，被选中的行的EN降低，T触发器123开启。
在t2时段：在CLK的两个上升沿，T触发器123的Q端各发生一次翻转，产生一个正脉冲。该正脉冲经过缓冲反相器122后输出到屏幕内的像素阵列。
在t3时段：CLKR上升沿到来，重置模块13启动，EN恢复到高电压，T触发器123关闭。
在t4时段：由于T触发器123关闭，此后的CLK上升沿无法对其输出产生影响，故输出端（OUT）维持低电压。
图20是采用图18的电路的多个GOA单元10的示意图和时序波形示意图。
本发明实施例的方案，提供了一种支持随机寻址的GOA电路，该GOA电路允许数据不按照行的顺序写入屏幕，在屏幕大部分区域是静态图像，只有少部分区域不断变化时，只需要对该部分区域进行编程，且由于图像不变的行未选通，所以动态功耗有效降低，同时可以增加留给图像改变的每一行的时间，使得在显示尺寸和显示功率、显示刷新率之间可以实现实时、动态调整的可能。
另外，本发明的GOA电路中后级触发不依赖于前级的触发，所以当孤立一级GOA单元10出现缺陷时，其余GOA单元10的功能不会受到影响，使屏幕的和评级得到提升，提供了动态修理屏幕的可能。而且本发明的GOA电路不使用传统的自举结构，时钟线不需要直接驱动GOA单元10中的输出晶体管，因此，可以大大减少（N-1）级非活跃GOA单元10对动态功耗的影响。
本发明的GOA电路适用于高分辨率、大尺寸屏幕。
进一步地，本发明还提供了一种显示装置，该显示装置包括前述实施例的GOA电路。其中，该显示装置包括但不限于LTPS显示装置、AMOLED显示装置。
以上实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据此实施，并不能限制本发明的保护范围。凡跟本发明权利要求范围所做的均等变化与修饰，均应属于本发明权利要求的涵盖范围。
应当理解的是，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，而所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (17)

  1. 一种GOA电路，其特征在于，包括多个相互独立的GOA单元，每一个所述GOA单元包括一个使能模块以及与所述使能模块对应设置的驱动模块；
    所述使能模块包括用于接收行地址信号的行地址信号的输入端，以及用于根据所述行地址信号输出使能信号的使能信号输出端；
    所述驱动模块包括与所述使能模块的使能信号输出端连接、用于接收所述使能信号输出端输出的使能信号的使能信号输入端，以及用于根据所述使能信号输出驱动信号的驱动信号输出端，所述驱动信号输出端连接与所述驱动模块对应设置的行的栅线，以将所述驱动信号发送至所述对应行的栅线，选通所述对应行。
  2. 根据权利要求1所述的GOA电路，其特征在于，所述使能模块为基于格雷码编码的行译码器。
  3. 根据权利要求2所述的GOA电路，其特征在于，所述每一行译码器包括多个串联的晶体管，且相邻行、同一列的两个晶体管在满足预设条件时合并为一个晶体管。
  4. 根据权利要求3所述的GOA电路，其特征在于，所述相邻行、同一列的两个晶体管满足预设条件包括：
    两个晶体管的栅极短接在一起，且各自是本行译码器的最高位的晶体管，或者两个晶体管的栅极短接在一起，且紧邻前一高位的晶体管合并在一起。
  5. 根据权利要求1所述的GOA电路，其特征在于，每一个所述GOA单元还包括与所述使能模块的使能信号输出端连接、用于在所述驱动模块输出驱动信号后并将所述对应行选通后、将所述使能模块重置的重置模块。
  6. 根据权利要求5所述的GOA电路，其特征在于，所述重置模块包括P型重置晶体管和反相器；
    所述P型重置晶体管的第一电极连接高电平信号（VDD），所述P型重置晶体管的第二电极连接所述使能模块的使能信号输出端，所述P型重置晶体管的栅极连接所述反相器的输出端，所述反相器的输入端连接时钟信号（CLKR）。
  7. 根据权利要求5所述的GOA电路，其特征在于，所述重置模块包括N型重置晶体管，所述N型重置晶体管的第一电极连接所述使能模块的使能信号输出端，所述N型重置晶体管的第二电极连接地信号（GND）。
  8. 根据权利要求1所述的GOA电路，其特征在于，所述驱动模块包括：上拉P型晶体管和下拉N型晶体管；
    所述上拉P型晶体管的第一电极连接上拉时钟信号（CLK），所述上拉P型晶体管的第二电极连接所述下拉N型晶体管的第一电极，所述上拉P型晶体管的栅极作为所述驱动模块的使能信号输入端连接所述使能模块的使能输出端；
    所述下拉N型晶体管的第二电极连接恒压低电位（VGL），所述下拉N型晶体管的栅极连接时钟信号（CLKR）；
    所述上拉P型晶体管的第二电极还作为所述驱动模块的驱动信号输出端连接与所述驱动模块对应设置的行的栅线。
  9. 根据权利要求1所述的GOA电路，其特征在于，所述驱动模块包括：驱动反相器和T触发器；
    所述驱动反相器的输入端作为所述驱动模块的使能信号输入端连接所述使能模块的使能输出端，所述驱动反相器的输出端连接所述T触发器的输入信号输入端，所述T触发器的时钟信号输入端连接上拉时钟信号（CLK），所述T触发器的输出端驱动信号。
  10. 根据权利要求8所述的GOA电路，其特征在于，所述驱动模块还包括：串联在所述上拉P型晶体管的第二电极与所述下拉N型晶体管的第一电极之间的第二P型晶体管；
    所述第二P型晶体管的第一电极与所述上拉P型晶体管的第二电极连接，所述第二P型晶体管的第二电极与所述下拉N型晶体管的第一电极连接，所述第二P型晶体管的栅极与所述下拉N型晶体管的栅极短接。
  11. 根据权利要求10所述的GOA电路，其特征在于，所述驱动模块还包括：电压域转换放大器和缓冲反相器；
    所述电压域转换放大器的输入端与所述第二P型晶体管的第二电极和所述下拉N型晶体管的第一电极的连接节点连接，所述电压域转换放大器的输出端连接所述缓冲反相器的输入端，所述缓冲反相器的输出端作为所述驱动模块的驱动信号输出端连接与所述驱动模块对应设置的行的栅线。
  12. 根据权利要求11所述的GOA电路，其特征在于，所述电压域转换放大器包括第一N型晶体管和第二N型晶体管；
    所述第一N型晶体管的第一电极和栅极一并连接恒压高电位（VGH），所述第一N型晶体管的第二电极连接所述第二N型晶体管的第一电极，所述第二N型晶体管的第二电极连接恒压低电位（VGL），所述第二N型晶体管的栅极作为所述电压域转换放大器的输入端连接所述第二P型晶体管的第二电极和所述下拉N型晶体管的第一电极的连接节点；
    所述第一N型晶体管的第二电极与所述第二N型晶体管的第一电极的连接节点为所述电压域转换放大器的输出端。
  13. 根据权利要求12所述的GOA电路，其特征在于，所述缓冲反相器包括M个串联的反相模块；M为大于1的自然数；
    每一个反相模块包括第一P型晶体管和第三N型晶体管，所述第一P型晶体管的第一电极连接恒压高电位（VGH），所述第一P型晶体管的第二电极和所述第三N型晶体管的第一电极连接，所述第三N型晶体管的第二电极连接恒压低电位（VGL）；
    每一个反相模块中的第一P型晶体管的栅极和第三N型晶体管的栅极短接的节点为反相模块的输入端，每一个反相模块中的第一P型晶体管的第二电极和第三N型晶体管的第一电极连接的节点为反相模块的输出端；
    其中，第一个反相模块的输入端作为缓冲反相器的输入端连接至所述电压域转换放大器的输出端；第M个反相模块的输出端为所述缓冲反相器的输出端。
  14. 根据权利要求1所述的GOA电路，其特征在于，所述GOA单元还包括稳压模块，所述稳压模块包括使能节点和稳压电容；
    所述使能节点分别连接所述使能模块的使能信号输出端和所述驱动模块的使能信号输入端，所述稳压电容的第一端连接所述使能节点，所述稳压电容的第二端连接恒压高电位（VGH）、恒压低电位（VGL）和恒低电压（VGLL）中的任意一种。
  15. 根据权利要求1所述的GOA电路，其特征在于，每一个所述GOA单元中的P型晶体管是低温多晶硅、无定型硅、或者是由碳、硅、锗三种元素按任意比例混合的材料制作沟道的薄膜晶体管。
  16. 根据权利要求1所述的GOA电路，其特征在于，每一个所述GOA单元中的N型晶体管是基于金属氧化物制作沟道的薄膜晶体管。
  17. 一种显示装置，其特征在于，包括权利要求1-16任一项所述的GOA电路。
     
PCT/CN2018/109648 2018-10-10 2018-10-10 一种goa电路及显示装置 Ceased WO2020073231A1 (zh)

Priority Applications (8)

Application Number Priority Date Filing Date Title
CN201880096064.2A CN112703552A (zh) 2018-10-10 2018-10-10 一种goa电路及显示装置
PCT/CN2018/109648 WO2020073231A1 (zh) 2018-10-10 2018-10-10 一种goa电路及显示装置
CN201880095926.XA CN112639954A (zh) 2018-10-10 2018-12-10 一种goa电路、显示装置和显示器控制方法
CN201880095933.XA CN112639955A (zh) 2018-10-10 2018-12-10 一种goa电路、像素电路、显示装置、显示器的驱动方法
PCT/CN2018/120046 WO2020073471A1 (zh) 2018-10-10 2018-12-10 一种goa电路、显示装置和显示器控制方法
PCT/CN2018/120050 WO2020073472A1 (zh) 2018-10-10 2018-12-10 一种goa电路、像素电路、显示装置、显示器的驱动方法
US17/226,714 US11355046B2 (en) 2018-10-10 2021-04-09 GOA circuit supporting random addressing, display device, and method for controlling display
US17/226,846 US20220114968A1 (en) 2018-10-10 2021-04-09 Goa circuit, pixel circuit, display device and method for driving display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/109648 WO2020073231A1 (zh) 2018-10-10 2018-10-10 一种goa电路及显示装置

Publications (1)

Publication Number Publication Date
WO2020073231A1 true WO2020073231A1 (zh) 2020-04-16

Family

ID=70164132

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/CN2018/109648 Ceased WO2020073231A1 (zh) 2018-10-10 2018-10-10 一种goa电路及显示装置
PCT/CN2018/120050 Ceased WO2020073472A1 (zh) 2018-10-10 2018-12-10 一种goa电路、像素电路、显示装置、显示器的驱动方法
PCT/CN2018/120046 Ceased WO2020073471A1 (zh) 2018-10-10 2018-12-10 一种goa电路、显示装置和显示器控制方法

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/CN2018/120050 Ceased WO2020073472A1 (zh) 2018-10-10 2018-12-10 一种goa电路、像素电路、显示装置、显示器的驱动方法
PCT/CN2018/120046 Ceased WO2020073471A1 (zh) 2018-10-10 2018-12-10 一种goa电路、显示装置和显示器控制方法

Country Status (3)

Country Link
US (2) US11355046B2 (zh)
CN (3) CN112703552A (zh)
WO (3) WO2020073231A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883081A (zh) * 2020-07-28 2020-11-03 重庆惠科金渝光电科技有限公司 显示驱动电路及显示面板

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117334148A (zh) 2020-07-31 2024-01-02 京东方科技集团股份有限公司 显示面板及显示装置
CN112863452B (zh) * 2021-02-09 2021-11-23 河南省华锐光电产业有限公司 一种发光基板及其驱动方法、显示装置
CN114078415B (zh) * 2021-11-23 2023-12-12 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路、显示装置及其驱动方法
CN117174009B (zh) * 2022-05-27 2025-09-30 荣耀终端股份有限公司 一种屏幕驱动电路、屏幕刷新方法及电子设备
US11994888B2 (en) * 2022-07-18 2024-05-28 Nxp Usa, Inc. Power supply handling for multiple package configurations
CN116129789B (zh) * 2023-02-08 2026-01-27 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、显示面板
WO2026020264A1 (zh) * 2024-07-22 2026-01-29 京东方科技集团股份有限公司 显示基板和显示装置
WO2026044663A1 (zh) * 2024-08-30 2026-03-05 京东方科技集团股份有限公司 驱动电路、驱动方法、驱动模组和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09325320A (ja) * 1996-06-04 1997-12-16 Nec Kansai Ltd 半導体集積回路装置
JP2000163018A (ja) * 1998-11-26 2000-06-16 Nec Kansai Ltd 集積回路装置およびそれを用いた液晶表示装置
CN101034236A (zh) * 2006-03-06 2007-09-12 株式会社日立显示器 图像显示装置
CN101329832A (zh) * 2008-07-29 2008-12-24 友达光电股份有限公司 信号产生方法及应用其的显示装置与时钟脉冲控制器
CN101499242A (zh) * 2008-01-28 2009-08-05 联咏科技股份有限公司 行驱动装置、驱动装置及相关序列式传输电路装置
CN101577102A (zh) * 2008-05-08 2009-11-11 联咏科技股份有限公司 扫描驱动器
CN103366665A (zh) * 2013-02-22 2013-10-23 友达光电股份有限公司 位准移位电路及其驱动方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8728433D0 (en) * 1987-12-04 1988-01-13 Emi Plc Thorn Display device
JP3108626B2 (ja) * 1996-03-26 2000-11-13 シャープ株式会社 インバータブリッジのゲート駆動信号発生方法
KR100666317B1 (ko) * 1999-12-15 2007-01-09 삼성전자주식회사 구동 신호 인가시점 결정모듈, 이를 포함한 액정표시패널어셈블리 및 액정표시패널 어셈블리의 구동 방법
JP2004205725A (ja) * 2002-12-25 2004-07-22 Semiconductor Energy Lab Co Ltd 表示装置および電子機器
JP4390469B2 (ja) * 2003-03-26 2009-12-24 Ｎｅｃエレクトロニクス株式会社 画像表示装置、該画像表示装置に用いられる信号線駆動回路及び駆動方法
CN100389448C (zh) * 2004-05-21 2008-05-21 联咏科技股份有限公司 串行协议式面板显示系统与显示方法
US7529333B2 (en) * 2005-10-27 2009-05-05 Lg Display Co., Ltd. Shift register
TW200807369A (en) * 2006-07-28 2008-02-01 Innolux Display Corp Driving system of liquid crystal display device
TWI364022B (en) * 2007-04-24 2012-05-11 Raydium Semiconductor Corp Scan driver
CN100505029C (zh) * 2007-04-28 2009-06-24 深圳安凯微电子技术有限公司 一种lcd数据写入控制方法及先入先出存储器
CN101303837B (zh) * 2007-05-11 2010-09-15 瑞鼎科技股份有限公司 扫描驱动器
TWI386903B (zh) * 2008-05-05 2013-02-21 Novatek Microelectronics Corp 掃描驅動器
JP2009276460A (ja) * 2008-05-13 2009-11-26 Sony Corp 表示装置
CN102629459A (zh) * 2011-10-26 2012-08-08 北京京东方光电科技有限公司 栅线驱动方法、移位寄存器及栅线驱动装置
CN202473187U (zh) * 2012-02-29 2012-10-03 四川虹视显示技术有限公司 一种显示屏行扫描驱动平台
CN103730147B (zh) * 2012-10-10 2016-05-04 旺宏电子股份有限公司 动态驱动器电路及其操作方法
CN103730094B (zh) * 2013-12-30 2016-02-24 深圳市华星光电技术有限公司 Goa电路结构
CN104901666B (zh) * 2015-05-20 2017-11-24 广州金升阳科技有限公司 一种igbt驱动保护电路、应用该电路的驱动芯片及该芯片的保护电路
CN104835452B (zh) * 2015-05-28 2017-04-19 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
TWI626640B (zh) * 2015-08-26 2018-06-11 矽創電子股份有限公司 閘極驅動電路與電泳顯示器
CN105321492B (zh) * 2015-11-18 2017-06-27 武汉华星光电技术有限公司 栅极驱动基板和使用栅极驱动基板的液晶显示器
CN105355179B (zh) * 2015-12-03 2018-03-02 武汉华星光电技术有限公司 一种扫描驱动电路及其显示装置
CN207398851U (zh) * 2016-08-19 2018-05-22 深圳市柔宇科技有限公司 充电器、电子装置及充电系统
US10490130B2 (en) * 2017-02-10 2019-11-26 Semiconductor Energy Laboratory Co., Ltd. Display system comprising controller which process data
CN106898319B (zh) * 2017-02-20 2019-02-26 武汉华星光电技术有限公司 一种goa电路及液晶显示面板
CN106652963B (zh) * 2017-03-09 2020-01-17 南京迈智芯微光电科技有限公司 一种数模融合驱动的硅基显示器
CN207301963U (zh) * 2017-08-28 2018-05-01 珠海格力电器股份有限公司 一种复位检测电路
TWI664618B (zh) * 2017-11-13 2019-07-01 友達光電股份有限公司 閘極驅動器及其觸控顯示裝置
CN108010498A (zh) * 2017-11-28 2018-05-08 武汉华星光电技术有限公司 一种goa电路及液晶面板、显示装置
CN108447436B (zh) * 2018-03-30 2019-08-09 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09325320A (ja) * 1996-06-04 1997-12-16 Nec Kansai Ltd 半導体集積回路装置
JP2000163018A (ja) * 1998-11-26 2000-06-16 Nec Kansai Ltd 集積回路装置およびそれを用いた液晶表示装置
CN101034236A (zh) * 2006-03-06 2007-09-12 株式会社日立显示器 图像显示装置
CN101499242A (zh) * 2008-01-28 2009-08-05 联咏科技股份有限公司 行驱动装置、驱动装置及相关序列式传输电路装置
CN101577102A (zh) * 2008-05-08 2009-11-11 联咏科技股份有限公司 扫描驱动器
CN101329832A (zh) * 2008-07-29 2008-12-24 友达光电股份有限公司 信号产生方法及应用其的显示装置与时钟脉冲控制器
CN103366665A (zh) * 2013-02-22 2013-10-23 友达光电股份有限公司 位准移位电路及其驱动方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883081A (zh) * 2020-07-28 2020-11-03 重庆惠科金渝光电科技有限公司 显示驱动电路及显示面板
US11308913B2 (en) 2020-07-28 2022-04-19 Chongqing Hkc Optoelectronics Technology Co., Ltd. Display driving circuit and display panel

Also Published As

Publication number Publication date
CN112639954A (zh) 2021-04-09
CN112703552A (zh) 2021-04-23
US20210225243A1 (en) 2021-07-22
CN112639955A (zh) 2021-04-09
WO2020073472A1 (zh) 2020-04-16
US11355046B2 (en) 2022-06-07
WO2020073471A1 (zh) 2020-04-16
US20220114968A1 (en) 2022-04-14

Similar Documents

Publication Publication Date Title
WO2020073231A1 (zh) 一种goa电路及显示装置
CN109427310B (zh) 移位寄存器单元、驱动装置、显示装置以及驱动方法
JP2024105456A (ja) シフトレジスタユニットおよびその駆動方法、ゲート駆動回路および表示装置
JP4990034B2 (ja) シフトレジスタ回路およびそれを備える画像表示装置
CN100583297C (zh) 移位寄存器电路和具备该电路的图像显示装置
JP2626451B2 (ja) 液晶表示装置の駆動方法
TWI409748B (zh) 輸出緩衝器及使用該輸出緩衝器的源極驅動器
CN1254915C (zh) 自举电路、缓冲器电路和有源矩阵显示器
US11626050B2 (en) GOA circuit and display panel
CN115331644B (zh) 栅极驱动电路及其驱动方法、显示装置
US6433768B1 (en) Liquid crystal display device having a gray-scale voltage producing circuit
CN104361852A (zh) 移位寄存器、栅极驱动电路及显示装置
WO2016078141A1 (zh) 一种移位寄存器单元、栅极驱动电路及显示装置
WO2016078143A1 (zh) 一种移位寄存器单元、栅极驱动电路及显示装置
CN114038437B (zh) 移位寄存器单元、栅极驱动电路及显示装置
JP2002014322A (ja) ドット反転式アクティブマトリックス液晶表示器
CN111276177B (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN101026011A (zh) 移位寄存器电路及设有该电路的图像显示装置
JP2001255857A (ja) 駆動回路
US10482834B2 (en) Pixel circuit, display device, display apparatus and driving method
TW584753B (en) Liquid crystal drive circuit
JP2011150256A (ja) 駆動回路及び駆動方法
CN115985266A (zh) 栅极驱动电路、显示面板和显示装置
JP2007207411A (ja) シフトレジスタ回路およびそれを備える画像表示装置
CN111477194B (zh) 公共电压输出电路、显示装置及公共电压补偿方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18936371

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18936371

Country of ref document: EP

Kind code of ref document: A1