WO2020063342A1 - Transistor à couches minces et son procédé de fabrication, substrat de réseau, panneau d'affichage, et capteur - Google Patents

Transistor à couches minces et son procédé de fabrication, substrat de réseau, panneau d'affichage, et capteur Download PDF

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WO2020063342A1
WO2020063342A1 PCT/CN2019/105284 CN2019105284W WO2020063342A1 WO 2020063342 A1 WO2020063342 A1 WO 2020063342A1 CN 2019105284 W CN2019105284 W CN 2019105284W WO 2020063342 A1 WO2020063342 A1 WO 2020063342A1
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layer
base substrate
gate
source
drain
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PCT/CN2019/105284
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English (en)
Chinese (zh)
Inventor
贵炳强
曲连杰
齐永莲
赵合彬
邱云
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/650,484 priority Critical patent/US11670702B2/en
Publication of WO2020063342A1 publication Critical patent/WO2020063342A1/fr

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Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof, an array substrate, a display device, and a sensor.
  • a display panel generally includes a plurality of pixel units, and each pixel unit is provided with a thin film transistor (Thin Film Transistor, TFT).
  • TFT is a basic circuit element that controls the display brightness of a pixel unit.
  • the TFT may include a buffer layer, an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode that are stacked on a base substrate.
  • the source and drain include a source and a drain, and the active layer provides a conductive channel for the source and the drain.
  • the buffer layer is usually made of silicon nitride (SiN x ) or silicon oxide (SiO 2 ).
  • a-Si amorphous silicon
  • the active layer may be made of a metal oxide material such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the active layer is a polycrystalline silicon (P-Si) layer, and the polycrystalline silicon layer is obtained by crystallizing an amorphous silicon.
  • Embodiments of the present disclosure provide a thin film transistor and a manufacturing method thereof, an array substrate, a display device, and a sensor.
  • the technical solution is as follows:
  • a thin film transistor including: a highly textured dielectric layer, an active layer, a gate, and a source / drain disposed on a substrate;
  • the active layer is located on a side of the high-texture dielectric layer away from the base substrate;
  • the gate is insulated from the active layer, and the source and drain include a source and a drain , The source electrode and the drain electrode are electrically connected to the active layer, respectively;
  • the active layer is a semiconductor film layer including a single crystal silicon-like material.
  • the crystal orientation index of the constituent particles of the high-texture dielectric layer is the same as the crystal orientation index of the single crystal silicon.
  • the preparation material of the high-texture dielectric layer includes any one of magnesium oxide, cerium oxide, or yttrium-doped zirconia.
  • the gate is located on a side of the active layer away from the base substrate, and the source and drain are located on a side of the gate away from the base substrate.
  • the thin film transistor further includes a first gate insulating layer and a second gate insulating layer;
  • the first gate insulating layer is located between the active layer and the gate, and the second gate insulating layer is located between the gate and the source and drain.
  • the gate is located on a side of the high-texture dielectric layer close to the base substrate, and the source and drain are located on a side of the active layer remote from the base substrate.
  • the thin film transistor further includes a first gate insulating layer; the first gate insulating layer is located between the high-texture dielectric layer and the gate.
  • a method for manufacturing a thin film transistor includes:
  • a gate and a source and drain are formed on the base substrate, the source and drain include a source and a drain, the gate is insulated from the active layer, and the source and the drain are respectively And is electrically connected to the active layer.
  • the method further includes:
  • the amorphous silicon layer is subjected to a dehydrogenation treatment.
  • the forming an amorphous silicon layer on the base substrate on which the high-textured dielectric layer is formed includes:
  • An amorphous silicon material is deposited on a side of the high-textured dielectric layer remote from the base substrate to form the amorphous silicon layer.
  • the crystallization processing the amorphous silicon layer includes:
  • the amorphous silicon layer is crystallized by an excimer laser annealing process.
  • the forming a highly textured dielectric layer on the base substrate includes:
  • the highly textured dielectric layer is formed on the base substrate by an electron beam evaporation process or an ion beam deposition process.
  • the forming a gate and a source / drain on the base substrate includes:
  • a gate and a source / drain are sequentially formed on the base substrate on which the active layer is formed.
  • the method further includes: on the base substrate on which the active layer is formed Forming a first gate insulating layer thereon;
  • the method further includes:
  • a second gate insulating layer is formed on a base substrate on which the gate is formed.
  • the forming a gate and a source / drain on a base substrate on which the active layer is formed includes:
  • a source and a drain are formed on a base substrate on which the active layer is formed.
  • the crystal orientation index of the constituent particles of the high-texture dielectric layer is the same as the crystal orientation index of the single crystal silicon.
  • the preparation material of the high-texture dielectric layer includes any one of magnesium oxide, cerium oxide, or yttrium-doped zirconia.
  • an array substrate including: a base substrate and the thin film transistor according to any one of the above aspects provided on the base substrate.
  • a display device including the array substrate according to the above aspect.
  • the display device is a liquid crystal display, an organic light emitting diode display, or a quantum dot light emitting diode display.
  • a sensor including: the array substrate according to the above aspect; the sensor is a photoelectric sensor, a pressure sensor, or a fingerprint sensor.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 3 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 4 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of forming a highly textured dielectric layer according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of forming an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of performing a dehydrogenation treatment on an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of performing crystallization treatment on an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 9 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • the performance of the LTPS TFT in the related art is poor.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present disclosure. As shown in FIG. 1, the thin film transistor 10 includes:
  • a highly textured dielectric layer 101, an active layer 102, a gate 103, and a source / drain 104 are provided on the base substrate 00.
  • the active layer 102 is located on a side of the high-textured dielectric layer 101 away from the base substrate 00, that is, the active layer 102 is formed on the high-textured dielectric layer 101.
  • the gate 103 is insulated from the active layer 102.
  • the source and drain 104 include a source 1041 and a drain 1042, and the source 1041 and the drain 1042 are electrically connected to the active layer 102, respectively.
  • the active layer is a semiconductor film layer including a single crystal-like silicon structure material.
  • the active layer may be a semiconductor film layer composed of a single-crystal-like silicon structure material.
  • the orientation of the crystal grains is high and the size uniformity of the crystal grains is high, that is, the semiconductor film layer including the single-crystal-like silicon structural material is highly textured.
  • highly textured refers to the high consistency of the crystal orientation index in the crystal, and the crystal orientation index can also be referred to as the lattice orientation.
  • the thin film transistor provided in the embodiments of the present disclosure by forming an active layer on a base substrate on which a highly textured dielectric layer is formed, the uniformity of the crystal orientation index of the constituent particles of the highly textured dielectric layer Higher, can induce the active layer to grow into a single crystal silicon-like structure.
  • the thin film transistor provided by the embodiment of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with the LTPS TFT in the related art. .
  • single-crystal silicon-like structures have higher carrier mobility, thereby improving the performance of thin film transistors.
  • the thin film transistor 10 may be a thin film transistor with a top-gate structure.
  • the gate 103 may be located on a side of the active layer 102 away from the base substrate 00, and the source and drain 104 may be located on a side of the gate 103 away from the base substrate 00.
  • the thin film transistor 10 may further include a first gate insulating layer 105 and a second gate insulating layer 106.
  • the first gate insulating layer 105 is located between the active layer 102 and the gate 103
  • the second gate insulating layer 106 is located between the gate 103 and the source and drain 104.
  • the source 1041 and the drain 1042 are connected to the active layer 102 through via holes provided in the second gate insulating layer 106, respectively.
  • the thin film transistor 10 may be a thin film transistor with a bottom gate structure.
  • the gate electrode 103 may be located on a side of the highly textured dielectric layer 101 near the base substrate 00, and the source and drain electrodes 104 may be located on a side of the active layer 102 away from the base substrate 00.
  • the thin film transistor 10 may further include a first gate insulating layer 105.
  • the first gate insulating layer 105 is located between the gate 103 and the highly textured dielectric layer 101.
  • the crystal orientation index of the constituent particles of the highly textured dielectric layer is the same as the crystal orientation index of the single crystal silicon.
  • the crystal orientation index of the single crystal silicon can be (111), and then a particle with a crystal orientation index (111) can be used to form a highly textured dielectric layer on the substrate.
  • the crystal orientation index of the single crystal silicon may be (100), and the fine grained crystal orientation index (100) may also be used to form a highly textured dielectric layer on the substrate.
  • the high-texture dielectric layer can substantially function as a buffer layer and an induction template layer, and the induction template layer is used to induce the constituent particles of the active layer to crystallize with a specified crystal orientation index when growing.
  • the preparation material of the high-texture dielectric layer includes any one of magnesium oxide (MgO), cerium oxide (CeO 2 ) or yttrium-doped zirconia (YS-ZrO 2 ).
  • the material for preparing the electrical layer may also be other materials, which are not limited in the embodiments of the present disclosure.
  • the thin film transistor provided in the embodiments of the present disclosure by forming an active layer on a base substrate on which a highly textured dielectric layer is formed, the uniformity of the crystal orientation index of the constituent particles of the highly textured dielectric layer Higher, can induce the active layer to grow into a single crystal silicon-like structure.
  • the thin film transistor provided by the embodiment of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with the LTPS TFT in the related art. .
  • single-crystal silicon-like structures have higher carrier mobility, thereby improving the performance of thin film transistors.
  • FIG. 3 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. This manufacturing method can be used for manufacturing the thin film transistor provided in the above embodiments. As shown in Figure 3, the method includes the following working processes:
  • Step 201 Provide a base substrate.
  • Step 202 Form a highly textured dielectric layer on the base substrate.
  • Step 203 An amorphous silicon layer is formed on the base substrate on which the highly textured dielectric layer is formed.
  • Step 204 Crystallize the amorphous silicon layer to convert the amorphous silicon layer into a semiconductor film layer composed of a single-crystal silicon-like material to form an active layer.
  • Step 205 Form a gate and a source and a drain on the base substrate.
  • the source and the drain include the source and the drain.
  • the gate is insulated from the active layer, and the source and the drain are electrically connected to the active layer respectively.
  • step 205 can be performed after step 204, or the step of forming a gate in step 205 is also It may be performed before step 204, for example, it may be performed between step 201 and step 202.
  • an amorphous silicon layer is formed on a base substrate on which a highly textured dielectric layer is formed.
  • the uniformity of the orientation index is high.
  • the highly textured dielectric layer can induce the constituent particles of the amorphous silicon layer toward the crystal orientation of the constituent particles of the highly textured dielectric layer. Crystallize in the same direction, that is, induce the constituent particles of the amorphous silicon layer to change from an amorphous silicon structure to a single-crystal silicon-like structure to generate an active layer.
  • the thin film transistor provided by the embodiments of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with LTPS TFTs in the related art.
  • single-crystal silicon-like structures have higher carrier mobility, thereby improving the performance of thin film transistors.
  • FIG. 4 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • This manufacturing method can be used to manufacture, for example, a thin-film transistor with a top-gate structure as shown in FIG. 1.
  • the method includes the following working processes:
  • Step 301 Provide a base substrate.
  • the base substrate may be made of a material such as glass, silicon wafer, quartz, or plastic.
  • the embodiment of the present disclosure does not limit the material of the base substrate.
  • Step 302 Form a highly textured dielectric layer on the base substrate.
  • a highly textured dielectric layer 101 may be formed by depositing a highly textured dielectric material on the base substrate 00.
  • a highly textured dielectric layer is formed on a substrate by an electron beam evaporation process or an ion beam deposition process.
  • a highly textured dielectric layer can also be formed on the substrate by magnetron sputtering or plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the crystal orientation index of the constituent particles of the highly textured dielectric layer is the same as the crystal orientation index of the single crystal silicon.
  • the crystal orientation index of the single crystal silicon can be (111), and then a particle with a crystal orientation index (111) can be used to form a highly textured dielectric layer on the substrate.
  • the crystal orientation index of the single crystal silicon may be (100), and the fine grained crystal orientation index (100) may also be used to form a highly textured dielectric layer on the substrate.
  • the high-texture dielectric layer can substantially function as a buffer layer and an induction template layer, and the induction template layer is used to induce the constituent particles of the active layer to crystallize with a specified crystal orientation index when growing.
  • the preparation material of the high-texture dielectric layer includes any one of magnesium oxide, cerium oxide, or yttrium-doped zirconia.
  • the preparation material of the high-texture dielectric layer may also be other materials. The present disclosure The embodiment does not limit this.
  • Step 303 An amorphous silicon layer is formed on the base substrate on which the highly textured dielectric layer is formed.
  • an amorphous silicon material may be deposited on a side of the highly textured dielectric layer 101 away from the base substrate 00 to form an amorphous silicon layer 102 a.
  • Step 304 Dehydrogenate the amorphous silicon layer.
  • the amorphous silicon layer 102 a may be dehydrogenated (H) treated to prevent the amorphous silicon layer 102 a from appearing during crystallization
  • H dehydrogenated
  • Step 305 Crystallize the amorphous silicon layer after the dehydrogenation treatment, so that the amorphous silicon layer is converted into a semiconductor film layer composed of a single-crystal silicon-like structural material to form an active layer.
  • the amorphous silicon layer 102 a may be crystallized by an excimer laser annealing (ELA) process.
  • ELA excimer laser annealing
  • the highly textured dielectric layer can induce the amorphous silicon layer.
  • Step 306 Form a first gate insulating layer on the base substrate on which the active layer is formed.
  • a method such as magnetron sputtering, thermal evaporation, or PECVD may be used to deposit an insulating material with a certain thickness on the substrate substrate on which the active layer is formed to obtain a first insulating material layer. Then, the first insulating material layer is processed by a patterning process to obtain a first gate insulating layer.
  • the insulating material may be silicon nitride (SiN X ), silicon dioxide (SiO 2 ), or an organic insulating material.
  • the thickness of the first gate insulating layer may be determined according to actual needs.
  • Step 307 Form a gate on the base substrate on which the first gate insulating layer is formed.
  • a method such as magnetron sputtering, thermal evaporation, or PECVD can be used to deposit a gate metal material with a certain thickness on the substrate substrate on which the first gate insulating layer is formed to obtain a gate metal material layer. Then, the gate metal material layer is processed by a patterning process to obtain a gate.
  • the gate metal material may be metal molybdenum (Mo), metal copper (Cu), metal aluminum (Al), or an alloy material of the foregoing metal materials.
  • the thickness of the gate can be determined according to actual needs.
  • the first gate insulation layer is used to isolate and isolate the active layer from the gate.
  • the orthographic projection of the first gate insulating layer on the base substrate may cover the orthographic projection of the gate on the base substrate.
  • the orthographic projection of the first gate insulating layer on the base substrate and the orthographic projection of the gate on the base substrate may coincide.
  • the first gate insulating layer and the gate can be formed by a patterning process.
  • the formation process may include: sequentially forming a first insulating material layer and a gate metal material layer on a base substrate on which an active layer is formed; and performing a first patterning process on the first insulating material layer and the gate metal material layer. The process obtains a first gate insulating layer and a gate.
  • the first gate insulating layer and the gate are formed by a single patterning process, compared with an implementation method in which the first gate insulating layer and the gate are separately formed by using a patterning process, at least one patterning process can be reduced to simplify the thin film transistor manufacturing process And manufacturing costs.
  • Step 308 Form a second gate insulating layer on the base substrate on which the gate is formed.
  • a method such as magnetron sputtering, thermal evaporation, or PECVD may be used to deposit a second insulating material with a certain thickness on the substrate substrate on which the gate is formed, to obtain a second insulating material layer, and then use a patterning process to The second insulating material layer is processed to obtain a second gate insulating layer, and a plurality of via holes are formed on the second gate insulating layer to ensure effective contact between the active layer and the source and the active layer and the drain.
  • a method such as magnetron sputtering, thermal evaporation, or PECVD may be used to deposit a second insulating material with a certain thickness on the substrate substrate on which the gate is formed, to obtain a second insulating material layer, and then use a patterning process to The second insulating material layer is processed to obtain a second gate insulating layer, and a plurality of via holes are formed on the second gate insulating layer to ensure effective contact between the active layer and the source and the
  • the second insulating material may be silicon nitride, silicon dioxide, or an organic insulating material.
  • the second insulating material may be the same as or different from the first insulating material, which is not limited in the embodiments of the present disclosure.
  • Step 309 Form a source and a drain on the base substrate on which the second gate insulating layer is formed.
  • the source-drain metal thin film layer can be obtained by depositing source and drain metal materials with a certain thickness on the base substrate on which the second gate insulating layer is formed by using methods such as magnetron sputtering, thermal evaporation, or PECVD. Then, the source-drain metal thin film layer is processed by a patterning process to obtain a source-drain.
  • the source and drain electrodes include a source electrode and a drain electrode, and the source electrode and the drain electrode can be connected to the active layer through vias on the second gate insulating layer, respectively.
  • the source / drain metal material may be metal Mo, metal Cu, metal Al, or an alloy material of the foregoing metal materials.
  • the thickness of the source and drain can be determined according to actual needs.
  • the orthographic projection of the active layer on the base substrate and the orthographic projection of the gate on the base substrate may have non-overlapping areas
  • the orthographic projection of the source layer on the base substrate and the orthographic projection of the first gate insulating layer on the base substrate may have non-overlapping areas, so that a via is provided on the second gate insulating layer above the non-overlapping area, so that The source and drain can be connected to the active layer through the vias, respectively.
  • FIG. 9 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present disclosure. This manufacturing method can be used for manufacturing a thin-film transistor having a bottom-gate structure as shown in FIG. 2. As shown in Figure 9, the method includes the following working processes:
  • Step 401 Provide a base substrate.
  • Step 402 Form a gate on the base substrate.
  • Step 403 Form a first gate insulating layer on the base substrate on which the gate is formed.
  • Step 404 Form a highly textured dielectric layer on the base substrate on which the first gate insulating layer is formed.
  • Step 405 An amorphous silicon layer is formed on the base substrate on which the highly textured dielectric layer is formed.
  • Step 406 Dehydrogenate the amorphous silicon layer.
  • Step 407 Crystallize the amorphous silicon layer after the dehydrogenation treatment, so that the amorphous silicon layer is converted into a semiconductor film layer composed of a single-crystal silicon-like structural material to form an active layer.
  • Step 408 Form a source and a drain on the base substrate on which the active layer is formed.
  • an amorphous silicon layer is formed on a base substrate on which a highly textured dielectric layer is formed.
  • the uniformity of the orientation index is high.
  • the highly textured dielectric layer can induce the constituent particles of the amorphous silicon layer toward the crystal orientation of the constituent particles of the highly textured dielectric layer. Crystallize in the same direction, that is, induce the constituent particles of the amorphous silicon layer to change from an amorphous silicon structure to a single-crystal silicon-like structure to generate an active layer.
  • the thin film transistor provided by the embodiments of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with LTPS TFTs in the related art.
  • single-crystal silicon-like structures have higher carrier mobility, thereby improving the performance of thin film transistors.
  • the equipment and process parameters used in the process of preparing the thin film transistor can refer to the LTPS TFT, so the compatibility with the existing processes and equipment is higher and the Production achievability.
  • the array substrate may include a base substrate 00 and a thin film transistor provided on the base substrate 00 according to the foregoing embodiment.
  • the array substrate provided by the embodiment of the present disclosure may be applied to a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display or sensor.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • QLED quantum dot light emitting diode
  • the array substrate when the array substrate is used for a liquid crystal display, the array substrate may include a base substrate, and a thin film transistor, a flat layer, an electrode layer (a common electrode layer or a pixel electrode layer), and an alignment layer disposed on the base substrate.
  • the array substrate when the array substrate is used for an OLED display or a QLED display, the array substrate may include a base substrate, and a thin film transistor, a first electrode, a pixel defining layer, a light emitting layer, and a second electrode disposed on the base substrate.
  • An electrode and a second electrode are one of an anode and a cathode, respectively.
  • the thin film transistor of the array substrate by forming an active layer on a base substrate on which a highly textured dielectric layer is formed, since the highly textured dielectric layer The uniformity of the crystal orientation index of the constituent particles is relatively high, which can induce the active layer to grow into a single crystal silicon-like structure.
  • the single crystal-like silicon structure has smaller grain boundary defects compared to polysilicon, the thin film transistor provided by the embodiment of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with the LTPS TFT in the related art.
  • the structure of single-crystal silicon has higher carrier mobility, which improves the performance of the thin film transistor, and further improves the performance of the array substrate.
  • An embodiment of the present disclosure provides a display device including the above array substrate.
  • the display device may be a liquid crystal display, an OLED display, or a QLED display.
  • the display device may be a product or component having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
  • the thin film transistor of the display device by forming an active layer on a base substrate on which a highly textured dielectric layer is formed, since the highly textured dielectric layer The uniformity of the crystal orientation index of the constituent particles is relatively high, which can induce the active layer to grow into a single crystal silicon-like structure.
  • the single crystal-like silicon structure has smaller grain boundary defects compared to polysilicon, the thin film transistor provided by the embodiment of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with the LTPS TFT in the related art.
  • the structure of single-crystal silicon has higher carrier mobility, which further improves the performance of the thin film transistor, thereby improving the display performance of the display device.
  • An embodiment of the present disclosure further provides a sensor.
  • the sensor may include the foregoing array substrate.
  • the sensor may be a photoelectric sensor, a pressure sensor, or a fingerprint sensor.
  • the photoelectric sensor may be an X-ray sensor or the like.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un transistor à couches minces et son procédé de fabrication, un substrat de réseau, un dispositif d'affichage, et un capteur, relevant du domaine technique de l'affichage. Le transistor à couches minces comprend : une couche diélectrique hautement texturée (101), une couche active (102), une électrode de grille (103), et une électrode de source et de drain (104) qui sont empilées sur un substrat de base (00), l'électrode de source et de drain (104) comprenant une électrode de source (1041) et une électrode de drain (1042), l'électrode de grille (103) étant isolée de la couche active (102), et l'électrode de source (1041) et l'électrode de drain (1042) étant électriquement connectées à la couche active (102) ; des particules formant la couche active (102) ont une structure de type silicium monocristallin. La couche tampon d'origine est remplacée par la couche diélectrique hautement texturée (101), de manière à entraîner la croissance de la couche active (102) dans une structure de type silicium monocristallin, ce qui permet d'améliorer les performances du transistor à couches minces.
PCT/CN2019/105284 2018-09-25 2019-09-11 Transistor à couches minces et son procédé de fabrication, substrat de réseau, panneau d'affichage, et capteur WO2020063342A1 (fr)

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