WO2020063342A1 - 薄膜晶体管及其制造方法、阵列基板、显示装置及传感器 - Google Patents

薄膜晶体管及其制造方法、阵列基板、显示装置及传感器 Download PDF

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WO2020063342A1
WO2020063342A1 PCT/CN2019/105284 CN2019105284W WO2020063342A1 WO 2020063342 A1 WO2020063342 A1 WO 2020063342A1 CN 2019105284 W CN2019105284 W CN 2019105284W WO 2020063342 A1 WO2020063342 A1 WO 2020063342A1
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layer
base substrate
gate
source
drain
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PCT/CN2019/105284
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English (en)
French (fr)
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贵炳强
曲连杰
齐永莲
赵合彬
邱云
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/650,484 priority Critical patent/US11670702B2/en
Publication of WO2020063342A1 publication Critical patent/WO2020063342A1/zh

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Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof, an array substrate, a display device, and a sensor.
  • a display panel generally includes a plurality of pixel units, and each pixel unit is provided with a thin film transistor (Thin Film Transistor, TFT).
  • TFT is a basic circuit element that controls the display brightness of a pixel unit.
  • the TFT may include a buffer layer, an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode that are stacked on a base substrate.
  • the source and drain include a source and a drain, and the active layer provides a conductive channel for the source and the drain.
  • the buffer layer is usually made of silicon nitride (SiN x ) or silicon oxide (SiO 2 ).
  • a-Si amorphous silicon
  • the active layer may be made of a metal oxide material such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the active layer is a polycrystalline silicon (P-Si) layer, and the polycrystalline silicon layer is obtained by crystallizing an amorphous silicon.
  • Embodiments of the present disclosure provide a thin film transistor and a manufacturing method thereof, an array substrate, a display device, and a sensor.
  • the technical solution is as follows:
  • a thin film transistor including: a highly textured dielectric layer, an active layer, a gate, and a source / drain disposed on a substrate;
  • the active layer is located on a side of the high-texture dielectric layer away from the base substrate;
  • the gate is insulated from the active layer, and the source and drain include a source and a drain , The source electrode and the drain electrode are electrically connected to the active layer, respectively;
  • the active layer is a semiconductor film layer including a single crystal silicon-like material.
  • the crystal orientation index of the constituent particles of the high-texture dielectric layer is the same as the crystal orientation index of the single crystal silicon.
  • the preparation material of the high-texture dielectric layer includes any one of magnesium oxide, cerium oxide, or yttrium-doped zirconia.
  • the gate is located on a side of the active layer away from the base substrate, and the source and drain are located on a side of the gate away from the base substrate.
  • the thin film transistor further includes a first gate insulating layer and a second gate insulating layer;
  • the first gate insulating layer is located between the active layer and the gate, and the second gate insulating layer is located between the gate and the source and drain.
  • the gate is located on a side of the high-texture dielectric layer close to the base substrate, and the source and drain are located on a side of the active layer remote from the base substrate.
  • the thin film transistor further includes a first gate insulating layer; the first gate insulating layer is located between the high-texture dielectric layer and the gate.
  • a method for manufacturing a thin film transistor includes:
  • a gate and a source and drain are formed on the base substrate, the source and drain include a source and a drain, the gate is insulated from the active layer, and the source and the drain are respectively And is electrically connected to the active layer.
  • the method further includes:
  • the amorphous silicon layer is subjected to a dehydrogenation treatment.
  • the forming an amorphous silicon layer on the base substrate on which the high-textured dielectric layer is formed includes:
  • An amorphous silicon material is deposited on a side of the high-textured dielectric layer remote from the base substrate to form the amorphous silicon layer.
  • the crystallization processing the amorphous silicon layer includes:
  • the amorphous silicon layer is crystallized by an excimer laser annealing process.
  • the forming a highly textured dielectric layer on the base substrate includes:
  • the highly textured dielectric layer is formed on the base substrate by an electron beam evaporation process or an ion beam deposition process.
  • the forming a gate and a source / drain on the base substrate includes:
  • a gate and a source / drain are sequentially formed on the base substrate on which the active layer is formed.
  • the method further includes: on the base substrate on which the active layer is formed Forming a first gate insulating layer thereon;
  • the method further includes:
  • a second gate insulating layer is formed on a base substrate on which the gate is formed.
  • the forming a gate and a source / drain on a base substrate on which the active layer is formed includes:
  • a source and a drain are formed on a base substrate on which the active layer is formed.
  • the crystal orientation index of the constituent particles of the high-texture dielectric layer is the same as the crystal orientation index of the single crystal silicon.
  • the preparation material of the high-texture dielectric layer includes any one of magnesium oxide, cerium oxide, or yttrium-doped zirconia.
  • an array substrate including: a base substrate and the thin film transistor according to any one of the above aspects provided on the base substrate.
  • a display device including the array substrate according to the above aspect.
  • the display device is a liquid crystal display, an organic light emitting diode display, or a quantum dot light emitting diode display.
  • a sensor including: the array substrate according to the above aspect; the sensor is a photoelectric sensor, a pressure sensor, or a fingerprint sensor.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 3 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 4 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of forming a highly textured dielectric layer according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of forming an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of performing a dehydrogenation treatment on an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of performing crystallization treatment on an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 9 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • the performance of the LTPS TFT in the related art is poor.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present disclosure. As shown in FIG. 1, the thin film transistor 10 includes:
  • a highly textured dielectric layer 101, an active layer 102, a gate 103, and a source / drain 104 are provided on the base substrate 00.
  • the active layer 102 is located on a side of the high-textured dielectric layer 101 away from the base substrate 00, that is, the active layer 102 is formed on the high-textured dielectric layer 101.
  • the gate 103 is insulated from the active layer 102.
  • the source and drain 104 include a source 1041 and a drain 1042, and the source 1041 and the drain 1042 are electrically connected to the active layer 102, respectively.
  • the active layer is a semiconductor film layer including a single crystal-like silicon structure material.
  • the active layer may be a semiconductor film layer composed of a single-crystal-like silicon structure material.
  • the orientation of the crystal grains is high and the size uniformity of the crystal grains is high, that is, the semiconductor film layer including the single-crystal-like silicon structural material is highly textured.
  • highly textured refers to the high consistency of the crystal orientation index in the crystal, and the crystal orientation index can also be referred to as the lattice orientation.
  • the thin film transistor provided in the embodiments of the present disclosure by forming an active layer on a base substrate on which a highly textured dielectric layer is formed, the uniformity of the crystal orientation index of the constituent particles of the highly textured dielectric layer Higher, can induce the active layer to grow into a single crystal silicon-like structure.
  • the thin film transistor provided by the embodiment of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with the LTPS TFT in the related art. .
  • single-crystal silicon-like structures have higher carrier mobility, thereby improving the performance of thin film transistors.
  • the thin film transistor 10 may be a thin film transistor with a top-gate structure.
  • the gate 103 may be located on a side of the active layer 102 away from the base substrate 00, and the source and drain 104 may be located on a side of the gate 103 away from the base substrate 00.
  • the thin film transistor 10 may further include a first gate insulating layer 105 and a second gate insulating layer 106.
  • the first gate insulating layer 105 is located between the active layer 102 and the gate 103
  • the second gate insulating layer 106 is located between the gate 103 and the source and drain 104.
  • the source 1041 and the drain 1042 are connected to the active layer 102 through via holes provided in the second gate insulating layer 106, respectively.
  • the thin film transistor 10 may be a thin film transistor with a bottom gate structure.
  • the gate electrode 103 may be located on a side of the highly textured dielectric layer 101 near the base substrate 00, and the source and drain electrodes 104 may be located on a side of the active layer 102 away from the base substrate 00.
  • the thin film transistor 10 may further include a first gate insulating layer 105.
  • the first gate insulating layer 105 is located between the gate 103 and the highly textured dielectric layer 101.
  • the crystal orientation index of the constituent particles of the highly textured dielectric layer is the same as the crystal orientation index of the single crystal silicon.
  • the crystal orientation index of the single crystal silicon can be (111), and then a particle with a crystal orientation index (111) can be used to form a highly textured dielectric layer on the substrate.
  • the crystal orientation index of the single crystal silicon may be (100), and the fine grained crystal orientation index (100) may also be used to form a highly textured dielectric layer on the substrate.
  • the high-texture dielectric layer can substantially function as a buffer layer and an induction template layer, and the induction template layer is used to induce the constituent particles of the active layer to crystallize with a specified crystal orientation index when growing.
  • the preparation material of the high-texture dielectric layer includes any one of magnesium oxide (MgO), cerium oxide (CeO 2 ) or yttrium-doped zirconia (YS-ZrO 2 ).
  • the material for preparing the electrical layer may also be other materials, which are not limited in the embodiments of the present disclosure.
  • the thin film transistor provided in the embodiments of the present disclosure by forming an active layer on a base substrate on which a highly textured dielectric layer is formed, the uniformity of the crystal orientation index of the constituent particles of the highly textured dielectric layer Higher, can induce the active layer to grow into a single crystal silicon-like structure.
  • the thin film transistor provided by the embodiment of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with the LTPS TFT in the related art. .
  • single-crystal silicon-like structures have higher carrier mobility, thereby improving the performance of thin film transistors.
  • FIG. 3 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. This manufacturing method can be used for manufacturing the thin film transistor provided in the above embodiments. As shown in Figure 3, the method includes the following working processes:
  • Step 201 Provide a base substrate.
  • Step 202 Form a highly textured dielectric layer on the base substrate.
  • Step 203 An amorphous silicon layer is formed on the base substrate on which the highly textured dielectric layer is formed.
  • Step 204 Crystallize the amorphous silicon layer to convert the amorphous silicon layer into a semiconductor film layer composed of a single-crystal silicon-like material to form an active layer.
  • Step 205 Form a gate and a source and a drain on the base substrate.
  • the source and the drain include the source and the drain.
  • the gate is insulated from the active layer, and the source and the drain are electrically connected to the active layer respectively.
  • step 205 can be performed after step 204, or the step of forming a gate in step 205 is also It may be performed before step 204, for example, it may be performed between step 201 and step 202.
  • an amorphous silicon layer is formed on a base substrate on which a highly textured dielectric layer is formed.
  • the uniformity of the orientation index is high.
  • the highly textured dielectric layer can induce the constituent particles of the amorphous silicon layer toward the crystal orientation of the constituent particles of the highly textured dielectric layer. Crystallize in the same direction, that is, induce the constituent particles of the amorphous silicon layer to change from an amorphous silicon structure to a single-crystal silicon-like structure to generate an active layer.
  • the thin film transistor provided by the embodiments of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with LTPS TFTs in the related art.
  • single-crystal silicon-like structures have higher carrier mobility, thereby improving the performance of thin film transistors.
  • FIG. 4 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • This manufacturing method can be used to manufacture, for example, a thin-film transistor with a top-gate structure as shown in FIG. 1.
  • the method includes the following working processes:
  • Step 301 Provide a base substrate.
  • the base substrate may be made of a material such as glass, silicon wafer, quartz, or plastic.
  • the embodiment of the present disclosure does not limit the material of the base substrate.
  • Step 302 Form a highly textured dielectric layer on the base substrate.
  • a highly textured dielectric layer 101 may be formed by depositing a highly textured dielectric material on the base substrate 00.
  • a highly textured dielectric layer is formed on a substrate by an electron beam evaporation process or an ion beam deposition process.
  • a highly textured dielectric layer can also be formed on the substrate by magnetron sputtering or plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the crystal orientation index of the constituent particles of the highly textured dielectric layer is the same as the crystal orientation index of the single crystal silicon.
  • the crystal orientation index of the single crystal silicon can be (111), and then a particle with a crystal orientation index (111) can be used to form a highly textured dielectric layer on the substrate.
  • the crystal orientation index of the single crystal silicon may be (100), and the fine grained crystal orientation index (100) may also be used to form a highly textured dielectric layer on the substrate.
  • the high-texture dielectric layer can substantially function as a buffer layer and an induction template layer, and the induction template layer is used to induce the constituent particles of the active layer to crystallize with a specified crystal orientation index when growing.
  • the preparation material of the high-texture dielectric layer includes any one of magnesium oxide, cerium oxide, or yttrium-doped zirconia.
  • the preparation material of the high-texture dielectric layer may also be other materials. The present disclosure The embodiment does not limit this.
  • Step 303 An amorphous silicon layer is formed on the base substrate on which the highly textured dielectric layer is formed.
  • an amorphous silicon material may be deposited on a side of the highly textured dielectric layer 101 away from the base substrate 00 to form an amorphous silicon layer 102 a.
  • Step 304 Dehydrogenate the amorphous silicon layer.
  • the amorphous silicon layer 102 a may be dehydrogenated (H) treated to prevent the amorphous silicon layer 102 a from appearing during crystallization
  • H dehydrogenated
  • Step 305 Crystallize the amorphous silicon layer after the dehydrogenation treatment, so that the amorphous silicon layer is converted into a semiconductor film layer composed of a single-crystal silicon-like structural material to form an active layer.
  • the amorphous silicon layer 102 a may be crystallized by an excimer laser annealing (ELA) process.
  • ELA excimer laser annealing
  • the highly textured dielectric layer can induce the amorphous silicon layer.
  • Step 306 Form a first gate insulating layer on the base substrate on which the active layer is formed.
  • a method such as magnetron sputtering, thermal evaporation, or PECVD may be used to deposit an insulating material with a certain thickness on the substrate substrate on which the active layer is formed to obtain a first insulating material layer. Then, the first insulating material layer is processed by a patterning process to obtain a first gate insulating layer.
  • the insulating material may be silicon nitride (SiN X ), silicon dioxide (SiO 2 ), or an organic insulating material.
  • the thickness of the first gate insulating layer may be determined according to actual needs.
  • Step 307 Form a gate on the base substrate on which the first gate insulating layer is formed.
  • a method such as magnetron sputtering, thermal evaporation, or PECVD can be used to deposit a gate metal material with a certain thickness on the substrate substrate on which the first gate insulating layer is formed to obtain a gate metal material layer. Then, the gate metal material layer is processed by a patterning process to obtain a gate.
  • the gate metal material may be metal molybdenum (Mo), metal copper (Cu), metal aluminum (Al), or an alloy material of the foregoing metal materials.
  • the thickness of the gate can be determined according to actual needs.
  • the first gate insulation layer is used to isolate and isolate the active layer from the gate.
  • the orthographic projection of the first gate insulating layer on the base substrate may cover the orthographic projection of the gate on the base substrate.
  • the orthographic projection of the first gate insulating layer on the base substrate and the orthographic projection of the gate on the base substrate may coincide.
  • the first gate insulating layer and the gate can be formed by a patterning process.
  • the formation process may include: sequentially forming a first insulating material layer and a gate metal material layer on a base substrate on which an active layer is formed; and performing a first patterning process on the first insulating material layer and the gate metal material layer. The process obtains a first gate insulating layer and a gate.
  • the first gate insulating layer and the gate are formed by a single patterning process, compared with an implementation method in which the first gate insulating layer and the gate are separately formed by using a patterning process, at least one patterning process can be reduced to simplify the thin film transistor manufacturing process And manufacturing costs.
  • Step 308 Form a second gate insulating layer on the base substrate on which the gate is formed.
  • a method such as magnetron sputtering, thermal evaporation, or PECVD may be used to deposit a second insulating material with a certain thickness on the substrate substrate on which the gate is formed, to obtain a second insulating material layer, and then use a patterning process to The second insulating material layer is processed to obtain a second gate insulating layer, and a plurality of via holes are formed on the second gate insulating layer to ensure effective contact between the active layer and the source and the active layer and the drain.
  • a method such as magnetron sputtering, thermal evaporation, or PECVD may be used to deposit a second insulating material with a certain thickness on the substrate substrate on which the gate is formed, to obtain a second insulating material layer, and then use a patterning process to The second insulating material layer is processed to obtain a second gate insulating layer, and a plurality of via holes are formed on the second gate insulating layer to ensure effective contact between the active layer and the source and the
  • the second insulating material may be silicon nitride, silicon dioxide, or an organic insulating material.
  • the second insulating material may be the same as or different from the first insulating material, which is not limited in the embodiments of the present disclosure.
  • Step 309 Form a source and a drain on the base substrate on which the second gate insulating layer is formed.
  • the source-drain metal thin film layer can be obtained by depositing source and drain metal materials with a certain thickness on the base substrate on which the second gate insulating layer is formed by using methods such as magnetron sputtering, thermal evaporation, or PECVD. Then, the source-drain metal thin film layer is processed by a patterning process to obtain a source-drain.
  • the source and drain electrodes include a source electrode and a drain electrode, and the source electrode and the drain electrode can be connected to the active layer through vias on the second gate insulating layer, respectively.
  • the source / drain metal material may be metal Mo, metal Cu, metal Al, or an alloy material of the foregoing metal materials.
  • the thickness of the source and drain can be determined according to actual needs.
  • the orthographic projection of the active layer on the base substrate and the orthographic projection of the gate on the base substrate may have non-overlapping areas
  • the orthographic projection of the source layer on the base substrate and the orthographic projection of the first gate insulating layer on the base substrate may have non-overlapping areas, so that a via is provided on the second gate insulating layer above the non-overlapping area, so that The source and drain can be connected to the active layer through the vias, respectively.
  • FIG. 9 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present disclosure. This manufacturing method can be used for manufacturing a thin-film transistor having a bottom-gate structure as shown in FIG. 2. As shown in Figure 9, the method includes the following working processes:
  • Step 401 Provide a base substrate.
  • Step 402 Form a gate on the base substrate.
  • Step 403 Form a first gate insulating layer on the base substrate on which the gate is formed.
  • Step 404 Form a highly textured dielectric layer on the base substrate on which the first gate insulating layer is formed.
  • Step 405 An amorphous silicon layer is formed on the base substrate on which the highly textured dielectric layer is formed.
  • Step 406 Dehydrogenate the amorphous silicon layer.
  • Step 407 Crystallize the amorphous silicon layer after the dehydrogenation treatment, so that the amorphous silicon layer is converted into a semiconductor film layer composed of a single-crystal silicon-like structural material to form an active layer.
  • Step 408 Form a source and a drain on the base substrate on which the active layer is formed.
  • an amorphous silicon layer is formed on a base substrate on which a highly textured dielectric layer is formed.
  • the uniformity of the orientation index is high.
  • the highly textured dielectric layer can induce the constituent particles of the amorphous silicon layer toward the crystal orientation of the constituent particles of the highly textured dielectric layer. Crystallize in the same direction, that is, induce the constituent particles of the amorphous silicon layer to change from an amorphous silicon structure to a single-crystal silicon-like structure to generate an active layer.
  • the thin film transistor provided by the embodiments of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with LTPS TFTs in the related art.
  • single-crystal silicon-like structures have higher carrier mobility, thereby improving the performance of thin film transistors.
  • the equipment and process parameters used in the process of preparing the thin film transistor can refer to the LTPS TFT, so the compatibility with the existing processes and equipment is higher and the Production achievability.
  • the array substrate may include a base substrate 00 and a thin film transistor provided on the base substrate 00 according to the foregoing embodiment.
  • the array substrate provided by the embodiment of the present disclosure may be applied to a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display or sensor.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • QLED quantum dot light emitting diode
  • the array substrate when the array substrate is used for a liquid crystal display, the array substrate may include a base substrate, and a thin film transistor, a flat layer, an electrode layer (a common electrode layer or a pixel electrode layer), and an alignment layer disposed on the base substrate.
  • the array substrate when the array substrate is used for an OLED display or a QLED display, the array substrate may include a base substrate, and a thin film transistor, a first electrode, a pixel defining layer, a light emitting layer, and a second electrode disposed on the base substrate.
  • An electrode and a second electrode are one of an anode and a cathode, respectively.
  • the thin film transistor of the array substrate by forming an active layer on a base substrate on which a highly textured dielectric layer is formed, since the highly textured dielectric layer The uniformity of the crystal orientation index of the constituent particles is relatively high, which can induce the active layer to grow into a single crystal silicon-like structure.
  • the single crystal-like silicon structure has smaller grain boundary defects compared to polysilicon, the thin film transistor provided by the embodiment of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with the LTPS TFT in the related art.
  • the structure of single-crystal silicon has higher carrier mobility, which improves the performance of the thin film transistor, and further improves the performance of the array substrate.
  • An embodiment of the present disclosure provides a display device including the above array substrate.
  • the display device may be a liquid crystal display, an OLED display, or a QLED display.
  • the display device may be a product or component having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
  • the thin film transistor of the display device by forming an active layer on a base substrate on which a highly textured dielectric layer is formed, since the highly textured dielectric layer The uniformity of the crystal orientation index of the constituent particles is relatively high, which can induce the active layer to grow into a single crystal silicon-like structure.
  • the single crystal-like silicon structure has smaller grain boundary defects compared to polysilicon, the thin film transistor provided by the embodiment of the present disclosure can alleviate the problem of large leakage current due to grain boundary defects compared with the LTPS TFT in the related art.
  • the structure of single-crystal silicon has higher carrier mobility, which further improves the performance of the thin film transistor, thereby improving the display performance of the display device.
  • An embodiment of the present disclosure further provides a sensor.
  • the sensor may include the foregoing array substrate.
  • the sensor may be a photoelectric sensor, a pressure sensor, or a fingerprint sensor.
  • the photoelectric sensor may be an X-ray sensor or the like.

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Abstract

提供了一种薄膜晶体管及其制造方法、阵列基板、显示装置及传感器，属于显示技术领域。包括：层叠设置在衬底基板（00）上的高织构介电层（101）、有源层（102）、栅极（103）和源漏极（104），所述源漏极（104）包括源极（1041）和漏极（1042），所述栅极（103）与所述有源层（102）绝缘设置，所述源极（1041）和所述漏极（1042）分别与所述有源层（102）电连接；其中，所述有源层（102）的组成微粒为类单晶硅结构。采用高织构介电层（101）替代原有的缓冲层，以诱导有源层（102）生长成类单晶硅结构，从而提高了薄膜晶体管的性能。

Description

薄膜晶体管及其制造方法、阵列基板、显示装置及传感器
本申请要求于2018年09月25日提交的申请号为201811119902.1、发明名称为“薄膜晶体管及其制造方法、阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种薄膜晶体管及其制造方法、阵列基板、显示装置及传感器。
背景技术
显示面板通常包括多个像素单元，每个像素单元中均设置有薄膜晶体管(Thin Film Transistor，TFT)。TFT是控制像素单元显示亮度的基本电路元件。TFT可以包括：层叠设置在衬底基板上的缓冲层、有源层、栅极绝缘层、栅电极和源漏极等。该源漏极包括源极和漏极，有源层为源极和漏极提供导电通道。其中，缓冲层通常由氮化硅(SiN x)或氧化硅(SiO 2)制备得到，传统的非晶硅(Amorphous silicone，a-Si)TFT中，有源层为非晶硅层。
随着显示技术的快速发展，对显示产品的性能要求越来越高。传统的a-Si TFT无法满足显示产品的需求，因此相关技术中提供了氧化物(oxide)TFT和低温多晶硅(Low Temperature Poly-silicon，LTPS)TFT。氧化物TFT中，有源层可以由铟镓锌氧化物(indium gallium zinc oxide，IGZO)等金属氧化物材料制成。LTPS TFT中，有源层为多晶硅(polycrystalline silicon，P-Si)层，该多晶硅层由对非晶硅进行晶化处理得到。
发明内容
本公开实施例提供了一种薄膜晶体管及其制造方法、阵列基板、显示装置及传感器。所述技术方案如下：
一方面，提供了一种薄膜晶体管，包括：设置在衬底基板上的高织构介电层、有源层、栅极和源漏极；
其中，所述有源层位于所述高织构介电层远离所述衬底基板的一侧；所述栅极与所述有源层绝缘设置，所述源漏极包括源极和漏极，所述源极和所述漏极分别与所述有源层电连接；
所述有源层为包括类单晶硅结构材料的半导体膜层。
可选的，所述高织构介电层的组成微粒的晶向指数与单晶硅的晶向指数相同。
可选的，所述高织构介电层的制备材料包括氧化镁、氧化铈或掺杂有钇的氧化锆中的任意一种。
可选的，所述栅极位于所述有源层远离所述衬底基板的一侧，所述源漏极位于所述栅极远离所述衬底基板的一侧。
可选的，所述薄膜晶体管还包括第一栅绝缘层和第二栅绝缘层；
所述第一栅绝缘层位于所述有源层和所述栅极之间，所述第二栅绝缘层位于所述栅极和所述源漏极之间。
可选的，所述栅极位于所述高织构介电层靠近所述衬底基板的一侧，所述源漏极位于所述有源层远离所述衬底基板的一侧。
可选的，所述薄膜晶体管还包括第一栅绝缘层；所述第一栅绝缘层位于所述所述高织构介电层和所述栅极之间。
另一方面，提供了一种薄膜晶体管的制造方法，所述方法包括：
提供一衬底基板；
在所述衬底基板上形成高织构介电层；
在形成有所述高织构介电层的衬底基板上形成非晶硅层；
对所述非晶硅层进行晶化处理，使所述非晶硅层转换为由类单晶硅结构材料组成的半导体膜层，以形成有源层；
在所述衬底基板上形成栅极和源漏极，所述源漏极包括源极和漏极，所述栅极与所述有源层绝缘设置，所述源极和所述漏极分别与所述有源层电连接。
可选的，在对所述非晶硅层进行晶化处理之前，所述方法还包括：
对所述非晶硅层进行脱氢处理。
可选的，所述在形成有所述高织构介电层的衬底基板上形成非晶硅层，包括：
在所述高织构介电层远离所述衬底基板的一面上沉积非晶硅材料，以形成 所述非晶硅层。
可选的，所述对所述非晶硅层进行晶化处理，包括：
通过准分子激光退火工艺对所述非晶硅层进行晶化处理。
可选的，所述在所述衬底基板上形成高织构介电层，包括：
通过电子束蒸发工艺或离子束沉积工艺在所述衬底基板上形成所述高织构介电层。
可选的，所述在所述衬底基板上形成栅极和源漏极，包括：
在形成有所述有源层的衬底基板上依次形成栅极和源漏极。
可选的，在形成所述有源层之后，且在形成有所述有源层的衬底基板上形成栅极之前，所述方法还包括：在形成有所述有源层的衬底基板上形成第一栅绝缘层；
在形成所述栅极之后，且在形成所述源漏极之前，所述方法还包括：
在形成有所述栅极的衬底基板上形成第二栅绝缘层。
可选的，所述在形成有所述有源层的衬底基板上形成栅极和源漏极，包括：
在形成所述高织构介电层之前，在所述衬底基板上形成栅极；
在形成所述有源层之后，在形成有所述有源层的衬底基板上形成源漏极。
可选的，所述高织构介电层的组成微粒的晶向指数与单晶硅的晶向指数相同。
可选的，所述高织构介电层的制备材料包括氧化镁、氧化铈或掺杂有钇的氧化锆中的任意一种。
又一方面，提供了一种阵列基板，包括：衬底基板以及设置在所述衬底基板上的如上述方面任一所述的薄膜晶体管。
再一方面，提供了一种显示装置，包括：如上述方面所述的阵列基板。所述显示装置为液晶显示器、有机发光二极管显示器或量子点发光二极管显示器。
再一方面，提供了一种传感器，包括：如上述方面所述的阵列基板；所述传感器为光电传感器、压力传感器或指纹传感器。
附图说明
图1是本公开实施例提供的一种薄膜晶体管的结构示意图；
图2是本公开实施例提供的另一种薄膜晶体管的结构示意图；
图3是本公开实施例提供的一种薄膜晶体管的制造方法的流程图；
图4是本公开实施例提供的另一种薄膜晶体管的制造方法的流程图；
图5是本公开实施例提供的一种形成高织构介电层的示意图；
图6是本公开实施例提供的一种形成非晶硅层的示意图；
图7是本公开实施例提供的一种对非晶硅层进行脱氢处理的示意图；
图8是本公开实施例提供的一种对非晶硅层进行晶化处理的示意图；
图9是本公开实施例提供的又一种薄膜晶体管的制造方法的流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
相关技术中的LTPS TFT中，由于有源层中的多晶硅存在晶界缺陷的问题，会导致漏电流较大，影响TFT的性能，因此相关技术中的LTPS TFT的性能较差。
图1是本公开实施例提供的一种薄膜晶体管的结构示意图。如图1所示，薄膜晶体管10包括：
设置在衬底基板00上的高织构介电层101、有源层102、栅极103和源漏极104。其中，该有源层102位于该高织构介电层101远离衬底基板00的一侧，即该有源层102形成于高织构介电层101上。该栅极103与有源层102绝缘设置，源漏极104包括源极1041和漏极1042，源极1041和漏极1042分别与有源层102电连接。
其中，有源层为包括类单晶硅结构材料的半导体膜层，例如，该有源层可以为由类单晶硅结构材料组成的半导体膜层。该包括类单晶硅结构材料的半导体膜层中，晶粒的取向一致性高且晶粒的尺寸均匀性高，也即是，该包括类单晶硅结构材料的半导体膜层是高织构的半导体膜层。
需要说明的是，高织构(Highly textured)指晶体中晶向指数的一致性高，晶向指数也可称为晶格取向。
综上所述，本公开实施例提供的薄膜晶体管，通过在形成有高织构介电层的衬底基板上形成有源层，由于高织构介电层的组成微粒的晶向指数一致度较高，能够诱导有源层生长成类单晶硅结构。又由于类单晶硅结构与多晶硅相比， 晶界缺陷较小，因此与相关技术中的LTPS TFT相比，本公开实施例提供的薄膜晶体管可以减轻由于晶界缺陷导致漏电流较大的问题。另外，类单晶硅结构相较于多晶硅，其载流子迁移率较高，进而提升了薄膜晶体管的性能。
作为一种可选的实现方式，该薄膜晶体管10可以为顶栅结构的薄膜晶体管。相应的，参见图1，栅极103可以位于有源层102远离衬底基板00的一侧，源漏极104可以位于该栅极103远离衬底基板00的一侧。
继续参考图1，该薄膜晶体管10还可以包括第一栅绝缘层105和第二栅绝缘层106。第一栅绝缘层105位于有源层102和栅极103之间，第二栅绝缘层106位于栅极103和源漏极104之间。源极1041和漏极1042分别通过该第二栅绝缘层106中设置的过孔与有源层102连接。
作为另一种可选的实现方式，该薄膜晶体管10可以为底栅结构的薄膜晶体管。相应的，参见图2，栅极103可以位于高织构介电层101靠近衬底基板00的一侧，源漏极104可以位于该有源层102远离衬底基板00的一侧。
继续参考图2，该薄膜晶体管10还可以包括第一栅绝缘层105。该第一栅绝缘层105位于栅极103和高织构介电层101之间。
可选的，高织构介电层的组成微粒的晶向指数与单晶硅的晶向指数相同。例如，单晶硅的晶向指数可以为(111)，则可以采用晶向指数为(111)的微粒在衬底基板上形成高织构介电层。又例如，单晶硅的晶向指数可以为(100)，则也可以采用晶向指数为(100)的微粒在衬底基板上形成高织构介电层。在本公开实施例中，该高织构介电层实质上可起到缓冲层和诱导模板层的作用，该诱导模板层用于诱导有源层的组成微粒生长时以指定晶向指数结晶。
可选的，高织构介电层的制备材料包括氧化镁(MgO)、氧化铈(CeO 2)或掺杂有钇的氧化锆(YS-ZrO 2)中的任意一种，高织构介电层的制备材料还可以为其他材料，本公开实施例对此不做限定。
综上所述，本公开实施例提供的薄膜晶体管，通过在形成有高织构介电层的衬底基板上形成有源层，由于高织构介电层的组成微粒的晶向指数一致度较高，能够诱导有源层生长成类单晶硅结构。又由于类单晶硅结构与多晶硅相比，晶界缺陷较小，因此与相关技术中的LTPS TFT相比，本公开实施例提供的薄膜晶体管可以减轻由于晶界缺陷导致漏电流较大的问题。另外，类单晶硅结构相较于多晶硅，其载流子迁移率较高，进而提升了薄膜晶体管的性能。
图3是本公开实施例提供的一种薄膜晶体管的制造方法的流程图。该制造方法可以用于制造上述实施例提供的薄膜晶体管。如图3所示，该方法包括以下工作过程：
步骤201、提供一衬底基板。
步骤202、在衬底基板上形成高织构介电层。
步骤203、在形成有高织构介电层的衬底基板上形成非晶硅层。
步骤204、对非晶硅层进行晶化处理，使非晶硅层转换为由类单晶硅结构材料组成的半导体膜层，以形成有源层。
步骤205、在衬底基板上形成栅极和源漏极，源漏极包括源极和漏极，栅极与有源层绝缘设置，源极和漏极分别与有源层电连接。
需要说明的是，上述薄膜晶体管的制造方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减，例如步骤205可以在步骤204之后执行，或者步骤205中形成栅极的步骤也可以在步骤204之前执行，例如可以在步骤201和步骤202之间执行。
综上所述，本公开实施例提供的薄膜晶体管的制造方法，通过在形成有高织构介电层的衬底基板上形成非晶硅层，由于高织构介电层的组成微粒的晶向指数一致度较高，在对非晶硅层进行晶化处理的过程中，高织构介电层能够诱导非晶硅层的组成微粒朝与高织构介电层的组成微粒的晶向指数相同的方向结晶，即诱导非晶硅层的组成微粒从非晶硅结构转换为类单晶硅结构，以生成有源层。由于类单晶硅结构与多晶硅相比，晶界缺陷较小，因此与相关技术中的LTPS TFT相比，本公开实施例提供的薄膜晶体管可以减轻由于晶界缺陷导致漏电流较大的问题。另外，类单晶硅结构相较于多晶硅，其载流子迁移率较高，进而提升了薄膜晶体管的性能。
图4是本公开实施例提供的另一种薄膜晶体管的制造方法的流程图。该制造方法可以用于制造例如图1所示的顶栅结构的薄膜晶体管。如图4所示，该方法包括以下工作过程：
步骤301、提供一衬底基板。
可选的，衬底基板可以由玻璃、硅片、石英或塑料等材料制成，本公开实 施例对衬底基板的材质不做限定。
步骤302、在衬底基板上形成高织构介电层。
可选的，如图5所示，可以通过在衬底基板00上沉积高织构的介电材料以形成高织构介电层101。例如，通过电子束蒸发工艺或离子束沉积工艺在衬底基板上形成高织构介电层。或者，也可以通过磁控溅射或等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)在衬底基板上形成高织构介电层，本公开实施例对高织构介电层的制备工艺不做限定。
可选的，高织构介电层的组成微粒的晶向指数与单晶硅的晶向指数相同。例如，单晶硅的晶向指数可以为(111)，则可以采用晶向指数为(111)的微粒在衬底基板上形成高织构介电层。又例如，单晶硅的晶向指数可以为(100)，则也可以采用晶向指数为(100)的微粒在衬底基板上形成高织构介电层。
在本公开实施例中，该高织构介电层实质上可起到缓冲层和诱导模板层的作用，该诱导模板层用于诱导有源层的组成微粒生长时以指定晶向指数结晶。
可选的，高织构介电层的制备材料包括氧化镁、氧化铈或掺杂有钇的氧化锆中的任意一种，高织构介电层的制备材料还可以为其他材料，本公开实施例对此不做限定。
步骤303、在形成有高织构介电层的衬底基板上形成非晶硅层。
可选的，如图6所示，可以在高织构介电层101远离衬底基板00的一面上沉积非晶硅材料，以形成非晶硅层102a。
步骤304、对非晶硅层进行脱氢处理。
需要说明的是，参考图7，在对非晶硅层102a进行晶化处理之前，可以对非晶硅层102a进行脱氢(H)处理，以防止非晶硅层102a在晶化过程中出现氢爆的问题，避免对器件造成损伤。
步骤305、对经过脱氢处理后的非晶硅层进行晶化处理，使非晶硅层转换为由类单晶硅结构材料组成的半导体膜层，以形成有源层。
可选的，参考图8，可以通过准分子激光退火(excimer laser annealing，ELA)工艺对非晶硅层102a进行晶化处理，本公开实施例对采用的晶化工艺不做限定。
需要说明的是，由于高织构介电层的组成微粒的晶向指数一致度较高，在对非晶硅层进行晶化处理的过程中，高织构介电层能够诱导非晶硅层的组成微粒朝与高织构介电层的组成微粒的晶向指数相同的方向结晶，即诱导非晶硅层 的组成微粒从非晶硅结构转换为类单晶硅结构，以形成有源层。
步骤306、在形成有有源层的衬底基板上形成第一栅绝缘层。
可选的，可以采用磁控溅射、热蒸发或者PECVD等方法在形成有有源层的衬底基板上，沉积具有一定厚度的绝缘材料，得到第一绝缘材质层。然后通过构图工艺对第一绝缘材质层进行处理得到第一栅绝缘层。其中，绝缘材料可以为氮化硅(SiN X)、二氧化硅(SiO 2)或有机绝缘材料等。第一栅绝缘层的厚度可以根据实际需要确定。
步骤307、在形成有第一栅绝缘层的衬底基板上形成栅极。
可选的，可以采用磁控溅射、热蒸发或者PECVD等方法，在形成有第一栅绝缘层的衬底基板上沉积具有一定厚度的栅极金属材料，得到栅极金属材质层。然后通过构图工艺对栅极金属材质层进行处理得到栅极。其中，栅极金属材料可以为金属钼(Mo)、金属铜(Cu)、金属铝(Al)或上述金属材料的合金材料。栅极的厚度可以根据实际需要确定。
需要说明的是，第一栅绝缘层用于将有源层与栅极进行绝缘隔离。并且，为了保证有源层与栅极的有效绝缘，第一栅绝缘层在衬底基板上的正投影可以覆盖栅极在衬底基板上的正投影。
例如，第一栅绝缘层在衬底基板上的正投影与栅极在衬底基板上的正投影可以重合。此时，可以采用一次构图工艺形成该第一栅绝缘层和该栅极。其形成过程可以包括：在形成有有源层的衬底基板上依次形成第一绝缘材质层和栅极金属材质层；通过一次构图工艺对该第一绝缘材质层和该栅极金属材质层进行处理得到第一栅绝缘层和栅极。
当通过一次构图工艺形成第一栅绝缘层和栅极时，相较于分别采用构图工艺形成第一栅绝缘层和栅极的实现方式，可以减少至少一次构图工艺，以简化薄膜晶体管的制造过程和制造成本。
步骤308、在形成有栅极的衬底基板上形成第二栅绝缘层。
可选的，可以采用磁控溅射、热蒸发或者PECVD等方法在形成有栅极的衬底基板上，沉积具有一定厚度的第二绝缘材料，得到第二绝缘材质层，然后通过构图工艺对第二绝缘材质层进行处理得到第二栅绝缘层，且该第二栅绝缘层上形成有多个过孔，以保证有源层与源极，及有源层与漏极的有效接触。
其中，第二绝缘材料可以为氮化硅、二氧化硅或有机绝缘材料等。第二绝 缘材料与第一绝缘材料可以相同，也可以不同，本公开实施例对此不做限定。
步骤309、在形成第二栅绝缘层的衬底基板上形成源漏极。
可选的，可以采用磁控溅射、热蒸发或者PECVD等方法在形成有第二栅绝缘层的衬底基板上，沉积具有一定厚度的源漏极金属材料，得到源漏极金属薄膜层，然后通过构图工艺对该源漏极金属薄膜层进行处理，以得到源漏极。
其中，该源漏极包括源极和漏极，该源极和该漏极可以分别通过第二栅绝缘层上的过孔与有源层连接。该源漏极金属材料可以为金属Mo、金属Cu、金属Al或上述金属材料的合金材料。源漏极的厚度可以根据实际需要进行确定。
在本公开实施例中，为了保证源漏极与有源层的有效接触，有源层在衬底基板上的正投影与栅极在衬底基板上的正投影可以存在不重叠区域，且有源层在衬底基板上的正投影与第一栅绝缘层在衬底基板上的正投影可以存在不重叠区域，以便于在该不重叠区域上方的第二栅绝缘层上设置过孔，使源极和漏极可以分别通过该过孔与有源层连接。
图9是本公开实施例提供的又一种薄膜晶体管的制造方法的流程图。该制造方法可以用于制造例如图2所示的底栅结构的薄膜晶体管。如图9所示，该方法包括以下工作过程：
步骤401、提供一衬底基板。
步骤402、在衬底基板上形成栅极。
步骤403、在形成有栅极的衬底基板上形成第一栅绝缘层。
步骤404、在形成有第一栅绝缘层的衬底基板上形成高织构介电层。
步骤405、在形成有高织构介电层的衬底基板上形成非晶硅层。
步骤406、对非晶硅层进行脱氢处理。
步骤407、对经过脱氢处理后的非晶硅层进行晶化处理，使非晶硅层转换为由类单晶硅结构材料组成的半导体膜层，以形成有源层。
步骤408、在形成有有源层的衬底基板上形成源漏极。
上述步骤401至步骤408的实现过程可以参考步骤301至步骤309中的相关描述，此处不再赘述。
需要说明的是，本公开实施例提供的薄膜晶体管的制造方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减，任何熟悉本技术领 域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内，因此不再赘述。
综上所述，本公开实施例提供的薄膜晶体管的制造方法，通过在形成有高织构介电层的衬底基板上形成非晶硅层，由于高织构介电层的组成微粒的晶向指数一致度较高，在对非晶硅层进行晶化处理的过程中，高织构介电层能够诱导非晶硅层的组成微粒朝与高织构介电层的组成微粒的晶向指数相同的方向结晶，即诱导非晶硅层的组成微粒从非晶硅结构转换为类单晶硅结构，以生成有源层。由于类单晶硅结构与多晶硅相比，晶界缺陷较小，因此与相关技术中的LTPS TFT相比，本公开实施例提供的薄膜晶体管可以减轻由于晶界缺陷导致漏电流较大的问题。另外，类单晶硅结构相较于多晶硅，其载流子迁移率较高，进而提升了薄膜晶体管的性能。进一步的，本公开实施例提供的薄膜晶体管的制造方法，在制备薄膜晶体管的过程中所采用的设备以及工艺参数均可参照LTPS TFT，因此与现有工艺及设备的兼容度较高，提高了生产可实现性。
本公开实施例提供了一种阵列基板，参见图1和图2，该阵列基板可以包括：衬底基板00以及设置在衬底基板00上的如上述实施例所提供的薄膜晶体管。
可选的，本公开实施例提供的阵列基板可以应用于液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode，OLED)显示器、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示器或传感器(sensor)。
示例的，当阵列基板用于液晶显示器，则该阵列基板可以包括衬底基板，以及设置在衬底基板上的薄膜晶体管、平坦层、电极层(公共电极层或像素电极层)和取向层。当阵列基板用于OLED显示器或QLED显示器，则该阵列基板可以包括衬底基板，以及设置在衬底基板上的薄膜晶体管、第一电极、像素界定层、发光层和第二电极，其中，第一电极和第二电极分别为阳极和阴极中的一个。
综上所述，本公开实施例提供的阵列基板，在该阵列基板的薄膜晶体管中，通过在形成有高织构介电层的衬底基板上形成有源层，由于高织构介电层的组成微粒的晶向指数一致度较高，能够诱导有源层生长成类单晶硅结构。又由于类单晶硅结构与多晶硅相比，晶界缺陷较小，因此与相关技术中的LTPS TFT相 比，本公开实施例提供的薄膜晶体管可以减轻由于晶界缺陷导致漏电流较大的问题。另外，类单晶硅结构相较于多晶硅，其载流子迁移率较高，提升了薄膜晶体管的性能，进而提升了该阵列基板的性能。
本公开实施例提供了一种显示装置，包括：上述阵列基板。
可选的，显示装置可以为液晶显示器、OLED显示器或QLED显示器等。例如，该显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等具有显示功能的产品或部件。
综上所述，本公开实施例提供的显示装置，在该显示装置的薄膜晶体管中，通过在形成有高织构介电层的衬底基板上形成有源层，由于高织构介电层的组成微粒的晶向指数一致度较高，能够诱导有源层生长成类单晶硅结构。又由于类单晶硅结构与多晶硅相比，晶界缺陷较小，因此与相关技术中的LTPS TFT相比，本公开实施例提供的薄膜晶体管可以减轻由于晶界缺陷导致漏电流较大的问题。另外，类单晶硅结构相较于多晶硅，其载流子迁移率较高，进而提升了薄膜晶体管的性能，从而提高了显示装置的显示性能。
本公开实施例还提供了一种传感器，该传感器可以包括：上述阵列基板。示例的，该传感器可以为光电传感器、压力传感器或指纹传感器等。其中，该光电传感器可以为X射线(X-ray)传感器等。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种薄膜晶体管，包括：设置在衬底基板上的高织构介电层、有源层、栅极和源漏极；
    其中，所述有源层位于所述高织构介电层远离所述衬底基板的一侧；
    所述栅极与所述有源层绝缘设置，所述源漏极包括源极和漏极，所述源极和所述漏极分别与所述有源层电连接；
    所述有源层为包括类单晶硅结构材料的半导体膜层。
  2. 根据权利要求1所述的薄膜晶体管，
    所述高织构介电层的组成微粒的晶向指数与单晶硅的晶向指数相同。
  3. 根据权利要求1或2所述的薄膜晶体管，
    所述高织构介电层的制备材料包括氧化镁、氧化铈或掺杂有钇的氧化锆中的任意一种。
  4. 根据权利要求1至3任一所述的薄膜晶体管，所述栅极位于所述有源层远离所述衬底基板的一侧，所述源漏极位于所述栅极远离所述衬底基板的一侧。
  5. 根据权利要求4所述的薄膜晶体管，所述薄膜晶体管还包括第一栅绝缘层和第二栅绝缘层；
    所述第一栅绝缘层位于所述有源层和所述栅极之间，所述第二栅绝缘层位于所述栅极和所述源漏极之间。
  6. 根据权利要求1至3任一所述的薄膜晶体管，所述栅极位于所述高织构介电层靠近所述衬底基板的一侧，所述源漏极位于所述有源层远离所述衬底基板的一侧。
  7. 根据权利要求6所述的薄膜晶体管，所述薄膜晶体管还包括第一栅绝缘层；所述第一栅绝缘层位于所述所述高织构介电层和所述栅极之间。
  8. 一种薄膜晶体管的制造方法，所述方法包括：
    提供一衬底基板；
    在所述衬底基板上形成高织构介电层；
    在形成有所述高织构介电层的衬底基板上形成非晶硅层；
    对所述非晶硅层进行晶化处理，使所述非晶硅层转换为包括类单晶硅结构材料的半导体膜层，以形成有源层；
    在所述衬底基板上形成栅极和源漏极，所述源漏极包括源极和漏极，所述栅极与所述有源层绝缘设置，所述源极和所述漏极分别与所述有源层电连接。
  9. 根据权利要求8所述的方法，在对所述非晶硅层进行晶化处理之前，所述方法还包括：
    对所述非晶硅层进行脱氢处理。
  10. 根据权利要求8或9所述的方法，所述在形成有所述高织构介电层的衬底基板上形成非晶硅层，包括：
    在所述高织构介电层远离所述衬底基板的一面上沉积非晶硅材料，以形成所述非晶硅层。
  11. 根据权利要求8至10任一所述的方法，所述对所述非晶硅层进行晶化处理，包括：
    通过准分子激光退火工艺对所述非晶硅层进行晶化处理。
  12. 根据权利要求8至11任一所述的方法，所述在所述衬底基板上形成高织构介电层，包括：
    通过电子束蒸发工艺或离子束沉积工艺在所述衬底基板上形成所述高织构介电层。
  13. 根据权利要求8至12任一所述的方法，所述在所述衬底基板上形成栅极和源漏极，包括：
    在形成有所述有源层的衬底基板上依次形成栅极和源漏极。
  14. 根据权利要求13所述的方法，在形成所述有源层之后，且在形成有所述有源层的衬底基板上形成栅极之前，所述方法还包括：
    在形成有所述有源层的衬底基板上形成第一栅绝缘层；
    在形成所述栅极之后，且在形成所述源漏极之前，所述方法还包括：
    在形成有所述栅极的衬底基板上形成第二栅绝缘层。
  15. 根据权利要求8至12任一所述的方法，所述在形成有所述有源层的衬底基板上形成栅极和源漏极，包括：
    在形成所述高织构介电层之前，在所述衬底基板上形成栅极；
    在形成所述有源层之后，在形成有所述有源层的衬底基板上形成源漏极。
  16. 根据权利要求8至15任一所述的方法，
    所述高织构介电层的组成微粒的晶向指数与单晶硅的晶向指数相同。
  17. 根据权利要求8至16任一所述的方法，
    所述高织构介电层的制备材料包括氧化镁、氧化铈或掺杂有钇的氧化锆中的任意一种。
  18. 一种阵列基板，包括：衬底基板以及设置在所述衬底基板上的如权利要求1至7任一所述的薄膜晶体管。
  19. 一种显示装置，包括：如权利要求18所述的阵列基板；所述显示装置为液晶显示器、有机发光二极管显示器或量子点发光二极管显示器。
  20. 一种传感器，包括：如权利要求18所述的阵列基板；所述传感器为光电传感器、压力传感器或指纹传感器。
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