WO2020062306A1 - 一种指令时间的测试方法和系统、及计算机存储介质 - Google Patents

一种指令时间的测试方法和系统、及计算机存储介质 Download PDF

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Publication number
WO2020062306A1
WO2020062306A1 PCT/CN2018/109218 CN2018109218W WO2020062306A1 WO 2020062306 A1 WO2020062306 A1 WO 2020062306A1 CN 2018109218 W CN2018109218 W CN 2018109218W WO 2020062306 A1 WO2020062306 A1 WO 2020062306A1
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WO
WIPO (PCT)
Prior art keywords
falling edge
result
preset
time
adapter
Prior art date
Application number
PCT/CN2018/109218
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English (en)
French (fr)
Inventor
田晨
Original Assignee
Oppo广东移动通信有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oppo广东移动通信有限公司 filed Critical Oppo广东移动通信有限公司
Priority to KR1020217003905A priority Critical patent/KR102557374B1/ko
Priority to PCT/CN2018/109218 priority patent/WO2020062306A1/zh
Priority to CN201880033229.1A priority patent/CN111263891B/zh
Priority to JP2021506302A priority patent/JP7223835B2/ja
Priority to EP18934529.1A priority patent/EP3709036B1/en
Priority to US16/730,615 priority patent/US11614484B2/en
Publication of WO2020062306A1 publication Critical patent/WO2020062306A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2882—Testing timing characteristics
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00036—Charger exchanging data with battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00045—Authentication, i.e. circuits for checking compatibility between one component, e.g. a battery or a battery charger, and another component, e.g. a power source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/30—Charge provided using DC bus or data bus of a computer

Definitions

  • the embodiments of the present application relate to charging technologies in the field of terminals, and in particular, to a method and system for testing instruction time, and a computer storage medium.
  • the fast charging technology can charge the battery of the terminal through the adapter in a segmented constant current manner, so that fast charging can be performed on the premise of ensuring safety and reliability, which greatly improves the charging speed of the terminal.
  • the time for the adapter to send instructions will have a certain effect on the effect of flash charging.
  • the embodiments of the present application provide a method and system for testing instruction time, and a computer storage medium.
  • the adapter performs instruction time detection on an adapter, it can reduce the number of detection instructions and simplify the detection process, thereby greatly improving detection efficiency and accuracy.
  • An embodiment of the present application provides a method for testing instruction time.
  • the method includes:
  • a test result of instruction time is generated according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.
  • the embodiments of the present application provide a method and system for testing instruction time, and a computer storage medium.
  • the test system receives a clock signal sent by the adapter; wherein, the clock signal Used to indicate the instruction transmission time; obtain the first valid interrupt corresponding to the clock signal, the square wave corresponding to the first valid interrupt, and the next valid interrupt corresponding to the first valid interrupt; obtain the first falling edge and The first rising edge acquires the second falling edge corresponding to the square wave and the third falling edge corresponding to the next valid interrupt; generates an instruction based on the first falling edge, the first rising edge, the second falling edge, and the third falling edge Time test results.
  • test system of the present application can directly detect the instruction time of the adapter when communicating with the adapter, and can further reduce the number of detection instructions and simplify the detection process when detecting the time of sending instructions to the adapter, thereby greatly improving the detection process. Detection efficiency and accuracy.
  • FIG. 1 is a schematic flowchart of an instruction time test method according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a test system in an embodiment of the present application.
  • Figure 3 is a schematic diagram of a test board
  • Figure 4 is a schematic diagram of the connection between the test system and the adapter
  • FIG. 5 is a schematic diagram of a clock signal in this application.
  • FIG. 6 is a schematic diagram of a clock signal and a data signal when an instruction is transmitted in an embodiment of the present application
  • FIG. 7 is a schematic diagram of effectively interrupting rising and falling edges in the embodiment of the present application.
  • FIG. 8 is a first schematic structural diagram of a composition of a test system according to an embodiment of the present application.
  • FIG. 9 is a second schematic diagram of a composition structure of a test system according to an embodiment of the present application.
  • a custom adapter and battery are required to implement the flash charge function.
  • a micro controller unit (MCU) smart chip is configured in the adapter for flash charge, so the adapter is Upgradeable smart charger.
  • the process of fast charging the terminal by the adapter may mainly include the following five stages:
  • Phase 1 The terminal detects the adapter type.
  • the adapter starts the handshake communication between the adapter and the terminal.
  • the adapter sends a first instruction to ask the terminal whether to enable the fast charging mode. After the terminal agrees to enable fast charging, the fast charging communication process enters phase 2.
  • Phase 2 The adapter sends a second instruction to the terminal to ask whether the output voltage of the adapter matches. After the terminal responds that the output voltage of the adapter is high, low, or matched, the adapter adjusts the output voltage until the output voltage is appropriate.
  • Phase 3 The adapter sends a third instruction to the terminal, asking the terminal for the maximum charging current currently supported, the terminal responds to the adapter's maximum charging current, and enters phase 4.
  • Phase 4 The adapter can set the output current to the maximum charging current currently supported by the terminal and enter the constant current phase, which is Phase 5.
  • Phase 5 When entering the constant current phase, the adapter can send a fourth command at intervals to query the current voltage of the terminal battery.
  • the terminal can feed back the current voltage of the terminal battery to the adapter.
  • the adapter can respond to the current voltage of the terminal battery by the terminal. Feedback to determine whether the contact is good and whether the current charging current of the terminal needs to be reduced.
  • constant current phase does not mean that the output current of the adapter has remained constant during phase 5.
  • constant current is segmented constant current, that is, it remains unchanged for a period of time.
  • FIG. 1 is a schematic flowchart of an instruction time testing method according to an embodiment of the present application. As shown in FIG. 1, in the embodiment of the present application, the test method for the instruction time of the test system may include the following steps:
  • Step 101 After establishing a connection with the adapter, receive a clock signal sent by the adapter; wherein the clock signal is used to indicate a transmission time of the instruction.
  • the test system may receive a clock signal sent by the adapter.
  • the clock signal may be used to control the transmission time of the instructions.
  • the adapter sends the above to the test system.
  • a clock signal so that the adapter and the test system can perform bidirectional communication according to a clock cycle of the clock signal.
  • the test system may be a system for performing parameter detection on the adapter.
  • FIG. 2 is a schematic diagram of a test system according to an embodiment of the present application.
  • the test system may include a test board, an electronic load, and a host computer.
  • the test board may be connected to the electronic load and cooperate with it. Control the field-effect transistor (Metal-Oxide-Semiconductor, Field-Effect, Transistor, MOSFET, MOS) switch, so as to simulate the state of the terminal.
  • the test board may transmit various values of the detected adapter to the host computer, for example, the test board may report the output status of the detected adapter to the host computer.
  • FIG. 3 is a schematic diagram of a test board, as shown in FIG. 3, the test board may be integrated with MCU and MOS, where VBUS is a USB voltage GND is the power ground.
  • FIG. 4 is a schematic diagram of the connection between the test system and the adapter.
  • the test board in the test system can be connected to the adapter and can be connected to the adapter. For two-way communication.
  • the above-mentioned test system can simulate the process of fast charging the terminal by the adapter through connection and communication with the adapter, so that various parameters of the adapter can be directly tested without Then you need to get the parameter test results of the adapter through the oscilloscope.
  • the first interrupt in the clock signal received by the test system during the process of fast charging the terminal by the adapter through the connection and communication with the adapter may be the adapter.
  • the first byte in the fast charging process with the terminal may be the first byte in the first instruction in the above-mentioned phase 1 for inquiring whether to enable the fast charging mode.
  • the first interrupt in the clock signal may also be a test byte sent by the adapter to perform parameter detection on the adapter.
  • the above-mentioned adapter can be used to quickly charge the terminal.
  • the above-mentioned adapter and the terminal can be connected through a Universal Serial Bus (USB) interface.
  • the USB interface can be Ordinary USB interface can also be micro USB interface or Type C interface.
  • the power cable in the USB interface is used for charging the terminal by the foregoing adapter.
  • the power cable in the USB interface may be a VBus line and / or a ground cable in the USB interface.
  • the data line in the USB interface is used for the two-way communication between the adapter and the terminal.
  • the data line may be a D + line and / or a D- line in the USB interface.
  • the so-called two-way communication may refer to the information exchange between the adapter and the terminal.
  • the adapter may support a normal charging mode and a fast charging mode, wherein a charging current of the fast charging mode is greater than a charging current of the normal charging mode, that is, a charging speed of the fast charging mode is greater than the normal charging mode.
  • Charging speed in charging mode can be understood as a charging mode with a rated output voltage of 5V and a rated output current of 2.5A or less.
  • the adapter output ports D + and D- can be shorted, while in the fast charging mode
  • the adapter can use D + and D- to communicate and exchange data with the mobile terminal.
  • the performance parameters of the adapter may include sending instructions. Time parameters, output voltage, output current, etc.
  • the adapter may send a clock signal to the test system through a data line in a USB interface, where the clock signal is used to indicate the adapter. And the timing of communication between the test system. Specifically, the adapter actively sends a clock signal to the test system, and the adapter can keep sending the clock signal throughout the connection with the test system, so that it can perform two-way communication with the test system under the control of the communication timing.
  • the communication sequence includes the instruction sending period of the adapter and the instruction receiving period of the adapter generated alternately.
  • the test system may receive the clock signal sent by the adapter through a D + data line.
  • FIG. 5 is a schematic diagram of a clock signal in the present application.
  • the clock signal of the D + data line includes a low level and a high level.
  • one low level and one high level constitute one clock cycle.
  • one clock cycle includes a 10us low level and a 500us high level.
  • FIG. 5 and FIG. 6 are schematic diagrams of a clock signal and a data signal when an instruction is transmitted in the embodiment of the present application.
  • each instruction sent by the adapter to the terminal includes 8 bits of data.
  • the adapter sends 8-bit data to the mobile terminal through 8 consecutive clock cycles of the clock signal.
  • the first 10us of each consecutive 8 clock cycles are interrupts, and the last 500us are data.
  • each reply command received by the adapter includes 10 bits of data.
  • the adapter receives 10 bits of data from the terminal through 10 consecutive clock cycles of the clock signal. Each of the 10 consecutive clock cycles
  • the first 500us is data and the last 10us is interrupt.
  • the instruction time is tested by using the received clock signal.
  • Step 102 Obtain the first valid interrupt corresponding to the clock signal, the square wave corresponding to the first valid interrupt, and the next valid interrupt corresponding to the first valid interrupt.
  • the test system may collect a first valid interrupt corresponding to the clock signal, a square wave corresponding to the first valid interrupt, and the first valid interrupt corresponding. The next valid interrupt.
  • the test system may collect valid interrupts and square waves in the clock signal to obtain a first valid terminal, a first For each square wave and the second valid interrupt, the first valid interrupt, the square wave corresponding to the first valid interrupt, and the next valid interrupt can be obtained.
  • the test system since the first instruction sent by the adapter in the above stage 1 is used to determine whether to enable fast charging, the test system needs to perform a test on the instruction time.
  • the first instruction sent by the adapter performs timing detection, so it is necessary to collect and obtain the first valid interrupt and the square wave corresponding to the first valid interrupt.
  • the interval and duration of data transmission can be determined through two consecutive effective interrupts, so it is necessary to collect the first effective interrupt. Corresponding to the above next valid interrupt.
  • Step 103 Obtain a first falling edge and a first rising edge corresponding to the first valid interrupt, obtain a second falling edge corresponding to the square wave, and obtain a third falling edge corresponding to the next valid interrupt.
  • the test system may obtain a first falling edge and a first rising edge corresponding to the first valid interrupt. It is also possible to obtain the second falling edge corresponding to the square wave, and simultaneously obtain the third falling edge corresponding to the next valid interrupt.
  • the test system may further determine whether the adapter meets the instruction timing requirements according to the first valid interrupt, the square wave, and the next valid interrupt. Specifically, the test The system can detect the rising and falling edges of the first valid interrupt, the square wave, and the next valid interrupt first, so that the first rising edge and the first falling edge of the first valid interrupt can be obtained. The second falling edge corresponding to the square wave can be obtained, and the third falling edge corresponding to the next valid interrupt can also be obtained.
  • FIG. 7 is a schematic diagram of the effective interruption rising and falling edges in the embodiment of the present application.
  • the test system can acquire the rising and falling edges of the first effective interrupt, and also obtain a square wave. Corresponding falling edge, at the same time get the falling edge corresponding to the second valid interrupt.
  • Step 104 Generate a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.
  • the test system obtains the first falling edge and the first rising edge corresponding to the first valid interrupt, the second falling edge corresponding to the square wave, and the next valid interrupt corresponding to the first valid interrupt.
  • the test result may be further generated according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.
  • the test system may determine the first falling edge according to the first falling edge.
  • the interruption time of the valid interrupt is determined with the first rising edge, and the data transmission time can also be determined according to the first falling edge and the second falling edge.
  • the second falling edge and the third falling edge can also be determined. Determine the interval time.
  • the test system when the test system generates the test result according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge, the test system may The interruption time, the transmission time, and the interval time can be directly obtained through the test small board.
  • the first falling edge, the first rising edge, the second falling edge, and the third falling edge can also be obtained through the test small board first. It is transmitted to the upper computer along the edge, and then obtains the interruption time, the transmission time, and the interval time through the upper computer.
  • test results are used to characterize the results of testing the time parameters corresponding to the adapters. Specifically, it can be determined whether the time parameters corresponding to the adapters meet the timing according to the test results. Claim.
  • test results may include a first result used to characterize an interruption duration of an effective interruption, a second result used to characterize a duration of instruction data transmission, and may further include: A third result that characterizes the transmission interval.
  • An embodiment of the present application provides a method for testing instruction time. After a connection is established with an adapter, the test system receives a clock signal sent by the adapter; wherein the clock signal is used to indicate the instruction transmission time; the first valid time corresponding to the clock signal is obtained. Interrupt, the first valid interrupt corresponds to the square wave, and the next valid interrupt corresponds to the first valid interrupt; obtain the first falling edge and the first rising edge corresponding to the first effective interrupt, obtain the second falling edge corresponding to the square wave, and obtain The third falling edge corresponding to the next valid interrupt; according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge, a test result of the instruction time is generated.
  • the test system of the present application can directly detect the instruction time of the adapter when communicating with the adapter, and can further reduce the number of detection instructions and simplify the detection process when detecting the time of sending instructions to the adapter, thereby greatly improving the detection process. Detection efficiency and accuracy.
  • the test system generates an instruction time according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.
  • the method of testing results can include the following steps:
  • Step 104a Determine an interruption time according to the first falling edge and the first rising edge.
  • test system after the test system obtains the first falling edge and the first rising edge corresponding to the first valid interrupt, it may further determine according to the first falling edge and the first rising edge. Outage time.
  • the interruption time may be used to characterize an interruption duration of a valid interruption in the clock signal sent by the adapter. Therefore, the test system may determine the interruption time first. To further determine whether the clock signal of the adapter meets the timing requirements.
  • Step 104b Determine the transmission time according to the first falling edge and the second falling edge.
  • the test system may further perform the operations according to the first falling edge and the first falling edge. Two falling edges determine the transmission time.
  • the transmission time may be used to characterize the data transmission time when the adapter sends an instruction. Therefore, the test system may first determine the transmission time to further determine the performance of the adapter. Whether the instruction time meets the timing requirements.
  • the above transmission time is used to characterize the time required for a complete byte transmission, that is, the test system from the first valid interrupt corresponding to a byte to the completion of the reply.
  • the duration of the last bit corresponding to the byte is used to characterize the time required for a complete byte transmission, that is, the test system from the first valid interrupt corresponding to a byte to the completion of the reply.
  • Step 104c Determine an interval time according to the second falling edge and the third falling edge.
  • the test system may further perform the operations according to the second falling edge and the first falling edge. Three falling edges determine the interval.
  • the above-mentioned interval time may be used to characterize the transmission interval between different bytes when the adapter sends a command. Therefore, the test system may first determine the above-mentioned interval time to It is further determined whether the instruction time of the adapter meets timing requirements.
  • the above-mentioned interval time is used to characterize a time interval between two adjacent bytes, that is, an interval time between the two consecutive bytes sent by the adapter.
  • Step 104d Determine the test result according to the interruption time, transmission time, and interval time.
  • the test system may determine the test result according to the interruption time, the transmission time, and the interval time.
  • the preset interruption threshold, transmission threshold, and interval threshold may be respectively different from the foregoing.
  • the outage time, the transmission time, and the interval time are compared, so that the test result can be determined based on the comparison result.
  • An embodiment of the present application provides a method for testing instruction time. After a connection is established with an adapter, the test system receives a clock signal sent by the adapter; wherein the clock signal is used to indicate the instruction transmission time; the first valid time corresponding to the clock signal is obtained. Interrupt, the first valid interrupt corresponds to the square wave, and the next valid interrupt corresponds to the first valid interrupt; obtain the first falling edge and the first rising edge corresponding to the first effective interrupt, obtain the second falling edge corresponding to the square wave, and obtain The third falling edge corresponding to the next valid interrupt; according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge, a test result of the instruction time is generated.
  • the test system of the present application can directly detect the instruction time of the adapter when communicating with the adapter, and can further reduce the number of detection instructions and simplify the detection process when detecting the time of sending instructions to the adapter, thereby greatly improving the detection process. Detection efficiency and accuracy.
  • the test system determines the test result based on the interruption time, the transmission time, and the interval time, that is, before step 104d, the test system performs
  • the test method of the instruction time may further include the following steps:
  • Step 105 Obtain a preset interruption time threshold, a preset transmission time threshold, and a preset interval time threshold.
  • the test system may first obtain a preset interruption time threshold, a preset transmission time threshold, and Set the interval time threshold.
  • the preset interruption time threshold, the preset transmission time threshold, and the preset interval time threshold may represent a timing requirement corresponding to the adapter.
  • the test system may preset the preset interruption time threshold, the preset transmission time threshold, and the preset interval time threshold, wherein the preset interruption time threshold is used for characterization The timing requirements for valid interrupts in the clock signal sent by the adapter; the preset transmission time threshold is used to characterize the timing requirements of the adapter to transmit data; the preset interval time threshold is used to characterize the two consecutive bytes that the adapter should meet to send The timing requirements of the interval.
  • the method for the test system to determine the test result according to the interruption time, the transmission time, and the interval time may include the following steps:
  • Step 201 Obtain a first result according to the interruption time and a preset interruption time threshold.
  • the test system may further obtain a first result according to the interruption time and the preset interruption time threshold.
  • the test system may compare the interruption time with the preset interruption time threshold, so that the first result may be further determined according to a comparison result.
  • the first result is used to determine whether the adapter meets a timing requirement of a valid interrupt in a clock signal.
  • the test system compares the interruption time with the preset interruption time threshold, if the interruption time is greater than or equal to the preset interruption time threshold, then the first The result is that the timing requirements described above are not met.
  • the test system compares the interruption time with the preset interruption time threshold, if the interruption time is less than the preset interruption time threshold, the first result may be determined as Meet the above timing requirements.
  • Step 202 Obtain a second result according to the transmission time and a preset transmission time threshold.
  • the test system may further obtain a second result according to the transmission time and the preset transmission time threshold.
  • the test system may compare the transmission time and the preset transmission time threshold, so that the second result may be further determined according to a comparison result.
  • the second result is used to determine whether the adapter meets a timing requirement for sending a byte.
  • the test system compares the transmission time and the preset transmission time threshold, if the transmission time is greater than or equal to the preset transmission time threshold, then the second The result is that the timing requirements described above are not met.
  • the second result may be determined as Meet the above timing requirements.
  • Step 203 Obtain a third result according to the interval time and a preset interval time threshold.
  • the test system may further obtain the third result according to the interval time and the preset interval time threshold.
  • the test system may compare the interval time and the preset interval time threshold, so that the third result may be further determined according to a comparison result.
  • the third result is used to determine whether the adapter meets a timing requirement for a time interval of sending two consecutive bytes.
  • the test system compares the interval time with the preset interval time threshold, if the interval time is greater than or equal to the preset interval time threshold, then the third The result is that the timing requirements described above are not met.
  • the third result may be determined as Meet the above timing requirements.
  • Step 204 Determine a test result according to the first result, the second result, and the third result.
  • the test system may generate the adapter according to the first result, the second result, and the third result. Corresponding test results.
  • the test result can determine whether the time parameter of the adapter meets a preset timing requirement, that is, whether the adapter meets the interrupt timing requirement of a valid interrupt, and whether it meets the requirement to send a byte. Duration timing requirements, and whether the adapter meets the timing requirements for a time interval of sending two consecutive bytes.
  • An embodiment of the present application provides a method for testing instruction time. After a connection is established with an adapter, the test system receives a clock signal sent by the adapter; wherein the clock signal is used to indicate the instruction transmission time; the first valid time corresponding to the clock signal is obtained. Interrupt, the first valid interrupt corresponds to the square wave, and the next valid interrupt corresponds to the first valid interrupt; obtain the first falling edge and the first rising edge corresponding to the first effective interrupt, obtain the second falling edge corresponding to the square wave, and obtain The third falling edge corresponding to the next valid interrupt; according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge, a test result of the instruction time is generated.
  • the test system of the present application can directly detect the instruction time of the adapter when communicating with the adapter, and can further reduce the number of detection instructions and simplify the detection process when detecting the time of sending instructions to the adapter, thereby greatly improving the detection process. Detection efficiency and accuracy.
  • FIG. 8 is a first schematic structural diagram of a composition of a test system according to an embodiment of the present application. As shown in FIG. 11. An acquisition section 12 and a generation section 13.
  • the receiving section 11 is configured to receive a clock signal sent by the adapter after establishing a connection with the adapter, wherein the clock signal is used to indicate a transmission time of an instruction.
  • the acquiring section 12 is configured to acquire a first valid interrupt corresponding to the clock signal, a square wave corresponding to the first valid interrupt, and a next valid interrupt corresponding to the first valid interrupt; and to obtain the first valid interrupt; A first falling edge and a first rising edge corresponding to the effective interrupt, a second falling edge corresponding to the square wave is obtained, and a third falling edge corresponding to the next effective interrupt is obtained.
  • the generating section 13 is configured to generate a test result of an instruction time according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.
  • the generating section 13 is specifically configured to determine an interruption time according to the first falling edge and the first rising edge; and according to the first falling edge and the first falling edge Determine a transmission time on a second falling edge; and determine an interval time based on the second falling edge and the third falling edge; and determine the test based on the interruption time, the transmission time, and the interval time result.
  • the obtaining section 12 is further configured to obtain a preset interruption time threshold, before determining the test result according to the interruption time, the transmission time, and the interval time, A preset transmission time threshold and a preset interval time threshold; wherein the preset interruption time threshold, the preset transmission time threshold, and the preset interval time threshold are used to characterize the timing requirements corresponding to the adapter.
  • the obtaining section 12 is specifically configured to obtain a first result according to the interruption time and the preset interruption time threshold; and according to the transmission time and the presetting Transmitting a time threshold to obtain a second result; and obtaining a third result according to the interval time and the preset interval time threshold.
  • the generating section 13 is specifically configured to determine the test result according to the first result, the second result, and the third result.
  • the obtaining section 12 is further specifically configured to: when the interruption time is greater than or equal to the preset interruption time threshold, the first result is that the timing requirements are not met. And when the interruption time is less than the preset interruption time threshold, the first result is that the timing requirements are met; and when the transmission time is greater than or equal to the preset transmission time threshold, the first The second result is that the timing requirements are not met; and when the transmission time is less than the preset transmission time threshold, the second result is that the timing requirements are met; and when the interval time is greater than or equal to the pre- When the interval time threshold is set, the third result is that the timing requirements are not met; and when the interval time is less than the preset interval time threshold, the third result is that the timing requirements are met.
  • FIG. 9 is a second schematic diagram of the composition and structure of a test system according to an embodiment of the present application.
  • the test board is integrated with a processor and a memory storing instructions executable by the processor.
  • the test system 1 may further include a communication interface 17 and a bus 18 for connecting the test board 14, the host computer 15, the electronic load 16, and the communication interface 17.
  • a processor and a memory may also be integrated into the above-mentioned upper computer, and the functions of the processor and the memory in the test board 16 are the same.
  • the processor may be an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), or a Digital Signal Processing Device (DSPD). , Programmable logic device (ProgRAMmableLogic Device, PLD), field programmable gate array (FieldProgRAMmableGateArray, FPGA), central processing unit (CPU), controller, microcontroller, microprocessor at least One. It can be understood that, for different devices, the electronic device used to implement the processor function may be other, which is not specifically limited in the embodiment of the present application.
  • the test system 1 may further include a memory, which may be connected to a processor, where the memory is used to store executable program code, the program code includes computer operation instructions, and the memory may include a high-speed RAM memory or a non-volatile memory. Memory, for example, at least two disk memories.
  • the memory is configured to store instructions and data.
  • the processor is configured to receive a clock signal sent by the adapter after establishing a connection with the adapter; wherein the clock signal is used to indicate a transmission time of an instruction; and obtain the A first valid interrupt corresponding to the clock signal, a square wave corresponding to the first valid interrupt, and a next valid interrupt corresponding to the first valid interrupt; obtaining a first falling edge and a first rising corresponding to the first valid interrupt Edge, obtain a second falling edge corresponding to the square wave, and obtain a third falling edge corresponding to the next valid interrupt; according to the first falling edge, the first rising edge, the second falling edge, and The third falling edge generates a test result of the instruction time.
  • the foregoing memory may be a volatile first memory (volatile memory), such as a random access first memory (Random-Access Memory, RAM); or a non-volatile first memory (non-volatile memory)
  • volatile first memory such as a random access first memory (Random-Access Memory, RAM)
  • non-volatile first memory non-volatile memory
  • read-only memory Read-Only Memory
  • flash memory flash memory
  • hard disk Hard Disk Drive, HDD
  • SSD solid state drive
  • the functional modules in this embodiment may be integrated into one processing unit, or each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional modules.
  • the integrated unit is implemented in the form of a software functional module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of this embodiment is essentially Part of the prior art contribution or all or part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium and includes several instructions to make a computer device (which can be a personal A computer, a server, or a network device) or a processor executes all or part of the steps of the method in this embodiment.
  • the foregoing storage media include: U disks, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, which can store program codes.
  • An embodiment of the present application provides a test system. After establishing a connection with an adapter, the test system receives a clock signal sent by the adapter; wherein the clock signal is used to indicate the instruction transmission time; the first valid interrupt and the first corresponding to the clock signal are obtained. Square wave corresponding to each valid interrupt and the next valid interrupt corresponding to the first valid interrupt; obtain the first falling edge and the first rising edge corresponding to the first valid interrupt, obtain the second falling edge corresponding to the square wave, and obtain the next valid interrupt The third falling edge corresponding to the interrupt is generated; a test result of the instruction time is generated according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.
  • the test system of the present application can directly detect the instruction time of the adapter when communicating with the adapter, and can further reduce the number of detection instructions and simplify the detection process when detecting the time of sending instructions to the adapter, thereby greatly improving the detection process. Detection efficiency and accuracy.
  • An embodiment of the present application provides a first computer-readable storage medium on which a program is stored, and when the program is executed by a processor, the method for testing the instruction time as described above is implemented.
  • the program instructions corresponding to a method for testing instruction time in this embodiment may be stored on a storage medium such as an optical disc, a hard disk, a USB flash drive, and the like.
  • a program instruction When a program instruction is read or executed by an electronic device, it includes the following steps:
  • a test result of instruction time is generated according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Therefore, this application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) containing computer-usable program code.
  • a computer-usable storage media including, but not limited to, disk storage, optical storage, and the like
  • These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, so that the instructions generated by the processor of the computer or other programmable data processing device are used to generate instructions Means for realizing the functions specified in a process flow diagram or a plurality of flow diagrams and / or a block diagram or a block or flow diagrams of the block diagram.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to work in a particular manner such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device, the instructions
  • the device implements the functions specified in the implementation flow diagram, one flow or multiple flows, and / or the block diagram, one block or multiple blocks.
  • These computer program instructions can also be loaded on a computer or other programmable data processing device, so that a series of steps can be performed on the computer or other programmable device to produce a computer-implemented process, which can be executed on the computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in implementing one or more of the flowcharts and / or one or more of the block diagrams of the block diagrams.
  • the embodiments of the present application provide a method and system for testing instruction time, and a computer storage medium.
  • the test system receives a clock signal sent by the adapter; Used to indicate the instruction transmission time; obtain the first valid interrupt corresponding to the clock signal, the square wave corresponding to the first valid interrupt, and the next valid interrupt corresponding to the first valid interrupt; obtain the first falling edge and The first rising edge acquires the second falling edge corresponding to the square wave and the third falling edge corresponding to the next valid interrupt; generates an instruction based on the first falling edge, the first rising edge, the second falling edge, and the third falling edge Time test results.
  • the test system of the present application can directly detect the instruction time of the adapter when communicating with the adapter, and can further reduce the number of detection instructions and simplify the detection process when detecting the time of sending instructions to the adapter, thereby greatly improving the detection process. Detection efficiency and accuracy.

Abstract

一种指令时间的测试方法和系统、及计算机存储介质，该测试方法包括：在与适配器建立连接之后，接收适配器发送的时钟信号；其中，时钟信号用于指示指令的传输时间（101）；获取时钟信号对应的首个有效中断、首个有效中断对应的方波以及首个有效中断对应的下一个有效中断（102）；获取首个有效中断对应的第一下降沿和第一上升沿，获取方波对应的第二下降沿，获取下一个有效中断对应的第三下降沿（103）；根据第一下降沿、第一上升沿、第二下降沿以及第三下降沿，生成指令时间的测试结果（104）。

Description

一种指令时间的测试方法和系统、及计算机存储介质 技术领域
本申请实施例涉及终端领域的充电技术，尤其涉及一种指令时间的测试方法和系统、及计算机存储介质。
背景技术
快速充电技术可以通过适配器采用分段恒流的方式为终端的电池进行充电，从而可以在保证安全可靠的前提下进行快速充电，大大提高了终端的充电速度。其中，在进行快速充电时，由于需要适配器与终端进行双向通信，因此适配器发送指令的时间会对闪充的效果具有一定影响。
现有技术中，通过示波器对适配器发送指令的时间进行检测时，检测指令数量大且检测过程复杂，检测效率低、精度差。
发明内容
本申请实施例提供一种指令时间的测试方法和系统、及计算机存储介质，在对适配器进行发送指令的时间检测时，能够减少检测指令数量，简化检测过程，从而可以大大提高检测效率和精度。
本申请实施例的技术方案是这样实现的：
本申请实施例提供了一种指令时间的测试方法，所述方法包括：
在与适配器建立连接之后，接收所述适配器发送的时钟信号；其中，所述时钟信号用于指示指令的传输时间；
获取所述时钟信号对应的首个有效中断、所述首个有效中断对应的方波以及所述首个有效中断对应的下一个有效中断；
获取所述首个有效中断对应的第一下降沿和第一上升沿，获取所述方波对应的第二下降沿，获取所述下一个有效中断对应的第三下降沿；
根据所述第一下降沿、所述第一上升沿、所述第二下降沿以及所述第三下降沿，生成指令时间的测试结果。
本申请实施例提供了一种指令时间的测试方法和系统、及计算机存储介质，测试系统在与适配器建立连接之后，在与适配器建立连接之后，测试系统接收适配器发送的时钟信号；其中，时钟信号用于指示指令的传输时间；获取时钟信号对应的首个有效中断、首个有效中断对应的方波以及首个有效中断对应的下一个有效中断；获取首个有效中断对应的第一下降沿和第一上升沿，获取方波对应的第二下降沿，获取下一个有效中断对应的第三下降沿；根据第一下降沿、第一上升沿、第二下降沿以及第三下降 沿，生成指令时间的测试结果。由此可见，在本申请的实施例中，测试系统可以在与配置器建立连接之后，根据配置器发送的时钟信号，分别确定进行通信时首个有效中断、方波以及下一个有效中断对应的下降沿和上升沿，从而可以根据时钟信号的上升沿和下降沿，进一步获得适配器对应的指令时间的检测结果。正是由于本申请的测试系统可以在与适配器进行通信时直接对适配器进行指令时间的检测，进而在对适配器进行发送指令的时间检测时，能够减少检测指令数量，简化检测过程，从而可以大大提高检测效率和精度。
附图说明
图1为本申请实施例提出的一种指令时间的测试方法的实现流程示意图；
图2为本申请实施例中测试系统的示意图；
图3为测试小板的示意图；
图4为测试系统与适配器的连接示意图；
图5为本申请中时钟信号的示意图；
图6为本申请实施例中传输指令时时钟信号和数据信号的示意图；
图7为本申请实施例中有效中断上升沿和下降沿的示意图；
图8为本申请实施例提出的测试系统的组成结构示意图一；
图9为本申请实施例提出的测试系统的组成结构示意图二。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
终端在进行快速充电时，需要通过定制的适配器和电池来实现闪充的功能，一般情况下，用于闪充的适配器中配置有微控制单元(Microcontroller Unit，MCU)智能芯片，因此该适配器为可以升级的智能充电器。
进一步地，在本申请的实施例中，该适配器在对终端进行快速充电的过程主要可以包括以下五个阶段：
阶段1：终端检测适配器类型，适配器开启适配器与终端之间的握手通信，适配器发送第一指令询问终端是否开启快速充电模式，当终端同意开启快充后，快充通信流程进入阶段2。
阶段2：适配器向终端发送第二指令，询问适配器的输出电压是否匹配，终端答复适配器其输出电压偏高、偏低或匹配后，适配器调整输出电压，直到输出电压合适。
阶段3：适配器向终端发送第三指令，询问终端当前支持的最大充电电流，终端答复适配器最大充电电流，并进入阶段4。
阶段4：适配器可以设置输出电流为终端当前支持的最大充电电流，进入恒流阶段，即阶段5。
阶段5：当进入恒流阶段时，适配器可以每间隔一段时间发送一次第四指令，询问终端电池的当前电压，终端可以向适配器反馈终端电池的当前电压，适配器可以根据终端关于终端电池的当前电压的反馈，判断接触是否良好以及是否需要降低终端当前的充电电流值。
需要说明的是，恒流阶段并非指适配器的输出电流在阶段5一直保持不变，所谓恒流是分段恒流，即在一段时间内保持不变。
正是由于快速充电是通过适配器与终端建立双向通信来对终端进行分段恒流充电实现的，因此，适配器发送指令的各项参数都对闪充的效果有着很大的影响，对适配器发送指令的参数进行检测就尤为重要。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
本申请一实施例提供了一种指令时间的测试方法，图1为本申请实施例提出的一种指令时间的测试方法的实现流程示意图，如图1所示，在本申请的实施例中，上述测试系统进行指令时间的测试方法可以包括以下步骤：
步骤101、在与适配器建立连接之后，接收适配器发送的时钟信号；其中，时钟信号用于指示指令的传输时间。
在本申请的实施例中，上述测试系统在与适配器建立连接之后，可以接收上述适配器发送的时钟信号。
需要说明的是，在本申请的实施例中，上述适配器和上述测试系统在进行指令传输时，上述时钟信号可以用于对指令的传输时间进行控制，具体地，上述适配器向上述测试系统发送上述时钟信号，从而可以使得上述适配器和上述测试系统按照上述时钟信号的时钟周期进行双向通信。
需要说明的是，在本申请的实施例中，上述测试系统可以为对上述适配器进行参数检测的一种系统。图2为本申请实施例中测试系统的示意图，如图2所示，测试系统可以包括测试小板、电子负载以及上位机，其中，测试小板可以与电子负载连接并进行配合，同时可以通过控制场效应管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET，MOS)开关，从而便可以模拟终端的状态。具体地，在本申请的实施例中，测试小板可以将检测到的适配器的各项数值传输至上位机，例如，测试小板可以将检测到的适配器的输出状态上报给上位机。
需要说明的是，在本申请的实施例中，基于上述图2，图3为测试小板的示意图，如图3所示，测试小板中可以集成有MCU和MOS，其中，VBUS为USB电压，GND为电源地。
进一步地，在本申请的实施例中，基于上述图2，图4为测试系统与适配器的连接示意图，如图4所示，测试系统中的测试小板可以与适配器进 行连接，并且可以与适配器进行双向通信。
需要说明的是，在本申请的实施例中，上述测试系统可以通过与上述适配器的连接和通信，模拟适配器对终端进行快充的过程，从而可以直接对适配器的各项参数进行测试，而不再需要通过示波器获取适配器的参数测试结果。
进一步地，在本申请的实施例中，上述测试系统在通过与上述适配器的连接和通信，模拟适配器对终端进行快充的过程中，接收到的上述时钟信号中的首个中断可以为上述适配器与终端进行快速充电过程中的第一个字节，即可以为上述阶段1中的、用于询问是否开启快速充电模式的上述第一指令中的第一个字节。
需要说明的是，在本申请的实施例中，上述时钟信号中的首个中断也可以为上述适配器发送的、用于对上述适配器进行参数检测的测试字节。
进一步地，在本申请的实施例中，上述适配器可以用于对终端进行快速充电，具体地，上述适配器与终端可以通过通用串行总线(Universal Serial Bus，USB)接口相连，该USB接口可以是普通的USB接口，也可以是micro USB接口或Type C接口等。USB接口中的电源线用于上述适配器为终端充电，其中，USB接口中的电源线可以是USB接口中的VBus线和/或地线。USB接口中的数据线用于上述适配器和终端进行双向通信，该数据线可以是USB接口中的D+线和/或D-线，所谓双向通信可以指适配器和终端双方进行信息的交互。
进一步地，在本申请的实施例中，上述适配器可以支持普通充电模式和快速充电模式，其中，快速充电模式的充电电流大于普通充电模式的充电电流，即快速充电模式的充电速度大于所述普通充电模式的充电速度。一般而言，普通充电模式可以理解为额定输出电压为5V，额定输出电流小于等于2.5A的充电模式，此外，在普通充电模式下，适配器输出端口D+和D-可以短路，而快速充电模式下适配器可以利用D+和D-与移动终端进行通信和数据交换。
需要说明的是，在本申请的实施例中，由于上述适配器对终端快充的效果有着较为决定性的作用，因此，对适配器的性能参数测试尤为重要，其中，适配器的性能参数可以包括发送指令的时间参数、输出电压、输出电流等。
需要说明的是，在本申请的实施例中，上述测试系统在与上述适配器建立连接之后，上述适配器可以通过USB接口中的数据线向测试系统发送时钟信号，其中，时钟信号用于指示上述适配器和测试系统之间的通信时序。具体地，上述适配器主动向测试系统发送时钟信号，且上述适配器可以在与测试系统连接的整个过程中保持该时钟信号的发送，从而便可以在该通信时序的控制下与测试系统进行双向通信。
进一步地，在本申请的实施例中，通信时序包括交替产生的上述适配 器的指令发送时段和上述适配器的指令接收时段。
进一步地，在本申请的实施例中，上述测试系统在与上述适配器建立连接之后，上述测试系统可以通过D+数据线接收由上述适配器发送的上述时钟信号。
图5为本申请中时钟信号的示意图，如图5所示，在本申请的实施例中，D+数据线的时钟信号包括低电平和高电平。其中，一个低电平和一个高电平组成一个时钟周期，例如，一个时钟周期包括10us低电平和500us的高电平。
基于上述图5，图6为本申请实施例中传输指令时时钟信号和数据信号的示意图，如图6所示，一方面，适配器向终端发送的每个指令包括8个比特的数据。适配器通过时钟信号的连续的8个时钟周期向移动终端发送8个比特的数据。连续的8个时钟周期中的每个时钟周期的前10us为中断，后500us为数据。另一方面，适配器从接收的每个回复指令包括10个比特的数据，适配器通过时钟信号的连续10个时钟周期从终端接收10个比特的数据，连续的10个时钟周期中的每个时钟周期的前500us为数据，后10us为中断。
进一步地，在本申请的实施例中，上述测试系统可以在与上述适配器建立连接之后，通过接收到的上述时钟信号对指令时间进行测试。
步骤102、获取时钟信号对应的首个有效中断、首个有效中断对应的方波以及首个有效中断对应的下一个有效中断。
在本申请的实施例中，上述测试系统在接收上述适配器发送的上述时钟信号之后，可以采集上述时钟信号对应的首个有效中断、上述首个有效中断对应的方波以及上述首个有效中断对应的下一个有效中断。
进一步地，在本申请的实施例中，上述测试系统在接收上述时钟信号之后，可以对上述时钟信号中的有效中断和方波进行采集，获得上述时钟信号中的第一个有效终端、第一个方波以及第二个有效中断，即可以获得上述首个有效中断、上述首个有效中断对应的上述方波以及上述下一个有效中断。
需要说明的是，在本申请的实施例中，由于上述适配器在上述阶段1发送的第一指令用于对是否开启快充进行确定，因此，上述测试系统在进行指令时间的测试时，需要对上述适配器发送的首个指令进行时序检测，因此需要采集获得上述首个有效中断和上述首个有效中断对应的上述方波。
需要说明的是，在本申请的实施例中，上述测试系统在进行指令时间的测试时，可以通过连续的两个有效中断确定数据传输的间隔时间和持续时间，因此需要采集上述首个有效中断对应的上述下一个有效中断。
步骤103、获取首个有效中断对应的第一下降沿和第一上升沿，获取方波对应的第二下降沿，获取下一个有效中断对应的第三下降沿。
在本申请的实施例中，上述测试系统在采集获得上述首个有效中断、 所述方波以及上述下一个有效中断之后，可以获取上述首个有效中断对应的第一下降沿和第一上升沿，还可以获取上述方波对应的第二下降沿，同时获取上述下一个有效中断对应的第三下降沿。
需要说明的是，在本申请的实施例中，上述测试系统可以根据上述首个有效中断、上述方波以及上述下一个有效中断对上述适配器是否满足指令时序要求进行进一步判定，具体地，上述测试系统可以先对上述首个有效中断、上述方波以及上述下一个有效中断的上升沿和下降沿进行检测，从而可以获得上述首个有效中断的上述第一上升沿和上述第一下降沿，还可以获取上述方波对应的第二下降沿，同时还可以获得上述下一个有效中断对应的上述第三下降沿。
基于上述图6，图7为本申请实施例中有效中断上升沿和下降沿的示意图，如图7所示，测试系统可以采集获取第一个有效中断的上升沿和下降沿，还获取方波对应的下降沿，同时获取第二个有效中断对应的下降沿。
步骤104、根据第一下降沿、第一上升沿、第二下降沿以及第三下降沿，生成指令时间的测试结果。
在本申请的实施例中，上述测试系统在获取上述首个有效中断对应的上述第一下降沿和上述第一上升沿，上述方波对应的上述第二下降沿，上述下一个有效中断对应的上述第三下降沿之后，便可以进一步根据上述第一下降沿、上述第一上升沿、上述第二下降沿以及上述第三下降沿，生成上述测试结果。
进一步地，在本申请的实施例中，上述测试系统在确定出上述第一下降沿、上述第一上升沿、上述第二下降沿以及上述第三下降沿之后，便可以根据上述第一下降沿和上述第一上升沿确定出有效中断的中断时间，还可以根据上述第一下降沿和上述第二下降沿确定出数据的传输时间，同时也可以根据上述第二下降沿和上述第三下降沿确定出间隔时间。
需要说明的是，在本申请的实施例中，上述测试系统在根据上述第一下降沿、上述第一上升沿、上述第二下降沿以及上述第三下降沿，生成上述测试结果时，既可以通过上述测试小板直接获得上述中断时间、上述传输时间以及上述间隔时间，也可以先通过上述测试小板将上述第一下降沿、上述第一上升沿、上述第二下降沿以及上述第三下降沿传输至上述上位机，再通过上述上位机获得上述中断时间、上述传输时间以及上述间隔时间。
需要说明的是，在本申请的实施例中，上述测试结果用于表征对上述适配器对应的时间参数进行测试的结果，具体地，根据上述测试结果可以确定出上述适配器对应的时间参数是否满足时序要求。
进一步地，在本申请的实施例中，上述测试结果中可以包括用于表征有效中断的中断持续时间的第一结果、用于表征指令数据传输的持续时间的第二结果，还可以包括有用于表征传输间隔时间的第三结果。
本申请实施例提供的一种指令时间的测试方法，在与适配器建立连接 之后，测试系统接收适配器发送的时钟信号；其中，时钟信号用于指示指令的传输时间；获取时钟信号对应的首个有效中断、首个有效中断对应的方波以及首个有效中断对应的下一个有效中断；获取首个有效中断对应的第一下降沿和第一上升沿，获取方波对应的第二下降沿，获取下一个有效中断对应的第三下降沿；根据第一下降沿、第一上升沿、第二下降沿以及第三下降沿，生成指令时间的测试结果。由此可见，在本申请的实施例中，测试系统可以在与配置器建立连接之后，根据配置器发送的时钟信号，分别确定进行通信时首个有效中断、方波以及下一个有效中断对应的下降沿和上升沿，从而可以根据时钟信号的上升沿和下降沿，进一步获得适配器对应的指令时间的检测结果。正是由于本申请的测试系统可以在与适配器进行通信时直接对适配器进行指令时间的检测，进而在对适配器进行发送指令的时间检测时，能够减少检测指令数量，简化检测过程，从而可以大大提高检测效率和精度。
基于上述实施例，在本申请的另一实施例中，上述测试系统根据所述第一下降沿、所述第一上升沿、所述第二下降沿以及所述第三下降沿，生成指令时间的测试结果的方法可以包括以下步骤：
步骤104a、根据第一下降沿和第一上升沿，确定中断时间。
在本申请的实施例中，上述测试系统在获取上述首个有效中断对应的上述第一下降沿和上述第一上升沿之后，便可以进一步根据上述第一下降沿和上述第一上升沿，确定中断时间。
需要说明的是，在本申请的实施例中，上述中断时间可以用于表征上述适配器发送的上述时钟信号中的有效中断的中断持续时间，因此，上述测试系统可以先对上述中断时间进行确定，以进一步判断上述适配器的时钟信号是否满足时序要求。
步骤104b、根据第一下降沿和第二下降沿，确定传输时间。
在本申请的实施例中，上述测试系统在获取上述首个有效中断对应的上述第一下降沿和上述方波对应的上述第二下降沿之后，便可以进一步根据上述第一下降沿和上述第二下降沿，确定传输时间。
需要说明的是，在本申请的实施例中，上述传输时间可以用于表征上述适配器发送指令时的数据传输时间，因此，上述测试系统可以先对上述传输时间进行确定，以进一步判断上述适配器的指令时间是否满足时序要求。
需要说明的是，在本申请的实施例中，上述传输时间用于表征一个完整的字节传输所需要的时间，即上述测试系统从接收到一个字节对应的首个有效中断到回复完该字节对应的最后一个比特所持续的时间。
步骤104c、根据第二下降沿和第三下降沿，确定间隔时间。
在本申请的实施例中，上述测试系统在获取上述方波对应的上述第二下降沿和上述下一个有效中断对应的上述第三下降沿之后，便可以进一步 根据上述第二下降沿和上述第三下降沿，确定间隔时间。
需要说明的是，在本申请的实施例中，上述间隔时间可以用于表征上述适配器发送指令时的不同字节之间的传输间隔，因此，上述测试系统可以先对上述间隔时间进行确定，以进一步判断上述适配器的指令时间是否满足时序要求。
进一步地，在本申请的实施例中，上述间隔时间用于表征两个相邻的字节之间的时间间隔，即上述适配器连续发送两个相邻的字节之间的间隔时间。
步骤104d、根据中断时间、传输时间以及间隔时间，确定测试结果。
在本申请的实施例中，上述测试系统在确定上述中断时间、上述传输时间以及上述间隔时间之后，可以根据上述中断时间、上述传输时间以及上述间隔时间，确定上述测试结果。
进一步地，在本申请的实施例中，上述测试系统在根据上述中断时间、上述传输时间以及上述间隔时间，确定上述测试结果时，可以将预先设置的中断阈值、传输阈值以及间隔阈值分别与上述中断时间、上述传输时间以及上述间隔时间进行比较，从而可以根据比较结果确定上述测试结果。
本申请实施例提供的一种指令时间的测试方法，在与适配器建立连接之后，测试系统接收适配器发送的时钟信号；其中，时钟信号用于指示指令的传输时间；获取时钟信号对应的首个有效中断、首个有效中断对应的方波以及首个有效中断对应的下一个有效中断；获取首个有效中断对应的第一下降沿和第一上升沿，获取方波对应的第二下降沿，获取下一个有效中断对应的第三下降沿；根据第一下降沿、第一上升沿、第二下降沿以及第三下降沿，生成指令时间的测试结果。由此可见，在本申请的实施例中，测试系统可以在与配置器建立连接之后，根据配置器发送的时钟信号，分别确定进行通信时首个有效中断、方波以及下一个有效中断对应的下降沿和上升沿，从而可以根据时钟信号的上升沿和下降沿，进一步获得适配器对应的指令时间的检测结果。正是由于本申请的测试系统可以在与适配器进行通信时直接对适配器进行指令时间的检测，进而在对适配器进行发送指令的时间检测时，能够减少检测指令数量，简化检测过程，从而可以大大提高检测效率和精度。
基于上述实施例，在本申请的再一实施例中，上述测试系统根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果之前，即步骤104d之前，上述测试系统进行指令时间的测试方法还可以包括以下步骤：
步骤105、获取预设中断时间阈值、预设传输时间阈值以及预设间隔时间阈值。
在本申请的实施例中，上述测试系统在根据上述中断时间、上述传输时间以及上述间隔时间，生成上述测试结果之前，上述测试系统可以先获 取预设中断时间阈值、预设传输时间阈值以及预设间隔时间阈值。
需要说明的是，在本申请的实施例中，上述预设中断时间阈值、上述预设传输时间阈值以及所述预设间隔时间阈值，可以表征上述适配器对应的时序要求。
进一步地，在本申请的实施例中，上述测试系统可以预先设置上述预设中断时间阈值、上述预设传输时间阈值以及所述预设间隔时间阈值，其中，上述预设中断时间阈值用于表征上述适配器发送时钟信号中的有效中断的时序要求；上述预设传输时间阈值用于表征上述适配器传输数据的时序要求；上述预设间隔时间阈值用于表征上述适配器应该满足的发送两个连续字节的时间间隔的时序要求。
在本申请的实施例中，进一步地，上述测试系统根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果的方法可以包括以下步骤：
步骤201、根据中断时间和预设中断时间阈值，获得第一结果。
在本申请的实施例中，上述测试系统在获得上述中断时间和上述预设中断时间阈值之后，可以进一步根据上述中断时间和上述预设中断时间阈值，获得第一结果。
需要说明的是，在本申请的实施例中，上述测试系统可以将上述中断时间和上述预设中断时间阈值进行比较，从而可以根据比较结果进一步确定上述第一结果。其中，上述第一结果用于确定上述适配器是否满足时钟信号中有效中断的时序要求。
进一步地，在本申请的实施例中，上述测试系统在对上述中断时间和上述预设中断时间阈值进行比较之后，如果上述中断时间大于或者等于上述预设中断时间阈值，那么可以确定上述第一结果为不满足上述时序要求。
进一步地，在本申请的实施例中，上述测试系统在对上述中断时间和上述预设中断时间阈值进行比较之后，如果上述中断时间小于上述预设中断时间阈值，那么可以确定上述第一结果为满足上述时序要求。
步骤202、根据传输时间和预设传输时间阈值，获得第二结果。
在本申请的实施例中，上述测试系统在获得上述传输时间和上述预设传输时间阈值之后，可以进一步根据上述传输时间和上述预设传输时间阈值，获得第二结果。
需要说明的是，在本申请的实施例中，上述测试系统可以将上述传输时间和上述预设传输时间阈值进行比较，从而可以根据比较结果进一步确定上述第二结果。其中，上述第二结果用于确定上述适配器是否满足发送一个字节的时序要求。
进一步地，在本申请的实施例中，上述测试系统在对上述传输时间和上述预设传输时间阈值进行比较之后，如果上述传输时间大于或者等于上述预设传输时间阈值，那么可以确定上述第二结果为不满足上述时序要求。
进一步地，在本申请的实施例中，上述测试系统在对上述传输时间和上述预设传输时间阈值进行比较之后，如果上述传输时间小于上述预设传输时间阈值，那么可以确定上述第二结果为满足上述时序要求。
步骤203、根据间隔时间和预设间隔时间阈值，获得第三结果。
在本申请的实施例中，上述测试系统在获得上述间隔时间和上述预设间隔时间阈值之后，可以进一步根据上述间隔时间和上述预设间隔时间阈值，获得上述第三结果。
需要说明的是，在本申请的实施例中，上述测试系统可以将上述间隔时间和上述预设间隔时间阈值进行比较，从而可以根据比较结果进一步确定上述第三结果。其中，上述第三结果用于确定上述适配器是否满足发送两个连续字节的时间间隔的时序要求。
进一步地，在本申请的实施例中，上述测试系统在对上述间隔时间和上述预设间隔时间阈值进行比较之后，如果上述间隔时间大于或者等于上述预设间隔时间阈值，那么可以确定上述第三结果为不满足上述时序要求。
进一步地，在本申请的实施例中，上述测试系统在对上述间隔时间和上述预设间隔时间阈值进行比较之后，如果上述间隔时间小于上述预设间隔时间阈值，那么可以确定上述第三结果为满足上述时序要求。
步骤204、根据第一结果、第二结果以及第三结果，确定测试结果。
在本申请的实施例中，上述测试系统在获得上述第一结果、上述第二结果以及上述第三结果之后，便可以根据上述第一结果、上述第二结果以及上述第三结果，生成上述适配器对应的测试结果。
需要说明的是，在本申请的实施例中，上述测试结果可以判定上述适配器的时间参数是否满足预设的时序要求，即上述适配器是否满足有效中断的中断时序要求，是否满足发送一个字节的持续时间时序要求，以及上述适配器是否满足发送两个连续字节的时间间隔的时序要求。
本申请实施例提供的一种指令时间的测试方法，在与适配器建立连接之后，测试系统接收适配器发送的时钟信号；其中，时钟信号用于指示指令的传输时间；获取时钟信号对应的首个有效中断、首个有效中断对应的方波以及首个有效中断对应的下一个有效中断；获取首个有效中断对应的第一下降沿和第一上升沿，获取方波对应的第二下降沿，获取下一个有效中断对应的第三下降沿；根据第一下降沿、第一上升沿、第二下降沿以及第三下降沿，生成指令时间的测试结果。由此可见，在本申请的实施例中，测试系统可以在与配置器建立连接之后，根据配置器发送的时钟信号，分别确定进行通信时首个有效中断、方波以及下一个有效中断对应的下降沿和上升沿，从而可以根据时钟信号的上升沿和下降沿，进一步获得适配器对应的指令时间的检测结果。正是由于本申请的测试系统可以在与适配器进行通信时直接对适配器进行指令时间的检测，进而在对适配器进行发送指令的时间检测时，能够减少检测指令数量，简化检测过程，从而可以大 大提高检测效率和精度。
基于上述实施例，本申请的又一实施例中，图8为本申请实施例提出的测试系统的组成结构示意图一，如图8所示，本申请实施例提出的测试系统1可以包括接收部分11，获取部分12以及生成部分13。
所述接收部分11，用于在与适配器建立连接之后，接收所述适配器发送的时钟信号；其中，所述时钟信号用于指示指令的传输时间。
所述获取部分12，用于获取所述时钟信号对应的首个有效中断、所述首个有效中断对应的方波以及所述首个有效中断对应的下一个有效中断；以及获取所述首个有效中断对应的第一下降沿和第一上升沿，获取所述方波对应的第二下降沿，获取所述下一个有效中断对应的第三下降沿。
所述生成部分13，用于根据所述第一下降沿、所述第一上升沿、所述第二下降沿以及所述第三下降沿，生成指令时间的测试结果。
进一步地，在本申请的实施例中，所述生成部分13，具体用于根据所述第一下降沿和所述第一上升沿，确定中断时间；以及根据所述第一下降沿和所述第二下降沿，确定传输时间；以及根据所述第二下降沿和所述第三下降沿，确定间隔时间；以及根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果。
进一步地，在本申请的实施例中，所述获取部分12，还用于根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果之前，获取预设中断时间阈值、预设传输时间阈值以及预设间隔时间阈值；其中，所述预设中断时间阈值、所述预设传输时间阈值以及所述预设间隔时间阈值用于表征所述适配器对应的时序要求。
进一步地，在本申请的实施例中，所述获取部分12，具体用于根据所述中断时间和所述预设中断时间阈值，获得第一结果；以及根据所述传输时间和所述预设传输时间阈值，获得第二结果；以及根据所述间隔时间和所述预设间隔时间阈值，获得第三结果。
所述生成部分13，具体用于根据所述第一结果、所述第二结果以及第三结果，确定所述测试结果。
进一步地，在本申请的实施例中，所述获取部分12，还具体用于当所述中断时间大于或者等于所述预设中断时间阈值时，所述第一结果为不满足所述时序要求；以及当所述中断时间小于所述预设中断时间阈值时，所述第一结果为满足所述时序要求；以及当所述传输时间大于或者等于所述预设传输时间阈值时，所述第二结果为不满足所述时序要求；以及当所述传输时间小于所述预设传输时间阈值时，所述第二结果为满足所述时序要求；以及当所述间隔时间大于或者等于所述预设间隔时间阈值时，所述第三结果为不满足所述时序要求；以及当所述间隔时间小于所述预设间隔时间阈值时，所述第三结果为满足所述时序要求。
图9为本申请实施例提出的测试系统的组成结构示意图二，如图9所 示，本申请实施例提出的测试系统1还可以包括测试小板14、上位机15以及电子负载16。其中，测试小板中集成有处理器、存储有处理器可执行指令的存储器。可选的，上述测试系统1还可以包括通信接口17，和用于连接测试小板14、上位机15、以及电子负载16以及通信接口17的总线18。
进一步地，在本申请的实施例中，上述上位机中也可以集成有处理器和存储器，且与上述测试小板16中的处理器和存储器的作用相同。
在本申请的实施例中，上述处理器可以为特定用途集成电路(Application Specific Integrated Circuit，ASIC)、数字信号处理器(Digital Signal Processor，DSP)、数字信号处理装置(Digital Signal Processing Device，DSPD)、可编程逻辑装置(ProgRAMmable Logic Device，PLD)、现场可编程门阵列(Field ProgRAMmable Gate Array，FPGA)、中央处理器(CentralProcessing Unit，CPU)、控制器、微控制器、微处理器中的至少一种。可以理解地，对于不同的设备，用于实现上述处理器功能的电子器件还可以为其它，本申请实施例不作具体限定。测试系统1还可以包括存储器，该存储器可以与处理器连接，其中，存储器用于存储可执行程序代码，该程序代码包括计算机操作指令，存储器可能包含高速RAM存储器，也可能还包括非易失性存储器，例如，至少两个磁盘存储器。
在本申请的实施例中，存储器，用于存储指令和数据。
进一步地，在本申请的实施例中，上述处理器，用于在与适配器建立连接之后，接收所述适配器发送的时钟信号；其中，所述时钟信号用于指示指令的传输时间；获取所述时钟信号对应的首个有效中断、所述首个有效中断对应的方波以及所述首个有效中断对应的下一个有效中断；获取所述首个有效中断对应的第一下降沿和第一上升沿，获取所述方波对应的第二下降沿，获取所述下一个有效中断对应的第三下降沿；根据所述第一下降沿、所述第一上升沿、所述第二下降沿以及所述第三下降沿，生成指令时间的测试结果。
在实际应用中，上述存储器可以是易失性第一存储器(volatile memory)，例如随机存取第一存储器(Random-Access Memory，RAM)；或者非易失性第一存储器(non-volatile memory)，例如只读第一存储器(Read-Only Memory，ROM)，快闪第一存储器(flash memory)，硬盘(Hard Disk Drive，HDD)或固态硬盘(Solid-State Drive，SSD)；或者上述种类的第一存储器的组合，并向处理器提供指令和数据。
另外，在本实施例中的各功能模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
集成的单元如果以软件功能模块的形式实现并非作为独立的产品进行销售或使用时，可以存储在一个计算机可读取存储介质中，基于这样的理 解，本实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或processor(处理器)执行本实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请实施例提出的一种测试系统，在与适配器建立连接之后，测试系统接收适配器发送的时钟信号；其中，时钟信号用于指示指令的传输时间；获取时钟信号对应的首个有效中断、首个有效中断对应的方波以及首个有效中断对应的下一个有效中断；获取首个有效中断对应的第一下降沿和第一上升沿，获取方波对应的第二下降沿，获取下一个有效中断对应的第三下降沿；根据第一下降沿、第一上升沿、第二下降沿以及第三下降沿，生成指令时间的测试结果。由此可见，在本申请的实施例中，测试系统可以在与配置器建立连接之后，根据配置器发送的时钟信号，分别确定进行通信时首个有效中断、方波以及下一个有效中断对应的下降沿和上升沿，从而可以根据时钟信号的上升沿和下降沿，进一步获得适配器对应的指令时间的检测结果。正是由于本申请的测试系统可以在与适配器进行通信时直接对适配器进行指令时间的检测，进而在对适配器进行发送指令的时间检测时，能够减少检测指令数量，简化检测过程，从而可以大大提高检测效率和精度。
本申请实施例提供第一计算机可读存储介质，其上存储有程序，该程序被处理器执行时实现如上所述的指令时间的测试方法。
具体来讲，本实施例中的一种指令时间的测试方法对应的程序指令可以被存储在光盘，硬盘，U盘等存储介质上，当存储介质中的与一种指令时间的测试方法对应的程序指令被一电子设备读取或被执行时，包括如下步骤：
在与适配器建立连接之后，接收所述适配器发送的时钟信号；其中，所述时钟信号用于指示指令的传输时间；
获取所述时钟信号对应的首个有效中断、所述首个有效中断对应的方波以及所述首个有效中断对应的下一个有效中断；
获取所述首个有效中断对应的第一下降沿和第一上升沿，获取所述方波对应的第二下降沿，获取所述下一个有效中断对应的第三下降沿；
根据所述第一下降沿、所述第一上升沿、所述第二下降沿以及所述第三下降沿，生成指令时间的测试结果。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其 中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的实现流程示意图和/或方框图来描述的。应理解可由计算机程序指令实现流程示意图和/或方框图中的每一流程和/或方框、以及实现流程示意图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在实现流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在实现流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在实现流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。
工业实用性
本申请实施例提供了一种指令时间的测试方法和系统、及计算机存储介质，测试系统在与适配器建立连接之后，在与适配器建立连接之后，测试系统接收适配器发送的时钟信号；其中，时钟信号用于指示指令的传输时间；获取时钟信号对应的首个有效中断、首个有效中断对应的方波以及首个有效中断对应的下一个有效中断；获取首个有效中断对应的第一下降沿和第一上升沿，获取方波对应的第二下降沿，获取下一个有效中断对应的第三下降沿；根据第一下降沿、第一上升沿、第二下降沿以及第三下降沿，生成指令时间的测试结果。由此可见，在本申请的实施例中，测试系统可以在与配置器建立连接之后，根据配置器发送的时钟信号，分别确定进行通信时首个有效中断、方波以及下一个有效中断对应的下降沿和上升沿，从而可以根据时钟信号的上升沿和下降沿，进一步获得适配器对应的指令时间的检测结果。正是由于本申请的测试系统可以在与适配器进行通信时直接对适配器进行指令时间的检测，进而在对适配器进行发送指令的时间检测时，能够减少检测指令数量，简化检测过程，从而可以大大提高检测效率和精度。

Claims (13)

  1. 一种指令时间的测试方法，所述方法包括：
    在与适配器建立连接之后，接收所述适配器发送的时钟信号；
    获取所述时钟信号对应的首个有效中断、所述首个有效中断对应的方波以及所述首个有效中断对应的下一个有效中断；
    获取所述首个有效中断对应的第一下降沿和第一上升沿，获取所述方波对应的第二下降沿，获取所述下一个有效中断对应的第三下降沿；
    根据所述第一下降沿、所述第一上升沿、所述第二下降沿以及所述第三下降沿，生成指令时间的测试结果。
  2. 根据权利要求1所述的方法，其中，所述根据所述第一下降沿、所述第一上升沿、所述第二下降沿以及所述第三下降沿，生成指令时间的测试结果，包括：
    根据所述第一下降沿和所述第一上升沿，确定中断时间；
    根据所述第一下降沿和所述第二下降沿，确定传输时间；
    根据所述第二下降沿和所述第三下降沿，确定间隔时间；
    根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果。
  3. 根据权利要求2所述的方法，其中，所述根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果之前，所述方法还包括：
    获取预设中断时间阈值、预设传输时间阈值以及预设间隔时间阈值；其中，所述预设中断时间阈值、所述预设传输时间阈值以及所述预设间隔时间阈值用于表征所述适配器对应的时序要求。
  4. 根据权利要求3所述的方法，其中，所述根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果，包括：
    根据所述中断时间和所述预设中断时间阈值，获得第一结果；
    根据所述传输时间和所述预设传输时间阈值，获得第二结果；
    根据所述间隔时间和所述预设间隔时间阈值，获得第三结果；
    根据所述第一结果、所述第二结果以及第三结果，确定所述测试结果。
  5. 根据权利要求4所述的方法，其中，所述根据所述中断时间和所述预设中断时间阈值，获得第一结果，包括：
    当所述中断时间大于或者等于所述预设中断时间阈值时，所述第一结果为不满足所述时序要求；
    当所述中断时间小于所述预设中断时间阈值时，所述第一结果为满足所述时序要求。
  6. 根据权利要求4所述的方法，其中，所述根据所述传输时间和所述预设传输时间阈值，获得第二结果，包括：
    当所述传输时间大于或者等于所述预设传输时间阈值时，所述第二结 果为不满足所述时序要求；
    当所述传输时间小于所述预设传输时间阈值时，所述第二结果为满足所述时序要求。
  7. 根据权利要求4所述的方法，其中，所述根据所述间隔时间和所述预设间隔时间阈值，获得第三结果，包括：
    当所述间隔时间大于或者等于所述预设间隔时间阈值时，所述第三结果为不满足所述时序要求；
    当所述间隔时间小于所述预设间隔时间阈值时，所述第三结果为满足所述时序要求。
  8. 一种测试系统，其中，所述测试系统包括：接收部分、获取部分以及生成部分，
    所述接收部分，用于在与适配器建立连接之后，接收所述适配器发送的时钟信号；其中，所述时钟信号用于指示指令的传输时间；
    所述获取部分，用于获取所述时钟信号对应的首个有效中断、所述首个有效中断对应的方波以及所述首个有效中断对应的下一个有效中断；以及获取所述首个有效中断对应的第一下降沿和第一上升沿，获取所述方波对应的第二下降沿，获取所述下一个有效中断对应的第三下降沿；
    所述生成部分，用于根据所述第一下降沿、所述第一上升沿、所述第二下降沿以及所述第三下降沿，生成指令时间的测试结果。
  9. 根据权利要求8所述的测试系统，其中，
    所述生成部分，具体用于根据所述第一下降沿和所述第一上升沿，确定中断时间；以及根据所述第一下降沿和所述第二下降沿，确定传输时间；以及根据所述第二下降沿和所述第三下降沿，确定间隔时间；以及根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果。
  10. 根据权利要求9所述的测试系统，其中，
    所述获取部分，还用于根据所述中断时间、所述传输时间以及所述间隔时间，确定所述测试结果之前，获取预设中断时间阈值、预设传输时间阈值以及预设间隔时间阈值；其中，所述预设中断时间阈值、所述预设传输时间阈值以及所述预设间隔时间阈值用于表征所述适配器对应的时序要求。
  11. 根据权利要求10所述的测试系统，其中，
    所述获取部分，具体用于根据所述中断时间和所述预设中断时间阈值，获得第一结果；以及根据所述传输时间和所述预设传输时间阈值，获得第二结果；以及根据所述间隔时间和所述预设间隔时间阈值，获得第三结果；
    所述生成部分，具体用于根据所述第一结果、所述第二结果以及第三结果，确定所述测试结果；
    所述获取部分，还具体用于当所述中断时间大于或者等于所述预设中断时间阈值时，所述第一结果为不满足所述时序要求；以及当所述中断时 间小于所述预设中断时间阈值时，所述第一结果为满足所述时序要求；以及当所述传输时间大于或者等于所述预设传输时间阈值时，所述第二结果为不满足所述时序要求；以及当所述传输时间小于所述预设传输时间阈值时，所述第二结果为满足所述时序要求；以及当所述间隔时间大于或者等于所述预设间隔时间阈值时，所述第三结果为不满足所述时序要求；以及当所述间隔时间小于所述预设间隔时间阈值时，所述第三结果为满足所述时序要求。
  12. 一种测试系统，其中，所述测试系统包括测试小板、上位机以及电子负载，其中，所述测试小板和所述上位机中集成有处理器、存储有所述处理器可执行指令的存储器，当所述指令被执行时，所述处理器执行时实现如权利要求1-7任一项所述的方法。
  13. 一种计算机可读存储介质，其上存储有程序，应用于测试系统中，其中，所述程序被处理器执行时实现如权利要求1-7任一项所述的方法。
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