WO2020061786A1 - 一种低压差线性稳压系统 - Google Patents

一种低压差线性稳压系统 Download PDF

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Publication number
WO2020061786A1
WO2020061786A1 PCT/CN2018/107454 CN2018107454W WO2020061786A1 WO 2020061786 A1 WO2020061786 A1 WO 2020061786A1 CN 2018107454 W CN2018107454 W CN 2018107454W WO 2020061786 A1 WO2020061786 A1 WO 2020061786A1
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Prior art keywords
fet
effect transistor
field
drain
gate
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PCT/CN2018/107454
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English (en)
French (fr)
Inventor
张�浩
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2018/107454 priority Critical patent/WO2020061786A1/zh
Priority to CN201880002315.6A priority patent/CN111316188B/zh
Publication of WO2020061786A1 publication Critical patent/WO2020061786A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • Embodiments of the present invention relate to a voltage stabilization circuit technology, and in particular, to a low-dropout linear voltage stabilization system.
  • LDO Low Dropout Regulator
  • FET field-effect transistor
  • the LDO includes the main components of a pass element (transistor or FET), a reference voltage, and an error signal amplifier.
  • the applicable condition of the existing low dropout linear regulator is that the input voltage must be higher than the segmentation point Vx of the pass element.
  • the segmentation point Vx is the threshold voltage value of the circuit working between two states. Once the input voltage is lower than the segmentation At Vx, the low-dropout linear regulator will not work properly, or it will show a large resistance between the output and the input. At this time, the charging speed of the load energy storage element (such as a capacitor) is very slow.
  • the fluctuation range of the segmentation point Vx is greatly affected by the process and temperature. Generally, the fluctuation range of the segmentation point Vx is about 0.8V, which seriously affects the normal use of the circuit.
  • the present invention provides a low dropout linear voltage stabilization system to solve the problem of slow charging of the load capacitor when the input voltage is less than the segment point Vx.
  • a low-dropout linear voltage stabilization system includes:
  • Reference voltage circuit receiving the input voltage provided by the power supply, and providing a reference current and a reference voltage
  • a first-level control circuit receives the input voltage and a reference current provided by the reference voltage circuit, and outputs a first control signal.
  • the first-level control circuit has a first segmentation point, and the first segmentation point is greater than the first segmentation point.
  • a secondary control circuit that receives the input voltage and a reference voltage provided by the reference voltage circuit and outputs a second control signal.
  • the secondary control circuit has a second segmentation point, and the second segmentation point changes.
  • the range is smaller than the change range of the first segmentation point;
  • a logic circuit connected to an output terminal of the primary control circuit and an output terminal of the secondary control circuit to receive the first control signal and the second control signal, and to the first control signal and Performing an AND logic operation on the second control signal;
  • the low-dropout linear regulator circuit receives the input voltage and is connected to an output terminal of the logic circuit.
  • the output terminal of the low-dropout linear regulator circuit is used to connect a load.
  • the first-level control circuit includes: a first current mirror that receives the input voltage and the reference current, and outputs a first mirror current, and a mirror ratio of the first mirror current is 1: 1; Two current mirrors receiving the first mirror current and outputting a second mirror current, the ratio of the second mirror current is 1: x, where x is greater than 1; and an inverter connected to the first current mirror With the second current mirror, an output terminal of the inverter is used as an output terminal of the primary control circuit.
  • the first current mirror includes: a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, and a sixth field effect tube, wherein: The source of the first FET and the source of the second FET are connected to the power source to receive the input voltage; the gate of the first FET and the second FET The gate of is connected to the first output terminal of the reference voltage circuit to receive the reference current; the source of the third FET and the source of the fourth FET are respectively connected to the first field The drain of the FET and the drain of the second FET are connected one by one; the gate of the third FET and the gate of the fourth FET are connected to the second of the reference voltage circuit.
  • An output end for receiving the reference current; the source of the fifth FET and the source of the sixth FET are respectively connected to the drain of the third FET and the fourth field effect
  • the drains of the tubes are connected one by one, the gate of the fifth field effect tube is connected to the drain, and the gate of the sixth field effect tube is connected. And drain connections.
  • the second current mirror includes: a seventh field-effect transistor and an eighth field-effect transistor, wherein: a drain of the seventh field-effect transistor and a gate of the seventh field-effect transistor and the fifth The drain of the FET and the gate of the fifth FET are connected; the drain of the eighth FET is connected to the drain of the sixth FET and the sixth FET The grids are all connected; the grid of the seventh FET is connected to the grid of the eighth FET; the source of the seventh FET and the source of the eighth FET are grounded .
  • the inverter includes: a ninth FET, a tenth FET, an eleventh FET, a twelfth FET, and a thirteenth FET, wherein: the ninth The source of the FET is connected to the power source; the drain of the ninth FET and the gate of the ninth FET are connected to the source of the tenth FET; the tenth field effect The drain of the tube and the gate of the tenth field-effect transistor are connected to the source of the eleventh field-effect transistor; the drain of the eleventh field-effect transistor and the The gate is connected to the source of the twelfth field effect transistor; the drain of the twelfth field effect transistor and the gate of the twelfth field effect transistor and the drain of the thirteenth field effect transistor are respectively Electrodes and the gate of the thirteenth field-effect transistor are connected one by one, and the connection point between the drain of the twelfth field-effect transistor and the drain of the thirteenth field-effect transistor is used as the output of the first-level
  • the first-level control circuit further includes a first resistor, one end of the first resistor is connected to a power source, and the other end is connected to the drain of the sixth field-effect transistor, the gate of the sixth field-effect transistor, The source of the eighth field effect transistor, the gate of the twelfth field effect transistor, and the gate of the thirteenth field effect transistor are all connected.
  • the first field effect tube, the second field effect tube, the third field effect tube, the fourth field effect tube, the fifth field effect tube, and the sixth field effect are all P-channel metal-oxide-semiconductor field-effect transistors;
  • the seventh FET, the eighth FET, and the thirteenth FET are all N-channel metal oxide semiconductor field effect transistors.
  • the secondary control circuit includes a resistance component including a second resistance and a third resistance, one end of the second resistance and one end of the third resistance being connected in series, and the other end of the second resistance Connect the power supply, the other end of the third resistor is grounded; the first comparator, the connection point of the second resistor and the third resistor is connected to the positive input terminal of the first comparator, and the reverse input of the first comparator The terminal is connected to the third output terminal of the reference voltage circuit to receive the reference voltage, and the output terminal of the first comparator is used as the output terminal of the secondary control circuit.
  • a resistance component including a second resistance and a third resistance, one end of the second resistance and one end of the third resistance being connected in series, and the other end of the second resistance Connect the power supply, the other end of the third resistor is grounded; the first comparator, the connection point of the second resistor and the third resistor is connected to the positive input terminal of the first comparator, and the reverse input of the first comparator The terminal is connected to the third output terminal of the reference
  • the third output terminal of the reference voltage circuit outputs a reference voltage of 1.2V.
  • the second control signal when the voltage at the forward input terminal of the first comparator is greater than a minimum voltage value required by the reference voltage circuit to fully establish the reference voltage and is less than a second segment point, the second control signal is low Level, when the voltage at the positive input terminal of the first comparator is greater than the second segment point, the second control signal is at a high level.
  • the logic circuit includes: a fourteenth FET, a fifteenth FET, a sixteenth FET, a seventeenth FET, an eighteenth FET, and a nineteenth FET Tube, twentieth field-effect tube, twenty-first field-effect tube, twenty-second field-effect tube, and capacitor, wherein: the source of the fourteenth field-effect tube is connected to a power source; the fourteenth field-effect tube The gate of the tube and the drain of the fourteenth field effect tube are connected to the source of the fifteenth field effect tube; the gate of the fifteenth field effect tube, the fifteenth field effect The drain of the tube and the source of the sixteenth field-effect tube are connected to the gate of the twenty-first field-effect tube; the gate of the sixteenth field-effect tube and the sixteenth field The drain of the FET and the source of the seventeenth FET are connected to the source of the twentieth FET; the drain of the seventeenth FET, and the eighteenth FET The drain of the capacitor, the drain of the twentieth field-effect transistor and the gate
  • the fourteenth FET, the fifteenth FET, the sixteenth FET, the seventeenth FET, and the twentieth FET are all P-channel metal-oxide-semiconductor field-effect transistor, the eighteenth field-effect transistor, the nineteenth field-effect transistor, the twenty-first field-effect transistor, and the twenty-second field-effect transistor are all N-channel metal oxide semiconductor field effect transistor.
  • the low-dropout linear voltage regulator circuit includes: a twenty-third field effect transistor connected to an output end of the logic circuit to receive a signal output by the logic circuit; a twenty-fourth field effect transistor, and The twenty-second field-effect transistor is connected; a resistance component includes a fourth resistor and a fifth resistor connected in series, wherein the fourth resistor is connected to the drain of the twenty-fourth field-effect transistor and the fifth resistor Ground; second comparator, the voltage at the connection point of the fourth resistor and the fifth resistor is used as the forward input terminal of the second comparator, and the reverse input terminal of the second comparator is connected to the reference voltage The third output terminal of the circuit and the output terminal of the second comparator are connected to the gate of the twenty-third field effect transistor.
  • the source of the twenty-third field-effect transistor is connected to a power source
  • the gate of the twenty-third field-effect transistor is connected to an output terminal of the logic circuit
  • the The drain is connected to the source of the twenty-fourth field-effect transistor, its connection point is used as the output terminal of the low-dropout linear voltage regulator circuit, and the gate of the twenty-fourth field-effect transistor is connected to the second Gate of twelve FETs.
  • the twenty-third field effect transistor and the twenty-fourth field effect transistor are P-channel metal oxide semiconductor field effect transistors.
  • the load includes an energy storage element.
  • the first control signal when the input voltage is less than the first segment point, the first control signal is low level, and when the input voltage is greater than the first segment point, the first control signal is high voltage level.
  • the low-dropout linear voltage stabilization system of the embodiment of the present invention uses an AND logic operation on the first control signal and the second control signal to control the fluctuation of the segmentation point Vx of the low-pressure drop linear voltage-stabilization system in a small range. In order to make it less affected by the process and temperature, the low-dropout linear voltage regulator system can quickly load the load capacitor.
  • FIG. 1 is a schematic block diagram of a low-dropout linear voltage stabilization system according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a first-stage control circuit in a low-dropout linear voltage stabilization system according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a secondary control circuit in a low-dropout linear voltage stabilization system according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of a logic circuit of a low-dropout linear voltage stabilization system according to an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a logic circuit in a low-dropout linear voltage stabilization system according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of a low-dropout linear voltage regulator circuit in an embodiment of the low-dropout linear voltage regulator system of the present application.
  • FIG. 7 is a schematic circuit structure diagram of a low-dropout linear voltage stabilization system according to an embodiment of the present application.
  • FIG. 1 is a schematic block diagram of a low-dropout linear voltage regulator system.
  • the low-dropout linear voltage stabilization system includes a reference voltage circuit 110, a primary control circuit 120, a secondary control circuit 130, a logic circuit 140, and a low-dropout linear voltage stabilization circuit 150.
  • the low-dropout linear regulator circuit 150 may be a low-dropout linear regulator circuit that stably outputs a voltage of 2.7V.
  • the present application does not limit the specific specifications and forms of the low-dropout linear voltage regulator circuit 150, and may be a low-dropout linear voltage regulator circuit with stable output higher or lower than a voltage of 2.7V, and the low-dropout linear voltage regulator circuit 150 may be Any type of commercially available LDO chip with external pins can also be a circuit with the equivalent function of these LDO chips and be packaged with other functional circuits and auxiliary circuits to form some kind of chip.
  • the input voltage VIN provides power for the reference voltage circuit 110, the primary control circuit 120, the secondary control circuit 130, the logic circuit 140, and the low-dropout linear voltage stabilization circuit 150, or the reference voltage circuit 110 and the primary control circuit. 120.
  • the secondary control circuit 130, the logic circuit 140, and the low-dropout linear voltage stabilization circuit 150 receive the input voltage VIN.
  • the reference voltage circuit 110 is used to provide a reference current and a reference voltage; the primary control circuit 120 receives the reference current provided by the reference voltage circuit; the secondary control circuit 130 receives the reference voltage provided by the reference voltage circuit; the logic circuit 140 and a
  • the output of the stage control circuit 120 is connected to the output of the stage two control circuit 130 and is used to receive the output of the stage one control circuit 120 and the stage two control circuit 130 to perform an AND logic operation on the two received inputs.
  • the low-dropout linear voltage regulator circuit 150 is connected to the output terminal of the logic circuit 140 and receives the input voltage, and its output terminal charges the load.
  • the reference voltage circuit receives the input voltage (or input power voltage), and outputs one or more reference voltages or reference currents through one or more output terminals to provide the required reference voltage and bias current for different circuits, respectively. Or provide bias voltage and reference current.
  • the reference voltage circuit provides a bias voltage and a bias current to make the first-level control circuit and the second-level control circuit work normally, and the reference voltage circuit provides a reference voltage and a reference current to the first-level control circuit and the second-level control circuit.
  • the control circuit provides a reference value.
  • FIG. 2 is a schematic diagram of an embodiment of a stage control circuit in the low-dropout linear voltage regulator system shown in FIG. 1.
  • the first-level control circuit includes a first field-effect tube MP1, a second field-effect tube MP2, a third field-effect tube MP3, a fourth field-effect tube MP4, a fifth field-effect tube MP5, a sixth field-effect tube MP6, a first Seven field effect transistors MN1, eighth field effect transistors MN2, ninth field effect transistors MP7, tenth field effect transistors MP8, eleventh field effect transistors MP9, twelfth field effect transistors MP10, and thirteenth field effect transistors MN3 And the first resistor R1.
  • the field effect transistor MP6, the ninth field effect transistor MP7, the tenth field effect transistor MP8, the eleventh field effect transistor MP9, and the twelfth field effect transistor MP10 are P-channel metal oxide semiconductor field effect transistors, respectively;
  • the seventh field The effect transistor MN1, the eighth field effect transistor MN2, and the thirteenth field effect transistor MN3 are N-channel metal oxide semiconductor field effect transistors, respectively.
  • the first field-effect tube MP1, the third field-effect tube MP3, the fifth field-effect tube MP5, the second field-effect tube MP2, the fourth field-effect tube MP4, and the sixth field-effect tube MP6 can form a first current mirror.
  • the current mirror ratio is 1: 1.
  • the output current of the first current mirror follows the input current, that is, the value of the output current is equal to the value of the input current.
  • the seventh field-effect transistor MN1 and the eighth field-effect transistor MN2 are formed.
  • the second current mirror 202 has a current mirror ratio of 1: x (x> 1), and the value of the output current of the second current mirror is greater than the value of the input current.
  • the source of the first FET MP1 and the source of the second MOSFET MP2 are both connected to the input voltage VIN; the gate of the first MOSFET MP1 and the gate of the second MOSFET MP2 are connected The first output terminal VBPA of the reference voltage circuit; the source of the third field effect transistor MP3 is connected to the drain of the first field effect transistor MP1, the source of the fourth field effect transistor MP4 and the drain of the second field effect transistor MP2 Connected to improve the mirror accuracy of the first current mirror 201; the gate of the third field effect transistor MP3 and the gate of the fourth field effect transistor MP4 are connected to the second output terminal VBPB of the reference voltage circuit; the first output of the reference voltage circuit The terminal VBPA and the second output terminal VBPAB are used to output a reference current.
  • the source of the fifth field effect transistor MP5 is connected to the drain of the third field effect transistor MP3; the source of the sixth field effect transistor MP6 is connected to the drain of the fourth field effect transistor MP4; the gate of the fifth field effect transistor MP5 The electrode is connected to the drain, and the gate of the sixth field effect transistor MP6 is connected to the drain.
  • the drain of the seventh field effect transistor MN1 and the gate of the seventh field effect transistor MN1 are connected and connected to the drain of the fifth field effect transistor MP5; the drain of the eighth field effect transistor MN2 and the sixth field effect transistor MP6
  • the drain of the seventh field effect transistor MN1 is connected to the gate of the eighth field effect transistor MN2; the source of the seventh field effect transistor MN1 and the source of the eighth field effect transistor MN2 are both Ground.
  • the input voltage VIN is connected to the source of the ninth MOSFET MP7, the drain of the ninth MOSFET MP7 and the gate of the ninth MOSFET MP7 are connected to the source of the tenth MOSFET MP8, and the tenth MOSFET MP8
  • the drain and the gate of the tenth field effect transistor MP8 are connected to the source of the eleventh field effect transistor MP9.
  • the drain of the eleventh field effect transistor MP9 is connected to the gate of the eleventh field effect transistor MP9.
  • the field effect tube MP7, the tenth field effect tube MP8 and the eleventh field effect tube MP9 provide a 5V withstand voltage effect.
  • the source of the twelfth field effect transistor MP10 is connected to the drain and gate of the eleventh field effect transistor MP9, and the drain of the twelfth field effect transistor MP10 is connected to the drain of the thirteenth field effect transistor MN3. Dot serves as the output A of the primary control circuit 120.
  • the ninth field-effect tube MP7, the tenth field-effect tube MP8, the eleventh field-effect tube MP9, the twelfth field-effect tube MP10, and the thirteenth field-effect tube MN3 can form an inverter 203, that is, an inverter
  • the output terminal of 203 is also the output terminal A of the primary control circuit 120.
  • the source of the thirteenth field-effect transistor MN3 is grounded.
  • One end of the first resistor R1 is connected to the input voltage VIN, and the other end is connected to the drain and gate of the sixth MOSFET MP6, the source of the eighth MOSFET MN2, the gate of the twelfth MOSFET MP10, and the thirteen The gates of the field effect transistor MN3 are all connected.
  • the reference voltage circuit 110 provides a bias voltage and a reference current for the primary control circuit, so that the primary control circuit works normally.
  • the first segmentation point of the first-level control circuit is Vx 1.
  • the segmentation point indicates the critical voltage value of the circuit working between two states.
  • the first segmentation point is the operation of the first-level control circuit 120.
  • Threshold voltage in two states also called output two states.
  • FIG. 3 is a schematic diagram of a secondary control circuit.
  • the two-level control circuit includes a second resistor R2, a third resistor R3, and a first comparator EA1.
  • the reference voltage circuit provides a bias current and a reference voltage for the secondary control circuit, so that the secondary control circuit works normally.
  • the second segmentation point of the secondary control circuit is Vx 2 .
  • One end of the second resistor R2 is connected to the input voltage VIN, and the other end is connected to the third resistor R3.
  • the connection point of the second resistor R2 and the third resistor R3 serves as the forward input terminal (labeled "+") of the first comparator EA1.
  • a reverse input terminal (labeled "-") of a comparator EA1 is connected to the third output terminal of the reference voltage circuit, and receives the reference voltage VBG generated by the reference voltage circuit.
  • the reference voltage VBG generated by the reference voltage circuit 110 may be 1.2V.
  • the input voltage VIN is input to the forward input terminal of the first comparator EA1 through the resistor divided voltage to generate the voltage VINP.
  • the voltage VINP is compared with the reference voltage VBG generated by the reference voltage circuit, and the output terminal B outputs the comparison result.
  • the reference voltage circuit 110 is not fully established reference voltage VBG, which is unstable reference voltage VBG, uncertain at this time the output of the comparison result of the first comparator B outputs EA1, when the input voltage VIN is greater than
  • V a the reference voltage is fully established, VBG is stable, and the corresponding output terminal B can output a determined comparison result.
  • V a is the minimum voltage required for the reference voltage circuit to fully establish the reference voltage, and the range of the second segment point Vx 2 is between 3V and 3.2V. In a preferred embodiment, V a can take 1.9V.
  • the comparison result output at the output terminal B is low level.
  • the input voltage VIN is greater than Vx 2
  • the input voltage VIN is divided by the positive input of the resistor R1 and the resistor R2.
  • the terminal voltage VINP is greater than the reference voltage VBG, and the comparison result output from the output terminal B becomes a high level.
  • the comparison result output by the output terminal B is an indeterminate value.
  • the first-level control circuit may be another circuit, for example, it may be a circuit where the first segment point Vx 1 is greater than a minimum voltage value required for the reference voltage circuit to completely establish the reference voltage, which is not limited in this application.
  • the secondary control circuit may be another circuit, for example, it may be a circuit whose variation range of the second segment point Vx 2 is smaller than the variation range of the first segment point Vx 1 , which is not limited in this application.
  • variation range refers to the size of the uncertainty interval caused by the segmentation point affected by the process and temperature of the components in the circuit.
  • FIG. 4 is a functional schematic diagram of the logic circuit shown in FIG. 1.
  • the logic circuit is a circuit capable of implementing AND logic.
  • the logic circuit receives three input signals, namely: a input, which is the input voltage VIN; b input, which is the comparison signal output by the comparator EA1 output terminal B; c input, which is the first-level control output by the first-level control circuit. output signal.
  • the input voltage VIN of channel a rises from 0V to 5V. When the input voltage VIN is less than 2.2V, the output terminal A is low. When the input voltage VIN is greater than 3V, the output terminal A is high.
  • the output terminal A is The uncertain state, that is, the primary control circuit is affected by process parameters and temperature, and its first segment point Vx 1 is an uncertain value between 2.2V and 3V.
  • the output terminal B is an indeterminate value.
  • the input voltage VIN is between 1.9V and Vx 2
  • the output terminal B is low.
  • the output signal B is uncertain.
  • the output terminal B is high.
  • the second segment point Vx 2 is an uncertain value between 3V and 3.2V.
  • the output signal d is obtained, the logic function of "AND” is realized, and the Gate_P signal is generated. Specifically, when the input voltage VIN is less than 3V, the output Gate_P is low, when the input voltage VIN is greater than 3.2V, the output Gate_P is high, and when the input voltage VIN is between 3V and 3.2V, the output Gate_P is not Determine the value. At this time, the logic circuit reduces the variation range of the low-dropout linear voltage regulator system segment point to between 3V and 3.2V.
  • the logic circuit may also be another circuit capable of performing an AND logic operation, which is not limited in the present application.
  • FIG. 5 shows a specific embodiment of the logic circuit.
  • the logic circuit includes: a fourteenth field effect transistor MP11, a fifteenth field effect transistor MP12, a sixteenth field effect transistor MP13, a seventeenth field effect transistor MP14, The eighteenth field effect transistor MN4, the nineteenth field effect transistor MN5, the twentieth field effect transistor MP15, the twenty-first field effect transistor MN6, the twenty-second field effect transistor MN7, and the capacitor C2.
  • the source of the fourteenth MOSFET MP11 is connected to the input voltage, and the gate and drain of the fourteenth MOSFET MP11 are connected to the source of the fifteenth MOSFET MP12;
  • the grid, the drain of the fifteenth field effect transistor MP12, the source of the sixteenth field effect transistor MP13, and the gate of the twenty-first field effect transistor MN6 are connected to each other through a VH connection point;
  • the sixteenth field effect transistor MP13 The drain of the MOSFET, the gate of the sixteenth MOSFET MP13, and the source of the seventeenth MOSFET MP14 are connected to the source of the twentieth MOSFET MP15.
  • the drain of the seventeenth field-effect transistor MP14, the drain of the eighteenth field-effect transistor MN4, the drain of the twentieth field-effect transistor MP15, and the gate of the twenty-second field-effect transistor MN7 are all connected to one end of the capacitor C2, The other end of the capacitor C2 is connected to the input voltage; the gate of the seventeenth field effect transistor MP14 and the gate of the eighteenth field effect transistor MN4 are connected to the output terminal of the first-stage control circuit, and receive the output signal of the first-stage control circuit.
  • the source of the eighteenth MOSFET MN4 is connected to the drain of the nineteenth MOSFET MN5, the source of the nineteenth MOSFET MN5 and the source of the twenty-second MOSFET MN7 are grounded, and the tenth The grid of the nine field effect transistor MN5 and the grid of the twentieth field effect transistor MP15 are connected to the output end of the secondary control circuit, and receive the output signal of the secondary control circuit.
  • the source of the twenty-first field-effect transistor MN6 is connected to the drain of the twenty-second field-effect transistor MN7, and the drain of the twenty-first field-effect transistor MN6 serves as an output terminal of the logic circuit, and outputs a signal Gate_P.
  • the tube MP15 is a P-channel metal oxide semiconductor field effect transistor;
  • the eighteenth field effect transistor MN4, the nineteenth field effect transistor MN5, the twenty-first field effect transistor MN6, and the twenty-second field effect transistor MN7 are respectively N-channel metal oxide semiconductor field effect transistor.
  • the main function of the capacitor C2 is: when the input voltage VIN rises in the low voltage range of 1V to 3V, the signal Gate_SW of the gate of the twenty-second field effect transistor MN7 is quickly coupled to a high level, thereby lowering the level of the signal Gate_P.
  • the main role of the twenty-first field effect transistor MN6 is: when the input voltage VIN reaches 5V, the signal Gate_P will reach 4V, and the twenty-second field effect transistor MN7 is a device withstand voltage 3.3V, so add the twenty-first The field effect transistor MN6 can achieve the withstand voltage under the input voltage VIN of 5V.
  • the fourteenth field effect transistor MP11, the fifteenth field effect transistor MP12, and the sixteenth field effect transistor MP13 are also used to achieve the withstand voltage under the 5V input voltage VIN.
  • FIG. 6 is a schematic diagram of a low-dropout linear voltage regulator circuit.
  • the low-dropout linear voltage regulator circuit includes: a twenty-third field effect transistor MP18, a twenty-fourth field effect transistor MP19, a resistance component, and a second comparator EA2.
  • the resistance component includes a fourth resistor R4 and a fifth resistor R5 connected in series.
  • the source of the twenty-third field effect transistor MP18 is connected to the input voltage VIN, and the gate of the twenty-third field effect transistor MP18 is connected to the output terminal of the logic circuit.
  • the drain of the twenty-third field-effect transistor MP18 is connected to the source of the twenty-fourth field-effect transistor MP19, where the connection point is used as the output terminal VOUT of the low-dropout linear voltage regulator circuit.
  • the gate of the twenty-fourth field effect transistor MP19 is connected to the gate of the twenty-second field effect transistor MN7, and the drain of the twenty-fourth field effect transistor MP19 is grounded through a fourth resistor R4 and a fifth resistor R5 connected in series.
  • the voltage at the connection point of the fourth resistor and the fifth resistor is used as the forward input terminal of the second comparator EA2, and the reverse input terminal of the second comparator EA2 is connected to the third output terminal of the reference voltage circuit, and the second comparator The output terminal is connected to the gate of the twenty-third FET.
  • both the twenty-third field effect transistor and the twenty-fourth field effect transistor are P-channel metal oxide semiconductor field effect transistors.
  • the twenty-third field effect transistor MP18 is a power tube of the output stage of the low-dropout linear voltage regulator circuit.
  • the tube MP19 functions as a switching tube, and the path is opened.
  • the input voltage VIN is greater than the segment point Vx
  • the output VOUT outputs 2.7V.
  • the twenty-fourth field-effect transistor MP19 is turned on to realize the standard low-dropout linear voltage regulator circuit function.
  • the second comparator EA2 compares the output voltage with a reference voltage, and plays a role of negative feedback to regulate the output stability.
  • FIG. 7 is a connection principle diagram of an input voltage, a primary control circuit, a secondary control circuit, a logic circuit, and a low-dropout linear voltage regulator circuit.
  • the input voltage VIN is connected to the primary control circuit, the secondary control circuit, the logic circuit, and the low-dropout linear voltage regulator circuit.
  • the first output terminal and the second output terminal of the reference voltage circuit are respectively connected to the input terminals VBPA and VBPB of the primary control circuit.
  • the third output terminal of the reference voltage circuit is connected to the input terminal VBG of the secondary control circuit and the input terminal of the low dropout linear voltage regulator circuit.
  • the output terminal A of the primary control circuit and the output terminal B of the secondary control circuit are connected to the input of the logic circuit. end.
  • the output end of the logic circuit is connected to the input end of the low dropout linear voltage regulator circuit.
  • the output VOUT of the low-dropout linear regulator circuit charges the load quickly.
  • the low-dropout linear voltage regulator circuits described in the embodiments of the present application may be low-dropout linear voltage regulator circuits of various specifications, and the form may be an LDO chip separately packaged with external pins, and
  • the other circuits of the low-dropout linear voltage stabilization system (such as a first-level control circuit, a second-level control circuit, and a logic circuit) are combined into the low-dropout linear voltage-stabilization system; the low-dropout linear voltage-stabilization circuit can also be combined with other circuits in the system.
  • the circuit is packaged together to form an LDO chip with external pins.
  • the number and setting of external pins may be different from the previous example; of course, the primary control in the low-dropout linear voltage regulator system of this application Circuits, secondary control circuits, logic circuits, and low-dropout linear voltage regulator circuits may not be in the form of separate chips, but integrated into certain functional chips, and connected to certain modules within the functional chip to provide voltage regulation functions .
  • the logical output of the primary control circuit and the secondary control circuit is logically ANDed with a logic circuit, which can quickly charge the load capacitor when the input voltage is smaller than the segment point, and reduce the low voltage.
  • the fluctuation of the segmented point Vx of the differential linear voltage stabilization system is controlled in a smaller range, so that the influence of process and temperature is small.

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Abstract

一种低压差线性稳压系统，包括：基准电压电路（110），其接收电源提供的输入电压（VIN）；一级控制电路（120），接收输入电压（VIN）和基准电压电路（110）提供的基准电流，输出第一控制信号；二级控制电路（130），接收输入电压（VIN）和基准电压电路（110）提供的基准电压，输出第二控制信号；逻辑电路（140），接收第一控制信号和第二控制信号，用于对第一控制信号和第二控制信号进行"与"逻辑运算；低压差线性稳压电路（150），其接收输入电压（VIN）并与逻辑电路（140）的输出端连接，低压差线性稳压电路（150）的输出端用于连接负载。低压差线性稳压系统受工艺和温度的影响较小，能够对负载电容快速充电。

Description

一种低压差线性稳压系统 技术领域
本发明实施例涉及稳压电路技术，尤其涉及一种低压差线性稳压系统。
背景技术
LDO(Low Dropout Regulator，低压差线性稳压器)使用在其线性区域内运行的晶体管或场效应管(FET)，从输入电压中减去超额的电压，以此产生经过调节的输出电压。因其成本低，噪音低，静态电流小的特点，广泛应用于电源电路中。通常，LDO包括通路元件(晶体管或FET)、参考电压和误差信号放大器这几个主要部分。
现有的低压差线性稳压器适用条件为输入电压必须高于通路元件的分段点Vx，分段点Vx是电路工作在两种状态之间的临界电压值，一旦输入电压低于分段点Vx，低压差线性稳压器将无法正常工作，或者在输出与输入之间呈现较大的电阻特性，此时对负载储能元件(比如电容)的充电速度非常慢。并且，分段点Vx的波动范围受工艺和温度影响较大，通常分段点Vx的波动范围在0.8V左右，严重影响电路正常使用。
发明内容
鉴于现有技术的不足，本发明提供了一种低压差线性稳压系统，以解决输入电压小于分段点Vx时，对负载电容充电慢的问题。
根据本发明实施例的第一方面，提供了一种低压差线性稳压系统。该低压差线性稳压电路包括：
基准电压电路，接收电源提供的输入电压，并提供基准电流和基准电压；
一级控制电路，接收所述输入电压和所述基准电压电路提供的基准电流，输出第一控制信号，所述一级控制电路具有第一分段点，所述第一分段点大于所述基准电压电路完全建立所述基准电压所需的最小电压值；
二级控制电路，接收所述输入电压和所述基准电压电路提供的基准电压，并输出第二控制信号，所述二级控制电路具有第二分段点，所述第二分段点的变化范围小于第一分段点的变化范围；
逻辑电路，与所述一级控制电路的输出端和所述二级控制电路的输出端相连，以接收所述第一控制信号和所述第二控制信号，并对所述第一控制信号和所述第二控制信号进行“与”逻辑运算；和
低压差线性稳压电路，其接收所述输入电压并与所述逻辑电路的输出端连接，所述低压差线性稳压电路的输出端用于连接负载。
可选地，所述一级控制电路包括：第一电流镜，接收所述输入电压和所述基准电流，并输出第一镜像电流，所述第一镜像电流的镜像比为1∶1；第二电流镜，接收所述第一镜像电流，并输出第二镜像电流，所述第二镜像电流的比为1∶x，其中x大于1；以及反相器，连接于所述第一电流镜与所述第二电流镜，所述反相器的输出端作为所述一级控制电路的输出端。
可选地，所述第一电流镜包括：第一场效应管、第二场效应管、第三场效应管、第四场效应管、第五场效应管和第六场效应管，其中：所述第一场效应管的源极和所述第二场效应管的源极连接所述电源以接收所述输入电压；所述第一场效应管的栅极和所述第二场效应管的栅极连接所述基准电压电路的第一输出端以接收所述基准电流；所述第三场效应管的源极和所述第四场效应管的源极，分别与所述第一场效应管的漏极和所述第二场效应管的漏极一一连接；所述第三场效应管的栅极和所述第四场效应管的栅极连接所述基准电压电路的第二输出端以接收所述基准电流；所述第五场效应管的源极和所述第六场效应管的源极，分别与所述第三场效应管的漏极和所述第四场效应管的漏极一一连接，所述第五场效应管的栅极和漏极连接，所述第六场效应管的栅极和漏极连接。
可选地，所述第二电流镜包括：第七场效应管和第八场效应管，其中：所述第七场效应管的漏极以及第七场效应管的栅极与所述第五场效应管的漏极以及所述第五场效应管的栅极均连接；所述第八场效应管的漏极与所述第六场效应管的漏极以及所述第六场效应管的栅极均连接；所述第七场效应管的栅极连接所述第八场效应管的栅极；所述第七场效应管的源极与所述第八场效应管的源极均接地。
可选地，所述反相器包括：第九场效应管、第十场效应管、第十一场效应管、第十二场效应管和第十三场效应管，其中：所述第九场效应管的源极连接所述电源；所述第九场效应管的漏极以及所述第九场效应管的栅极连接所述第十场效应管的源极；所述第十场效应管的漏极以及所述第十场效应管的栅极连接所述第十一场效应管的源极；所述第十一场效应管的的漏极以及所述第十一场效应管的栅极连接所述第十二场效应管的源极；所述第十二场效应管的漏极以及所述第十二场效应管的栅极分别与所述第十三场效应管的漏极以及所述第十三场效应管的栅极一一连接，所述第十二场效应管的漏极与所述第十三场效应管的漏极的连接点作为一级控制电路的输出端；所述第十三场效应管的源极接地。
可选地，所述一级控制电路还包括第一电阻，所述第一电阻一端连接电源，另一端与所述第六场效应管的漏极、所述第六场效应管的栅极、所述第八场效应管的源极、所述第十二场效应管的栅极和所述第十三场效应管的栅极均连接。
可选地，所述第一场效应管、所述第二场效应管、所述第三场效应管、所述第四场效应管、所述第五场效应管、所述第六场效应管、所述第九场效应管、所述第十场效应管、所述第十一场效应管、所述第十二场效应管均为P沟道金属氧化物半导体场效应晶体管；所述第七场效应管、所述第八场效应管、所述第十三场效应管均为N沟道金属氧化物半导体场效应晶体管。
可选地，所述二级控制电路包括：电阻部件，所述电阻部件包括第二电阻和第三电阻，所述第二电阻一端和所述第三电阻一端串联，所述第二电阻另一端连接电源，所述第三电阻另一端接地；第一比较器，所述第二电阻和所述第三电阻的连接点连接第一比较器的正向输入端，第一比较器的反向输入端连接所述基准电压电路的第三输出端以接收所述基准电压，第一比较器的输出端作为二级控制电路的输出端。
可选地，所述基准电压电路的第三输出端输出基准电压为1.2V。
可选地，当所述第一比较器的正向输入端的电压大于基准电压电路完全建立所述基准电压所需的最小电压值且小于第二分段点时，所述第二控制信号为低电平，当所述第一比较器的正向输入端的电压大于第二分段点时，所述第二控制信号为高电平。
可选地，所述逻辑电路包括：第十四场效应管、第十五场效应管、第十六场效应管、第十七场效应管、第十八场效应管、第十九场效应管、第二十场效应管、第二十一场效应管、第二十二场效应管和电容，其中：所述第十四场效应管的源极连接电源；所述第十四场效应管的栅极以及所述第十四场效应管的漏极与所述第十五场效应管的源极均连接；所述第十五场效应管的栅极、所述第十五场效应管的漏极以及所述第十六场效应管的源极与所述第二十一场效应管的栅极均连接；所述第十六场效应管的栅极、所述第十六场效应管的漏极以及所述第十七场效应管的源极与所述第二十场效应管的源极均连接；所述第十七场效应管的漏极、第十八场效应管的漏极、所述第二十场效应管的漏极以及所述第二十二场效应管的栅极与所述电容一端均连接，电容另一端连接所述电源；所述第十七场效应管的栅极以及所述第十八场效应管的栅极连接一级控制电路的输出端；所述第十八场效应管的源极连接所述第十九场效应管的漏极；所述第十九场效应管的源极以及所述第二十二场效应管的源极接地；所述第十九场效应管的栅极、所述第二十场效应管的栅极与所述二级控制电路的输出端连接；所述第二十一场效应管的源极连接所述第二十二场效应管的漏极；所述第二十一场效应管的漏极作为所述逻辑电路的输出端。
可选地，所述第十四场效应管、所述第十五场效应管、所述第十六场效应管、所述第十七场效应管、所述第二十场效应管均为P沟道金属氧化物半导体场效应晶体管，所述第十八场效应管、所述第十九场效应管、所述第二十一场效应管、所述第二十二场效应管均为N沟道金属氧化物半导体场效应晶体管。
可选地，所述低压差线性稳压电路包括：第二十三场效应管，与所述逻辑电路的输出端连接，用来接收逻辑电路输出的信号；第二十四场效应管，与所述第二十二场效应管连接；电阻部件，包括串联的第四电阻和第五电阻，其中所述第四电阻连接所述第二十四场效应管的漏极，所述第五电阻接地；第二比较器，所述第四电阻和所述第五电阻的连接点的电压作为所述第二比较器的正向输入端，第二比较器的反向输入端连接所述基准电压电路的第三输出端，第二比较器的输出端与所述第二十三场效应管的栅极连接。
可选地，所述第二十三场效应管的源极连接电源，所述第二十三场效应 管的栅极连接所述逻辑电路的输出端，所述第二十三场效应管的漏极与所述第二十四场效应管的源极连接，其连接点作为所述低压差线性稳压电路的输出端，所述第二十四场效应管的栅极连接所述第二十二场效应管的栅极。
可选地，所述第二十三场效应管、所述第二十四场效应管为P沟道金属氧化物半导体场效应晶体管。
可选地，所述负载包括储能元件。
可选地，当所述输入电压小于第一分段点时，所述第一控制信号为低电平，当所述输入电压大于第一分段点时，所述第一控制信号为高电平。
本发明实施例的低压差线性稳压系统，采用对第一控制信号和第二控制信号进行“与”逻辑运算，将低压差线性稳压系统的分段点Vx的波动控制在较小的范围内，使其受工艺和温度的影响较小，实现低压差线性稳压系统对负载电容快速充电的功能。
附图说明
图1为本申请实施方式低压差线性稳压系统的示意框图；
图2为本申请实施例低压差线性稳压系统中的一级控制电路的示意图；
图3为本申请实施例低压差线性稳压系统中的二级控制电路的结构示意图；
图4为本申请实施例低压差线性稳压系统的的逻辑电路的原理图；
图5为本申请实施例的低压差线性稳压系统中的逻辑电路的结构示意图；
图6为本申请低压差线性稳压系统中一个实施例的低压差线性稳压电路的示意图；以及
图7为本申请实施例的低压差线性稳压系统的电路结构示意图。
具体实施方式
为使得本发明实施例的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明实施例一部分实施例，而非全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创 造性劳动前提下所获得的所有其他实施例，都属于本发明实施例保护的范围。
图1为低压差线性稳压系统的示意框图。如图1所示，在一个实施例中，低压差线性稳压系统包括基准电压电路110、一级控制电路120、二级控制电路130、逻辑电路140和低压差线性稳压电路150。其中，低压差线性稳压电路150可以是稳定输出2.7V电压的低压差线性稳压电路。当然，本申请对于低压差线性稳压电路150的具体规格、形式不做限制，可以是稳定输出高于或者低于2.7V电压的低压差线性稳压电路，低压差线性稳压电路150可以是市场上可售的任何型号的具有外部管脚的LDO芯片，也可以是具有这些LDO芯片同等功能的电路而与其他功能电路、辅助电路封装形成某种芯片。
具体的，通过输入电压VIN为基准电压电路110、一级控制电路120、二级控制电路130、逻辑电路140和低压差线性稳压电路150提供电源，或者说基准电压电路110、一级控制电路120、二级控制电路130、逻辑电路140和低压差线性稳压电路150接收输入电压VIN。基准电压电路110用于提供基准电流和基准电压；一级控制电路120接收所述基准电压电路提供的基准电流；二级控制电路130接收所述基准电压电路提供的基准电压；逻辑电路140与一级控制电路120的输出端和二级控制电路130的输出端相连，用于接收一级控制电路120的输出和二级控制电路130的输出，以对接收的两个输入进行“与”逻辑运算，并对应输出逻辑运算结果；低压差线性稳压电路150连接逻辑电路140的输出端，并接收所述输入电压，其输出端对负载进行充电。
基准电压电路接收输入电压(或者称作输入电源电压)，通过一个或者多个输出端输出一路或者多路基准电压或基准电流，以分别为不同的电路提供所需的基准电压、偏置电流，或者提供偏置电压、基准电流。在本申请实施例中，基准电压电路提供偏置电压和偏置电流，使一级控制电路和二级控制电路正常工作，基准电压电路提供基准电压和基准电流，为一级控制电路和二级控制电路提供一个参考值。
图2为图1所示低压差线性稳压系统中的一级控制电路的一种实施例的示意图。该一级控制电路包括：第一场效应管MP1、第二场效应管MP2、第三场效应管MP3、第四场效应管MP4、第五场效应管MP5、第六场效应管MP6、第七场效应管MN1、第八场效应管MN2、第九场效应管MP7、第十 场效应管MP8、第十一场效应管MP9、第十二场效应管MP10、第十三场效应管MN3和第一电阻R1。
在本实施例一种可选的电路结构中，第一场效应管MP1、第二场效应管MP2、第三场效应管MP3、第四场效应管MP4、第五场效应管MP5、第六场效应管MP6、第九场效应管MP7、第十场效应管MP8、第十一场效应管MP9、第十二场效应管MP10分别为P沟道金属氧化物半导体场效应晶体管；第七场效应管MN1、第八场效应管MN2、第十三场效应管MN3分别为N沟道金属氧化物半导体场效应晶体管。其中，第一场效应管MP1、第三场效应管MP3、以及第五场效应管MP5与第二场效应管MP2、第四场效应管MP4以及第六场效应管MP6可以组成第一电流镜201，其电流镜像比例为1∶1，第一电流镜的输出电流跟随输入电流，也就是输出电流的值等于输入电流的值；第七场效应管MN1与所述第八场效应管MN2形成第二电流镜202，电流镜像比例为1∶x(x＞1)，第二电流镜的输出电流的值大于输入电流的值。
具体的，第一场效应管MP1的源极和第二场效应管MP2的源极，均与输入电压VIN连接；第一场效应管MP1的栅极和第二场效应管MP2的栅极连接基准电压电路的第一输出端VBPA；第三场效应管MP3的源极和第一场效应管MP1的漏极连接，第四场效应管MP4的源极和第二场效应管MP2的漏极连接，以提高第一电流镜201的镜像精度；第三场效应管MP3的栅极和第四场效应管MP4的栅极连接基准电压电路的第二输出端VBPB；基准电压电路的第一输出端VBPA和第二输出端VBPAB用来输出基准电流。第五场效应管MP5的源极和第三场效应管MP3的漏极连接；第六场效应管MP6的源极和第四场效应管MP4的漏极连接；第五场效应管MP5的栅极与漏极相连，第六场效应管MP6的栅极与漏极相连。第七场效应管MN1的漏极以及第七场效应管MN1的栅极相连，并连接到第五场效应管MP5的漏极；第八场效应管MN2的漏极与第六场效应管MP6的漏极相连接；第七场效应管MN1的栅极连接所述第八场效应管MN2的栅极；第七场效应管MN1的源极与所述第八场效应管MN2的源极均接地。输入电压VIN连接第九场效应管MP7的源极，第九场效应管MP7的漏极以及第九场效应管MP7的栅极连接第十场效应管MP8的源极，第十场效应管MP8的漏极以及第十场效应管MP8的栅极连接第十一场效应管MP9的源极，第十一场效应管MP9的漏极与第 十一场效应管MP9的栅极连接，第九场效应管MP7、第十场效应管MP8和第十一场效应管MP9提供5V耐压的作用。第十二场效应管MP10的源极连接第十一场效应管MP9的漏极和栅极，第十二场效应管MP10的漏极与第十三场效应管MN3的漏极连接，其中连接点作为一级控制电路120的输出端A。其中，第九场效应管MP7、第十场效应管MP8、第十一场效应管MP9、第十二场效应管MP10和第十三场效应管MN3可以组成反相器203，即反相器203的输出端也是一级控制电路120的输出端A。第十三场效应管MN3的源极接地。第一电阻R1一端连接输入电压VIN，另一端与第六场效应管MP6的漏极和栅极、第八场效应管MN2的源极、第十二场效应管MP10的栅极和第十三场效应管MN3的栅极均连接。
基准电压电路110为一级控制电路提供偏置电压和基准电流，使一级控制电路正常工作。一级控制电路的第一分段点为Vx 1，本文中，分段点表示的是电路工作在两种状态之间的临界电压值，例如第一分段点即是一级控制电路120工作在两种状态(或者称为输出两种状态)的临界电压。当输入电压VIN在1～Vx 1之间时，基准电压电路110的基准电流尚未建立起来，此时，在电阻R1的作用下，A_N被拉至高电平，经过反相器203的作用，一级控制电路120的输出端A为低电平；当输入电压大于第一分段点Vx 1时，基准电流完全建立起来，由于第二电流镜的镜像比例为MN1∶MN2＝1∶x(x＞1)，在一种优选的实施例中，x可以是16，此时A_N被拉至低电平，一级控制电路输出端A为高电平。由于一级控制电路受温度和工艺影响较大，第一分段点Vx 1在2.2V～3V之间变动，当输入电压VIN正好处于2.2V～3V这个范围之内时，输出端A的输出为不确定值，所以通过一级控制电路120只能保证在输入电压VIN小于2.2V时，输出端A的输出可确定为低电平，输入电压VIN高于3V时，输出端A的输出可确定为高电平。可以看出，第一分段点Vx 1的范围变化较大。本申请通过二级控制电路和逻辑电路来进一步将低压差线性稳压系统的分段点的变化范围缩小。图3为二级控制电路的示意图。二级控制电路包括：第二电阻R2、第三电阻R3和第一比较器EA1。
基准电压电路为二级控制电路提供偏置电流和基准电压，使二级控制电路正常工作。二级控制电路的第二分段点为Vx 2。第二电阻R2一端连接输入电压VIN，另一端连接第三电阻R3，第二电阻R2和第三电阻R3的连接点 作为第一比较器EA1的正向输入端(标记为“+”)，第一比较器EA1的反向输入端(标记为“-”)连接基准电压电路的第三输出端，接收基准电压电路产生的基准电压VBG。在一种可选的实施例中，基准电压电路110产生的基准电压VBG可以为1.2V。输入电压VIN经过电阻分压产生电压VINP输入到第一比较器EA1的正向输入端，由此，电压VINP与基准电压电路产生的基准电压VBG进行比较，输出端B输出比较结果。当输入电压VIN小于V a时，基准电压电路110没有完全建立基准电压VBG，也就是基准电压VBG不稳定，此时第一比较器EA1的输出端B输出的比较结果不定，当输入电压VIN大于V a时，基准电压完全建立，VBG稳定，对应的输出端B可以输出确定的比较结果。V a是基准电压电路完全建立基准电压所需的最小电压值，第二分段点Vx 2的范围在3V～3.2V之间。在一种优选的实施例中，V a可以取1.9V。输入电压VIN大于1.9V且小于Vx 2时，输出端B输出的比较结果为低电平，当输入电压VIN大于Vx 2时，输入电压VIN在经过电阻R1和电阻R2分压所得的正向输入端电压VINP大于基准电压VBG，输出端B输出的比较结果变为高电平。当输入电压VIN在3V～3.2V之间时，输出端B输出的比较结果为不确定值。
可选地，一级控制电路可以是其他电路，比如，可以是第一分段点Vx 1大于基准电压电路完全建立基准电压所需的最小电压值的电路，本申请对此不作限制。
可选地，二级控制电路可以是其他电路，比如，可以是第二分段点Vx 2的变化范围小于第一分段点Vx 1的变化范围的电路，本申请对此不作限制。应理解，对于“变化范围”，指的是分段点受电路中元件的工艺以及温度影响而产生的不确定区间的大小。
图4是图1所示逻辑电路的功能示意图。在本实施例中，逻辑电路是能实现“与”逻辑的电路。逻辑电路接收三路输入信号，分别为：a路输入，为输入电压VIN；b路输入，为比较器EA1输出端B输出的比较信号；c路输入，为一级控制电路输出的一级控制输出信号。a路的输入电压VIN从0V上升到5V。当输入电压VIN小于2.2V时，输出端A为低电平，当输入电压VIN大于3V时，输出端A为高电平，当输入电压VIN在2.2V～3V之间时，输出端A为不确定状态，也就是一级控制电路受工艺参数和温度的影响，其 第一分段点Vx 1为2.2V～3V之间的一个不确定值。当输入电压VIN在1V～1.9V之间时，输出端B为不确定值，当输入电压VIN在1.9V～Vx 2之间时，输出端B为低电平，当输入电压VIN在3V～3.2V之间时，输出信号B不确定，当输入电压VIN大于Vx 2时，输出端B为高电平。此时第二分段点Vx 2在3V～3.2V之间的一个不确定值。输出信号A和B经过逻辑电路140后，得到输出信号d，实现了“与”的逻辑功能，产生Gate_P信号。具体的，当输入电压VIN小于3V时，输出Gate_P为低电平，当输入电压VIN大于3.2V时，输出Gate_P为高电平，输入电压VIN在3V～3.2V之间时，输出Gate_P为不确定值，此时，逻辑电路将低压差线性稳压系统分段点的变化范围缩小为3V～3.2V之间。
可选地，逻辑电路也可以是其他能够实现“与”逻辑运算的其他电路，本申请对此不作限制。
图5所示为该逻辑电路的一个具体实施例，逻辑电路包括：第十四场效应管MP11、第十五场效应管MP12、第十六场效应管MP13、第十七场效应管MP14、第十八场效应管MN4、第十九场效应管MN5、第二十场效应管MP15、第二十一场效应管MN6、第二十二场效应管MN7和电容C2。
具体的，第十四场效应管MP11的源极连接输入电压，第十四场效应管MP11的栅极以及漏极连接第十五场效应管MP12的源极；第十五场效应管MP12的栅极、第十五场效应管MP12的漏极以及第十六场效应管MP13的源极与第二十一场效应管MN6的栅极通过VH连接点相互连接；第十六场效应管MP13的漏极、第十六场效应管MP13的栅极以及第十七场效应管MP14的源极与第二十场效应管MP15的源极均连接。第十七场效应管MP14的漏极、第十八场效应管MN4的漏极、第二十场效应管MP15的漏极以及第二十二场效应管MN7的栅极均连接电容C2一端，电容C2另一端连接输入电压；第十七场效应管MP14的栅极以及第十八场效应管MN4的栅极连接一级控制电路的输出端，接收一级控制电路的输出信号。第十八场效应管MN4的源极连接所述第十九场效应管MN5的漏极，第十九场效应管MN5的源极以及第二十二场效应管MN7的源极接地，第十九场效应管MN5的栅极以及第二十场效应管MP15的栅极连接二级控制电路的输出端，接收二级控制电路的输出信号。第二十一场效应管MN6的源极连接第二十二场效应管MN7的漏极， 第二十一场效应管MN6的漏极作为所述逻辑电路的输出端，并输出信号Gate_P。
在本实施例一种可选的电路结构中，第十四场效应管MP11、第十五场效应管MP12、第十六场效应管MP13、第十七场效应管MP14、第二十场效应管MP15分别为P沟道金属氧化物半导体场效应晶体管；第十八场效应管MN4、第十九场效应管MN5、第二十一场效应管MN6、第二十二场效应管MN7分别为N沟道金属氧化物半导体场效应晶体管。
电容C2的主要作用为：输入电压VIN在低电压域1V～3V上升时，将第二十二场效应管MN7栅极的信号Gate_SW快速耦合至高电平，从而拉低信号Gate_P电平。第二十一场效应管MN6的主要作用为：当输入电压VIN达到5V时，信号Gate_P将会达到4V，第二十二场效应管MN7为耐压3.3V的器件，因此添加第二十一场效应管MN6可实现5V输入电压VIN下的耐压，第十四场效应管MP11，第十五场效应管MP12，第十六场效应管MP13也是为了实现5V输入电压VIN下的耐压。
图6是低压差线性稳压电路原理图。低压差线性稳压电路包括：第二十三场效应管MP18、第二十四场效应管MP19、电阻部件和第二比较器EA2。其中，电阻部件包括串联的第四电阻R4、第五电阻R5。
具体的，第二十三场效应管MP18的源极连接输入电压VIN，第二十三场效应管MP18的栅极连接逻辑电路的输出端。第二十三场效应管MP18的漏极与第二十四场效应管MP19的源极连接，其中，连接点作为低压差线性稳压电路的输出端VOUT。第二十四场效应管MP19的栅极连接第二十二场效应管MN7的栅极，第二十四场效应管MP19的漏极通过串联的第四电阻R4和第五电阻R5接地。第四电阻和第五电阻的连接点的电压作为第二比较器EA2的正向输入端，第二比较器EA2的反向输入端连接所述基准电压电路的第三输出端，第二比较器的输出端与第二十三场效应管的栅极连接。
可选地，第二十三场效应管、第二十四场效应管均为P沟道金属氧化物半导体场效应晶体管。
第二十三场效应管MP18为低压差线性稳压电路输出级的功率管，在输出跟随输入时，为防止在第四电阻R4和第五电阻R5通路上漏电，添加第二十四场效应管MP19作为开关管，将该通路断开。在输入电压VIN大于分段 点Vx时，输出端VOUT输出2.7V，此时第二十四场效应管MP19导通，实现标准的低压差线性稳压电路功能。第二比较器EA2比较输出电压和基准电压，起到负反馈调节输出稳定的作用。
图7是输入电压、一级控制电路、二级控制电路、逻辑电路和低压差线性稳压电路的连接原理图。输入电压VIN连接一级控制电路、二级控制电路、逻辑电路和低压差线性稳压电路，基准电压电路的第一输出端和第二输出端分别连接一级控制电路的输入端VBPA和VBPB，基准电压电路的第三输出端连接二级控制电路的输入端VBG和低压差线性稳压电路的输入端，一级控制电路的输出端A和二级控制电路的输出端B连接逻辑电路的输入端。逻辑电路的输出端与低压差线性稳压电路的输入端连接。低压差线性稳压电路的输出端VOUT对负载快速充电。
需要说明的是，本申请各实施方式中所描述的低压差线性稳压电路可以是各种规格的低压差线性稳压电路，其形态可以是一颗单独封装具有外接引脚的LDO芯片，与低压差线性稳压系统的其他电路(比如一级控制电路、二级控制电路、逻辑电路等)组合成所述的低压差线性稳压系统；低压差线性稳压电路还可以与系统中的其他电路一起封装形成一颗具有外接引脚的LDO芯片，此种情况下外接引脚的数量和设置与前一例子可能会存在区别；当然，本申请的低压差线性稳压系统中的一级控制电路、二级控制电路、逻辑电路、低压差线性稳压电路也可以不是单独的芯片形态，而是统一整合到某些功能芯片中，与功能芯片内的某些模块进行连接以提供稳压功能。
本发明的实施方式，通过逻辑电路，将一级控制电路和二级控制电路的输出结果进行“与”的逻辑功能，能够在输入电压小于分段点时，对负载电容快速充电，并且将低压差线性稳压系统的分段点Vx的波动控制在较小的范围内，使得受工艺和温度的影响较小。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述电路结构亦可以采用其他相同逻辑的器件实现。最后应说明的是：以上实施例仅用以说明本发明实施例的技术方案，而非对其限制；尽管参照前述实施例对本发明实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离 本发明各实施例技术方案的精神和范围。

Claims (17)

  1. 一种低压差线性稳压系统，其特征在于，包括：
    基准电压电路，接收电源提供的输入电压，并提供基准电流和基准电压；
    一级控制电路，接收所述输入电压和所述基准电压电路提供的基准电流，输出第一控制信号，所述一级控制电路具有第一分段点，所述第一分段点大于所述基准电压电路完全建立所述基准电压所需的最小电压值；
    二级控制电路，接收所述输入电压和所述基准电压电路提供的基准电压，并输出第二控制信号，所述二级控制电路具有第二分段点，所述第二分段点的变化范围小于第一分段点的变化范围；
    逻辑电路，与所述一级控制电路的输出端和所述二级控制电路的输出端相连，以接收所述第一控制信号和所述第二控制信号，并对所述第一控制信号和所述第二控制信号进行“与”逻辑运算；和
    低压差线性稳压电路，其接收所述输入电压并与所述逻辑电路的输出端连接，所述低压差线性稳压电路的输出端用于连接负载。
  2. 根据权利要求1所述的低压差线性稳压系统，其中，所述一级控制电路包括：
    第一电流镜，接收所述输入电压和所述基准电流，并输出第一镜像电流，所述第一镜像电流的镜像比为1∶1；
    第二电流镜，接收所述第一镜像电流，并输出第二镜像电流，所述第二镜像电流的比为1∶x，其中x大于1；以及
    反相器，连接于所述第一电流镜与所述第二电流镜，所述反相器的输出端作为所述一级控制电路的输出端。
  3. 根据权利要求2所述的低压差线性稳压系统，其中，所述第一电流镜包括：
    第一场效应管、第二场效应管、第三场效应管、第四场效应管、第五场效应管和第六场效应管，其中：
    所述第一场效应管的源极和所述第二场效应管的源极连接所述电源以接收所述输入电压；
    所述第一场效应管的栅极和所述第二场效应管的栅极连接所述基准电压电路的第一输出端以接收所述基准电流；
    所述第三场效应管的源极和所述第四场效应管的源极，分别与所述第一场效应管的漏极和所述第二场效应管的漏极一一连接；
    所述第三场效应管的栅极和所述第四场效应管的栅极连接所述基准电压电路的第二输出端以接收所述基准电流；
    所述第五场效应管的源极和所述第六场效应管的源极，分别与所述第三场效应管的漏极和所述第四场效应管的漏极一一连接；
    所述第五场效应管的栅极和漏极连接，所述第六场效应管的栅极和漏极连接。
  4. 根据权利要求3所述的低压差线性稳压系统，其中，所述第二电流镜包括：第七场效应管和第八场效应管，其中：
    所述第七场效应管的漏极以及所述第七场效应管的栅极与所述第五场效应管的漏极以及所述第五场效应管的栅极均连接；
    所述第八场效应管的漏极与所述第六场效应管的漏极以及所述第六场效应管的栅极均连接；
    所述第七场效应管的栅极连接所述第八场效应管的栅极；
    所述第七场效应管的源极与所述第八场效应管的源极均接地。
  5. 根据权利要求4所述的低压差线性稳压系统，其中，所述反相器包括：第九场效应管、第十场效应管、第十一场效应管、第十二场效应管和第十三场效应管，其中：
    所述第九场效应管的源极连接所述电源；
    所述第九场效应管的漏极以及所述第九场效应管的栅极连接所述第十场效应管的源极；
    所述第十场效应管的漏极以及所述第十场效应管的栅极连接所述第十一场效应管的源极；
    所述第十一场效应管的的漏极以及所述第十一场效应管的栅极连接所述第十二场效应管的源极；
    所述第十二场效应管的漏极以及所述第十二场效应管的栅极分别与所述第十三场效应管的漏极以及所述第十三场效应管的栅极一一连接，所述第十二场效应管的漏极与所述第十三场效应管的漏极的连接点作为一级控制电路的输出端；
    所述第十三场效应管的源极接地。
  6. 根据权利要求5所述的低压差线性稳压系统，其中，所述一级控制电路还包括第一电阻，所述第一电阻一端连接电源，另一端与所述第六场效应管的漏极、所述第六场效应管的栅极、所述第八场效应管的源极、所述第十二场效应管的栅极和所述第十三场效应管的栅极均连接。
  7. 根据权利要求3-5任意一项所述的低压差线性稳压系统，其中，
    所述第一场效应管、所述第二场效应管、所述第三场效应管、所述第四场效应管、所述第五场效应管、所述第六场效应管、所述第九场效应管、所述第十场效应管、所述第十一场效应管、所述第十二场效应管均为P沟道金属氧化物半导体场效应晶体管；以及
    所述第七场效应管、所述第八场效应管、所述第十三场效应管均为N沟道金属氧化物半导体场效应晶体管。
  8. 根据权利要求1所述的低压差线性稳压系统，其中，所述二级控制电路包括：
    电阻部件，所述电阻部件包括第二电阻和第三电阻，所述第二电阻一端和所述第三电阻一端串联，所述第二电阻另一端连接电源，所述第三电阻另一端接地；
    第一比较器，所述第二电阻和所述第三电阻的连接点连接第一比较器的正向输入端，第一比较器的反向输入端连接所述基准电压电路的第三输出端以接收所述基准电压，第一比较器的输出端作为二级控制电路的输出端。
  9. 根据权利要求8所述的低压差线性稳压系统，其中，所述基准电压电路的第三输出端输出基准电压为1.2V。
  10. 根据权利要求8或9所述的低压差线性稳压系统，其中，当所述第一比较器的正向输入端的电压大于基准电压电路完全建立所述基准电压所需的最小电压值且小于第二分段点时，所述第二控制信号为低电平，当所述第一比较器的正向输入端的电压大于第二分段点时，所述第二控制信号为高电平。
  11. 根据权利要求1所述的低压差线性稳压系统，其中，所述逻辑电路包括：
    第十四场效应管、第十五场效应管、第十六场效应管、第十七场效应管、 第十八场效应管、第十九场效应管、第二十场效应管、第二十一场效应管、第二十二场效应管和电容，其中：
    所述第十四场效应管的源极连接电源；
    所述第十四场效应管的栅极以及所述第十四场效应管的漏极与所述第十五场效应管的源极均连接；
    所述第十五场效应管的栅极、所述第十五场效应管的漏极以及所述第十六场效应管的源极与所述第二十一场效应管的栅极均连接；
    所述第十六场效应管的栅极、所述第十六场效应管的漏极以及所述第十七场效应管的源极与所述第二十场效应管的源极均连接；
    所述第十七场效应管的漏极、所述第十八场效应管的漏极、所述第二十场效应管的漏极以及所述第二十二场效应管的栅极与所述电容一端均连接，所述电容另一端连接所述电源；
    所述第十七场效应管的栅极以及所述第十八场效应管的栅极连接一级控制电路的输出端；
    所述第十八场效应管的源极连接所述第十九场效应管的漏极；
    所述第十九场效应管的源极以及所述第二十二场效应管的源极接地；
    所述第十九场效应管的栅极、所述第二十场效应管的栅极与所述二级控制电路的输出端连接；
    所述第二十一场效应管的源极连接所述第二十二场效应管的漏极；
    所述第二十一场效应管的漏极作为所述逻辑电路的输出端。
  12. 根据权利要求11所述的低压差线性稳压系统，其中，
    所述第十四场效应管、所述第十五场效应管、所述第十六场效应管、所述第十七场效应管、所述第二十场效应管均为P沟道金属氧化物半导体场效应晶体管；以及
    所述第十八场效应管、所述第十九场效应管、所述第二十一场效应管、所述第二十二场效应管均为N沟道金属氧化物半导体场效应晶体管。
  13. 根据权利要求11或12所述的低压差线性稳压系统，其中，所述低压差线性稳压电路包括：
    第二十三场效应管，与所述逻辑电路的输出端连接，用来接收逻辑电路输出的信号；
    第二十四场效应管，与所述第二十二场效应管连接；
    电阻部件，包括串联的第四电阻和第五电阻，其中所述第四电阻连接所述第二十四场效应管的漏极，所述第五电阻接地；
    第二比较器，所述第四电阻和所述第五电阻的连接点的电压作为所述第二比较器的正向输入端，第二比较器的反向输入端连接所述基准电压电路的第三输出端，第二比较器的输出端与所述第二十三场效应管的栅极连接。
  14. 根据权利要求13所述的低压差线性稳压系统，其中，
    所述第二十三场效应管的源极连接电源，所述第二十三场效应管的栅极连接所述逻辑电路的输出端，所述第二十三场效应管的漏极与所述第二十四场效应管的源极连接，其连接点作为所述低压差线性稳压电路的输出端，所述第二十四场效应管的栅极连接所述第二十二场效应管的栅极。
  15. 根据权利要求13或14所述的低压差线性稳压系统，其中，
    所述第二十三场效应管、所述第二十四场效应管为P沟道金属氧化物半导体场效应晶体管。
  16. 根据权利要求1-15任意一项所述的低压差线性稳压系统，其中，所述负载包括储能元件。
  17. 根据权利要求1-16任意一项所述的低压差线性稳压系统，其中，当所述输入电压小于第一分段点时，所述第一控制信号为低电平，当所述输入电压大于第一分段点时，所述第一控制信号为高电平。
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