WO2020057371A1 - 一种电压转脉宽调制信号电路 - Google Patents

一种电压转脉宽调制信号电路 Download PDF

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WO2020057371A1
WO2020057371A1 PCT/CN2019/104381 CN2019104381W WO2020057371A1 WO 2020057371 A1 WO2020057371 A1 WO 2020057371A1 CN 2019104381 W CN2019104381 W CN 2019104381W WO 2020057371 A1 WO2020057371 A1 WO 2020057371A1
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width modulation
voltage
modulation signal
signal
pwm1
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朱金桥
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上海客益电子有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

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  • the invention relates to the field of integrated circuits, and in particular to a voltage-to-pulse-width-modulated (PWM) circuit of an integrated algorithm in the field of analog signal processing.
  • PWM voltage-to-pulse-width-modulated
  • the invention provides a voltage-to-pulse-width modulation signal circuit, which is a negative feedback system integrated with an integration circuit.
  • the precision is high, the system is stable, and calibration is easy.
  • the present invention provides a voltage-to-pulse-width modulation signal circuit, including:
  • Integrating filter its positive input terminal inputs the external input voltage signal Vin, its negative input terminal inputs the high-frequency pulse width modulation signal PWM1, and its output terminal outputs the voltage signal V INTEG ;
  • the dual-channel clock signal generating circuit has a voltage signal V INTEG at its input terminal and a first clock signal CLK0 and a second clock signal CLK1 at its output terminal;
  • Algorithm circuit whose input terminal inputs the first clock signal CLK0 and the second clock signal CLK1, and its output terminal outputs the high frequency pulse width modulation signal PWM1 and the frequency modulation pulse width modulation signal PWM2, and the average duty cycle of the high frequency pulse width modulation signal PWM1.
  • the average duty cycle of the high-frequency pulse width modulation signal PWM1 is equal to the average duty cycle of the frequency-modulated pulse width modulation signal PWM2.
  • the integration filter includes: an operational amplifier, a first resistor and a second resistor connected in series to a negative input terminal of the operational amplifier, a first integrating capacitor connected in series between a negative input terminal and an output terminal of the operational amplifier, and one end connected to the first resistor And a second resistor, a second integrating capacitor grounded at the other end;
  • the positive input terminal of the operational amplifier inputs the external input voltage signal Vin, and the negative input terminal thereof receives the feedback signal V FB , that is, the high-frequency pulse width modulation signal PWM1, and the output terminal outputs the voltage signal V INTEG .
  • the dual-channel clock signal generating circuit includes:
  • a fixed-frequency oscillator that outputs a second clock signal CLK1 of a fixed frequency
  • the voltage-controlled oscillator has a voltage signal V INTEG at its input, and the voltage-controlled oscillator adaptively adjusts and outputs a first clock signal CLK0 with an appropriate frequency under the control of the voltage signal V INTEG .
  • the output end of the algorithm circuit also outputs an FM pulse width modulation signal PWM2, and the average duty cycle of the FM pulse width modulation signal PWM2 is equal to the average duty cycle of the high frequency pulse width modulation signal PWM1.
  • the algorithm circuit includes:
  • the FM PWM algorithm module has an input terminal that inputs a first clock signal CLK0 and a second clock signal CLK1, and an output terminal that outputs the FM pulse width modulation signal PWM2 as an output signal of the entire voltage-to-pulse width modulation signal circuit for subsequent stages. Circuit use
  • the high-frequency pulse width modulation algorithm module has an input terminal that inputs a first clock signal CLK0 and a second clock signal CLK1, and an output terminal that outputs a high-frequency pulse width modulation signal PWM1 to the negative input terminal of the integration filter 101 for system feedback. control.
  • the algorithmic relationship between the average duty cycle of the high-frequency pulse width modulation signal PWM1 and the first clock signal CLK0 and the second clock signal CLK1 includes:
  • DUTY is the average duty cycle
  • T0 is the period of the first clock signal CLK0
  • T1 is the period of the second clock signal CLK1
  • k 1 / 2n
  • n is an integer.
  • the average voltage of the high-frequency pulse width modulation signal PWM1 is equal to the voltage value of the external input voltage signal Vin inputted from its positive input terminal:
  • Vin is the external input voltage
  • V REF + is the high level of the high-frequency pulse width modulation signal PWM1
  • V REF- is the low level of the high-frequency pulse width modulation signal PWM1.
  • the frequency of the high-frequency pulse-width modulation signal PWM1 and the frequency of the frequency-modulated pulse-width modulation signal PWM2 are multiples.
  • the frequency of the high-frequency pulse-width modulation signal PWM1 is F
  • the frequency of the frequency-modulated pulse-width modulation signal PWM2 is F / m
  • m is an integer .
  • the invention is a negative feedback system integrated with an integration circuit, which has high accuracy, stable system and easy calibration.
  • FIG. 1 is a circuit diagram of a voltage-to-pulse-width modulation signal circuit provided by the present invention.
  • FIG. 2 is a circuit diagram of an integration filter.
  • FIG. 3 is a circuit diagram of a dual-channel clock signal generating circuit.
  • FIG. 4 is a circuit diagram of an algorithm circuit.
  • the present invention provides a voltage-to-pulse-width modulation signal circuit, including:
  • the integration filter 101 has a positive input terminal inputting an external input voltage signal Vin, a negative input terminal inputting a high-frequency pulse width modulation signal PWM1, and an output terminal outputting a voltage signal V INTEG ;
  • the dual-channel clock signal generating circuit 102 has a voltage signal V INTEG at its input terminal and a first clock signal CLK0 and a second clock signal CLK1 at its output terminal.
  • the algorithm circuit 103 has an input terminal that inputs a first clock signal CLK0 and a second clock signal CLK1, and an output terminal that outputs a high-frequency pulse width modulation signal PWM1 and a frequency-modulated pulse width modulation signal PWM2.
  • the input voltage signal Vin is connected to the positive input terminal of the integration filter 101.
  • the voltage signal V INTEG output by the integrator circuit controls the dual clock signal generation circuit 102 to generate two clock signals, namely the first clock signal CLK0 and the second clock signal CLK1.
  • two pulse width modulation signals are generated, namely the high frequency pulse width modulation signal PWM1 and the frequency modulation pulse width modulation signal PWM2, and the high frequency pulse width modulation signal PWM1 is connected to the negative input signal of the integrator. End, to realize the negative feedback closed-loop control of the entire circuit.
  • the average duty cycle of the pulse width modulation signal (PWM) has an algorithmic relationship with the two clock signals, and the pulse width modulation signal (PWM) frequency can be amplified according to the application requirements while maintaining the algorithmic relationship.
  • the integration filter 101 includes: an operational amplifier 202, a first resistor 204 and a second resistor 206 connected in series to a negative input terminal of the operational amplifier 202, and connected in series between a negative input terminal and an output terminal of the operational amplifier 202.
  • the first integrating capacitor 203 and the second integrating capacitor 205 connected to the first resistor 204 and the second resistor 206 at one end and the ground to the other end.
  • the resistor-capacitor string in the integrating filter realizes the function of a low-pass filter. The effect can be to insert more resistance-capacitor strings at the input (such as the connection between the first resistor and the first integration capacitor).
  • the function of the integration filter is: the first input signal is a voltage signal, the second input signal is a PWM signal, and the output signal is a voltage signal.
  • the average voltage of the second input signal PWM signal is equal to the first The voltage value of an input signal.
  • the positive input terminal of the operational amplifier 202 inputs an external input voltage signal Vin, the negative input terminal thereof receives a feedback signal V FB , that is, the high-frequency pulse width modulation signal PWM1, and the output terminal thereof outputs a voltage signal V INTEG .
  • the dual clock signal generating circuit 102 includes:
  • a fixed frequency oscillator 302 which outputs a second clock signal CLK1 of a fixed frequency
  • the voltage-controlled oscillator 303 has a voltage signal V INTEG at its input, and the voltage-controlled oscillator 303 adaptively adjusts and outputs a first clock signal CLK0 with an appropriate frequency under the control of the voltage signal V INTEG .
  • the algorithm circuit 103 includes:
  • the FM pulse width modulation algorithm module 402 has an input terminal inputting a first clock signal CLK0 and a second clock signal CLK1, and an output terminal outputting the FM pulse width modulation signal PWM2 as an output signal of the entire voltage-to-pulse width modulation signal circuit for later use.
  • the high-frequency pulse-width modulation algorithm module 403 has an input terminal that inputs a first clock signal CLK0 and a second clock signal CLK1, and an output terminal that outputs a high-frequency pulse-width modulation signal PWM1 to the negative input terminal of the integration filter 101, which is used in the system. Feedback control.
  • the average duty cycle of the high frequency pulse width modulation signal PWM1 is equal to the average duty cycle of the frequency modulated pulse width modulation signal PWM2.
  • the average duty cycle of the high-frequency pulse width modulation signal PWM1 has a fixed algorithm relationship with the periods of the first clock signal CLK0 and the second clock signal CLK1:
  • DUTY is the average duty cycle
  • T0 is the period of the first clock signal CLK0
  • T1 is the period of the second clock signal CLK1
  • k 1 / 2n
  • n is an integer.
  • the integration filter 101 makes the average voltage of the high-frequency PWM signal PWM1 equal to the external input voltage:
  • Vin is the external input voltage
  • V REF + is the high level of the high-frequency pulse width modulation signal PWM1
  • V REF- is the low level of the high-frequency pulse width modulation signal PWM1.
  • the average duty cycle of the high-frequency pulse width modulation signal PWM1 and the average duty cycle of the frequency-modulated pulse width modulation signal PWM2 have a linear relationship with the external input voltage, which realizes a high-precision frequency-adjustable voltage-to-pulse-width modulation signal ( PWM) output.
  • the frequency of the high-frequency pulse-width modulation signal PWM1 and the frequency of the frequency-modulated pulse-width modulation signal PWM2 are multiples.
  • the frequency of the high-frequency pulse-width modulation signal PWM1 is F
  • the frequency of the frequency-modulated pulse-width modulation signal PWM2 is F / m
  • m is an integer. The value of m can be adjusted according to the requirements of the subsequent circuit.
  • the invention is a negative feedback system integrated with an integration circuit, which has high accuracy, stable system and easy calibration.

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Abstract

一种电压转脉宽调制信号电路，包含：积分滤波器（101），其正输入端输入外部输入电压信号Vin，其负输入端输入高频脉宽调制信号PWM1，其输出端输出电压信号VINTEG；双路时钟信号产生电路（102），其输入端输入电压信号VINTEG，其输出端输出第一时钟信号CLK0和第二时钟信号CLK1；算法电路（103），其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出高频脉宽调制信号PWM1和调频脉宽调制信号PWM2，高频脉宽调制信号PWM1的平均占空比与第一时钟信号CLK0和第二时钟信号CLK1的周期存在固定的算法关系，高频脉宽调制信号PWM1的平均占空比等于调频脉宽调制信号PWM2的平均占空比。上述电路是一种集成了积分电路的负反馈系统，精度较高，系统稳定，且易于校准。

Description

一种电压转脉宽调制信号电路 技术领域
本发明涉及集成电路领域，尤其涉及在模拟信号处理领域中的一种集成算法的电压转脉宽调制信号(PWM)电路。
背景技术
在很多工业控制系统中，一大类应用中需要通过模拟信号对终端设备进行控制，而且终端则经常以PWM信号作为控制方式；另一类常见的应用是模拟信号对终端控制时，为了保证互相之间的安全和抗干扰，往往会对模拟信号进行隔离，而模拟信号的隔离也是通过“电压‐PWM‐隔离‐PWM‐电压”的方式实现，所以一种高可靠、高精度的电压转PWM技术被广泛需求。
目前主流的电压转PWM技术有两种，一为通过分立元器件组成的模拟电路实现，二为通过集成ADC的单片机芯片实现。前者元器件众多，运算放大器、电容、电阻等都会引入误差，从而导致系统精度不高，并且校准困难。后者的单片机是基于程序运行，系统容易受到干扰而导致不稳定，片上集成的ADC的性能也不够乐观，所以在应用环境比较复杂和干扰较多时，系统的精度十分不可控。
发明的公开
本发明提供一种电压转脉宽调制信号电路，是一种集成了积分电路的负反馈系统，精度较高，系统稳定，且易于校准。
为了达到上述目的，本发明提供一种电压转脉宽调制信号电路，包含：
积分滤波器，其正输入端输入外部输入电压信号Vin，其负输入端输入高频脉宽调制信号PWM1，其输出端输出电压信号V INTEG；
双路时钟信号产生电路，其输入端输入电压信号V INTEG，其输出端输出第一时钟信号CLK0和第二时钟信号CLK1；
算法电路，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其 输出端输出高频脉宽调制信号PWM1和调频脉宽调制信号PWM2，高频脉宽调制信号PWM1的平均占空比与第一时钟信号CLK0和第二时钟信号CLK1的周期存在固定的算法关系，高频脉宽调制信号PWM1的平均占空比等于调频脉宽调制信号PWM2的平均占空比。
所述的积分滤波器包含：运算放大器，串联在运算放大器负输入端的第一电阻和第二电阻，串联在运算放大器负输入端和输出端之间的第一积分电容，以及一端连接第一电阻和第二电阻，另一端接地的第二积分电容；
运算放大器的正输入端输入外部输入电压信号Vin，其负输入端输入反馈信号V FB，即高频脉宽调制信号PWM1，其输出端输出电压信号V INTEG。
所述的双路时钟信号产生电路包含：
固定频率振荡器，其输出固定频率的第二时钟信号CLK1；
压控振荡器，其输入端输入电压信号V INTEG，在电压信号V INTEG的控制下压控振荡器自适应调节输出具有合适频率的第一时钟信号CLK0。
所述的算法电路的输出端还输出调频脉宽调制信号PWM2，调频脉宽调制信号PWM2的平均占空比等于高频脉宽调制信号PWM1的平均占空比。
所述的算法电路包含：
调频脉宽调制算法模块，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出调频脉宽调制信号PWM2作为整个电压转脉宽调制信号电路的输出信号，以供后级电路使用；
高频脉宽调制算法模块，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出高频脉宽调制信号PWM1给积分滤波器101的负输入端，用于系统的反馈控制。
所述的高频脉宽调制信号PWM1的平均占空比与第一时钟信号CLK0和第二时钟信号CLK1的算法关系包含：
DUTY PWM1＝DUTY PWM2＝k×T0/T1；
DUTY PWM1＝DUTY PWM2＝1‐k×T0/T1；
DUTY PWM1＝DUTY PWM2＝(1‐k×T0/T1)×2；
其中，DUTY是平均占空比，T0是第一时钟信号CLK0的周期，T1是第二时钟信号CLK1的周期，k＝1/2 n，变量n为整数。
高频脉宽调制信号PWM1的平均电压等于其正输入端输入的外部输入 电压信号Vin的电压值：
Vin＝V FB＝PWM1平均值＝DUTY PWM1×V REF++(1‐DUTY PWM1)×V REF‐；
其中，Vin是外部输入电压，V REF+是高频脉宽调制信号PWM1的高电平，V REF‐是高频脉宽调制信号PWM1的低电平。
高频脉宽调制信号PWM1的平均占空比和调频脉宽调制信号PWM2的平均占空比与外部输入电压呈线性关系：DUTY PWM1＝DUTY PWM2＝(Vin‐V REF‐)/(V REF+‐V REF‐)。
高频脉宽调制信号PWM1的频率与调频脉宽调制信号PWM2的频率呈倍数关系，高频脉宽调制信号PWM1的频率为F，调频脉宽调制信号PWM2的频率为F/m，m为整数。
本发明是一种集成了积分电路的负反馈系统，精度较高，系统稳定，且易于校准。
附图的简要说明
图1是本发明提供的一种电压转脉宽调制信号电路的电路图。
图2是积分滤波器的电路图。
图3是双路时钟信号产生电路的电路图。
图4是算法电路的电路图。
实现本发明的最佳方式
以下根据图1～图4，具体说明本发明的较佳实施例。
如图1所示，本发明提供一种电压转脉宽调制信号电路，包含：
积分滤波器101，其正输入端输入外部输入电压信号Vin，其负输入端输入高频脉宽调制信号PWM1，其输出端输出电压信号V INTEG；
双路时钟信号产生电路102，其输入端输入电压信号V INTEG，其输出端输出第一时钟信号CLK0和第二时钟信号CLK1；
算法电路103，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出高频脉宽调制信号PWM1和调频脉宽调制信号PWM2。
输入电压信号Vin连接到积分滤波器101的正输入端，积分器电路输出的电压信号V INTEG控制双路时钟信号产生电路102产生两路时钟信号，即第 一时钟信号CLK0和第二时钟信号CLK1，两路时钟信号通过算法电路103后产生两路脉宽调制信号，即高频脉宽调制信号PWM1和调频脉宽调制信号PWM2，高频脉宽调制信号PWM1接入到积分器的负输入信号端，实现整个电路的负反馈闭环控制。脉宽调制信号(PWM)的平均占空比与两路时钟信号存在算法关系，可以在保持算法关系的情况下，根据应用需要实现脉宽调制信号(PWM)频率的放大。
如图2所示，所述的积分滤波器101包含：运算放大器202，串联在运算放大器202负输入端的第一电阻204和第二电阻206，串联在运算放大器202负输入端和输出端之间的第一积分电容203，以及一端连接第一电阻204和第二电阻206，另一端接地的第二积分电容205，积分滤波器中的电阻电容串实现了低通滤波器的功能，为了优化滤波的效果可以在输入端插入更多的电阻电容串(如第一电阻和第一积分电容的连接方式)。所述的积分滤波器的功能为：第一输入信号为一路电压信号，第二输入信号为PWM信号，输出信号为电压信号，在系统正常工作时，第二输入信号PWM信号的平均电压等于第一输入信号的电压值。
运算放大器202的正输入端输入外部输入电压信号Vin，其负输入端输入反馈信号V FB，即高频脉宽调制信号PWM1，其输出端输出电压信号V INTEG。
如图3所示，所述的双路时钟信号产生电路102包含：
固定频率振荡器302，其输出固定频率的第二时钟信号CLK1；
压控振荡器303，其输入端输入电压信号V INTEG，在电压信号V INTEG的控制下压控振荡器303自适应调节输出具有合适频率的第一时钟信号CLK0。
如图4所示，所述的算法电路103包含：
调频脉宽调制算法模块402，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出调频脉宽调制信号PWM2作为整个电压转脉宽调制信号电路的输出信号，以供后级电路使用；
高频脉宽调制算法模块403，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出高频脉宽调制信号PWM1给积分滤波器101的负输入端，用于系统的反馈控制。
高频脉宽调制信号PWM1的平均占空比等于调频脉宽调制信号PWM2的平均占空比。
高频脉宽调制信号PWM1的平均占空比与第一时钟信号CLK0和第二时钟信号CLK1的周期存在固定的算法关系：
DUTY PWM1＝DUTY PWM2＝k×T0/T1；
或者，DUTY PWM1＝DUTY PWM2＝1‐k×T0/T1；
或者，DUTY PWM1＝DUTY PWM2＝(1‐k×T0/T1)×2；
其中，DUTY是平均占空比，T0是第一时钟信号CLK0的周期，T1是第二时钟信号CLK1的周期，k＝1/2 n，变量n为整数。
积分滤波器101使得高频脉宽调制信号PWM1的平均电压等于外部输入电压：
Vin＝V FB＝PWM1平均值＝DUTY PWM1×V REF++(1‐DUTY PWM1)×V REF‐；
其中，Vin是外部输入电压，V REF+是高频脉宽调制信号PWM1的高电平，V REF‐是高频脉宽调制信号PWM1的低电平。
则DUTY PWM1＝DUTY PWM2＝(Vin‐V REF‐)/(V REF+‐V REF‐)；
即，高频脉宽调制信号PWM1的平均占空比和调频脉宽调制信号PWM2的平均占空比与外部输入电压呈线性关系，实现了高精度的频率可调的电压转脉宽调制信号(PWM)输出。
以DUTY PWM1＝DUTY PWM2＝(1‐T0/T1)×2为例，设V REF‐＝0V，则Vin＝(1‐T0/T1)×2×V REF++0V；当Vin＝V REF+，则DUTY PWM1＝DUTY PWM2＝100％，T0/T1＝0.5；当Vin＝0V，则DUTY PWM1＝DUTY PWM2＝0％，T0/T1＝1；当Vin＝V REF+/2，则DUTY PWM1＝DUTY PWM2＝50％，T0/T1＝0.75。
高频脉宽调制信号PWM1的频率与调频脉宽调制信号PWM2的频率呈倍数关系，高频脉宽调制信号PWM1的频率为F，调频脉宽调制信号PWM2的频率为F/m，m为整数，m值可以根据后级电路的需求调整。
本发明是一种集成了积分电路的负反馈系统，精度较高，系统稳定，且易于校准。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (9)

  1. 一种电压转脉宽调制信号电路，其特征在于，包含：
    积分滤波器(101)，其正输入端输入外部输入电压信号Vin，其负输入端输入高频脉宽调制信号PWM1，其输出端输出电压信号V INTEG；
    双路时钟信号产生电路(102)，其输入端输入电压信号V INTEG，其输出端输出第一时钟信号CLK0和第二时钟信号CLK1；
    算法电路(103)，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出高频脉宽调制信号PWM1，高频脉宽调制信号PWM1的平均占空比与第一时钟信号CLK0和第二时钟信号CLK1的周期存在算法关系。
  2. 如权利要求1所述的电压转脉宽调制信号电路，其特征在于，所述的积分滤波器(101)包含：运算放大器(202)，串联在运算放大器(202)负输入端的第一电阻(204)和第二电阻(206)，串联在运算放大器(202)负输入端和输出端之间的第一积分电容(203)，以及一端连接第一电阻(204)和第二电阻(206)，另一端接地的第二积分电容(205)；
    运算放大器(202)的正输入端输入外部输入电压信号Vin，其负输入端输入反馈信号V FB，即高频脉宽调制信号PWM1，其输出端输出电压信号V INTEG。
  3. 如权利要求1所述的电压转脉宽调制信号电路，其特征在于，所述的双路时钟信号产生电路(102)包含：
    固定频率振荡器(302)，其输出固定频率的第二时钟信号CLK1；
    压控振荡器(303)，其输入端输入电压信号V INTEG，在电压信号V INTEG的控制下压控振荡器(303)自适应调节输出具有合适频率的第一时钟信号CLK0。
  4. 如权利要求1所述的电压转脉宽调制信号电路，其特征在于，所述的算法电路(103)的输出端还输出调频脉宽调制信号PWM2，调频脉宽调制信号PWM2的平均占空比等于高频脉宽调制信号PWM1的平均占空比。
  5. 如权利要求4所述的电压转脉宽调制信号电路，其特征在于，所述的算法 电路(103)包含：
    调频脉宽调制算法模块(402)，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出调频脉宽调制信号PWM2作为整个电压转脉宽调制信号电路的输出信号，以供后级电路使用；
    高频脉宽调制算法模块(403)，其输入端输入第一时钟信号CLK0和第二时钟信号CLK1，其输出端输出高频脉宽调制信号PWM1给积分滤波器(101)的负输入端，用于系统的反馈控制。
  6. 如权利要求1所述的电压转脉宽调制信号电路，其特征在于，所述的高频脉宽调制信号PWM1的平均占空比与第一时钟信号CLK0和第二时钟信号CLK1的算法关系包含：
    DUTY PWM1＝DUTY PWM2＝K×T0/T1；
    DUTY PWM1＝DUTY PWM2＝1-K×T0/T1；
    DUTY PWM1＝DUTY PWM2＝(1-k×T0/T1)×2；
    其中，DUTY是平均占空比，T0是第一时钟信号CLK0的周期，T1是第二时钟信号CLK1的周期，k＝1/2 n，变量n为整数。
  7. 如权利要求1所述的电压转脉宽调制信号电路，其特征在于，高频脉宽调制信号PWM1的平均电压等于其正输入端输入的外部输入电压信号Vin的电压值：
    Vin＝V FB＝PWM1平均值＝DUTY PWM1×V REF++(1-DUTY PWM1)×V REF-；
    其中，Vin是外部输入电压，V REF+是高频脉宽调制信号PWM1的高电平，V REF-是高频脉宽调制信号PWM1的低电平。
  8. 如权利要求6所述的电压转脉宽调制信号电路，其特征在于，高频脉宽调制信号PWM1的平均占空比和调频脉宽调制信号PWM2的平均占空比与外部输入电压呈线性关系：DUTY PWM1＝DUTY PWM2＝(Vin-V REF-)/(V REF+-V REF-)。
  9. 如权利要求4所述的电压转脉宽调制信号电路，其特征在于，高频脉宽调制信号PWM1的频率与调频脉宽调制信号PWM2的频率呈倍数关系，高频脉宽调制信号PWM1的频率为F，调频脉宽调制信号PWM2的频率为F/m，m为整数。
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