WO2020048537A1 - Procédé et dispositif de codage en cascade - Google Patents

Procédé et dispositif de codage en cascade Download PDF

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Publication number
WO2020048537A1
WO2020048537A1 PCT/CN2019/104786 CN2019104786W WO2020048537A1 WO 2020048537 A1 WO2020048537 A1 WO 2020048537A1 CN 2019104786 W CN2019104786 W CN 2019104786W WO 2020048537 A1 WO2020048537 A1 WO 2020048537A1
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code
subsequence
codeword
length
coding
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PCT/CN2019/104786
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Chinese (zh)
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张华滋
李榕
王献斌
皇甫幼睿
童佳杰
王俊
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the field of coding, and in particular, to a method and an apparatus for concatenated coding.
  • Polar codes are a structured channel coding method that has been theoretically strictly proven to reach the channel capacity. In recent years, it has been widely used and made great progress. However, with the rapid evolution of wireless communication systems, some new features will emerge in future communication systems (eg, 5G). For example, high-reliability and low-latency communication (URLLC), which is one of the three most typical three communication scenarios in 5G, has very high requirements for the reliability and delay of data transmission.
  • the most popular decoding method for polar codes is a serial cancellation list (SCL) decoding algorithm.
  • SCL decoding algorithm is judged and outputted bit by bit during decoding. The decoding delay is relatively large and needs to be further optimized.
  • the present application provides a method and a device for cascade coding, which can reduce the decoding delay of a polar code.
  • a concatenated coding method includes: group coding an information bit sequence to obtain a plurality of first codewords having a code length B, where B ⁇ 1 and an integer; The first codeword undergoes n-level polarization coding to obtain a second codeword with a code length of B ⁇ 2 n, where n ⁇ 1 and is an integer; and the second codeword is transmitted.
  • the outer code coding of the cascade coding uses block coding
  • the inner code coding uses polar coding.
  • the outer code encoding divides the information bit sequence into multiple groups and encodes them respectively, and the obtained multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually polar encoding in units of a block (ie, the first codeword) including multiple bits. Therefore, when decoding, it is no longer necessary to perform decision and decoding in units of bits, as in the existing SCL decoding algorithm, but to perform decoding in units of blocks. This can reduce the decoding delay.
  • Sequence determining the generation matrix required to encode each subsequence according to the number of bits included in each of the plurality of subsequences; using the generation matrix corresponding to each subsequence in the plurality of subsequences for the plurality of subsequences Encoding is performed to obtain a plurality of first codewords having a code length of B.
  • each subsequence of the information bit sequence can be encoded using any one of the following codes: repeating code, BCH code, simplex code, dual code of BCH code, polar Code, parity check code, dual code of simplex code.
  • an encoding device in a second aspect, has a function of implementing the method in the first aspect and any possible implementation manners thereof.
  • the functions may be implemented by hardware, and may also be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • the encoding device when part or all of the functions are implemented by hardware, includes: an input interface circuit for acquiring an information bit sequence to be encoded; and a logic circuit for performing an information bit sequence Group coding to obtain multiple first codewords with a code length B, B ⁇ 0 and an integer; perform n-level polarization coding on the multiple first codewords to obtain a second code with a length of B ⁇ 2 n Words, n ⁇ 1 and an integer; an output interface circuit for outputting the second codeword.
  • the outer code coding of the cascade coding uses block coding
  • the inner code coding uses polar coding.
  • the outer code encoding divides the information bit sequence into multiple groups and encodes them respectively, and the obtained multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually polar encoding in units of a block (ie, the first codeword) including multiple bits. Therefore, when decoding, it is no longer necessary to perform decision and decoding in units of bits, as in the existing SCL decoding algorithm, but to perform decoding in units of blocks. This can reduce the decoding delay.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the functions are implemented by software, the encoding device includes: a memory for storing a computer program; and a processor for executing the computer program stored in the memory.
  • the encoding device can implement the cascade encoding method described in the first aspect and any possible design of the first aspect.
  • the memory may be a physically separate unit or integrated with the processor.
  • the encoding device when part or all of the functions are implemented by software, the encoding device includes only a processor.
  • the memory for storing the program is located outside the encoding device, and the processor is connected to the memory through a circuit / wire for reading and running the program stored in the memory to execute the first aspect described above and any possible implementation of the first aspect Method of concatenated coding in.
  • the present application provides a decoding method, which includes: obtaining a bit sequence to be decoded, the length of the bit sequence to be decoded is N, and N is a positive integer; performing SCL translation on the bit sequence to be decoded Code to obtain N / B sub-code blocks, hard-decision the bits in each sub-code block of the N / B sub-code blocks, to obtain a hard decision result of each sub-code block, and The judgment results query the symptom diagnosis table to obtain multiple candidate codewords for each subcode block; calculate path metric values of multiple candidate codewords for each subcode block, and calculate path metrics for multiple candidate codewords for each subcode block Value to determine the decoding path of each sub-code block; multiple decoding paths corresponding to the multiple sub-code blocks are sequentially output as the decoding result.
  • the present application provides a decoding device having the function of implementing the method in the third aspect and any possible implementations thereof.
  • the functions may be implemented by hardware, and may also be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • the decoding device when part or all of the functions are implemented by hardware, includes: an input interface circuit for acquiring a bit sequence to be decoded; and a logic circuit for performing the above third
  • the decoding method in an aspect decodes the bit sequence to be decoded to obtain a decoding result; and an output interface circuit is used to output the decoding result.
  • the decoding device may be a chip or an integrated circuit.
  • the decoding device when part or all of the functions are implemented by software, the decoding device includes: a memory for storing a computer program; and a processor for executing the computer program stored in the memory.
  • the decoding device can implement the decoding method according to the third aspect.
  • the memory may be a physically separate unit or integrated with the processor.
  • the decoding device when part or all of the functions are implemented by software, the decoding device includes only a processor.
  • the memory for storing the program is located outside the encoding device, and the processor is connected to the memory through a circuit / wire for reading and running the program stored in the memory to perform the decoding method described in the third aspect.
  • the decoding device may be a chip or an integrated circuit.
  • the present application provides a network device, including a transceiver, a processor, and a memory.
  • the processor is used to control the transceiver to send and receive signals
  • the memory is used to store the computer program
  • the processor is used to call and run the computer program stored in the memory, so that the network device executes the method in any possible implementation manner of the first or second aspect.
  • the network device executes the cascading method in the first aspect and any possible implementation manners of the method, and performs ranking on the information and / or data to be sent.
  • Link encoding When the network device serves as a receiving end of information and / or data, the network device executes the decoding method according to the third aspect, and decodes the bit sequence to be decoded received from the transmitting end.
  • the present application provides a terminal device including a transceiver, a processor, and a memory.
  • the processor is used to control the transceiver to send and receive signals
  • the memory is used to store the computer program
  • the processor is used to call and run the computer program stored in the memory, so that the terminal device executes the method in any possible implementation manner of the first aspect or the second aspect.
  • the terminal device when the terminal device serves as a sender of information and / or data, the terminal device executes the cascading method in the first aspect and any possible implementation manners of the terminal device, and performs ranking on the information and / or data to be transmitted Link encoding.
  • the terminal device executes the decoding method according to the third aspect, and decodes the bit sequence to be decoded received from the transmitting end.
  • the present application provides a computer-readable storage medium having instructions stored in the computer-readable storage medium, which when executed on a computer, causes the computer to execute the first aspect or any possible implementation manner of the first aspect Method.
  • the present application provides a computer program product including computer program code.
  • the computer program code runs on a computer, the computer causes the computer to execute the first aspect and any one of its possible implementation manners. method.
  • the present application provides a chip including a processor.
  • the processor is configured to read and execute a computer program stored in the memory to perform the foregoing first aspect or the method in any possible implementation manner of the first aspect.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be encoded.
  • the processor obtains the information bit sequence from the communication interface and uses the cascade encoding method described in the first aspect to perform cascade encoding on the information bit sequence. After the communication interface outputs the encoding, Sequence of bits.
  • the communication interface may be an input-output interface.
  • the present application provides a computer-readable storage medium, where the computer-readable storage medium stores instructions, and when it runs on a computer, causes the computer to execute the third aspect or any possible implementation manner of the third aspect Method.
  • the present application provides a computer program product.
  • the computer program product includes computer program code, and when the computer program code runs on a computer, the computer executes the third aspect or any possible implementation manner of the third aspect. Methods.
  • the present application provides a chip including a processor.
  • the processor is configured to read and execute a computer program stored in the memory to perform the method in the third aspect or any possible implementation manner of the third aspect.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be decoded.
  • the processor obtains the bit sequence to be decoded from the communication interface, and uses the decoding method described in the third aspect to decode the bit sequence to be decoded to obtain Decoding result; the communication interface outputs the decoding result.
  • the communication interface may be an input-output interface.
  • the present application provides a communication system including the network device according to the fifth aspect and the terminal device according to the sixth aspect.
  • the outer code coding of the cascade coding uses block coding
  • the inner code coding uses polar coding.
  • the outer code encoding divides the information bit sequence into multiple groups and encodes them respectively, and the obtained multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually polar encoding in units of a block (ie, the first codeword) including multiple bits. Therefore, when decoding, it is no longer necessary to perform decision and decoding in units of bits, as in the existing SCL decoding algorithm, but to perform decoding in units of blocks. This can reduce the decoding delay.
  • FIG. 1 is an architecture diagram of a wireless communication system 100 applicable to an embodiment of the present application.
  • Fig. 2 is a basic flowchart of communication using wireless technology.
  • FIG. 3 is a schematic diagram of polar polarization code encoding.
  • Figure 4 is a schematic diagram of the input and output of an F2 polarization network.
  • FIG. 5 is a schematic flowchart of a concatenated coding method 200 provided in the present application.
  • FIG. 9 is a schematic block diagram of a communication device 500 provided in the present application.
  • FIG. 10 is a schematic structural diagram of a communication device 600 provided in the present application.
  • FIG. 11 is a schematic diagram of the internal structure of the processing device 601.
  • FIG. 12 is a schematic block diagram of a communication device 700 provided in the present application.
  • FIG. 13 is a schematic block diagram of a communication device 800 provided in the present application.
  • FIG. 14 is a schematic diagram of the internal structure of the processing device 802.
  • FIG. 15 is a schematic structural diagram of a network device 3000 provided in the present application.
  • FIG. 16 is a schematic structural diagram of a terminal device 900 provided in the present application.
  • FIG. 1 is a structural diagram of a wireless communication system 100 applicable to an embodiment of the present application.
  • the wireless communication system 100 may include at least one network device and one or more terminal devices.
  • a network device (such as 101 shown in FIG. 1) can wirelessly communicate with the one or more terminal devices (such as 102 and 103 shown in FIG. 1).
  • the wireless communication system involved in this application includes, but is not limited to, a global mobile communications (GSM) system, a code division multiple access (CDMA) system, and a wideband code division multiple access (wideband code division).
  • GSM global mobile communications
  • CDMA code division multiple access
  • WCDMA wideband code division multiple access
  • GPRS general packet radio service
  • LTE long term evolution
  • FDD frequency division duplex
  • TDD time division duplex
  • TDD time division duplex
  • TDD time division duplex
  • TDD time division
  • UMTS universal mobile communication system
  • WiMAX worldwide interoperability for microwave communication
  • next-generation 5G mobile communication system Namely enhanced mobile bandwidth (eMBB), high reliability, low latency communication (ultra low latency communication, URLLC), and enhanced mass machine type communication (eMTC) or new communication systems that will appear in the future .
  • eMBB enhanced mobile bandwidth
  • URLLC ultra low latency communication
  • eMTC enhanced mass machine type communication
  • the terminal equipment involved in the embodiment of the present application may refer to user equipment (UE), terminal, access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user Terminal, terminal, wireless communication device, user agent, or user device.
  • Terminal equipment can also be cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital processing (PDA), and wireless communication Functional handheld devices, computing devices, or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in the future 5G network, or public land mobile network (PLMN) in future evolution Terminal equipment and the like are not limited in this application.
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital processing
  • PLMN public land mobile network
  • the network device involved in this application may be a device for communicating with a terminal device.
  • the network device may be a base station, or a device in which the base station is integrated with a base station controller, or may be another device having a similar communication function.
  • the base station referred to here may be a global mobile communication (GSM) system or a base station (BTS) in code division multiple access (CDMA), or a broadband code division.
  • GSM global mobile communication
  • BTS base station
  • CDMA code division multiple access
  • the base station (nodeB, NB) in a multiple access (wideband code division, multiple access, WCDMA) system can also be an evolutionary base station (evolutional nodeB, eNB, or eNodeB) in a long term evolution (LTE) system. It is a wireless controller in a cloud radio access network (CRAN) scenario.
  • the network device may also be a relay station, an access point, a vehicle-mounted device, a wearable device, and a network device
  • Wireless technology is used for communication between the network device and the terminal device in FIG. 1.
  • a network device sends a signal, it is a sending end, and when a network device receives a signal, it is a receiving end.
  • the terminal device is the same.
  • the terminal device sends a signal, it is the sending end, and when the terminal device receives the signal, it is the receiving end.
  • Fig. 2 is a basic flowchart of communication using wireless technology.
  • the source at the sending end is transmitted on the channel after source coding, channel coding, rate matching, and modulation.
  • the receiving end obtains the sink after demodulating, de-rate matching, channel decoding, and source decoding.
  • Channel codec is one of the core technologies in the field of wireless communication, and its performance improvement will directly improve network coverage and user transmission rate.
  • polar codes are channel coding technologies that can theoretically prove to reach the Shannon limit and have practical linear complexity coding and decoding capabilities.
  • Polar code is a linear block code. Its coding matrix (also called generator matrix) is F N. The coding process can be expressed by the following formula:
  • F N is an N ⁇ N matrix, Defined as the Kronecker product of log 2 N matrices F 2 ,
  • the addition and multiplication operations involved in the above formulas are all addition and multiplication operations on the binary Galois field.
  • the encoding generated by this method will produce polarization phenomenon through the successful bit-cancellation (SC) decoding method. That is, some bits in u pass through an equivalent high-reliability channel and are translated with a high probability, and the remaining bits pass through an equivalent low-reliability channel and are translated with a low probability. Therefore, one can use a highly reliable channel for information transmission, and set the bits corresponding to the low reliability channel to zero (ie, freeze), not for transmitting data, or transmitting data known to both parties in the communication.
  • SC bit-cancellation
  • FIG. 3 is a schematic diagram of a polar polarization code encoding.
  • the symbol " ⁇ " represents binary addition, and the input is left and bottom, and the output is right.
  • Each solid line in FIG. 3 represents 1 bit.
  • the 8-bit coded bits are modulated and then sent over a noisy channel.
  • the network is polarized.
  • the input and output relationship of the F2 polarization network can be shown in FIG. 4.
  • FIG. 4 is a schematic diagram of input and output of an F2 polarization network.
  • the input-output relationship shown in Figure 4 is described by a formula, which can be expressed as:
  • [x 0 x 1 ] and [u 0 , u 1 ] are binary vectors, and all operations are performed in the binary field.
  • the decoding of polar codes uses the SCL decoding algorithm.
  • the decoder makes decisions and outputs bit by bit, and the decoding delay is large.
  • this application provides a cascade coding method, which can reduce the decoding delay and improve the decoding performance of the polar code.
  • Concatenated coding includes outer code coding and inner code coding.
  • the input of the outer code encoding is an information bit sequence to be encoded, and the output of the outer code is used as the input of the inner code.
  • the output of the inner code encoding is the codeword after the concatenated encoding is completed.
  • the outer code and the inner code are relative concepts. Take a system that includes three encodings as an example. The first encoding is an outer encoding compared to the second encoding, and the second encoding is an inner encoding relative to the first encoding.
  • the second encoding is an outer encoding relative to the third encoding
  • the third encoding is an inner encoding relative to the second encoding.
  • the outer code encoding is performed first, and the inner code encoding is performed later.
  • the output of the outer code encoding is used as the input of the inner code encoding.
  • concatenated encoding involves two encodings.
  • the outer code of the cascade coding is block coding
  • the inner code coding is polar coding
  • FIG. 5 is a schematic flowchart of a concatenated coding method 200 provided by the present application.
  • the method 200 may be performed by a transmitting end.
  • step 210 the encoder obtains the information bit sequence to be encoded, and performs group coding on the information bit sequence to obtain a plurality of first codewords.
  • step 210 is a block encoding process.
  • Block coding is to divide the information bit sequence to be coded into multiple groups and encode each group to obtain multiple first codewords with a code length of B.
  • the code length B of the block code is related to the complexity and delay of the decoding.
  • the code length B of the block code can be set in consideration of the compromise between complexity and delay.
  • step 220 the transmitting end performs n-level polarization coding on the plurality of first codewords obtained by the block coding in step 210 to obtain a second codeword having a length of B ⁇ 2n .
  • the transmitting end performs n-level polarization coding on the first codeword (also, after n polarizations), the obtained concatenated code has The length is B ⁇ 2 n .
  • the length of the concatenated code B ⁇ 2 n can be any size. That is, according to the concatenated coding method provided in this application, a concatenated code of an arbitrary code length can be generated.
  • the outer code coding of the cascade coding uses block coding
  • the inner code coding uses polar coding.
  • the outer code encoding divides the information bit sequence into a plurality of groups and performs encoding, respectively, and the obtained multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually polar encoding in units of a block (ie, the first codeword) including multiple bits. Therefore, when decoding, it is no longer necessary to perform decision and decoding in units of bits, as in the existing SCL decoding algorithm, but to perform decoding in units of blocks. This can reduce the decoding delay.
  • the information bit sequence is block-coded to obtain multiple first codewords with a code length of B, including:
  • N B ⁇ 2 n , where N is an integer
  • the code length of the block code is also set in advance during block coding.
  • the block code refers to the output of the block code, that is, the first codeword in this application. That is to say, before performing concatenated coding, first obtain a preset target code length N and a code length B of the block code. According to the target code length and the code length B of the block code, it is determined that the information bit sequence to be coded is specifically divided into several groups.
  • the process of grouping the information bit sequences involved in the block coding can refer to the prior art, which will not be described in detail here.
  • each subsequence includes one or more bits, or some subsequences may not include bits.
  • a generation matrix required for group coding of each subsequence is determined.
  • each sub-sequence is a sub-block of an information bit sequence, or is called a sub-code block.
  • each subsequence will be encoded into a first codeword with a length B.
  • the number of bits included in the multiple subsequences is not the same. Therefore, the generation matrix required to encode the subsequence needs to be determined according to the number of bits included in each subsequence. That is, each of the plurality of subsequences corresponds to a respective generation matrix.
  • the multiple subsequences are encoded using the multiple generation matrices to obtain multiple first codewords, each codeword having a code length of B.
  • rate matching is performed on the third codeword, and finally a second codeword having a code length of B ⁇ 2 n is obtained.
  • the plurality of codewords having a code length of 3 are subjected to 3 A level of polar coding yields a codeword with a length of 3 ⁇ 2 3 (denoted as the third codeword).
  • rate matching is performed on the third codeword with a code length of 24 (for example, 4 bits are eliminated by puncturing), and a second codeword with a length of 20 is finally obtained.
  • the target code length N and the code length B of the block code that is, the first codeword
  • the level After the concatenated coding the codeword of the target code length can be obtained directly.
  • polar codes which can only generate code lengths that are integer powers of two, no rate matching is required.
  • the target code length N and the code length B of the block code that is, the first codeword
  • R 2 n
  • N B ⁇ R
  • step 210 and step 220 the encoder completes concatenated encoding. After concatenated coding is completed, the second codeword is sent to the receiving end.
  • steps 210 and 230 may be performed by an encoder at the transmitting end.
  • Step 230 may be performed by a transceiver at the transmitting end.
  • the encoder may output the second codeword to the transceiver, so that the transceiver sends the second codeword.
  • the encoder may also send the second codeword to the transceiver after processing such as rate matching and modulation mapping, and then send the second codeword processed after the rate matching and modulation mapping to the transceiver, and the transceiver will send it Send to the receiving end.
  • the encoder performing steps 210 and 220 of the method 200 may include an outer code encoder and an inner code encoder.
  • the outer code encoder obtains the information bit sequence and performs group coding on the information bit sequence to obtain a plurality of first codewords with a code length of B, and completes the concatenated outer code encoding.
  • the outer code encoder inputs the plurality of first codewords to the inner code encoder.
  • the inner code encoder receives the plurality of first code words from the outer code encoder, performs n-level polar encoding on the plurality of first code words, obtains a second code word, and completes the inner code encoding. After the inner code encoding is completed, the inner code encoder outputs the second codeword.
  • the first bit sequence may be bit interleaved, and the interleaved bit sequence is input to the inner code encoder for inner code. coding.
  • the following factors may be considered to select a block code as the outer code.
  • the optimal block code can be selected.
  • some block codes with better code range spectrum characteristics and higher decoding parallelism are selected as outer codes.
  • they are polarized by the F N polarization network. This can improve decoding parallelism and reduce delay.
  • the code length of the outer code block code does not need to be an integer power of 2
  • the code length of the final concatenated code also has more options, and the rate matching process can be omitted, or only a small amount of rate matching is required.
  • the information bit sequence is [u 0 u 1 u 2 u 3 u 4 u 5 ]
  • the information bit sequence is divided into the following 4 subsequences: [u 0 ], [u 1 u 2 ], [u 3 u 4 u 5 ]. among them, Indicates that the subsequence contains no bits.
  • the number of bits contained in each subsequence can also be called the information length of the subsequence. According to the information length of each subsequence, its corresponding generation matrix can be expressed as:
  • the generation matrix can be expressed as
  • the generation matrix can be expressed as
  • the generation matrix can be expressed as
  • the information length is 0, which can be understood as no information input.
  • the outer code encoding uses block encoding.
  • the information bit sequence [u 0 u 1 u 2 u 3 u 4 u 5 ] is encoded by outer code, and finally 4 code words are output, which are [o 0 o 1 o 2 ], [o 3 o 4 o 5 ], [o 6 o 7 o 8 ] and [o 6 o 7 o 8 ], the code length of each codeword is 3.
  • Each codeword here is the first codeword mentioned in this application.
  • the inner code is a polar code.
  • the polarization process of the outer code codeword can be expressed as:
  • K i information bits of the i-th sub-code block of the block code before encoding B codeword bits after encoding the ith sub-code block. Is the generation matrix of the i-th sub-code block, and the size is K i ⁇ B.
  • N bits to be polarization-coded consisting of the j-th codeword bit of each sub-code block, Bits after polarization encoding.
  • the information length of the subsequence is denoted by K, and K is an integer. It should be understood that K ⁇ B.
  • the first column of Table 1 indicates the information length of the subsequence.
  • the second column of Table 1 indicates which code is selected as the outer code when concatenated.
  • the information lengths of the sub-sequences in the second column and the first column of Table 1 correspond. For example, if the information length of a certain subsequence obtained after grouping the information bit sequences is 1, a repeating code is selected as the outer code and the outer code encoding in step 210 is performed. For another example, if the information length of a certain subsequence is 6, the eBCH code is selected as the outer code and the outer code encoding of step 210 is performed. Other messages are similar in length and will not be explained one by one.
  • the third column in Table 1 shows the generator matrix used in the outer code encoding.
  • the third column of Table 1 corresponds to the second column and the first column, respectively.
  • the generator matrix used for outer code encoding is G 1 .
  • the generation matrix used for the outer code encoding is G 3 .
  • G in the third column in Table 1 is a generator matrix, and the matrix S is listed to simplify the representation of the generator matrix G.
  • the matrix H is a check matrix corresponding to some codes, and the generation matrix can be determined according to the check matrix H.
  • the generator matrix of code B is the same as the generator matrix of code A.
  • the check matrix H 9 of the dual code of the eBCH code is equal to the eBCH generation matrix.
  • the repetition code is to repeatedly transmit each bit to be transmitted, or to encode each source bit into multiple identical bits.
  • the binary repeating code (3,1) encodes each 0 in a binary bit sequence as 000 and each 1 as 111. Therefore, when the length of the information sequence is 1, the generation matrix of the repeating code is a 16-bit all-1 matrix.
  • the BCH code is taken from the abbreviations of Bose, Ray-Chaudhuri and Hocquenghem. It is a coding method that has been studied in coding theory, especially error correction codes.
  • the extended BCH code extended BCH, eBCH is obtained by expanding on the basis of the BCH code, and has the characteristics of simple structure and large code distance among known codes.
  • the linear block code generated by using the consistent check matrix of the linear block code as the generation matrix is called the dual coding of the original linear block code. It can be understood that when the length of the information sequence is 9 or 10, the linear block code generated by using the consistent check matrix of the eBCH code as the generation matrix is the dual code of the eBCH.
  • a parity check code is a coding method that adds redundant bits to a codeword so that the number of "1" s in the codeword is always odd or constant.
  • the generalized parity check code can be constructed by a cyclic shift register, whose check bit is the exclusive OR value of the binary value corresponding to the tap position in the register.
  • the shift register is divided into a feedforward shift register and a feedback shift register. If it is a feedforward shift register, the parity check code is a convolution check code. If it is a feedback shift register, the The parity code is a cyclic redundancy check code.
  • the single-bit parity code refers to a code with only one parity bit.
  • the information bit sequence is grouped to obtain multiple subsequences.
  • the corresponding outer code and generation matrix are selected from Table 2 to perform outer code encoding on the subsequence to obtain Multiple first codewords.
  • inner code encoding is performed on a plurality of first codewords obtained by outer code encoding of all subsequences to obtain a concatenated code.
  • the application of the block code to replace the outer code of the polar code herein means that the outer code of the polar code uses the block code described in this application.
  • the polar inner code is continued to be encoded.
  • K 16
  • Table 1 a repetition code is used, which is obtained by repeating the information bits in the sub-block 16 times, which is not listed in Table 2.
  • the first row of Table 2 indicates the code weight, which is the number of 1 in the codeword, and the number in the corresponding column indicates the number of codewords with the code weight.
  • the code weight distribution of all the codewords (such as one line in Table 2, not the first line) is the code distance spectrum of the code.
  • the first column of Table 2 shows the encoding method used for the outer code of the polar code.
  • the second column of Table 2 indicates the information length K of one subblock (ie, the above-mentioned subsequence).
  • the information bit sequence is [u 0 u 1 u 2 u 3 u 4 u 5 ] and is divided into three sub-blocks [u 0 ], [u 1 u 2 ], and [u 3 u 4 u 5 ].
  • the value of the first non-zero element indicates the number of code weights of the column in which the non-zero element is located. Among them, the later the position where the non-zero element appears in the line, the larger the corresponding code weight, indicating better performance. At the same time, for the same code weight, the smaller the corresponding non-zero element is, the smaller the number of code weights, the lower the possibility of bit errors, and the better the performance.
  • the code distance spectrum indicates the number of code weights of the column in which the non-zero element is located. Among them, the later the position where the non-zero element appears in the line, the larger the corresponding code weight, indicating better performance.
  • the smaller the corresponding non-zero element is, the smaller the number of code weights, the lower the possibility of bit errors, and the better the performance.
  • the line corresponding to the polar code has the first non-zero element appearing as 2, and the corresponding code weight is 8, indicating that there are 2 lines with a code weight of 8.
  • the line corresponding to Simplex encoding the first non-zero element that appears is 1, and the corresponding code weight is 10, indicating that there is 1 line with a code weight of 10.
  • the first non-zero element that appears in the row corresponding to the polar code is 6, and the corresponding code weight is 8, indicating that there are 6 rows with a code weight of 8.
  • the line corresponding to the Simplex code the first non-zero element that appears is 1, and the corresponding code weight is 8, indicating that there is 1 line with a code weight of 8.
  • the first non-zero element appears in two rows at the same position, and then the size of the non-zero element.
  • there are 6 lines with a code weight of 8, compared with only one line with a code weight of 8, the probability of bit errors is higher. Therefore, when K 3, simplex coding is used, and the performance is also better than polar coding.
  • the row corresponding to the polar code the first non-zero element that appears is 76, and the corresponding code weight is 4.
  • the first non-zero element that appears is 60, and the corresponding code weight is 4.
  • the position of the first non-zero element is the same (that is, the code weight corresponding to the first non-zero element is the same)
  • the performance of dual code using eBCH code is better than that of polar code.
  • dual eBCH indicates a dual code of the eBCH code.
  • Dual of Simplex represents a dual code of a simplex code.
  • B can be set to any positive integer.
  • the code rate allocation before polarization can be obtained recursively through the prior art until each outer code (block code) code is obtained Rate, and select the corresponding block code for outer code encoding.
  • the existing "polarization weight" method can be used to obtain the code rate allocation result of the original polar code on each sub-block, and then use this allocation result as the code rate allocation scheme for each sub-block of the concatenated code.
  • the above code rate allocation scheme may not be followed, and a method of avoiding some specific code rates may be used to reduce decoding complexity.
  • the "full expansion algorithm” and "symptom list” can be used to avoid the intermediate code rate of the concatenated code.
  • the full expansion algorithm is suitable for low-bit-rate sub-blocks
  • the symptom list method is suitable for high-bit-rate sub-blocks. It is a parallel decoding method.
  • the decoding method 300 of the present application will be described below with the symptom list method as an example.
  • the decoding method 300 in the embodiment of the present application may include the following steps 301-306.
  • the length of the bit sequence to be decoded is N, and N is a positive integer.
  • N is the length of the codeword after concatenated encoding is completed.
  • B is the length of each sub-block into which the information bit sequence is divided.
  • N is the length of the bit sequence to be decoded. B has the same meaning as the encoding side.
  • each bit of a bit sequence to be decoded is associated with a log likelihood ratio (LLR). Then, the N bits included in the bit sequence of length N to be decoded are associated with N LLRs one by one.
  • LLR log likelihood ratio
  • an F operation or a G operation is performed on the N LLRs according to a hierarchy, and a recursive operation is performed.
  • step 303 is performed.
  • the F operation and the G operation are well-known concepts of recursive operation on LLR in the SCL decoding algorithm.
  • the subcode blocks of the outer code have the same meaning as the subcode blocks of the outer code described in the above-mentioned concatenated coding method 200, and are not described again.
  • multiple candidate codewords of a subcode block are multiple candidate decoding paths of the subcode block.
  • a path metric can be used to measure the pros and cons of the decoding path.
  • PM path metric
  • the smaller the PM value the better the candidate decoding path.
  • the optimal path of each subcode block is selected as the decoding path of the subcode block according to the size of the PM.
  • steps 301-306 are only a few steps divided for the convenience of explaining the decoding process.
  • the decoding process can be designed with more steps based on steps 301-306.
  • some of the above steps 301-306 may also be combined together, and the decoding method 300 is described as fewer steps. This application is not limited.
  • the concatenated coding method 200 provided in the present application is used to perform outer code encoding and inner code encoding on the information bit sequence, and the outer code uses a block code and the inner code uses a polar code.
  • the decoding process it can be decoded by "block", so that the decoding result of each sub-block can be output at one time.
  • the decoding delay can be reduced.
  • N represents a code length
  • K represents a length of an information sequence.
  • K in FIG. 7 and FIG. 8 each includes a 16-bit cyclic redundancy check (CRC) bit.
  • Hybrid polarization refers to the cascade coding method provided in the present application.
  • outer code coding When outer code coding is performed, multiple subsequences obtained by dividing the information bit sequence are selected from Table 2 according to their information length. .
  • hybrid coding For information bit sequences, the coding methods corresponding to multiple subsequences are different, so it is called hybrid coding.
  • Hybrid polar FSL refers to a decoding method that adopts a "block-by-block” manner instead of a "bit-by-bit” manner for external code subcodes, and has a lower decoding delay.
  • the ordinate BLER in FIGS. 7 and 8 represents a block error ratio
  • the abscissa E S / N 0 represents a signal-to-noise ratio.
  • the performance curves shown in FIG. 7 and FIG. 8 are obtained by simulation under the channel condition of additive white gaussian noise (AWGN).
  • AWGN additive white gaussian noise
  • the concatenated coding method provided in the present application has been described in detail with reference to FIG. 1 to FIG. 8.
  • the process of decoding in units of "blocks" can refer to the prior art.
  • the present application provides a concatenated encoding method, so that the receiving end can perform decoding in units of blocks instead of bits, and a large number of simulation results show that the decoding performance has been improved. For example, the decoding delay is reduced and the bit error rate is reduced.
  • the process of decoding at the receiving end in units of blocks can refer to the prior art, which is not described in detail herein.
  • the communication device, the encoding device, the network device, and the terminal device provided in the present application are described below with reference to FIGS. 9 to 14.
  • FIG. 9 is a schematic block diagram of a communication apparatus 500 provided by the present application. As shown in FIG. 9, the apparatus 500 includes a processing unit 510 and a communication unit 520.
  • a processing unit 510 configured to perform group coding on the information bit sequence to obtain multiple first codewords with a code length B, B ⁇ 0 and an integer; and perform n-level polarization coding on the multiple first codewords, Get a second codeword of length B ⁇ 2 n , where n ⁇ 1 and an integer;
  • the communication unit 520 is configured to send a second codeword generated by the processing unit 510.
  • FIG. 10 is a schematic structural diagram of a communication device 600 provided by the present application.
  • the communication device 600 is configured to implement a coding function.
  • the communication device 600 includes:
  • a processing device 601 is configured to obtain an information bit sequence to be encoded, and perform group coding on the information bit sequence to obtain a plurality of first codewords having a code length B, where B ⁇ 0 and an integer; and the plurality of first codewords.
  • the word is subjected to n-level polarization coding to obtain a second codeword of length B ⁇ 2 n , where n ⁇ 1 and an integer;
  • the transceiver 602 is configured to send the second codeword.
  • the transceiver is connected to the antenna 603.
  • the processing device 601 may be a processor, a chip, or an integrated circuit.
  • the present application further provides a processing device 601, which is configured to implement the concatenated coding method in the foregoing method embodiments.
  • a processing device 601 which is configured to implement the concatenated coding method in the foregoing method embodiments.
  • Part or all of the processes of the cascade coding method 200 in the embodiment of the present application may be implemented by hardware, or may also be implemented by software.
  • the processing device 601 may be a processor.
  • FIG. 11 is a schematic diagram of the internal structure of the processing device 601.
  • the processing device 601 includes:
  • An input interface circuit 6011 configured to obtain an input information bit sequence
  • a logic circuit 6012 is configured to group and encode the information bit sequence to obtain multiple first codewords with a code length B, B ⁇ 0 and an integer; and perform n-level polarization coding on the multiple first codewords. To obtain a second codeword of length B ⁇ 2 n, where n ⁇ 1 and an integer;
  • the output interface circuit 6013 is configured to output a second codeword.
  • the above-mentioned logic circuit 6012 may be used to execute the concatenated coding method described in each embodiment of the present application. For the detailed process, refer to the description in the method embodiment above, which will not be repeated here.
  • part or all of the process of the cascade coding method 200 provided in this application may also be implemented by software.
  • the processing device 601 may be a processor.
  • the processor is configured to execute a computer program stored in a memory.
  • the processor executes the cascade coding method in the foregoing method embodiment.
  • the memory may be a physically independent unit.
  • the memory may also be integrated with the processor, which is not limited in this application.
  • the processing device 601 may include only a processor.
  • the processor is connected to the memory through a circuit / wire, and is used to read and execute the computer program stored in the memory.
  • the processing device 601 further includes a memory.
  • the chip may further include an input interface and an output interface.
  • the input interface is used to receive an input information bit sequence to be encoded.
  • the output interface is used to output the second codeword.
  • the present application further provides a communication device 700.
  • the communication device 700 is configured to execute the method 300 described above.
  • FIG. 12 is a schematic block diagram of a communication apparatus 700 provided in the present application.
  • the communication device 700 includes a communication unit 701 and a processing unit 702.
  • a communication unit 701 configured to receive a bit sequence to be decoded from a transmitting end
  • the processing unit 702 is configured to execute the decoding method 300 described above, and decode the bit sequence to be decoded to obtain a decoding result.
  • FIG. 13 is a schematic structural diagram of a communication device 800 provided in the present application.
  • the communication device 800 is configured to implement a decoding function.
  • the decoding device 800 includes:
  • a transceiver 801 configured to receive a bit sequence to be decoded from a transmitting end
  • the processing device 802 is configured to obtain a bit sequence to be decoded, execute the decoding method of the method 300 described above, and decode the bit sequence to be decoded to obtain a decoding result.
  • the transceiver 801 is connected to the antenna 803.
  • the processing device 802 may be a processor, a chip, or an integrated circuit.
  • the present application further provides a processing device 802 for implementing the decoding method 300 described above.
  • Part or all of the decoding method 300 in the embodiment of the present application may be implemented by hardware, or may also be implemented by software.
  • the processing device 802 may be a processor.
  • the processing device 802 may also be as shown in FIG. 14.
  • FIG. 14 is a schematic diagram of the internal structure of the processing device 802.
  • the processing device 601 includes:
  • An input interface circuit 8021 configured to obtain a bit sequence to be decoded
  • a logic circuit 8022 is configured to execute the decoding method 300 described above to decode the bit sequence to be decoded to obtain a decoding result;
  • An output interface circuit 8023 is used to output a decoding result.
  • the processing device 802 may be a processor.
  • the processor is configured to execute a computer program stored in a memory.
  • the processor executes the decoding method 300 described above.
  • the memory may be a physically independent unit.
  • the memory may also be integrated with the processor, which is not limited in this application.
  • the processing device 802 includes only a processor.
  • the processor is connected to the memory through a circuit / wire, and is used to read and execute the computer program stored in the memory.
  • the processing device 802 further includes a memory.
  • the chip may further include an input interface and an output interface.
  • the input interface is used to receive an input bit sequence to be decoded.
  • the output interface is used to output the decoding result.
  • the concatenated coding method 200 provided in this application may be performed by a sending end.
  • the network device 101 when the network device 101 sends a signal, the network device 101 is a transmitting end.
  • the terminal device 102 or 103 sends a signal, the terminal device 102 or 103 is a transmitting end. Therefore, the following application further provides a network device and a terminal device, and the network device and the terminal device have a function of implementing the above-mentioned cascade coding method.
  • FIG. 15 is a schematic structural diagram of a network device 3000 provided in the present application.
  • the network device 3000 may be applied to the wireless communication system shown in FIG. 1 described above, and has a function of executing the concatenated coding method provided by the present application.
  • the network device 3000 may be, for example, a base station.
  • the network device 3000 may include one or more radio frequency units, such as a remote radio unit (RRU) 3100 and one or more baseband units (BBU).
  • the baseband unit can also be referred to as a digital unit (DU) 3200.
  • the RRU 3100 may be referred to as a transceiver unit, and corresponds to the communication unit 520 in FIG. 9.
  • the transceiver unit 3100 may also be referred to as a transceiver, a transceiver circuit, or a transceiver, etc., which may include at least one antenna 3101 and a radio frequency unit 3102.
  • the transceiver unit 3100 may include a receiving unit and a transmitting unit.
  • the receiving unit may correspond to a receiver (or a receiver or a receiving circuit), and the transmitting unit may correspond to a transmitter (or a transmitter or a transmitting circuit).
  • the RRU 3100 part is mainly used for transmitting and receiving radio frequency signals and converting radio frequency signals and baseband signals, for example, for sending configuration information of a first random access resource to a terminal device.
  • the BBU 3200 part is mainly used for baseband processing and controlling base stations.
  • the RRU 3100 and the BBU 3200 may be physically located together, or may be physically separated, that is, a distributed base station.
  • the BBU 3200 is the control center of the network device 3000, and may also be called a processing unit, which may correspond to the processing unit 510 in FIG. 9 and is mainly used to complete baseband processing functions, such as channel coding, rate matching (optionally), Bit interleaving, modulation, etc.
  • the BBU Processed Unit
  • the information bit sequence to be coded is group-coded to obtain a plurality of first codewords having a code length of B; n-level polarization coding is performed on the plurality of first codewords to obtain a length of B ⁇ 2n .
  • the second codeword is the control center of the network device 3000, and may also be called a processing unit, which may correspond to the processing unit 510 in FIG. 9 and is mainly used to complete baseband processing functions, such as channel coding, rate matching (optionally), Bit interleaving, modulation, etc.
  • the BBU Processe.g., Processing Unit
  • the base station may perform the above-mentioned concat
  • the BBU 3200 may be composed of one or more boards, and multiple boards may jointly support a wireless access network (for example, an LTE network) of a single access system, or may separately support different access systems. Wireless access network (for example, LTE network, 5G network or other network).
  • the BBU 3200 further includes a memory 3201 and a processor 3202.
  • the memory 3201 is configured to store necessary instructions and data.
  • the processor 3202 is configured to control the network device 3000 to perform necessary actions.
  • the processor 3202 is configured to control the network device 3000 to execute the operation process performed by the network device in the foregoing method embodiment.
  • the memory 3201 and the processor 3202 may serve one or more single boards. That is, the memory and processor can be set separately on each board. It is also possible that multiple boards share the same memory and processor. In addition, the necessary circuits can be set on each board.
  • the network device 3000 shown in FIG. 15 can implement a method of polarization coding.
  • the operations and / or functions of the units in the network device 3000 are respectively to implement the corresponding processes in the embodiment of the method 200 for cascade coding. To avoid repetition, detailed descriptions are appropriately omitted here.
  • the above BBU 3200 can be used to perform the actions implemented by the network device described in the foregoing method embodiments, for example, performing concatenated coding on the information bit sequence.
  • the RRU 3100 can be used to perform the actions that the network device described in the foregoing method embodiment sends to or receives from the terminal device. For example, sending a second codeword to the terminal device.
  • the terminal device 102 or 103 When uplink transmission is performed in the wireless communication system shown in FIG. 1, the terminal device 102 or 103 is a transmitting end.
  • the terminal equipment provided in this application is described below.
  • FIG. 16 is a schematic structural diagram of a terminal device 900 provided in the present application.
  • the terminal device 900 includes: one or more processors 901, one or more memories 902, and one or more transceivers 903.
  • the processor 901 is configured to control the transceiver 903 to send and receive signals
  • the memory 902 is configured to store a computer program
  • the processor 901 is configured to call and run the computer program from the memory 902 to execute a corresponding method 200 of the cascade coding provided in this application. Process. For brevity, I will not repeat them here.
  • the terminal device 700 may be the terminal device 102 or 103 in the wireless communication system shown in FIG. 1.
  • the processor 901 may correspond to the processing unit 510 in FIG. 9, and the transceiver 903 may correspond to the communication unit 520 shown in FIG. 9.
  • the present application provides a computer-readable storage medium.
  • the computer-readable storage medium stores computer instructions.
  • the computer instructions When the computer instructions are run on a computer, the computer causes the computer to execute the cascade coding method 200 of the embodiment of the application. Corresponding operations and / or processes.
  • the present application also provides a computer program product.
  • the computer program product includes computer program code.
  • the computer program code runs on a computer, the computer causes the computer to perform corresponding operations of the cascade coding method 200 in the embodiment of the present application and / or Process.
  • the present application also provides a chip, including a processor.
  • the processor is configured to read and execute a computer program stored in the memory to perform corresponding operations and / or processes of the cascade-coded method 200 provided in the present application.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be encoded.
  • the processor obtains the information bit sequence from the communication interface and uses the cascade encoding method 200 of the embodiment of the present application to perform cascade encoding on the information bit sequence. After the communication interface outputs the encoding Sequence of bits.
  • the communication interface may be an input-output interface.
  • This application provides a computer-readable storage medium.
  • the computer-readable storage medium stores computer instructions.
  • the computer instructions When executed on a computer, the computer is caused to perform corresponding operations of the decoding method 300 in the embodiment of the application and / Or process.
  • the present application also provides a computer program product.
  • the computer program product includes computer program code.
  • the computer program code runs on a computer, the computer causes the computer to perform corresponding operations and / or processes of the decoding method 300 in the embodiment of the present application.
  • the present application also provides a chip, including a processor.
  • the processor is configured to read and execute the computer program stored in the memory to perform corresponding operations and / or processes of the decoding method 300 provided in the application.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be decoded.
  • the processor obtains the bit sequence to be decoded from the communication interface, and uses the decoding method 300 in the embodiment of the present application to decode the bit sequence to be decoded.
  • the communication interface is used to output the decoding result.
  • the communication interface may be an input-output interface.
  • each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the steps of the foregoing method embodiment may be directly embodied as being performed by a hardware processor, or may be performed by using a combination of hardware and software modules in the processor.
  • the software module may be located in a mature storage medium such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, and the like.
  • the storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the foregoing method in combination with its hardware.
  • the chip described in the embodiment of the present application may be a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system chip (SoC), a central Processor (central processor unit, CPU), network processor (Network processor, NP), digital signal processing circuit (digital signal processor, DSP), may also be a microcontroller (micro controller, unit, MCU, programmable controller ( programmable logic device (PLD) or other integrated chip.
  • FPGA field-programmable gate array
  • ASIC application-specific integrated circuit
  • SoC system chip
  • CPU central processor unit, CPU
  • Network processor Network processor
  • NP digital signal processing circuit
  • DSP digital signal processor
  • microcontroller microcontroller
  • MCU programmable controller
  • PLD programmable logic device
  • the processor in the embodiment of the present application may be an integrated circuit chip and has a signal processing capability.
  • each step of the foregoing method embodiment may be completed by using an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the processor may be a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly implemented by a hardware encoding processor, or may be performed by using a combination of hardware and software modules in the encoding processor.
  • the software module may be located in a mature storage medium such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, and the like.
  • the storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the foregoing method in combination with its hardware.
  • the memory in the embodiment of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrical memory Erase programmable read-only memory (EPROM, EEPROM) or flash memory.
  • the volatile memory may be a random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • double SDRAM double SDRAM
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • enhanced SDRAM enhanced SDRAM
  • SLDRAM synchronous connection dynamic random access memory
  • direct RAMbus RAM direct RAMbus RAM
  • the device embodiments described above in this application are merely schematic.
  • the division of the units is only a logical function division, and there may be another division manner in actual implementation.
  • multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each of the units may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of this application is essentially a part that contributes to the existing technology or a part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application.

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Abstract

L'invention concerne un procédé de codage en cascade qui comprend : l'exécution d'un codage de groupe sur une séquence de bits d'informations de façon à obtenir de multiples premiers mots de code ayant une longueur de code B (210) ; l'exécution d'un codage de polarisation de niveau n sur la pluralité de premiers mots de code pour obtenir un second mot de code ayant une longueur de B × 2 n (220) ; la sortie du second mot de code (230).
PCT/CN2019/104786 2018-09-07 2019-09-06 Procédé et dispositif de codage en cascade WO2020048537A1 (fr)

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