Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3674—Details of drivers for scan electrodes
  • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/3406—Control of illumination source
  • G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3685—Details of drivers for data electrodes
  • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0202—Addressing of scan or signal lines
  • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0237—Switching ON and OFF the backlight within one frame
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/024—Scrolling of light from the illumination source over the display in combination with the scanning of the display screen
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/04—Partial updating of the display screen
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0252—Improving the response speed
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2340/00—Aspects of display data processing
  • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame

Definitions

• Head-mounted display (HMD) devices are configured to be worn on, or otherwise affixed to, a user’s head.
• An HMD device may comprise one or more displays positioned in front of one, or both, of the user’s eyes.
• the HMD may display images (e.g., still images, sequences of images, and/or videos) from an image source overlaid with information and/or images from the user’s surrounding environment (e.g., as captured by a camera), for example, to immerse the user in a virtual world.
• HMD devices have
• An LCD display panel may be formed from an array of pixel elements (e.g., liquid crystal cells) arranged in rows and columns. Each row of pixel elements is coupled to a respective gate line, and each column of pixel elements is coupled to a respective data (or source) line.
• a pixel element may be accessed (e.g., updated with new pixel data) by driving a relatively high voltage on a gate line to“select” or activate a corresponding row of pixel elements, and driving another voltage on a corresponding data line to apply the update to the selected pixel element.
• the voltage level of the data line may depend on the desired color and/or intensity of the target pixel value.
• LCD display panels may be updated by successively“scanning” the rows of pixel elements (e.g., one row at a time), until each row of the pixel array has been updated.
• LCD overdrive is a technique for accelerating pixel transitions when updating an LCD display. Specifically, a pixel element is driven to a higher voltage than the target voltage associated with the desired color and/or brightness level. The higher voltage causes the liquid crystal to rotate faster, and thus reach the target brightness in less time.
• a pixel element is driven to a higher voltage than the target voltage associated with the desired color and/or brightness level. The higher voltage causes the liquid crystal to rotate faster, and thus reach the target brightness in less time.
• On fixed LCD displays e.g., televisions, monitors, mobile phones, etc.
• an object is often illuminated by the same pixel elements for the duration of multiple frames.
• the amount of overdrive applied to the pixel elements of a fixed LCD display can be
• the display device may include overdrive circuitry configured to determine a plurality of pixel values for the plurality of pixel elements, respectively, based on the received frame. For each pixel element in the array, the overdrive circuitry may determine a target voltage that causes the pixel element to settle at its target pixel value. The overdrive circuitry may further select at least some of the pixel elements to receive overdrive voltages, where the overdrive voltage for a pixel element is different than the target voltage for that pixel element. In some aspects, the overdrive circuitry may select the subset of rows to be rescanned based at least in part on the pixel elements selected to receive overdrive voltages.
• the data driver may scan each row of the pixel array by driving the overdrive voltages onto respective pixel elements in the subset of rows of the pixel array and driving the target voltages onto respective pixel elements in each of the remaining rows of the pixel array.
• the data driver may further rescan each row of the pixel array by driving the target voltages onto respective pixel elements in the subset of rows of the pixel array.
• the data driver may scan each row of the pixel array by activating groups of pixel elements in succession, where each group of pixel elements includes a plurality of rows of the pixel array, and driving the first voltages onto respective pixel elements in the plurality of rows, concurrently, for each activated group.
• the data driver may further rescan each row of the pixel array by activating each row of pixel elements in the subset of rows in succession and driving the second voltages onto respective pixel elements in each activated row.
• the scanning may be performed at a faster rate than the rescanning.
• FIG. 2 shows a timing diagram depicting an example operation for periodically updating the pixel elements of a display device.
• FIG. 11 shows an example frame buffer image, in accordance with some embodiments.
• FIGS 15A and 15B are timing diagrams depicting example timing signals that may be used to control an operation of a hierarchical gate driver circuit, in accordance with some embodiments.
• FIG. 16 is a timing diagram depicting an example timing of scan-rescan pixel update operations using a hierarchical gate driver circuit, in accordance with some embodiments.
• FIG. 19 is an illustrative flowchart depicting an example overdrive correction operation, in accordance with some embodiments.
• processors may refer to any general purpose processor, conventional processor, controller, microcontroller, and/or state machine capable of executing scripts or instructions of one or more software programs stored in memory.
• voltage source may refer to a direct-current (DC) voltage source, an alternating-current (AC) voltage source, or any other means of creating an electrical potential (such as ground).
• the backlight 124 may provide continuous illumination to the pixel array (e.g., the backlight is constantly on or at least pulse-width modulated to a desired brightness level).
• the backlight is constantly on or at least pulse-width modulated to a desired brightness level.
• any changes in pixel values may be noticeable as soon as the updated voltages are applied to the pixel elements.
• VR virtual reality
• an object viewed on the display may be illuminated by different pixels as the user’s head and/or eyes move. Rapid changes in pixel values may cause motion blur and/or other artifacts in the images rendered on the LCD display, which may impair the virtual reality experience.
• the display device may reduce or prevent motion blur by periodically (rather than continuously) updating the display. For example, the display device may flash the backlight at periodic intervals so that rapid changes in pixel values in between such intervals are suppressed (e.g., similar to the saccadic suppression
• the pixel array is scanned only once during each pixel adjustment period. For example, a voltage may be driven onto each pixel element of the pixel array only once before the pixel array is illuminated for display.
• the access transistor may be an NMOS (or PMOS) transistor having a gate terminal coupled to one of the gate lines GL(1 )-GL(M), a drain (or source) terminal coupled to one of the data lines DL(1 )-DL(N), and a source (or drain) terminal coupled to a corresponding pixel element in the array 310.
• the gate driver 314 may be configured to select or activate each of the gate lines GL(1 )-GL(M), in succession, until each row of the pixel array 310 has been updated.
• the display memory 330 may be configured to store or buffer display data 303 corresponding to an image to be displayed on the pixel array 310.
• the display data 303 may include pixel values 304 (e.g., corresponding to a color and/or intensity) for one or more pixel element in the array 310.
• each pixel element may comprise a plurality of subpixels including, but not limited to, red (R), green (G), and blue (B) subpixels.
• the display data 303 may indicate R, G, and B values for the subpixels of the image to be displayed.
• the R, G, and B values may affect the color and intensity (e.g., gray level) of each pixel element.
• the display update controller 340 may determine a respective pixel voltage 305 to be applied (e.g., by the data driver 312) to each pixel element of the pixel array 310. During a subsequent rescan of the pixel array, the display update controller 340 may determine adjusted pixel voltages 306 to be applied to respective pixel elements in one or more rows of the pixel array 310.
• each row of the pixel array 310 may be updated during the rescanning operation.
• the display update controller 340 may determine a pixel voltage 305 and an adjusted pixel voltage 306 for each pixel element of the pixel array 310.
• only a smaller subset of rows may be rescanned during the rescanning operation.
• the display update controller 340 may determine adjusted pixel voltages 306 only for respective pixel elements in the subset of rows.
• the display update controller 340 may provide a rescan control signal (R_CTRL) to the timing controller 320 indicating the subset of rows to be rescanned.
• R_CTRL rescan control signal
• each frame update interval comprises a pixel adjustment period (e.g., from times to to t3, t 4 to t7, and te to tn) followed by a display period (e.g., from times t3 to t 4 , t7 to te, and tn to t-12) to display a corresponding image (e.g., image 1 , image 2, and image 3).
• the display device may scan an array of pixel elements (e.g., from times to to ti, t 4 to ts, and te to t9) to update the pixel values for each pixel element of the display.
• the display device may then rescan one or more rows of pixel elements (e.g., from times ti to t2, ts to te, and t9 to tio), during the same pixel adjustment period, to further adjust the voltages and/or pixel values for a subset of pixel elements in the pixel array.
• aspects of the present disclosure may leverage the duration between display periods (specifically, between the end of a scan and the start of a display period) to refine or correct the pixel values for one or more pixel elements.
• the rescan operation may be used for overdrive correction.
• a pixel element may be driven with an overdrive voltage that exceeds (e.g., above or below) the target voltage that would cause the pixel element to settle at the target pixel value.
• the overdrive voltage may cause the pixel element to transition to the target pixel value at a faster rate.
• the overdrive voltage may also cause the pixel element to settle at a pixel value beyond (e.g., higher or lower than) the target pixel value. This may further complicate the pixel voltage calculations for the next image or frame to be displayed.
• the color and/or brightness of each pixel element may be adjusted by changing the voltage applied to that pixel element.
• the target voltage associated with a particular pixel value may represent the voltage which, when applied to a pixel element, causes the pixel element to settle at the desired pixel value.
• the degree of change in color and/or brightness that can be achieved in a single frame transition or update may be limited by the settling time of the pixel element.
• transitioning from a maximum brightness value (e.g., a“white” pixel) to a minimum brightness value (e.g., a“black” pixel) may require greater settling time than transitioning from an intermediate brightness value to another intermediate brightness value (e.g., from one shade of“gray” to a different shade of“gray”).
• the target voltage may be insufficient to drive the pixel element to the desired pixel value within a given frame update period. If the pixel element is unable to achieve the desired color and/or brightness between successive frame updates, artifacts (such as ghosting) may appear in the displayed image.
• LCD overdrive is a technique for increasing the speed of pixel transitions when updating an LCD display. Specifically, a pixel element is driven to a higher voltage than the target voltage associated with the desired color and/or brightness level. The higher voltage causes the liquid crystal in each pixel element to rotate faster, and thus transition to the target brightness in less time.
• a gate driver 514 is coupled to the pixel array 510 via the gate lines GL(1 )- GL(M).
• the gate driver 514 may be configured to select which row of pixel elements is to receive the pixel data driven by the data driver 512 at any given time. For example, the gate driver 514 may select or activate each of the gate lines GL(1 )-GL(M), in succession, until each row of the pixel array 510 has been updated.
• the pixel voltage to be applied to a particular pixel element may depend on the target pixel value to be reached by the start of the next display period (e.g., at time te) as well as its current pixel value (e.g., between times ⁇ b to t7). If an overdrive voltage was applied to the pixel element during the second pixel adjustment period (e.g., from times t3 to ts), the current pixel value for the pixel element may be different than its target pixel value for the previous frame.
• the display device 500 may reduce the complexity of pixel voltage calculations by causing each of the pixel elements in the pixel array 510 to settle at its target voltage 503. For example, during an initial scan of the pixel array 510, the display device 500 may apply overdrive voltages 504 to one or more pixel elements in the array 510. The display device 500 may then rescan at least a portion of the pixel array 510 by applying a respective target voltage 503 to any overdriven pixel elements (e.g., pixel elements to which an overdrive voltage was applied) from the initial scan.
• any overdriven pixel elements e.g., pixel elements to which an overdrive voltage was applied
• the scan/rescan circuitry 540 may generate scan voltages 505 and rescan voltages 506 based on the target voltages 503 and the overdrive voltages 504. For example, a respective scan voltage 505 may be applied to each pixel element in the pixel array 510 during the initial scan of the array 510. Thus, the scan voltages 505 may include overdrive voltages 504 for any pixel elements that are unable to settle to their target pixel values by the start of the next display period. Furthermore, the rescan voltages 506 may be used to drive each overdriven pixel element (e.g., from the initial scan) to its target voltage 503. Accordingly, the rescan voltages 506 may include only the target voltages 503 for one or more pixel elements.
• the scan/rescan circuitry 540 may provide a rescan control signal (R_CTRL) to the timing controller 520 indicating the subset of rows to be rescanned.
• R_CTRL rescan control signal
• the timing controller 520 may successively activate only the subset of rows indicated by the rescan control signal to be driven with rescan voltages 506.
• pixel elements associated with higher line numbers have less time to transition to their desired pixel values than pixel elements associated with lower line numbers (e.g., pixel elements that are updated earlier in the cascade).
• pixel elements at the top of the pixel array 510 may have the duration (T) of the pixel adjustment period to reach their target pixel values.
• pixel elements in the middle of the array 510 may have a significantly shorter duration (T-x) to reach their target pixel values
• pixel elements at the bottom of the array 510 may have an even shorter duration (T-2x) to reach their target pixel values.
• the overdrive circuitry 530 may progressively increase the amount of overdrive applied to the rows of pixel elements based, at least in part, on their position (e.g., line number) in the array 510. More
• FIG. 7A shows a timing diagram 700A depicting an example implementation of progressive overdrive, in accordance with some embodiments.
• the method of progressive overdrive illustrated in FIG. 7A may be implemented by the overdrive circuitry 530 of FIG. 5.
• the timing diagram 700A shows an example frame update interval (e.g. from times to to t2) which may comprise a pixel adjustment period (e.g., from times to to ti) followed by a display period (e.g., from times ti to t2).
• the curve 701 depicts example pixel update times for each row of the pixel array 510 based on the line number associated with that row.
• the amount of overdrive voltage may be progressively increased for each successive row of pixel elements from lines lo to l P.
• a pixel element coupled to line l P may be driven to a higher voltage than a pixel element coupled to line lo to effect the same change in pixel value (e.g., same change in grayscale level) before the start of the display period.
• the amount of overdrive that can be applied to the pixel elements may be limited by the voltage range of the data driver 512. In the example of FIG. 7A, the overdrive voltage may become saturated by the time the pixel elements coupled to line l P are updated.
• aspects of the present disclosure recognize that the need for progressive overdrive may vary depending on the characteristics of the LCD display (e.g., number of pixels, temperature, response time, etc.). For example, an LCD display with fewer pixel elements (or at least fewer lines of pixels) may require less time to update the entire pixel array. Thus, the change in overdrive from one row of pixel elements to another may be more gradual in a smaller pixel array. Aspects of the present disclosure further recognize that, in some embodiments, one or more rows of pixel elements may settle to their target pixel values, before the next display period, without the use of overdrive (e.g., by driving the pixel elements only up to the target voltage).
• overdrive e.g., by driving the pixel elements only up to the target voltage
• the timing diagram 700B shows an example frame update interval (e.g. from times to to t2) which may comprise a pixel adjustment period (e.g., from times to to ti) followed by a display period (e.g., from times ti to t2).
• the curve 702 depicts example pixel update times for each row of the pixel array 510 based on the line number (e.g., gate line) associated with that row.
• each pixel element between lines lo and l n may be driven to its target voltage during the pixel adjustment period.
• the overdrive circuitry 530 may generate progressive overdrive voltages for successive rows of pixel elements between lines l n to l P of the pixel array 510. As described above, the amount of overdrive voltage may be progressively increased for each successive row of pixel elements from lines l n to l P. In the example of FIG. 7B, the overdrive voltage may become saturated by the time the pixel elements coupled to line l P are updated. Thus, the overdrive circuitry 530 may apply maximum overdrive to the rows of pixel elements between lines l P and IM of the pixel array 510. In other words, if any of the pixel elements between lines l P and IM are to be updated during the pixel adjustment period, the overdrive circuitry 530 may apply the maximum overdrive voltage to change the pixel values of such pixel elements.
• FIG. 8 shows a timing diagram 800 depicting an example overdrive correction operation, in accordance with some embodiments.
• the overdrive correction operation illustrated in FIG. 8 may be implemented by any of the display devices 120, 300, or 500 of FIGS. 1 , 3, and 5, respectively.
• images may be periodically displayed by the pixel array 510 during successive frame update intervals.
• Each frame update interval (e.g. from times to to t 4 and t 4 to ts) may comprise a pixel adjustment period (e.g., from times to to t3 and t 4 to tz) followed by a display period (e.g., from times t3 to t 4 and t7 to te).
• the overdrive circuitry 530 may not apply any overdrive to the rows of pixel elements between lines lo and l n of the pixel array 510.
• each pixel element between lines lo and l n may be driven to its target voltage during the initial scans 812 and 822.
• the overdrive circuitry 530 may generate overdrive voltages for each row of pixel elements between lines l n to IM of the pixel array 510.
• the amount of overdrive voltage may be progressively increased for each successive row of pixel elements from lines l n to IM.
• each pixel element between lines In and IM may be driven to a respective overdrive voltage during the initial scans 812 to 822.
• each rescan 814 and 824 may be limited to the corresponding subset of rows of the pixel array 510. More specifically, each pixel element between lines l n and IM may be driven to its target voltage during the rescans 814 and 824.
• head-mounted display (HMD) devices are configured to be worn on, or otherwise affixed to, a user’s head.
• An HMD device may comprise one or more displays positioned in front of one, or both, of the user’s eyes.
• the HMD device may display images (e.g., still images, sequences of images, and/or videos) from an image source overlaid with information and/or images from the user’s surrounding environment (e.g., as captured by a camera), for example, to immerse the user in a virtual world.
• a display device may display a dynamically-updated image to a user based on the user’s eye position. More specifically, the display device may track the user’s eye movements and may display a portion of the image coinciding with a fixation point of the user (e.g., foveal region) with higher resolution than other regions of the image (e.g., the full field-of-view image). Thus, in some embodiments, the display device may display or render a high-resolution foveal image as an overlay in the foveal region of the full field-of-view (FFOV) image.
• FFOV full field-of-view
• a data driver 912 is coupled to the pixel array 910 via the data lines DL(1 )- DL(N).
• the data driver 912 may be configured to drive pixel data (e.g., in the form of a corresponding voltage) to individual pixel elements, via the data lines DL(1 )- DL(N), to update a frame or image displayed by the pixel array 910. It is noted that each row of pixel elements in the pixel array 910 is coupled to the same data lines DL(1 )-DL(N). Thus, the display device 900 may update the pixel array 910 by successively scanning the rows of pixel elements (e.g., one row at a time).
• a set of foveal coordinates 1106, specifying the foveal region 1108 of the FFOV image 1102, may be encoded in the frame buffer image 1100.
• the foveal coordinates 1106 may be encoded in a portion of the frame buffer image 1100 coinciding with a non-display region 1010 of the FFOV image 1102. In the example of FIG. 11 , the foveal coordinates 1106 are encoded in the upper-left corner of the frame buffer image 1100. In some embodiments, the foveal coordinates 1106 may be encoded as pixel data. For example, the foveal coordinates 1106 may be encoded using the first 32 pixels of the frame buffer image 1100. In some implementations, the foveal coordinates 1106 may be encoded using a 2-bits per pixel sparse encoding technique.
• each pixel of the FFOV image 1102 may correspond to a respective FFOV pixel value 901 and each pixel of the foveal image 1104 may correspond to a respective foveal pixel value 902. Since the FFOV image 1102 is to be displayed at an up-scaled resolution, the foveal rendering circuitry 930 may associate each FFOV pixel value 901 with a plurality of FFOV voltages 903 (e.g., to be applied to
• FIG. 13 shows a timing diagram 1300 depicting an example foveal rendering operation, in accordance with some embodiments.
• the foveal rendering operation illustrated in FIG. 8 may be implemented by any of the display devices 120, 300, or 900 of FIGS. 1 , 3, and 9, respectively.
• images may be periodically displayed by the pixel array 910 during successive frame update intervals.
• Each frame update interval (e.g. from times to to t 4 and t 4 to ts) may comprise a pixel adjustment period (e.g., from times to to t3 and t 4 to tz) followed by a display period (e.g., from times t3 to t 4 and t7 to te).
• curves 1312, 1314, 1322, and 1324 show example pixel update times for corresponding rows of the pixel array 910 based on the line number associated with each row. More specifically, curve 1312 corresponds to an initial scan of the pixel array 910 (e.g., from times to to ti) and curve 1314 corresponds to a rescan of the pixel array 910 (e.g., from times ti to t2) during a first pixel adjustment period (e.g., from times to to t3).
• curve 1322 corresponds to an initial scan of the pixel array (e.g., from times t 4 to ts) and curve 1324 corresponds to a rescan of the pixel array 910 (e.g., from times ts to te) during a second pixel adjustment period (e.g., from times t 4 to tz).
• the display device 900 may use dithering techniques to hide any unwanted edges that may occur between an initial scan and a rescan.
• the hierarchical manner in which the gate lines GL(1 )- GL(M) are driven allows the gate driver 914 to facilitate fast scans of the pixel array 910 (e.g., when rendering a relatively low-resolution FFOV image) and slower rescans of the pixel array 910 (e.g., when rendering a relatively high-resolution foveal image).
• the shift register 1410 may comprise multiple stages 1412-1418.
• the shift register (SR) stages 1412-1418 may be implemented as a cascade of flip-flops arranged in a serial-in/parallel-out (SIPO) configuration.
• the number of SR stages in the shift register 1410 may correspond with the number of gate driver groups in the hierarchical gate driver circuit 1400.
• S_PLS start pulse
• G_CLKA-G_CLKD gate clock signals
• the first SR stage 1412 in the cascade is configured to receive S_PLS as its input, and is configured to drive a first group select line (G_SEL1 ) based on S_PLS and a first gate clock signal (G_CLKA).
• the input of the second SR stage 1414 is coupled to the output of the first SR stage 1412.
• the second SR stage 1414 is configured to drive a second group select line (G_SEL2) based on G_SEL1 and a second gate clock signal (G_CLKB).
• the input of the third SR stage 1416 is coupled to the output of the second SR stage 1414.
• the third SR stage 1416 is configured to drive a third group select line (G_SEL3) based on G_SEL2 and a third gate clock signal (G_CLKC).
• the input of the fourth SR stage 1418 is coupled to the output of the third SR stage 1416.
• the fourth SR stage 1418 is configured to drive a fourth group select line (G_SEL4) based on G_SEL3 and a fourth gate clock signal (G_CLKD).
• the output of the fourth SR stage 1418 may be coupled to the input of a fifth SR stage in the cascade (not shown for simplicity).
• the start pulse S_PLS is asserted and the first gate clock signal G_CLKA transitions to a logic high state.
• the rising-edge transition of G_CLKA causes the first SR stage 1412 to shift-in (e.g., store) the current state of S_PLS. Since S_PLS is currently asserted to a logic high state, at time to, the first SR stage 1412 also drives the first group select line G_SEL1 to a logic high state.
• the activation of G_SEL1 enables the first gate driver group 1422 to drive the first group of gate lines g -gl D in response to gate pulses G_PLS1-G_PLS4.
• the first gate driver group 1422 may drive gate line g , at time to, for the duration in which G_SEL1 and G_PLS1 are concurrently asserted (e.g., from times to to ti).
• the first gate driver group 1422 may drive gate line g1 B, at time ti, for the duration in which G_SEL1 and G_PLS2 are concurrently asserted (e.g., from times ti to t2).
• the first gate driver group 1422 may drive gate line g1 c, at time t2, for the duration in which G_SEL1 and G_PLS3 are concurrently asserted (e.g., from times t2 to t3).
• the first gate drive group 1422 may drive gate line gl D, at time t3, for the duration in which G_SEL1 and G_PLS4 are concurrently asserted (e.g., from times t3 to t 4 ).
• the start pulse S_PLS is deasserted and the second gate clock signal G_CLKB transitions to a logic high state.
• the rising-edge transition of G_CLKB causes the second SR stage 1414 to shift-in the current state of G_SEL1. Since G_SEL1 is currently asserted to a logic high state, at time t 4 , the second SR stage 1414 also drives the second group select line G_SEL2 to a logic high state.
• the activation of G_SEL2 enables the second gate driver group 1424 to drive the second group of gate lines g2A-g2D in response to gate pulses G_PLS5-G_PLS8.
• the second gate driver group 1424 may drive gate line g2A, at time t 4 , for the duration in which G_SEL2 and G_PLS5 are concurrently asserted (e.g., from times t 4 to ts).
• the second gate driver group 1424 may drive gate line g2B, at time ts, for the duration in which G_SEL2 and G_PLS6 are concurrently asserted (e.g., from times ts to ⁇ b).
• the second gate driver group 1424 may drive gate line g2c, at time te, for the duration in which G_SEL2 and G_PLS7 are concurrently asserted (e.g., from times ⁇ b to t7).
• the second gate driver group 1424 may drive gate line g2D, at time t7, for the duration in which G_SEL2 and G_PLS8 are concurrently asserted (e.g., from times t7 to ts).
• the first gate clock signal G_CLKA transitions to a logic low state while the third gate clock signal G_CLKC transitions to a logic high state.
• the falling-edge transition of G_CLKA causes the first SR stage 1412 to shift-in the current state of S_PLS. Since S_PLS is currently deasserted to a logic low state, at time ts, the first SR stage 1412 also pulls G_SEL1 to a logic low state. The deactivation of G_SEL1 disables the first gate driver group 1422, thus preventing activation of any of the first group of gate lines glA-gl D.
• the third gate driver group 1426 may drive gate line g3A, at time te, for the duration in which G_SEL3 and G_PLS1 are concurrently asserted (e.g., from times te to t9).
• the third gate driver group 1426 may drive gate line g3B, at time t9, for the duration in which G_SEL3 and G_PLS2 are concurrently asserted (e.g., from times t9 to tio).
• the third gate driver group 1426 may drive gate line g3c, at time tio, for the duration in which G_SEL3 and G_PLS3 are concurrently asserted (e.g., from times tio to tn).
• the third gate driver group 1426 may drive gate line g3D, at time tn, for the duration in which G_SEL3 and G_PLS4 are concurrently asserted (e.g., from times tn to t-12).
• the second gate clock signal G_CLKB transitions to a logic low state while the fourth gate clock signal G_CLKD transitions to a logic high state.
• the falling-edge transition of G_CLKB causes the second SR stage 1414 to shift-in the current state of G_SEL1 . Since G_SEL1 is currently deasserted to a logic low state, at time t-12, the second SR stage 1414 also pulls G_SEL2 to a logic low state.
• the deactivation of G_SEL2 disables the second gate driver group 1424, thus preventing activation of any of the second group of gate lines g2A-g2D.
• the rising-edge transition of G_CLKD causes the fourth SR stage 1418 to shift-in the current state of G_SEL3. Since G_SEL3 is currently asserted to a logic high state, at time t-12, the fourth SR stage 1418 also drives the fourth group select line G_SEL4 to a logic high state.
• the activation of G_SEL4 enables the fourth gate driver group 1428 to drive the fourth group of gate lines g4A-g4D in response to gate pulses G_PLS5-G_PLS8.
• the fourth gate driver group 1428 may drive gate line g4A, at time t-12, for the duration in which G_SEL4 and G_PLS5 are concurrently asserted (e.g., from times t-12 to ti 3) .
• the fourth gate driver group 1428 may drive gate line g4B, at time ti3, for the duration in which G_SEL4 and G_PLS6 are concurrently asserted (e.g., from times ti3 to ti 4 ).
• the fourth gate driver group 1428 may drive gate line g4c, at time ti 4 , for the duration in which G_SEL4 and G_PLS7 are concurrently asserted (e.g., from times ti 4 to t-is).
• the fourth gate driver group 1428 may drive gate line g4D, at time t-is, for the duration in which G_SEL4 and G_PLS8 are concurrently asserted (e.g., from times t-is to t-
• the third gate clock signal G_CLKC transitions to a logic low state while the first gate clock signal G_CLKA transitions to a logic high state.
• the falling-edge transition of G_CLKC causes the third SR stage 1416 to shift-in the current state of
• G_SEL2 Since G_SEL2 is currently deasserted to a logic low state, at time tie, the third SR stage 1416 also pulls G_SEL3 to a logic low state. The rising-edge transition of G_CLKA causes the first SR stage 1412 to shift-in the current state of S_PLS. However, since S_PLS is still in a logic low state, at time tie, the first SR stage 1412 may continue to hold G_SEL1 in the logic low state.
• the fourth gate clock signal G_CLKD transitions to a logic low state while the second gate clock signal G_CLKB transitions to a logic high state.
• the falling- edge transition of G_CLKD causes the fourth SR stage 1418 to shift-in the current state of G_SEL3. Since G_SEL3 is currently deasserted to a logic low state, at time ti7, the fourth SR stage 1418 also pulls G_SEL4 to a logic low state.
• the rising-edge transition of G_CLKB causes the second SR stage 1414 to shift-in the current state of G_SEL1.
• the second SR stage 1414 may continue to hold G_SEL2 in the logic low state.
• the gate clock signals G_CLKA-G_CLKD at least partially overlap one another.
• G_CLKA remains asserted for at least part of the duration in which G_CLKB is asserted
• G_CLKB remains asserted for at least part of the duration in which G_CLKC is asserted
• G_CLKC remains asserted for at least part of the duration in which G_CLKD is asserted
• G_CLKD remains asserted for at least part of the duration in which G_CLKA is asserted.
• the gate pulses G_PLS1-G_PLS8 are asserted for such short durations that none of the gate pulses G_PLS1-G_PLS8 overlap. This enables the hierarchical gate driver circuit 1400 to drive multiple gate lines, in succession, during a single clock cycle of a particular gate clock signal.
• the hierarchical gate driver circuit 1400 may scan the rows of a pixel array with greater speed and flexibility than that of existing gate driver circuits. For example, since the input of the second SR stage 1414 is not tied to any of the first group of gate lines g -gl D, the second SR stage 1414 may drive the second group select line G_SEL2 without having to wait for any of the gate lines g -gl D to be driven to a sufficiently high voltage (e.g., >VGH). This may allow the hierarchical gate driver circuit 1400 to perform a scanning operation with coarser granularity and/or greater precision.
• a sufficiently high voltage e.g., >VGH
• the hierarchical gate driver circuit 1400 may include a gate line (GL) controller 1430 to control the flow of the gate pulses G_PLS1-G_PLS8 to the gate driver groups 1422-1428.
• the GL controller 1430 may suppress and/or redirect one or more of the gate pulses G_PLS1-G_PLS8 intended for the gate driver groups 1422-1428.
• the GL controller 1430 may cause two or more gate driver elements to drive respective gate lines, concurrently, in response to the same gate pulse.
• the GL controller 1430 may be coupled to a plurality of pulse filters 1402(1 )-1402(4).
• Each of the pulse filters 1402(1 )-1402(4) may selectively suppress the gate pulses provided to a respective one of the gate driver groups 1422-1428.
• the GL controller 1430 may control the pulse filters 1402(1 )-1402(4) via a plurality of pulse control signals P_CTRL1-P_CTRL4.
• each of the pulse filters 1402(1 )-1402(4) may comprise a set of AND logic gates.
• the first pulse filter 1402(1 ) may provide the gate pulses G_PLS1-G_PLS4 to the first gate driver group 1422 only when the first set of pulse control signals P_CTRL1 are asserted.
• the second pulse filter 1402(2) may provide the gate pulses G_PLS5-G_PLS8 to the second gate driver group 1424 only when the second set of pulse control signals P_CTRL2 are asserted.
• the third pulse filter 1402(3) may provide the gate pulses G_PLS1-G_PLS4 to the third gate driver group 1426 only when the third set of pulse control signals P_CTRL3 are asserted.
• the fourth pulse filter 1402(4) may provide the gate pulses G_PLS5-G_PLS8 to the fourth gate driver group 1428 only when the fourth set of pulse control signals P_CTRL4 are asserted.
• the first pulse filter 1402(1 ) may suppress a corresponding one or more of the gate pulses G_PLS1-G_PLS4. If one or more of the second set of pulse control signals P_CTRL2 are deasserted, the second pulse filter 1402(2) may suppress a corresponding one or more of the gate pulses G_PLS5-G_PLS8. If one or more of the third set of pulse control signals P_CTRL3 are deasserted, the third pulse filter 1402(3) may suppress a corresponding one or more of the gate pulses G_PLS1-G_PLS4. If one or more of the fourth set of pulse control signals P_CTRL4 are deasserted, the fourth pulse filter 1402(4) may suppress a corresponding one or more of the gate pulse G_PLS5-G_PLS8.
• the GL controller 1430 may redistribute one or more of the gate pulses G_PLS1-G_PLS8 among the gate driver elements within each of the gate driver groups 1422-1428.
• the first pulse filter 1402(1 ) may suppress gate pulses G_PLS2-G_PLS4 from being delivered to the first gate driver group 1422 in response to a first set of P_CTRL1 signals received from the GL controller 1430.
• the pulse filter 1402(1 ) may redistribute the first gate pulse G_PLS1 to each of the gate driver elements in the first gate driver group 1422.
• each of the gate lines glA-gl D coupled to the first gate driver group 1422 may be driven concurrently in response to the same gate pulse (e.g., G_PLS1 ).
• the hierarchical gate driver circuit 1400 may scan an array of display pixels with greater speed and/or flexibility than existing gate driver circuitry.
• the GL controller 1430 may suppress one or more of the gate pulses G_PLS1-G_PLS8 to perform a fast scan of the corresponding pixel array (e.g., to render an FFOV image on the pixel array).
• the GL controller 1430 may only enable one or more of the gate pulses G_PLS1 - G_PLS8 for a particular gate driver group to perform a slower rescan of only a subset of rows of the corresponding pixel array (e.g., to render a foveal image on the pixel array).
• FIG. 16 is a timing diagram 1600 depicting an example timing of scan-rescan pixel update operations using a hierarchical gate driver circuit, in accordance with some embodiments.
• the example operation of FIG. 16 may be performed by the hierarchical gate driver circuit 1400 to render a foveal image within an FFOV image on a pixel array.
• an FFOV image may be rendered on the pixel array during an initial scan (e.g., from times to to t 4 ) and a foveal image may be rendered on the pixel array during a subsequent rescan (e.g., from times t 4 to t9).
• the first group select line G_SEL1 is driven to a logic high state. Activation of G_SEL1 enables the first gate driver group 1422 to drive the first group of gate lines g -gl D in response to gate pulses G_PLS1-G_PLS4.
• the GL controller 1430 may suppress the gate pulses G_PLS2-G_PLS4, allowing only the gate pulse G_PLS1 to be supplied to the first gate driver group 1422. Accordingly, the first gate driver group 1422 may drive gate lines g -gl D, concurrently, in response to the gate pulse G_PLS5.
• the voltages (e.g., scan voltages 905) on the data lines (e.g., DL(1 )- DL(N)) may be driven onto respective pixel elements coupled to each of the gate lines glA- gl D, concurrently, at time to.
• the second group select line G_SEL2 is driven to a logic high state. Activation of G_SEL2 enables the second gate driver group 1424 to drive the second group of gate lines g2A-g2D in response to gate pulses G_PLS5-G_PLS8.
• the GL controller 1430 may suppress the gate pulses G_PLS6-G_PLS8, allowing only the gate pulse G_PLS5 to be supplied to the second gate driver group 1424.
• the second gate driver group 1424 may drive gate lines g2A-g2D, concurrently, in response to the gate pulse G_PLS5.
• the voltages e.g., scan voltages 905 on the data lines may be driven onto respective pixel elements coupled to each of the gate lines g2A- g2D, concurrently, at time ti.
• the third group select line G_SEL3 is driven to a logic high state. Activation of G_SEL3 enables the third gate driver group 1426 to drive the third group of gate lines g3A-g3D in response to gate pulses G_PLS1-G_PLS4. In the example of FIG.
• the GL controller 1430 may suppress the gate pulses G_PLS2-G_PLS4, allowing only the gate pulse G_PLS1 to be supplied to the third gate driver group 1426. Accordingly, the third gate driver group 1426 may drive gate lines g3A-g3D, concurrently, in response to the gate pulse G_PLS1. As a result, the voltages (e.g., scan voltages 905) on the data lines may be driven onto respective pixel elements coupled to each of the gate lines g3A-g3D, concurrently, at time t2.
• the voltages e.g., scan voltages 905
• the GL controller 1430 may suppress the gate pulses G_PLS6-G_PLS8, allowing only the gate pulse G_PLS5 to be supplied to the fourth gate driver group 1428. Accordingly, the fourth gate driver group 1428 may drive gate lines g4A-g4D, concurrently, in response to the gate pulse G_PLS5. As a result, the voltages (e.g., scan voltages 905) on the data lines may be driven onto respective pixel elements coupled to each of the gate lines g4A- g4D, concurrently, at time t3.
• the voltages e.g., scan voltages 905
• a rescan of the pixel array is triggered at time t 4 (e.g., in response to another start pulse S_PLS).
• the foveal region of the FFOV image may coincide with gate lines g2A-g2D. Since the display device may rescan only the foveal region when rendering the foveal image (e.g., from times t 4 to t9), the GL controller 1430 may suppress the gate pulses G_PLS1-G_PLS4 from being supplied to the first gate driver group 1422 and the third gate driver group 1426. The GL controller 1430 may also suppress the gate pulses G_PLS5-G_PLS8 from being supplied to the fourth gate driver group 1428. However, the GL controller 1430 may enable each of the gate pulses
• the second SR stage 1414 may activate the second group select line G_SEL2 almost immediately after the first group select line G_SEL1 is activated.
• the pixel elements coupled to gate lines g2A-g2D may be rescanned (e.g., at time ts) almost immediately after the pixel elements coupled to gate lines g4A-g4D are scanned (e.g., at time t3).
• FIG. 17 is a block diagram depicting a portion of a display device 1700, in accordance with some embodiments.
• the display device 1700 may be an example embodiment of the display device 900 of FIG. 9.
• the display device 1700 includes a shift register stage 1710, a gate driver group 1720, and a plurality of pixel elements 1701.
• the pixel elements 1701 may comprise at least a portion of the pixel array 910 of FIG. 9.
• the shift register stage 1710 and gate driver group 1720 may comprise at least a portion of the gate driver 914 and/or the hierarchical gate driver circuit 1400 of FIG. 14.
• the display device 1700 may include fewer or more shift register stages and/or gate driver groups than what is depicted in FIG. 17.
• the shift register stage 1710 may drive the group select line G_SEL when the input signal IN is asserted to a logic high state and the gate clock signal G_CLK also transitions to a logic high state. Activation of the group select line G_SEL enables the gate driver group 1720 to drive the individual gate lines GL(A)-GL(D).
• the gate driver group 1720 may comprise a plurality of gate driver elements 1720A-1720D.
• Each of the gate driver elements 1720A-1720D may be configured to drive a respective one of the gate lines GL(A)-GL(D) when the group select line G_SEL is activated.
• the gate driver elements 1720A-1720D may drive the gate lines GL(A)-GL(D) based on a plurality of gate pulses (G_PLS(A)- G_PLS(D)).
• the first gate driver element 1720A may drive a relatively high gate voltage (e.g., >VGH) onto the first gate line GL(A) for the duration in which G_SEL and G_PLS(A) are concurrently asserted to a logic high state.
• Activation of the first gate line GL(A) turns on the access transistors 1702 for the first row of pixel elements 1701 , thus allowing pixel data to be driven onto the first row of pixel elements 1701 (e.g., coupled to GL(A)) via the data lines DL(1 )-DL(N).
• the first gate pulse G_PLS(A) may be deasserted to a logic low state before the second gate pulse G_PLS(B) is asserted to a logic high state.
• the first gate driver element 1720A may deactivate the first gate line GL(A) (e.g., by pulling the gate voltage ⁇ VGL) before the second gate line GL(B) is activated.
• the fourth gate driver element 1720D may drive a relatively high gate voltage (e.g., >VGH) onto the fourth gate line GL(D) for the duration in which G_SEL and G_PLS(D) are concurrently asserted to a logic high state. Activation of the fourth gate line GL(D) turns on the access transistors 1702 for the fourth row of pixel elements 1701 , thus allowing pixel data to be driven onto the fourth row of pixel elements 1701 (e.g., coupled to GL(D)).
• the third gate pulse G_PLS(C) may be deasserted to a logic low state before the fourth gate pulse G_PLS(D) is asserted to a logic high state.
• the third gate driver element 1720C may deactivate the third gate line GL(C) (e.g., by pulling the gate voltage ⁇ VGL) before the fourth gate line GL(D) is activated.
• the gate driver elements 1720A-1720D should allow the full voltage swing of the gate pulses G_PLS(A)-G_PLS(D) to be driven onto the gate lines GL(A)-GL(D).
• the voltage on the group select line G_SEL may power each of the gate driver elements 1720A-1720D in driving the corresponding gate lines GL(A)-GL(D).
• the voltage on the group select line G_SEL may limit the amount of“turn-on” voltage that may be used to drive the gate lines GL(A)- GL(D).
• each of the gate driver elements 1720A-1720D may be configured to“boost” the voltage on the group select line G_SEL to allow the full voltage swing of the gate pulses G_PLS(A)-G_PLS(D) to be driven onto the gate lines GL(A)- GL(D).
• one or more of the gate driver elements 1720A-1720D may comprise a complementary MOS (CMOS) inverter.
• CMOS complementary MOS
• one or more of the gate driver elements 1720A-1720D may comprise a boosted NMOS driver or a boosted PMOS driver.
• FIG. 18 is an illustrative flowchart depicting an example scan-rescan pixel update operation 1800, in accordance with some embodiments.
• the example operation 1800 may be performed by any display device of the present disclosure including, for example, display devices 120, 300, 500, or 900 of FIGS. 1 , 3, 5, and 9. With reference for example to FIG. 3, the example operation 1800 may be performed by the display device 300 to scan a pixel array multiple times during a single frame update period.
• the display device scans each row of the pixel array, during a pixel
• the display update controller 340 may determine pixel voltages to be applied to one or more pixel elements in the array based, at least in part, on the pixel values.
• the first voltages may include overdrive voltages to be applied to respective pixel elements in one or more rows of the pixel array (e.g., as described above with respect to FIGS. 5-8).
• the first voltages may include FFOV voltages to be applied to respective pixel elements in each row of the pixel array (e.g., as described above with respect to FIGS. 9-13).
• the display device further rescans a subset of rows of the pixel array, during the pixel adjustment period, to drive second voltages onto respective pixel elements in the subset of rows (1830).
• the display update controller 340 may determine adjusted pixel voltages to be applied to respective pixel elements in one or more rows of the pixel array.
• the second voltages may include target voltages to be applied to respective overdriven pixel elements of the pixel array (e.g., as described above with respect to FIGS. 5-8).
• the second voltages may include foveal voltages to be applied to respective pixel elements in one or more rows of the pixel array (e.g., as described above with respect to FIGS. 9-13).
• the display device may then activate one or more light sources to illuminate the pixel array at the first instance of time (1840). For example, each pixel element of the pixel array may begin to transition towards a respective pixel value once the first voltage is applied.
• the second voltage may alter the state and/or rate of transition of respective pixel elements in the pixel array. Flowever, because the pixel elements are illuminated only during the display periods, any changes in pixel value exhibited before or after the display period will not be seen by the user.
• FIG. 19 is an illustrative flowchart depicting an example overdrive correction operation 1900, in accordance with some embodiments.
• the example operation 1900 may be performed by the display device 500 to correct the pixel values for one or more overdriven pixel elements of the pixel array 510.
• the display device may further determine overdrive voltages for respective pixel elements in a subset of rows of the pixel array (1920).
• the overdrive circuitry 530 may determine pixel voltages to be applied to teach of the pixel elements in the pixel array based, at least in part, on current pixel values and target pixel values for each pixel element in the array. It is noted however that if the change in pixel value exceeds a threshold amount, the target voltage may be insufficient to drive the pixel element to the desired pixel value within a given frame update period.
• the overdrive circuitry 530 may determine an overdrive voltage to be applied to one or more pixel elements in the array. As described above, the overdrive voltage may exceed (e.g., may be higher or lower than) the target voltage for a pixel element, thus causing the pixel element to transition (e.g., rotate) faster towards its target pixel value.
• the display device may further rescan the subset of rows by applying the target voltages to respective pixel elements in the subset of rows (1940).
• the scan/rescan circuitry 540 may generate rescan voltages based on the target voltages for any overdriven pixel elements.
• the rescan voltages may be used to drive each overdriven pixel element (e.g., from the initial scan) to its target voltage.
• the rescan voltages 506 may include only the target voltages for one or more pixel elements.
• the display device may drive only the smaller subset of pixel elements to their target voltages during the rescan.
• the display device may use dithering techniques to hide any unwanted edges that may occur between the initial scan and the rescan.
• the display device may determine an FFOV voltage for each pixel element of a pixel array (2010).
• the foveal rendering circuitry 930 may determine pixel voltages to be applied to each of the pixel elements in the pixel array based, at least in part, on FFOV pixel values and foveal pixel values from a received frame of display data.
• the FFOV pixel values may correspond with a full-frame image to be displayed across most (if not all) of the pixel elements of the pixel array. Since the FFOV image may span the periphery of the user’s line of sight, the FFOV pixel values may have a relatively low resolution.
• the foveal rendering circuitry 930 may associate each FFOV pixel value with a plurality of FFOV voltages (e.g., to be applied to respective pixel elements of the pixel array).
• the display device may further determine foveal voltages for respective pixel elements in a subset of rows of the pixel array (2020).
• the foveal rendering circuitry 930 may determine pixel voltages to be applied to each of the pixel elements in the pixel array based, at least in part, on FFOV pixel values and foveal pixel values from a received frame of display data.
• the foveal pixel values may correspond with a foveal image that spans only the foveal region of the user’s line of sight. Since the foveal region may correspond to the region in which the user is determined to have maximal visual acuity, the foveal pixel values may have a relatively high resolution.
• the foveal rendering circuitry 930 may associate each foveal pixel value with a respective foveal voltage (e.g., to be applied to respective pixel elements in a portion of the pixel array).
• a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

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