WO2020042533A1 - 显示面板 - Google Patents

显示面板 Download PDF

Info

Publication number
WO2020042533A1
WO2020042533A1 PCT/CN2019/072600 CN2019072600W WO2020042533A1 WO 2020042533 A1 WO2020042533 A1 WO 2020042533A1 CN 2019072600 W CN2019072600 W CN 2019072600W WO 2020042533 A1 WO2020042533 A1 WO 2020042533A1
Authority
WO
WIPO (PCT)
Prior art keywords
control line
control
combination
demultiplexing switch
display panel
Prior art date
Application number
PCT/CN2019/072600
Other languages
English (en)
French (fr)
Inventor
洪光辉
薛景峰
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/477,685 priority Critical patent/US11605326B2/en
Publication of WO2020042533A1 publication Critical patent/WO2020042533A1/zh

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0421Structural details of the set of electrodes
    • G09G2300/0426Layout of electrodes and connections
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0267Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0275Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0297Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/06Details of flat display driving waveforms
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/08Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel.
  • the demultiplexing circuit of the conventional display panel is generally used to demultiplex the data signals generated by the data driving circuit, and input the demultiplexed data signals to the pixel array.
  • the signal line that transmits the demultiplexed data signal and the control line that controls the demultiplexing circuit have overlapping (intersection) portions. Therefore, the demultiplexed data signal in the signal line will be transmitted by the control line. The effect of the control signal causes the picture displayed on the display panel to be affected.
  • An object of the present invention is to provide a display panel, which can prevent a derived pulse signal generated by a combination of a signal transmission line and a control line for controlling a demultiplexing switch from affecting an image displayed on the display panel.
  • a display panel includes: a pixel array, the pixel array includes at least one pixel column; a data driving circuit, the data driving circuit includes at least one data line; a scanning driving circuit, the scanning driving circuit is connected to an Said pixel array; a demultiplexing circuit, said demultiplexing circuit connecting said pixel array and said data line, said demultiplexing circuit comprising: a demultiplexing switch combination, said demultiplexing switch combination and said A data line connection; a signal transmission line, the two ends of which are respectively connected to the demultiplexing switch combination and the pixel column; and a control line combination, the control line combination connecting to the demultiplexing switch combination, the The control line combination includes a first control line and a second control line.
  • the level of the first control signal transmitted by the first control line and the level of the second control signal transmitted by the second control line are opposite to each other.
  • the number of the control line combinations where the signal transmission lines intersect is greater than or equal to 0; the control line combinations are disposed on a side of the demultiplexing switch combination near the pixel array And / or disposed on a side of the demultiplexing switch combination far from the pixel array; when the first control signal is high, the second control signal is low, and When the signal is low, the second control signal is high.
  • the intersection of the signal transmission line and the control line combination is located near the demultiplexing switch combination. Said one side of the pixel array.
  • the number of the control line combinations is two or three.
  • the high-level waveform / low-level waveform of one of the two control line combinations is delayed from the high-level waveform / low-level waveform of the other two control line combinations by a predetermined delay. time.
  • the first control signal and the second control signal having opposite levels are used to balance data transmitted to the data line due to the intersection of the control line combination and the signal transmission line. Coupling of signals.
  • a display panel includes: a pixel array, the pixel array includes at least one pixel column; a data driving circuit, the data driving circuit includes at least one data line; a scanning driving circuit, the scanning driving circuit is connected to an Said pixel array; a demultiplexing circuit, said demultiplexing circuit connecting said pixel array and said data line, said demultiplexing circuit comprising: a demultiplexing switch combination, said demultiplexing switch combination and said A data line connection; a signal transmission line, the two ends of which are respectively connected to the demultiplexing switch combination and the pixel column; and a control line combination, the control line combination connecting to the demultiplexing switch combination, the
  • the control line combination includes a first control line and a second control line. The level of the first control signal transmitted by the first control line and the level of the second control signal transmitted by the second control line are opposite to each other. The number of the control line combinations where the signal transmission lines meet is greater than or equal to zero.
  • control line combination is disposed on a side of the demultiplexing switch combination near the pixel array and / or on a side of the demultiplexing switch combination away from the pixel array.
  • the intersection of the signal transmission line and the control line combination is located near the demultiplexing switch combination. Said one side of the pixel array.
  • the number of the control line combinations is two or three.
  • control line combinations when the number of the control line combinations is three, one control line combination is disposed on a side of the demultiplexing switch combination near the pixel array, and two control line combinations And disposed on a side of the demultiplexing switch combination far from the pixel array.
  • control line combinations when the number of control line combinations is three, two control line combinations are disposed on a side of the demultiplexing switch combination near the pixel array, and one control line combination And disposed on a side of the demultiplexing switch combination far from the pixel array.
  • the number of the control line combinations is three, the number of the control line combinations provided on a side of the demultiplexing switch combination near the pixel array is zero.
  • the control line combinations are all disposed on a side of the demultiplexing switch combination away from the pixel array.
  • control line combinations when the number of control line combinations is two, one control line combination is disposed on a side of the demultiplexing switch combination near the pixel array, and one control line combination And disposed on a side of the demultiplexing switch combination far from the pixel array.
  • the number of control line combinations is two
  • the number of the control line combinations provided on a side of the demultiplexing switch combination close to the pixel array is zero, and two
  • the control line combinations are all disposed on a side of the demultiplexing switch combination away from the pixel array.
  • the first control signal and the second control signal having opposite levels are used to balance data transmitted to the data line due to the intersection of the control line combination and the signal transmission line. Coupling of signals.
  • the demultiplexing switch combination includes a first demultiplexing switch and a second demultiplexing switch; a first control end of the first demultiplexing switch is connected to the first control line, The second control terminal of the second demultiplexing switch is connected to the second control line; the first input terminal of the first demultiplexing switch and the second input terminal of the second demultiplexing switch are both Connected to the data line; both the first output terminal of the first demultiplexing switch and the second output terminal of the second demultiplexing switch are connected to one end of the signal transmission line.
  • the first demultiplexing switch and the second demultiplexing switch are configured to be turned on simultaneously when a level of the first control signal and a level of the second control signal are opposite. Or close at the same time.
  • the first demultiplexing switch when the first control signal is at a high level, the first demultiplexing switch is turned on, and when the first control signal is at a low level, the first demultiplexing switch is turned off;
  • the second control signal is at a high level, the second demultiplexing switch is turned off, and when the second control signal is at a low level, the second demultiplexing switch is turned on.
  • the second control signal when the first control signal is high, the second control signal is low; when the first control signal is low, the second control signal is high. level.
  • the high-level waveform / low-level waveform of one of the two control line combinations is delayed from the high-level waveform / low-level waveform of the other two control line combinations by a predetermined delay. time.
  • the present invention since the level of the first control signal transmitted by the first control line and the level of the second control signal transmitted by the second control line are opposite, and The number of the control line combination that intersects with the signal transmission line is greater than or equal to 0, so the first derived pulse signal corresponding to the first control signal and the second control signal formed on the signal transmission line The second derived pulse signal corresponding to the signal is cancelled, so that the derived pulse signal generated by the intersection of the signal transmission line and the control line for controlling the demultiplexing switch can be prevented from affecting the screen displayed on the display panel.
  • FIG. 1 is a schematic diagram of a first embodiment of a display panel of the present invention.
  • FIG. 2 is a waveform diagram of a control signal transmitted by a control line combination and a data signal transmitted by a signal transmission line in the display panel shown in FIG. 1.
  • FIG. 3 is a schematic diagram of a second embodiment of a display panel of the present invention.
  • FIG. 4 is a schematic diagram of a third embodiment of a display panel of the present invention.
  • FIG. 5 is a schematic diagram of a fourth embodiment of a display panel of the present invention.
  • FIG. 6 is a waveform diagram of a control signal transmitted by a control line combination and a data signal transmitted by a signal transmission line in the display panel shown in FIG. 5.
  • FIG. 7 is a schematic diagram of a fifth embodiment of a display panel of the present invention.
  • FIG. 1 is a schematic diagram of a first embodiment of a display panel of the present invention
  • FIG. 2 is a control line combination (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) in the display panel shown in FIG. 1
  • the display panel of this embodiment may be a TFT-LCD (Thin Film Transistor Liquid Crystal Display (OLED display panel), OLED (Organic Light Emitting Diode).
  • TFT-LCD Thin Film Transistor Liquid Crystal Display (OLED display panel)
  • OLED Organic Light Emitting Diode
  • the display panel of this embodiment includes a pixel array 101, a data driving circuit 102, a scan driving circuit, and a demultiplexing circuit.
  • the pixel array 101 includes at least one pixel column (1011, 1012, 1013, 1014, 1015, 1016).
  • the data driving circuit 102 includes at least one data line (1021, 1022).
  • the data lines (1021, 1022) are used to transmit data signals to be demultiplexed.
  • the scan driving circuit is connected to the pixel array 101.
  • the demultiplexing circuit connects the pixel array 101 and the data lines (1021, 1022).
  • the demultiplexing circuit includes a demultiplexing switch combination 103, a signal transmission line (104, 105, 106), and a control line combination. (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3).
  • the demultiplexing switch combination 103 is connected to the data lines (1021, 1022).
  • Two ends of the signal transmission line (104, 105, 106) are respectively connected to the demultiplexing switch combination 103 and the pixel column (1011, 1012, 1013, 1014, 1015, 1016).
  • the signal transmission lines (104, 105, 106) are used for transmitting demultiplexed data signals.
  • One of the data lines (1021, 1022) is connected to two / three of the demultiplexing switch combination 103, and the two / three of the demultiplexing switch combination 103 respectively pass the two / three of the signal transmission lines (104, 105). , 106) are connected to two or three of the pixel columns (1011, 1012, 1013, 1014, 1015, 1016).
  • the control line combination (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) is connected to the demultiplexing switch combination 103, and the control line combination (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) includes a first control Line (CK1, CK2, CK3) and a second control line (XCK1, XCK2, XCK3), the level of the first control signal transmitted by the first control line (CK1, CK2, CK3) and the second control line
  • the level of the second control signal transmitted by (XCK1, XCK2, XCK3) is opposite, and the control line combination (CK1 and XCK1, CK2 and XCK2, CK3, and XCK3) that intersect with the signal transmission line (104, 105, 106) ) Is greater than or equal to 0.
  • the second control signal when the first control signal is high, the second control signal is low; when the first control signal is low, all The second control signal is high.
  • the control line combination (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) is disposed on a side 107 of the demultiplexing switch combination 103 near the pixel array 101 and / or is disposed on the demultiplexing switch combination 103 is a side far from the pixel array 101.
  • the number of the control line combinations (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) is two or three.
  • the number of the control line combinations (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) is three.
  • One control line combination (CK1 and XCK1) is disposed on a side of the demultiplexing switch combination 103 near the pixel array 101, and two control line combinations (CK2 and XCK2, CK3 and XCK3) are provided on the A side of the demultiplexing switch combination 103 far from the pixel array 101.
  • the number of the control line combinations (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) that intersect with the signal transmission lines (104, 105, 106) is 1, and the signal transmission lines (104, 105, 106) Intersect with the control line combination (CK1 and XCK1) at a side of the demultiplexing switch combination 103 near the pixel array 101.
  • the first control line (CK1) and the second control line (XCK1) are located on the same side of the demultiplexing switch combination 103, and the first control line (CK1) and the second control line ( XCK1) Adjacent.
  • the first control signal and the second control signal of opposite levels are used to balance (cancel) the combination of the control lines (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) and the signal transmission line (104, (105, 106) coupling effect on the data signals transmitted by the data lines (1021, 1022).
  • the signal transmission line (104, 105, 106) intersects with the first control line (CK1) and the second control line (XCK1), the signal transmission line (104, 105, 106) A first capacitor is formed with the first control line (CK1), and a second capacitor is formed with the signal transmission line (104, 105, 106) and the second control line (XCK1).
  • the charge amount of a plate (the first control line (CK1)) of the first capacitor changes.
  • the charge amount of the other plate of the first capacitor (the signal transmission line (104, 105, 106)) will also change. Therefore, a signal will be formed on the signal transmission line (104, 105, 106). Derived signal (first derived pulse signal).
  • the signal transmission line (104, 105, 106) is used to transmit the demultiplexed data signal, the first derived pulse signal and the second derived pulse signal will be superimposed (multiplexed) with the data signal. And input to the pixel column (1011, 1012, 1013, 1014, 1015, 1016). At this time, the first derived pulse signal and the second derived pulse signal will affect the screen displayed on the display panel. .
  • the level of the first control signal transmitted by the first control line (CK1) and the level of the second control signal transmitted by the second control line (XCK1) are opposite Therefore, the levels of the first derived pulse signal and the second derived pulse signal are opposite.
  • the first demultiplexing switch 1031 and the second demultiplexing switch 1032 are both turned on, the first derived pulse signal and the second derived are superimposed (multiplexed) with the data signal.
  • the pulse signals cancel each other, that is, the coupling effect of the first control signal and the second control signal on the data signal is cancelled, thereby avoiding the pair of the first derived pulse signal and the second derived pulse signal
  • the picture displayed on the display panel has an impact.
  • both the first demultiplexing switch 1031 and the second demultiplexing switch 1032 are turned off, the first derived pulse signal and the second derived pulse signal will also cancel each other, and therefore will not It affects the picture displayed on the display panel.
  • the demultiplexing switch combination 103 includes a first demultiplexing switch 1031 and a second demultiplexing switch 1032.
  • a first control terminal of the first demultiplexing switch 1031 is connected to the first control line (CK1, CK2, CK3), and a second control terminal of the second demultiplexing switch 1032 is connected to the second control. (XCK1, XCK2, XCK3).
  • a first input terminal of the first demultiplexing switch 1031 and a second input terminal of the second demultiplexing switch 1032 are both connected to the data lines (1021, 1022).
  • Both the first output terminal of the first demultiplexing switch 1031 and the second output terminal of the second demultiplexing switch 1032 are connected to one end of the signal transmission line (104, 105, 106).
  • the first demultiplexing switch 1031 and the second demultiplexing switch 1032 are configured to be turned on or off at the same time when the level of the first control signal and the level of the second control signal are opposite, That is, the first demultiplexing switch 1031 and the second demultiplexing switch 1032 simultaneously output or do not output the data signals to the two signal transmission lines (104, 105, 106) that are respectively connected.
  • the first control terminal of the first demultiplexing switch 1031 is directly connected to the first control line (CK1, CK2, CK3), and the second of the second demultiplexing switch 1032 is The control end is connected to the second control line (XCK1, XCK2, XCK3) through an NOT gate.
  • the first demultiplexing switch 1031 When the first control signal is at a high level, the first demultiplexing switch 1031 is turned on, and when the first control signal is at a low level, the first demultiplexing switch 1031 is turned off.
  • the second demultiplexing switch 1032 When the second control signal is at a high level, the second demultiplexing switch 1032 is turned off, and when the second control signal is at a low level, the second demultiplexing switch 1032 is turned on.
  • High-level waveform / low-level waveform of one of the two control line combinations (CK1 and XCK1, CK2 and XCK2, CK3, and XCK3) relative to the two control line combinations (CK1 and XCK1, CK2 and XCK2, CK3)
  • the high-level waveform / low-level waveform of the other of XCK3) is delayed by a predetermined time.
  • the high-level / low-level waveforms of the second set of control line combinations (CK2 and XCK2) are delayed relative to the high-level / low-level waveforms of the first set of control line combinations (CK1 and XCK1).
  • the predetermined time The high-level waveform / low-level waveform of the third group of control line combinations (CK3 and XCK3) is delayed by the predetermined time relative to the high-level waveform / low-level waveform of the second group of control line combinations (CK2 and XCK2). .
  • none of the signals transmitted by the three signal transmission lines (104, 105, 106) is affected by the first control signal and the second control signal.
  • FIG. 3 is a schematic diagram of a second embodiment of a display panel of the present invention.
  • the second embodiment of the present invention is similar to the first embodiment described above, except that:
  • control line combinations (CK1 and XCK1, CK2, and XCK2) are disposed on a side of the demultiplexing switch combination 103 near the pixel array 101, and one control line combination (CK3 and XCK3) is disposed on a side of the demultiplexing switch combination 103 away from the pixel array 101.
  • the number of the control line combinations (CK1 and XCK1, CK2 and XCK2) that intersect with the signal transmission lines (104, 105, 106) is two, and the signal transmission lines (104, 105, 106) and the two The first control line (CK1, CK2, CK3) and the two second control lines (XCK1, XCK2, XCK3) meet at a side 107 of the demultiplexing switch combination 103 near the pixel array 101.
  • the first derived pulse signal and the second derived pulse signal generated by the signal transmission line (104, 105, 106) due to the intersection with the first set of control line combinations (CK1 and XCK1) are canceled;
  • the signal transmission line (104, 105, 106) generates another first derivative pulse signal and another second derivative due to the intersection with the second group of control line combinations (CK2 and XCK2).
  • the pulse signals are canceled.
  • FIG. 4 is a schematic diagram of a third embodiment of a display panel of the present invention.
  • the third embodiment of the present invention is similar to the first or second embodiment described above, except that:
  • the number of the control line combinations (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) provided on the side 107 of the demultiplexing switch combination 103 close to the pixel array 101 is zero.
  • the three control line combinations (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) are all disposed on a side of the demultiplexing switch combination 103 away from the pixel array 101.
  • the number of the control line combinations (CK1 and XCK1, CK2 and XCK2, CK3 and XCK3) that intersect with the signal transmission lines (104, 105, 106) is 0, and the signal transmission lines (104, 105, 106) No intersection with any line of control.
  • FIG. 5 is a schematic diagram of a fourth embodiment of a display panel of the present invention.
  • the fourth embodiment of the present invention is similar to the first embodiment described above, except that:
  • the number of the control line combinations (CK1 and XCK1, CK2, and XCK2) is two.
  • One control line combination (CK1 and XCK1) is provided on the side 107 of the demultiplexing switch combination 103 near the pixel array 101, and one control line combination (CK2 and XCK2) is provided on the demultiplexing
  • the switch combination 103 is far from a side of the pixel array 101.
  • the number of the control line combinations (CK1 and XCK1) that intersect with the signal transmission lines (104, 105, 106) is 1, and the signal transmission lines (104, 105, 106) are combined with the control lines (CK1 and XCK1) meet at a side of the demultiplexing switch combination 103 near the pixel array 101.
  • the high-level / low-level waveforms of the second set of control line combinations (CK2 and XCK2) are delayed relative to the high-level / low-level waveforms of the first set of control line combinations (CK1 and XCK1).
  • the two signal transmission lines (104, 105, 106) is affected by the first control signal and the second control signal.
  • FIG. 7 is a schematic diagram of a fifth embodiment of a display panel of the present invention.
  • the fifth embodiment of the present invention is similar to the fourth embodiment described above, except that:
  • the number of the control line combinations (CK1 and XCK1, CK2 and XCK2) provided on the side 107 of the demultiplexing switch combination 103 close to the pixel array 101 is zero, and the two control The line combinations (CK1 and XCK1, CK2, and XCK2) are all disposed on a side of the demultiplexing switch combination 103 away from the pixel array 101.
  • the number of the control line combinations (CK1 and XCK1, CK2 and XCK2) that intersect with the signal transmission lines (104, 105, 106) is 0, and the signal transmission lines (104, 105, 106) are not controlled by any Intersection of lines.
  • the level of the first control signal transmitted by the first control line is opposite to the level of the second control signal transmitted by the second control line, and is the same as the signal transmission line
  • the number of the combined control line combinations is greater than or equal to 0. Therefore, the first derived pulse signal corresponding to the first control signal and the second derived pulse signal corresponding to the second control signal formed on the signal transmission line.
  • the derived pulse signals are canceled, so that it is possible to prevent the derived pulse signal generated by the signal transmission line and the control line used to control the demultiplexing switch from intersecting from affecting the picture displayed on the display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板,包括解复用开关组合(103)、信号传输线(104、105、106)、第一控制线(CK1)和第二控制线(XCK1);第一控制线(CK1)和第二控制线(XCK1)连接解复用开关组合(102),第一控制线(CK1)的信号的电平和第二控制线(XCK1)的信号的电平相反,与信号传输线(104、105、106)交汇的第一控制线(CK1)和第二控制线(XCK1)的组合的数量大于或等于0。能避免显示面板的画面因线路交汇而受到影响。

Description

显示面板 技术领域
本发明涉及显示技术领域,特别涉及一种显示面板。
背景技术
传统的显示面板的解复用电路一般用于对数据驱动电路所产生的数据信号进行解复用,并将经过解复用的数据信号输入至像素阵列。
在实践中,发明人发现现有技术至少存在以下问题:
传输经过解复用的数据信号的信号线与控制解复用电路的控制线存在交叠(交汇)部分,因此,该信号线中的经过解复用的数据信号会受到该控制线所传输的控制信号的影响,从而导致显示面板所显示的画面受影响。
故,有必要提出一种新的技术方案,以解决上述技术问题。
技术问题
本发明的目的在于提供一种显示面板,其能避免信号传输线与用于控制解复用开关的控制线组合因交汇而产生的派生脉冲信号对显示面板所显示的画面造成影响。
技术解决方案
为解决上述问题,本发明的技术方案如下:
一种显示面板,所述显示面板包括:像素阵列,所述像素阵列包括至少一像素列;数据驱动电路,所述数据驱动电路至少包括一数据线;扫描驱动电路,所述扫描驱动电路连接所述像素阵列;解复用电路,所述解复用电路连接所述像素阵列和所述数据线,所述解复用电路包括:解复用开关组合,所述解复用开关组合与所述数据线连接;信号传输线,所述信号传输线的两端分别连接所述解复用开关组合和所述像素列;以及控制线组合,所述控制线组合连接所述解复用开关组合,所述控制线组合包括第一控制线和第二控制线,所述第一控制线所传输的第一控制信号的电平和所述第二控制线所传输的第二控制信号的电平相反,与所述信号传输线交汇的所述控制线组合的数量大于或等于0;所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧和/或设置于所述解复用开关组合远离所述像素阵列的一侧;在所述第一控制信号为高电平时,所述第二控制信号为低电平,在所述第一控制信号为低电平时,所述第二控制信号为高电平。
在上述显示面板中,在与所述信号传输线交汇的所述控制线组合的数量大于0的情况下,所述信号传输线与所述控制线组合的交汇处位于所述解复用开关组合靠近所述像素阵列的一侧。
在上述显示面板中,所述控制线组合的数量为2或3。
在上述显示面板中,两所述控制线组合中的一者的高电平波形/低电平波形相对两所述控制线组合中的另一者的高电平波形/低电平波形延迟预定时间。
在上述显示面板中,电平相反的所述第一控制信号和所述第二控制信号用于平衡由于所述控制线组合与所述信号传输线交汇而产生的对所述数据线所传输的数据信号的耦合作用。
一种显示面板,所述显示面板包括:像素阵列,所述像素阵列包括至少一像素列;数据驱动电路,所述数据驱动电路至少包括一数据线;扫描驱动电路,所述扫描驱动电路连接所述像素阵列;解复用电路,所述解复用电路连接所述像素阵列和所述数据线,所述解复用电路包括:解复用开关组合,所述解复用开关组合与所述数据线连接;信号传输线,所述信号传输线的两端分别连接所述解复用开关组合和所述像素列;以及控制线组合,所述控制线组合连接所述解复用开关组合,所述控制线组合包括第一控制线和第二控制线,所述第一控制线所传输的第一控制信号的电平和所述第二控制线所传输的第二控制信号的电平相反,与所述信号传输线交汇的所述控制线组合的数量大于或等于0。
在上述显示面板中,所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧和/或设置于所述解复用开关组合远离所述像素阵列的一侧。
在上述显示面板中,在与所述信号传输线交汇的所述控制线组合的数量大于0的情况下,所述信号传输线与所述控制线组合的交汇处位于所述解复用开关组合靠近所述像素阵列的一侧。
在上述显示面板中,所述控制线组合的数量为2或3。
在上述显示面板中,在所述控制线组合的数量为3的情况下,一所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧,两所述控制线组合设置于所述解复用开关组合远离所述像素阵列的一侧。
在上述显示面板中,在所述控制线组合的数量为3的情况下,两所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧,一所述控制线组合设置于所述解复用开关组合远离所述像素阵列的一侧。
在上述显示面板中,在所述控制线组合的数量为3的情况下,设置于所述解复用开关组合靠近所述像素阵列的一侧的所述控制线组合的数量为零,三所述控制线组合均设置于所述解复用开关组合远离所述像素阵列的一侧。
在上述显示面板中,在所述控制线组合的数量为2的情况下,一所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧,一所述控制线组合设置于所述解复用开关组合远离所述像素阵列的一侧。
在上述显示面板中,在所述控制线组合的数量为2的情况下,设置于所述解复用开关组合靠近所述像素阵列的一侧的所述控制线组合的数量为零,两所述控制线组合均设置于所述解复用开关组合远离所述像素阵列的一侧。
在上述显示面板中,电平相反的所述第一控制信号和所述第二控制信号用于平衡由于所述控制线组合与所述信号传输线交汇而产生的对所述数据线所传输的数据信号的耦合作用。
在上述显示面板中,所述解复用开关组合包括第一解复用开关和第二解复用开关;所述第一解复用开关的第一控制端与所述第一控制线连接,所述第二解复用开关的第二控制端与所述第二控制线连接;所述第一解复用开关的第一输入端和所述第二解复用开关的第二输入端均与所述数据线连接;所述第一解复用开关的第一输出端和所述第二解复用开关的第二输出端均与所述信号传输线的一端连接。
在上述显示面板中,所述第一解复用开关与所述第二解复用开关用于在所述第一控制信号的电平和所述第二控制信号的电平相反的情况下同时开启或同时关闭。
在上述显示面板中,在所述第一控制信号为高电平时,所述第一解复用开关开启,在所述第一控制信号为低电平时,所述第一解复用开关关闭;在所述第二控制信号为高电平时,所述第二解复用开关关闭,在所述第二控制信号为低电平时,所述第二解复用开关开启。
在上述显示面板中,在所述第一控制信号为高电平时,所述第二控制信号为低电平;在所述第一控制信号为低电平时,所述第二控制信号为高电平。
在上述显示面板中,两所述控制线组合中的一者的高电平波形/低电平波形相对两所述控制线组合中的另一者的高电平波形/低电平波形延迟预定时间。
有益效果
相对现有技术,在本发明中,由于所述第一控制线所传输的所述第一控制信号的电平和所述第二控制线所传输的所述第二控制信号的电平相反,并且与所述信号传输线交汇的所述控制线组合的数量大于或等于0,因此,所述信号传输线上所形成的与所述第一控制信号对应的第一派生脉冲信号和与所述第二控制信号对应的第二派生脉冲信号相抵消,因此能避免信号传输线与用于控制解复用开关的控制线组合因交汇而产生的派生脉冲信号对显示面板所显示的画面造成影响。
附图说明
图1为本发明的显示面板的第一实施例的示意图。
图2为图1所示的显示面板中控制线组合所传输的控制信号与信号传输线所传输的数据信号的波形图。
图3为本发明的显示面板的第二实施例的示意图。
图4为本发明的显示面板的第三实施例的示意图。
图5为本发明的显示面板的第四实施例的示意图。
图6为图5所示的显示面板中控制线组合所传输的控制信号与信号传输线所传输的数据信号的波形图。
图7为本发明的显示面板的第五实施例的示意图。
本发明的实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外,本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”,除非另外指定或从上下文可以清楚确定单数形式。
参考图1和图2,图1为本发明的显示面板的第一实施例的示意图,图2为图1所示的显示面板中控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)所传输的控制信号与信号传输线(104、105、106)所传输的数据信号的波形图。
本实施例的显示面板可以是TFT-LCD(Thin Film Transistor Liquid Crystal Display,薄膜晶体管液晶显示面板)、OLED(Organic Light Emitting Diode,有机发光二极管显示面板)等。
本实施例的显示面板包括像素阵列101、数据驱动电路102、扫描驱动电路、解复用电路。
所述像素阵列101包括至少一像素列(1011、1012、1013、1014、1015、1016)。
所述数据驱动电路102至少包括一数据线(1021、1022)。所述数据线(1021、1022)用于传输待解复用的数据信号。
所述扫描驱动电路连接所述像素阵列101。
所述解复用电路连接所述像素阵列101和所述数据线(1021、1022),所述解复用电路包括解复用开关组合103、信号传输线(104、105、106)、控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)。
所述解复用开关组合103与所述数据线(1021、1022)连接。
所述信号传输线(104、105、106)的两端分别连接所述解复用开关组合103和所述像素列(1011、1012、1013、1014、1015、1016)。所述信号传输线(104、105、106)用于传输经过解复用的数据信号。
其中,一所述数据线(1021、1022)与两/三所述解复用开关组合103连接,两/三所述解复用开关组合103分别通过两/三所述信号传输线(104、105、106)与两/三所述像素列(1011、1012、1013、1014、1015、1016)连接。
所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)连接所述解复用开关组合103,所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)包括第一控制线(CK1、CK2、CK3)和第二控制线(XCK1、XCK2、XCK3),所述第一控制线(CK1、CK2、CK3)所传输的第一控制信号的电平和所述第二控制线(XCK1、XCK2、XCK3)所传输的第二控制信号的电平相反,与所述信号传输线(104、105、106)交汇的所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)的数量大于或等于0。
具体地,在本实施例中,在同一时间中,在所述第一控制信号为高电平时,所述第二控制信号为低电平;在所述第一控制信号为低电平时,所述第二控制信号为高电平。
所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)设置于所述解复用开关组合103靠近所述像素阵列101的一侧107和/或设置于所述解复用开关组合103远离所述像素阵列101的一侧。
在与所述信号传输线(104、105、106)交汇的所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)的数量大于0的情况下,所述信号传输线(104、105、106)与所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)的交汇处位于所述解复用开关组合103靠近所述像素阵列101的一侧107。
所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)的数量为2或3。
如图1所示,所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)的数量为3。一所述控制线组合(CK1和XCK1)设置于所述解复用开关组合103靠近所述像素阵列101的一侧,两所述控制线组合(CK2和XCK2、CK3和XCK3)设置于所述解复用开关组合103远离所述像素阵列101的一侧。
即,与所述信号传输线(104、105、106)交汇的所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)的数量为1,并且,所述信号传输线(104、105、106)与所述控制线组合(CK1和XCK1)在所述解复用开关组合103靠近所述像素阵列101的一侧处交汇。
所述第一控制线(CK1)和所述第二控制线(XCK1)位于所述解复用开关组合103的同一侧,并且所述第一控制线(CK1)和所述第二控制线(XCK1)相邻。
电平相反的所述第一控制信号和所述第二控制信号用于平衡(抵消)由于所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)与所述信号传输线(104、105、106)交汇而产生的对所述数据线(1021、1022)所传输的数据信号的耦合作用。
具体地,由于所述信号传输线(104、105、106)与所述第一控制线(CK1)和所述第二控制线(XCK1)交汇,因此,所述信号传输线(104、105、106)与所述第一控制线(CK1)形成有第一电容,所述信号传输线(104、105、106)与所述第二控制线(XCK1)形成有第二电容。
当所述第一控制线(CK1)所传输的所述第一控制信号发生变化时,所述第一电容的一极板(所述第一控制线(CK1))的电荷量发生变化,此时,所述第一电容的另一极板(所述信号传输线(104、105、106))的电荷量也会发生变化,因此,所述信号传输线(104、105、106)上会形成一个派生信号(第一派生脉冲信号)。
同理,当所述第二控制线(XCK1)所传输的所述第二控制信号发生变化时,所述第二电容的一极板(所述第二控制线(XCK1))的电荷量发生变化,此时,所述第二电容的另一极板(所述信号传输线(104、105、106))的电荷量也会发生变化,因此,所述信号传输线(104、105、106)上会形成一个派生信号(第二派生脉冲信号)。
由于所述信号传输线(104、105、106)用于传输经过解复用后的数据信号,所述第一派生脉冲信号和所述第二派生脉冲信号会与所述数据信号叠加(复用),并输入至像素列(1011、1012、1013、1014、1015、1016),此时,所述第一派生脉冲信号和所述第二派生脉冲信号会对所述显示面板所显示的画面产生影响。
在本实施例中,由于所述第一控制线(CK1)所传输的所述第一控制信号的电平和所述第二控制线(XCK1)所传输的所述第二控制信号的电平相反,因此,所述第一派生脉冲信号和所述第二派生脉冲信号的电平相反。在所述第一解复用开关1031和所述第二解复用开关1032均开启的情况下,与所述数据信号叠加(复用)的所述第一派生脉冲信号和所述第二派生脉冲信号会相互抵消,即,所述第一控制信号和所述第二控制信号对所述数据信号的耦合作用相抵消,避免了所述第一派生脉冲信号和所述第二派生脉冲信号对所述显示面板所显示的画面产生影响。在所述第一解复用开关1031和所述第二解复用开关1032均关闭的情况下,所述第一派生脉冲信号和所述第二派生脉冲信号也会相互抵消,因此也不会对所述显示面板所显示的画面产生影响。
在本实施例中,所述解复用开关组合103包括第一解复用开关1031和第二解复用开关1032。
所述第一解复用开关1031的第一控制端与所述第一控制线(CK1、CK2、CK3)连接,所述第二解复用开关1032的第二控制端与所述第二控制线(XCK1、XCK2、XCK3)连接。
所述第一解复用开关1031的第一输入端和所述第二解复用开关1032的第二输入端均与所述数据线(1021、1022)连接。
所述第一解复用开关1031的第一输出端和所述第二解复用开关1032的第二输出端均与所述信号传输线(104、105、106)的一端连接。
所述第一解复用开关1031与所述第二解复用开关1032用于在所述第一控制信号的电平和所述第二控制信号的电平相反的情况下同时开启或同时关闭,即,所述第一解复用开关1031和所述第二解复用开关1032同时向分别连接的两所述信号传输线(104、105、106)输出或不输出所述数据信号。
具体地,所述第一解复用开关1031的所述第一控制端直接与所述第一控制线(CK1、CK2、CK3)连接,所述第二解复用开关1032的所述第二控制端通过非门与所述第二控制线(XCK1、XCK2、XCK3)连接。
在所述第一控制信号为高电平时,所述第一解复用开关1031开启,在所述第一控制信号为低电平时,所述第一解复用开关1031关闭。
在所述第二控制信号为高电平时,所述第二解复用开关1032关闭,在所述第二控制信号为低电平时,所述第二解复用开关1032开启。
两所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)中的一者的高电平波形/低电平波形相对两所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)中的另一者的高电平波形/低电平波形延迟预定时间。
如图2所示,第二组控制线组合(CK2和XCK2)的高电平波形/低电平波形相对第一组控制线组合(CK1和XCK1)的高电平波形/低电平波形延迟所述预定时间。第三组控制线组合(CK3和XCK3)的高电平波形/低电平波形相对所述第二组控制线组合(CK2和XCK2)的高电平波形/低电平波形延迟所述预定时间。此时,三所述信号传输线(104、105、106)所传输的信号均没有受到所述第一控制信号和所述第二控制信号的影响。
参考图3,图3为本发明的显示面板的第二实施例的示意图。本发明的第二实施例与上述第一实施例相似,不同之处在于:
在本实施例中,两所述控制线组合(CK1和XCK1、CK2和XCK2)设置于所述解复用开关组合103靠近所述像素阵列101的一侧,一所述控制线组合(CK3和XCK3)设置于所述解复用开关组合103远离所述像素阵列101的一侧。
即,与所述信号传输线(104、105、106)交汇的所述控制线组合(CK1和XCK1、CK2和XCK2)的数量为2,所述信号传输线(104、105、106)与两所述第一控制线(CK1、CK2、CK3)和两所述第二控制线(XCK1、XCK2、XCK3)在所述解复用开关组合103靠近所述像素阵列101的一侧107处交汇。
在第一时间,所述信号传输线(104、105、106)因与第一组控制线组合(CK1和XCK1)交汇而产生的第一派生脉冲信号和第二派生脉冲信号相抵消;在经过所述预定时间后的第二时间,所述信号传输线(104、105、106)因与第二组控制线组合(CK2和XCK2)交汇而产生的另一第一派生脉冲信号和另一第二派生脉冲信号相抵消。
参考图4,图4为本发明的显示面板的第三实施例的示意图。本发明的第三实施例与上述第一实施例或第二实施例相似,不同之处在于:
在本实施例中,设置于所述解复用开关组合103靠近所述像素阵列101的一侧107的所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)的数量为零,三所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)均设置于所述解复用开关组合103远离所述像素阵列101的一侧。
即,与所述信号传输线(104、105、106)交汇的所述控制线组合(CK1和XCK1、CK2和XCK2、CK3和XCK3)的数量为0,所述信号传输线(104、105、106)没有与任何控制线交汇。
此时,所述信号传输线(104、105、106)上不会产生任何派生脉冲信号。
参考图5,图5为本发明的显示面板的第四实施例的示意图。本发明的第四实施例与上述第一实施例相似,不同之处在于:
在本实施例中,所述控制线组合(CK1和XCK1、CK2和XCK2)的数量为2。一所述控制线组合(CK1和XCK1)设置于所述解复用开关组合103靠近所述像素阵列101的一侧107,一所述控制线组合(CK2和XCK2)设置于所述解复用开关组合103远离所述像素阵列101的一侧。
即,与所述信号传输线(104、105、106)交汇的所述控制线组合(CK1和XCK1)的数量为1,并且,所述信号传输线(104、105、106)与所述控制线组合(CK1和XCK1)在所述解复用开关组合103靠近所述像素阵列101的一侧处交汇。
如图6所示,第二组控制线组合(CK2和XCK2)的高电平波形/低电平波形相对第一组控制线组合(CK1和XCK1)的高电平波形/低电平波形延迟所述预定时间,此时,两所述信号传输线(104、105、106)所传输的信号均没有受到所述第一控制信号和所述第二控制信号的影响。
参考图7,图7为本发明的显示面板的第五实施例的示意图。本发明的第五实施例与上述第四实施例相似,不同之处在于:
在本实施例中,设置于所述解复用开关组合103靠近所述像素阵列101的一侧107的所述控制线组合(CK1和XCK1、CK2和XCK2)的数量为零,两所述控制线组合(CK1和XCK1、CK2和XCK2)均设置于所述解复用开关组合103远离所述像素阵列101的一侧。
即,与所述信号传输线(104、105、106)交汇的所述控制线组合(CK1和XCK1、CK2和XCK2)的数量为0,所述信号传输线(104、105、106)没有与任何控制线交汇。
此时,所述信号传输线(104、105、106)上不会产生任何派生脉冲信号。
在本发明中,由于所述第一控制线所传输的所述第一控制信号的电平和所述第二控制线所传输的所述第二控制信号的电平相反,并且与所述信号传输线交汇的所述控制线组合的数量大于或等于0,因此,所述信号传输线上所形成的与所述第一控制信号对应的第一派生脉冲信号和与所述第二控制信号对应的第二派生脉冲信号相抵消,因此能避免所述信号传输线与用于控制解复用开关的控制线组合因交汇而产生的派生脉冲信号对所述显示面板所显示的画面造成影响。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板,其中,所述显示面板包括:
    像素阵列,所述像素阵列包括至少一像素列;
    数据驱动电路,所述数据驱动电路至少包括一数据线;
    扫描驱动电路,所述扫描驱动电路连接所述像素阵列;
    解复用电路,所述解复用电路连接所述像素阵列和所述数据线,所述解复用电路包括:
    解复用开关组合,所述解复用开关组合与所述数据线连接;
    信号传输线,所述信号传输线的两端分别连接所述解复用开关组合和所述像素列;以及
    控制线组合,所述控制线组合连接所述解复用开关组合,所述控制线组合包括第一控制线和第二控制线,所述第一控制线所传输的第一控制信号的电平和所述第二控制线所传输的第二控制信号的电平相反,与所述信号传输线交汇的所述控制线组合的数量大于或等于0;
    所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧和/或设置于所述解复用开关组合远离所述像素阵列的一侧;
    在所述第一控制信号为高电平时,所述第二控制信号为低电平,在所述第一控制信号为低电平时,所述第二控制信号为高电平。
  2. 根据权利要求1所述的显示面板,其中,在与所述信号传输线交汇的所述控制线组合的数量大于0的情况下,所述信号传输线与所述控制线组合的交汇处位于所述解复用开关组合靠近所述像素阵列的一侧。
  3. 根据权利要求1所述的显示面板,其中,所述控制线组合的数量为2或3。
  4. 根据权利要求1所述的显示面板,其中,两所述控制线组合中的一者的高电平波形/低电平波形相对两所述控制线组合中的另一者的高电平波形/低电平波形延迟预定时间。
  5. 根据权利要求1所述的显示面板,其中,电平相反的所述第一控制信号和所述第二控制信号用于平衡由于所述控制线组合与所述信号传输线交汇而产生的对所述数据线所传输的数据信号的耦合作用。
  6. 一种显示面板,其中,所述显示面板包括:
    像素阵列,所述像素阵列包括至少一像素列;
    数据驱动电路,所述数据驱动电路至少包括一数据线;
    扫描驱动电路,所述扫描驱动电路连接所述像素阵列;
    解复用电路,所述解复用电路连接所述像素阵列和所述数据线,所述解复用电路包括:
    解复用开关组合,所述解复用开关组合与所述数据线连接;
    信号传输线,所述信号传输线的两端分别连接所述解复用开关组合和所述像素列;以及
    控制线组合,所述控制线组合连接所述解复用开关组合,所述控制线组合包括第一控制线和第二控制线,所述第一控制线所传输的第一控制信号的电平和所述第二控制线所传输的第二控制信号的电平相反,与所述信号传输线交汇的所述控制线组合的数量大于或等于0。
  7. 根据权利要求6所述的显示面板,其中,所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧和/或设置于所述解复用开关组合远离所述像素阵列的一侧。
  8. 根据权利要求7所述的显示面板,其中,在与所述信号传输线交汇的所述控制线组合的数量大于0的情况下,所述信号传输线与所述控制线组合的交汇处位于所述解复用开关组合靠近所述像素阵列的一侧。
  9. 根据权利要求7所述的显示面板,其中,所述控制线组合的数量为2或3。
  10. 根据权利要求9所述的显示面板,其中,在所述控制线组合的数量为3的情况下,一所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧,两所述控制线组合设置于所述解复用开关组合远离所述像素阵列的一侧。
  11. 根据权利要求9所述的显示面板,其中,在所述控制线组合的数量为3的情况下,两所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧,一所述控制线组合设置于所述解复用开关组合远离所述像素阵列的一侧。
  12. 根据权利要求9所述的显示面板,其中,在所述控制线组合的数量为3的情况下,设置于所述解复用开关组合靠近所述像素阵列的一侧的所述控制线组合的数量为零,三所述控制线组合均设置于所述解复用开关组合远离所述像素阵列的一侧。
  13. 根据权利要求9所述的显示面板,其中,在所述控制线组合的数量为2的情况下,一所述控制线组合设置于所述解复用开关组合靠近所述像素阵列的一侧,一所述控制线组合设置于所述解复用开关组合远离所述像素阵列的一侧。
  14. 根据权利要求9所述的显示面板,其中,在所述控制线组合的数量为2的情况下,设置于所述解复用开关组合靠近所述像素阵列的一侧的所述控制线组合的数量为零,两所述控制线组合均设置于所述解复用开关组合远离所述像素阵列的一侧。
  15. 根据权利要求6所述的显示面板,其中,电平相反的所述第一控制信号和所述第二控制信号用于平衡由于所述控制线组合与所述信号传输线交汇而产生的对所述数据线所传输的数据信号的耦合作用。
  16. 根据权利要求15所述的显示面板,其中,所述解复用开关组合包括第一解复用开关和第二解复用开关;
    所述第一解复用开关的第一控制端与所述第一控制线连接,所述第二解复用开关的第二控制端与所述第二控制线连接;
    所述第一解复用开关的第一输入端和所述第二解复用开关的第二输入端均与所述数据线连接;
    所述第一解复用开关的第一输出端和所述第二解复用开关的第二输出端均与所述信号传输线的一端连接。
  17. 根据权利要求16所述的显示面板,其中,所述第一解复用开关与所述第二解复用开关用于在所述第一控制信号的电平和所述第二控制信号的电平相反的情况下同时开启或同时关闭。
  18. 根据权利要求17所述的显示面板,其中,在所述第一控制信号为高电平时,所述第一解复用开关开启,在所述第一控制信号为低电平时,所述第一解复用开关关闭;
    在所述第二控制信号为高电平时,所述第二解复用开关关闭,在所述第二控制信号为低电平时,所述第二解复用开关开启。
  19. 根据权利要求6所述的显示面板,其中,在所述第一控制信号为高电平时,所述第二控制信号为低电平;
    在所述第一控制信号为低电平时,所述第二控制信号为高电平。
  20. 根据权利要求6所述的显示面板,其中,两所述控制线组合中的一者的高电平波形/低电平波形相对两所述控制线组合中的另一者的高电平波形/低电平波形延迟预定时间。
PCT/CN2019/072600 2018-08-31 2019-01-22 显示面板 WO2020042533A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/477,685 US11605326B2 (en) 2018-08-31 2019-01-22 Display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811009154.1 2018-08-31
CN201811009154.1A CN108877637B (zh) 2018-08-31 2018-08-31 显示面板

Publications (1)

Publication Number Publication Date
WO2020042533A1 true WO2020042533A1 (zh) 2020-03-05

Family

ID=64322719

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/072600 WO2020042533A1 (zh) 2018-08-31 2019-01-22 显示面板

Country Status (3)

Country Link
US (1) US11605326B2 (zh)
CN (1) CN108877637B (zh)
WO (1) WO2020042533A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108877637B (zh) 2018-08-31 2023-11-07 武汉华星光电技术有限公司 显示面板
CN110335561B (zh) * 2019-04-03 2021-03-16 武汉华星光电技术有限公司 多路复用电路
TWI698847B (zh) * 2019-04-15 2020-07-11 友達光電股份有限公司 低阻抗顯示器
CN110264970A (zh) * 2019-06-14 2019-09-20 武汉华星光电技术有限公司 显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1952765A (zh) * 2006-11-07 2007-04-25 友达光电股份有限公司 解复用器的布局结构及具有该解复用器的液晶显示面板
CN102682687A (zh) * 2011-03-10 2012-09-19 精工爱普生株式会社 驱动用集成电路及电子设备
CN104112423A (zh) * 2013-04-16 2014-10-22 三星显示有限公司 有机发光二极管显示器
CN106601164A (zh) * 2015-10-14 2017-04-26 群创光电股份有限公司 显示面板
JP2017227755A (ja) * 2016-06-22 2017-12-28 セイコーエプソン株式会社 電気光学装置、電気光学装置の駆動方法、および電子機器
CN108877637A (zh) * 2018-08-31 2018-11-23 武汉华星光电技术有限公司 显示面板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI447692B (zh) * 2011-11-18 2014-08-01 Au Optronics Corp 顯示面板及其中之多工器電路和信號傳送方法
US8836679B2 (en) * 2012-08-06 2014-09-16 Au Optronics Corporation Display with multiplexer feed-through compensation and methods of driving same
TWI496130B (zh) * 2013-03-13 2015-08-11 Au Optronics Corp 顯示器及其中之信號傳送方法
KR102058691B1 (ko) * 2013-06-26 2019-12-26 삼성디스플레이 주식회사 유기전계발광 표시장치 및 그의 구동방법
KR102098743B1 (ko) * 2013-10-02 2020-04-09 삼성디스플레이 주식회사 유기 발광 표시 패널
TWI549107B (zh) * 2014-11-05 2016-09-11 群創光電股份有限公司 顯示裝置
US9865189B2 (en) * 2015-09-30 2018-01-09 Synaptics Incorporated Display device having power saving glance mode
CN105810173B (zh) * 2016-05-31 2018-08-14 武汉华星光电技术有限公司 多路复用型显示驱动电路
KR102526355B1 (ko) * 2016-09-22 2023-05-02 엘지디스플레이 주식회사 유기 발광 표시 장치
JP2018124448A (ja) * 2017-02-01 2018-08-09 株式会社ジャパンディスプレイ 表示装置
CN208737862U (zh) * 2018-08-31 2019-04-12 武汉华星光电技术有限公司 显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1952765A (zh) * 2006-11-07 2007-04-25 友达光电股份有限公司 解复用器的布局结构及具有该解复用器的液晶显示面板
CN102682687A (zh) * 2011-03-10 2012-09-19 精工爱普生株式会社 驱动用集成电路及电子设备
CN104112423A (zh) * 2013-04-16 2014-10-22 三星显示有限公司 有机发光二极管显示器
CN106601164A (zh) * 2015-10-14 2017-04-26 群创光电股份有限公司 显示面板
JP2017227755A (ja) * 2016-06-22 2017-12-28 セイコーエプソン株式会社 電気光学装置、電気光学装置の駆動方法、および電子機器
CN108877637A (zh) * 2018-08-31 2018-11-23 武汉华星光电技术有限公司 显示面板

Also Published As

Publication number Publication date
CN108877637A (zh) 2018-11-23
US11605326B2 (en) 2023-03-14
CN108877637B (zh) 2023-11-07
US20210358363A1 (en) 2021-11-18

Similar Documents

Publication Publication Date Title
WO2020042533A1 (zh) 显示面板
KR101143004B1 (ko) 시프트 레지스터 및 이를 포함하는 표시 장치
US9870756B2 (en) Display panel
KR102349500B1 (ko) 액정표시장치
US8144114B2 (en) Liquid crystal display
KR102219667B1 (ko) 표시장치
TWI460708B (zh) 影像顯示裝置及驅動該影像顯示裝置的方法
US9607580B2 (en) Driving method to improve stereoscopic image display visibility
JP2007193340A (ja) 液晶表示装置
JP2006048051A (ja) 液晶表示装置
US9778528B2 (en) Display apparatus
US10573244B2 (en) Gate driving circuit and display device including the same
US20150364069A1 (en) Pixel structure and liquid crystal display device
US10008140B2 (en) Bright dot detection method and display panel
US20170146877A1 (en) Array Substrate And Liquid Crystal Display Panel
KR101957738B1 (ko) 영상표시장치 및 그 제조방법
US20150379952A1 (en) Display device
US11450288B2 (en) Display driving method, display driving circuit, and display device
US20090102764A1 (en) Liquid Crystal Display and Driving Method Therefor
US20170270883A1 (en) Gate driving circuit and display device including the same
WO2015096197A1 (zh) 画素结构及液晶显示装置
KR102332279B1 (ko) 게이트 구동회로와 그를 포함한 표시장치
KR102290615B1 (ko) 액정표시장치
JP2007212543A (ja) 表示ユニットおよびそれを備えた表示装置
KR20070116373A (ko) 액정 표시 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19855947

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19855947

Country of ref document: EP

Kind code of ref document: A1