WO2020042485A1 - 一种光电探测器及其制作方法 - Google Patents

一种光电探测器及其制作方法 Download PDF

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WO2020042485A1
WO2020042485A1 PCT/CN2018/123311 CN2018123311W WO2020042485A1 WO 2020042485 A1 WO2020042485 A1 WO 2020042485A1 CN 2018123311 W CN2018123311 W CN 2018123311W WO 2020042485 A1 WO2020042485 A1 WO 2020042485A1
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layer
semiconductor contact
photodetector
substrate
contact layer
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PCT/CN2018/123311
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English (en)
French (fr)
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胡艳
岳爱文
钟行
王权兵
林玲
刘科
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武汉电信器件有限公司
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Publication of WO2020042485A1 publication Critical patent/WO2020042485A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
    • H01L31/1035—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type the devices comprising active layers formed only by AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of chip manufacturing, in particular to a photodetector and a manufacturing method thereof.
  • photodetectors are widely used in optical communication systems as light receiving chips.
  • the photodetector rate of optical networks in 4G mobile communications for large-scale applications needs to reach 10 Gbit / s, and the optical networks in 5G mobile communications in the future need to reach 25 Gbit / s or higher.
  • Traditional planar photodetectors are trapped by too large junction capacitance and generally can only meet below 10Gbit / s, while waveguide detectors are difficult to apply on a large scale due to packaging and cost factors. Therefore, in order to achieve high transmission rates, high-speed photodetection
  • the device is mainly based on the structure of vertical light incident on the table.
  • the difficulty of the mesa photodetector process lies in the fabrication of mesa-type PN junctions.
  • Commonly used are reactive ion or inductively coupled plasma dry etching processes and selective chemical wet etching processes.
  • the dry etching process is easy to cause physical defects and reactive ion pollution, which affects the dark current and reliability of the photodetector; while the chemical wet etching process requires the selection of a suitable etching solution, the process consistency is difficult to control, and the yield is affected.
  • a mesa photodetector is generally formed using a dry etching process and a chemical wet etching process to ensure that the photodetector has a high transmission rate.
  • the photodetectors formed by these two processes have corresponding problems, which affect the performance of the photodetectors.
  • the mesa photodetector is formed by dry etching process, it is easy to cause physical defects and reactive ion pollution, which affects the dark current and reliability of the photodetector.
  • the mesa photodetector is formed by chemical wet etching process, the process consistency is difficult Control, affecting yield.
  • a method for manufacturing a photodetector includes:
  • a first semiconductor contact layer 2 and a dielectric layer 3 are sequentially grown on the substrate 1;
  • a mesa-shaped epitaxial layer 4 is selectively grown on the first semiconductor contact layer 2 by a deposition method
  • the dielectric layer 3 remaining on the first semiconductor contact layer 2 is removed, and a contact metal layer is formed on the substrate 1.
  • the mesa-shaped epitaxial layer 4 is selectively grown on the first semiconductor contact layer 2 by a deposition method including:
  • a mesa-shaped lower transition layer 41, an absorption layer 42, and an upper layer are selectively grown sequentially on the first semiconductor contact layer 2 by using a metal vapor organic vapor deposition or molecular beam deposition method.
  • the transition layer 43 and the second semiconductor contact layer 44 form a mesa-shaped epitaxial layer 4.
  • the epitaxial layer 4 includes a lower transition layer 41, an absorption layer 42, an upper transition layer 43 and a second semiconductor contact layer 44 which are arranged in a stack.
  • the removing the dielectric layer 3 remaining on the first semiconductor contact layer 2 and forming a contact metal layer on the substrate 1 includes:
  • a portion of the passivation layer 5 on the first semiconductor contact layer 2 is etched to obtain a first electrode contact region 21, and the passivation layer 5 on the second semiconductor contact layer 44 is etched to be exposed The second semiconductor contact layer 44;
  • a first contact metal layer 7 is formed on the passivation layer 5 on the left side of the substrate 1 and on the first electrode contact region 21, and on the passivation layer 5 on the right side of the substrate 1 and A second contact metal layer 8 is formed on the second electrode contact region 441.
  • the method for manufacturing the photodetector further includes:
  • a first electrode pad 71 is formed on the passivation layer 5 on the left side of the substrate 1, and on the passivation layer 5 on the right side of the substrate 1 Forming a second electrode pad 81;
  • the first electrode pad 71 is connected to the first contact metal layer 7, and the second electrode pad 81 is connected to the second contact metal layer 8.
  • the method for manufacturing the photodetector further includes:
  • the epitaxial layer 4 is cleaved to obtain a photodetector chip.
  • the first semiconductor contact layer 2 is an N-type InP contact layer
  • the second semiconductor contact layer 44 is a P-type InP contact layer
  • the lower transition layer 41 is an InGaAsP transition layer
  • the absorption layer 42 is The I-type InGaAs absorption layer
  • the upper transition layer 43 is an I-type InGaAsP transition layer.
  • removing the part of the dielectric layer 3 to form an opening 31 extending in a direction close to the first semiconductor contact layer 2 to define a growth region of the epitaxial layer 4 includes:
  • An etching or etching process is used to remove the dielectric layer 3 corresponding to the opening pattern, so as to form an opening 31 extending in a direction close to the first semiconductor contact layer 2 to define a growth area of the epitaxial layer 4.
  • sequentially growing the first semiconductor contact layer 2 and the dielectric layer 3 on the substrate 1 includes:
  • a dielectric layer 3 is grown on the first semiconductor contact layer 2 by means of plasma enhanced chemical vapor deposition.
  • the composition of the dielectric layer 3 includes silicon dioxide or silicon nitride.
  • a photodetector is provided.
  • the photodetector is manufactured by the method for manufacturing a photodetector according to the first aspect.
  • the embodiment of the present invention has the beneficial effect that the method for manufacturing the photodetector of the present invention first defines the growth region of the epitaxial layer, and then uses a deposition method to form a mesa-shaped epitaxy based on the growth region of the epitaxial layer. Layer, thereby forming a mesa-type PN junction.
  • the photodetector of the invention can effectively solve the problems of physical defects and reactive ion pollution caused by dry etching and the problem of poor consistency caused by chemical wet etching process.
  • the manufacturing method of the photodetector is not only simple in manufacturing process and suitable for mass production, but also has the advantages of high consistency and high reliability, and can effectively improve the performance of the photodetector.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a photodetector according to an embodiment of the present invention
  • FIG. 2 is a detailed flowchart of step 104
  • FIG. 3 is a schematic structural diagram of a photodetector formed after step 101;
  • FIG. 4 is a schematic structural diagram of a photodetector formed after step 102;
  • FIG. 5 is a schematic structural diagram of a photodetector formed after step 103;
  • FIG. 6 is a schematic structural diagram of a photodetector formed after step 1041;
  • FIG. 7 is a schematic structural diagram of a photodetector formed after step 1042;
  • FIG. 8 is a schematic structural diagram of a photodetector formed after step 1043;
  • FIG. 9 is a schematic structural diagram of a photodetector formed after step 1044;
  • FIG. 10 is a schematic structural diagram of a photodetector formed after step 1045;
  • FIG. 11 is a schematic structural diagram of a photodetector formed after step 1046;
  • FIG. 12 is a schematic top view of a photodetector according to an embodiment of the present invention.
  • orientations or positional relationships indicated by the terms “inside”, “outside”, “longitudinal”, “horizontal”, “upper”, “lower”, “top”, “bottom” and the like are based on the drawings
  • the orientations or positional relationships shown are merely for the convenience of describing the present invention and do not require that the present invention must be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention.
  • the photodetector is mainly composed of a vertical light incident table structure.
  • reactive ion or inductively coupled plasma dry etching process and selective chemical wet etching process are generally used. Form a mesa-type PN junction.
  • dry etching is easy to cause physical defects and reactive ion pollution, which affects the dark current and reliability of the photodetector; while the chemical wet etching process requires the selection of a suitable etching solution, the process consistency is difficult to control, and the yield is affected.
  • the present invention proposes a method for manufacturing a photodetector.
  • the method for manufacturing a photodetector first defines a growth region of an epitaxial layer, and then uses a deposition method to form a mesa-shaped epitaxial layer based on the growth region of the epitaxial layer. To form a mesa-type PN junction. It can effectively solve the problems of physical defects and reactive ion pollution caused by dry etching, and the problem of poor consistency caused by chemical wet etching.
  • the method for manufacturing a photodetector of the present invention specifically includes the following steps:
  • Step 101 A first semiconductor contact layer 2 and a dielectric layer 3 are sequentially grown on the substrate 1.
  • a substrate 1 is provided.
  • the substrate 1 may be an InP-Fe-doped semi-insulating substrate.
  • a first semiconductor contact layer 2 is grown on the substrate 1 by a metal vapor organic vapor deposition MOCVD (Metal-organic Chemical Vapor Deposition, MOCVD) or a molecular beam deposition MBE (Molecular Beam Epitaxy, MBE).
  • MOCVD Metal-organic Chemical Vapor Deposition
  • MBE molecular beam deposition
  • the first semiconductor contact layer 2 is an N-type InP contact layer.
  • the thickness of the first semiconductor contact layer 2 is 0.3 ⁇ m to 0.5 ⁇ m, and the N-type doping concentration is greater than 3e18 cm -3 .
  • a dielectric layer 3 is grown on the first semiconductor contact layer 2 by plasma enhanced chemical vapor deposition PECVD (Plasma Enhanced Chemical Deposition, PECVD for short).
  • PECVD Plasma enhanced chemical vapor deposition
  • the composition of the dielectric layer 3 includes silicon dioxide, and the thickness of the dielectric layer 3 is 2 ⁇ m to 2.5 ⁇ m.
  • the composition of the dielectric layer 3 includes silicon nitride. Since silicon dioxide is easier to be deposited, a thicker dielectric layer 3 can be made. In the actual manufacturing process, silicon dioxide is mostly used to form the dielectric layer 3.
  • Step 102 Remove a part of the dielectric layer 3 to form openings 31 extending along the direction near the first semiconductor contact layer 2 to define a growth region of the epitaxial layer 4, wherein the openings 31 penetrate the dielectric layer. 3.
  • the growth medium layer 3 has a thickness that is not less than a thickness of the epitaxial layer 4.
  • an opening 31 having a predetermined size is formed by a photolithography and an etching process.
  • the opening pattern is first defined by photolithography, and then the dielectric layer 3 corresponding to the opening pattern is removed by an etching or etching process, wherein the depth of the etching or etching is equal to the thickness of the dielectric layer 3, so that the formation along The opening 31 extends in the direction of the first semiconductor contact layer 2.
  • the shape corresponding to the opening pattern may be a square or a circle, and the size of the opening pattern may also be determined according to the actual situation.
  • the thickness of the dielectric layer 3 is greater than the thickness of the epitaxial layer 4. Since the size of the aperture directly affects the quality and performance of the photodetector, the quality of the epitaxial layer 4 cannot be guaranteed if the aperture is too small. 100fF and 3dB bandwidth cannot meet 25G applications. Therefore, the size of the aperture needs to be reasonably designed. In a preferred embodiment, the aperture is 12 ⁇ m to 18 ⁇ m.
  • the opening 31 formed in the dielectric layer 3 defines the growth region of the subsequent epitaxial layer 4.
  • the contact area of the intermediate region of the opening 31 in the horizontal direction is relatively small. Large, so the deposition speed is faster when the epitaxial layer 4 is deposited; and on the vertical plane near the edge area of the opening 31 (the area formed on the opposite side of the dielectric layer 3 on the left and right sides of the substrate 1) The contact area is small, and the deposition rate is slower when the epitaxial layer 4 is deposited. Therefore, when the epitaxial layer 4 is deposited, an epitaxial layer 4 with a mesa structure as shown in FIG. 5 is formed.
  • the deposition speed is along the direction close to the dielectric layer 3 It is getting slower and slower, which further promotes the formation of a mesa-type epitaxial layer 4 as shown in FIG. 5 when the epitaxial layer 4 is deposited. It can be known from the foregoing analysis that the contact area, the lattice, and other factors cause the epitaxial layer 4 formed by the deposition process to have a mesa structure as shown in FIG. 5.
  • Step 103 According to the growth region of the epitaxial layer 4, a mesa-shaped epitaxial layer 4 is selectively grown on the first semiconductor contact layer 2 by a deposition method.
  • a mesa-shaped epitaxial layer 4 is selectively grown on the first semiconductor contact layer 2 by a deposition method.
  • a mesa-shaped lower transition layer 41 is selectively grown sequentially on the first semiconductor contact layer 2 by using metal vapor organic vapor deposition MOCVD or molecular beam deposition MBE.
  • MOCVD metal vapor organic vapor deposition
  • MBE molecular beam deposition
  • the lower transition layer 41 is an I-type InGaAsP transition layer with a thickness of 0.017 ⁇ m to 0.019 ⁇ m, and a preferred thickness value is 0.018 ⁇ m.
  • the absorption layer 42 is an I-type InGaAs absorption layer with a thickness of 0.8.
  • the upper transition layer 43 is an I-type InGaAsP transition layer with a thickness of 0.017 ⁇ m to 0.019 ⁇ m, and a preferred thickness value is 0.018 ⁇ m
  • the second semiconductor contact layer 44 is a P-type InP contact layer with a thickness of 0.3 ⁇ m to 0.5 ⁇ m, the I-type doping concentration is lower than 5e15cm -3 , and the P-type doping concentration is higher than 3e18cm -3 .
  • Step 104 removing the dielectric layer 3 remaining on the first semiconductor contact layer 2 and forming a contact metal layer on the substrate 1.
  • the dielectric layer 3 is only used in an intermediate manufacturing process to form a growth region of the epitaxial layer 4 defined by the openings 31, thereby assisting in manufacturing a mesa-type epitaxial layer 4.
  • the remaining dielectric layer 3 needs to be removed, and then another layered structure is made.
  • the remaining dielectric layer 3 is the dielectric layer 3 that has not been removed in step 102.
  • step 104 The specific manufacturing process of step 104 is specifically described below with reference to FIG. 2.
  • Step 1041 using an etching solution to remove the dielectric layer 3 remaining on the first semiconductor contact layer 2.
  • the dielectric layer 3 remaining on the first semiconductor contact layer 2 is removed using an etching solution.
  • the dielectric layer 3 is a silicon dioxide dielectric layer
  • the dielectric layer 3 can be removed by using a buffered hydrofluoric acid solution (BOE).
  • BOE buffered hydrofluoric acid solution
  • Step 1042 removing part of the first semiconductor contact layer 2 located on the edge of the substrate 1 by photolithography and wet etching processes.
  • the etched area pattern is first defined by photolithography, and then the first semiconductor contact layer 2 corresponding to the etched area pattern is removed by a wet etching process according to the etched area pattern to form a first semiconductor contact layer table.
  • the first semiconductor contact layer 2 is an N-type InP contact layer.
  • an etching solution of hydrobromic acid: saturated bromine water: water (1: 1: 1) can be used to etch the N-type InP contact layer.
  • the specific structure is shown in Figure 7.
  • Step 1043 A passivation layer 5 is formed on the substrate 1, on the first semiconductor contact layer 2, and on the surface of the epitaxial layer 4.
  • a photosensitive BCB is spin-coated on the substrate 1, the first semiconductor contact layer 2 and the surface of the epitaxial layer 4 to form a passivation layer 5, wherein the passivation layer 5 has a thickness of 2 ⁇ m to 3 ⁇ m.
  • the specific structure is shown in Figure 8.
  • Step 1044 Etching a part of the passivation layer 5 on the first semiconductor contact layer 2 to obtain a first electrode contact region 21, and etching the passivation layer 5 on the second semiconductor contact layer 44 To expose the second semiconductor contact layer 44.
  • a portion of the passivation layer 5 located on the first semiconductor contact layer 2 is etched to obtain a first electrode contact region 21, and a portion of the passivation layer 5 located on the left side of the substrate 1 is removed. A portion of the first semiconductor contact layer 2 is exposed; the passivation layer 5 on the second semiconductor contact layer 44 is etched to expose the second semiconductor contact layer 44.
  • the specific structure is shown in Figure 9.
  • Step 1045 forming a photosensitive layer 6 and a second electrode contact region 441 on the second semiconductor contact layer 44.
  • Step 1046 forming a first contact metal layer 7 on the passivation layer 5 on the left side of the substrate 1 and on the first electrode contact region 21, and on the passivation layer 5 on the right side of the substrate 1
  • a second contact metal layer 8 is formed on and on the second electrode contact region 441.
  • a first contact metal layer 7 is formed on the passivation layer 5 on the left side of the substrate 1 and on the first electrode contact region 21 by using an electron beam evaporation and lift-off process.
  • a second contact metal layer 8 is formed on the passivation layer 5 on the right side of the bottom 1 and on the second electrode contact region 441. The specific structure is shown in Figure 11.
  • a first electrode pad 71 is formed on the passivation layer 5 on the left side of the substrate 1 by using an electron beam evaporation and stripping process, and an electron beam evaporation and stripping process is used on the passivation layer 5.
  • a second electrode pad 81 is formed on the passivation layer 5 on the right side of the substrate 1; wherein the first electrode pad 71 is connected to the first contact metal layer 7 so that the first electrode pad 71 It is connected to the first semiconductor contact layer 2; the second electrode pad 81 is connected to the second contact metal layer 8, so that the second electrode pad 81 is connected to the second semiconductor contact layer 44.
  • the epitaxial layer 4 is thinned to a predetermined size by a thinning and polishing process, and the epitaxial layer 4 is cleaved to obtain a photodetector chip.
  • the preset size depends on the actual situation, for example, it can be 140 ⁇ m to 150 ⁇ m.
  • the manufacturing method of the photodetector of the present invention first defines the growth region of the epitaxial layer, and then uses a deposition method to form a mesa-shaped epitaxial layer based on the growth region of the epitaxial layer to form a mesa-type PN junction.
  • the photodetector of the invention can effectively solve the problems of physical defects and reactive ion pollution caused by dry etching and the problem of poor consistency caused by chemical wet etching process.
  • the manufacturing method of the photodetector is not only simple in manufacturing process and suitable for mass production, but also has good consistency, high reliability, and can effectively improve the performance of the photodetector.
  • This embodiment provides a photodetector.
  • the photodetector can be made by the method for manufacturing the photodetector in the first embodiment.
  • the photodetector of this embodiment includes a substrate 1, and a first semiconductor contact layer 2 and an epitaxial layer 4 stacked on the substrate 1.
  • the epitaxial layer 4 includes a lower transition layer 41, an absorption layer, The layer 42, the upper transition layer 43 and the second semiconductor contact layer 44.
  • the cross-sections of the lower transition layer 41, the absorption layer 42, the upper transition layer 43 and the second semiconductor contact layer 44 are mesa-shaped, that is, the cross-section of the epitaxial layer 4 is mesa-shaped.
  • the periphery of the epitaxial layer 4 is covered with a passivation layer 5, and the epitaxial layer 4 and the passivation layer 5 covering the periphery form a channel, wherein the channel located on the right side of the substrate 1 is covered with a thinner passivation layer 5.
  • a second contact metal layer 8 and a second electrode pad 81 are provided on the passivation layer 5; a first electrode contact region 21 is provided at the bottom of the channel on the left side of the substrate 1, and A first contact metal layer 7 is disposed on the passivation layer 5 and the first electrode contact region 21, and a first electrode pad 71 is further disposed on the passivation layer 5 on the left side of the substrate 1.
  • the first semiconductor contact layer 2 is an N-type InP contact layer with a thickness of 0.3 ⁇ m to 0.5 ⁇ m;
  • the lower transition layer 41 is an I-type InGaAsP transition layer with a thickness of 0.017 ⁇ m to 0.019 ⁇ m, which is better.
  • the thickness is 0.018 ⁇ m.
  • the absorption layer 42 is an I-type InGaAs absorption layer with a thickness of 0.8 ⁇ m to 1.0 ⁇ m.
  • the upper transition layer 43 is an I-type InGaAsP transition layer with a thickness of 0.017 ⁇ m to 0.019 ⁇ m.
  • the second semiconductor contact layer 44 is a P-type InP contact layer having a thickness of 0.3 ⁇ m to 0.5 ⁇ m, an I-type doping concentration of less than 5e15 cm -3 , and a P-type doping concentration of more than 3e18 cm -3 .

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Abstract

一种光电探测器及其制作方法，该光电探测器的制作方法包括：在衬底上依次生长第一半导体接触层和介质层（101）；去除部分介质层，形成沿靠近第一半导体接触层方向延展的开孔，以限定外延层的生长区域，其中，开孔贯穿介质层（102）；根据外延层的生长区域，采用沉积的方式在第一半导体接触层上选择性生长台型形状的外延层（103）；去除第一半导体接触层上剩余的介质层，并在衬底上形成接触金属层（104）。该光电探测器可以解决干法刻蚀造成物理缺陷和反应离子污染的问题以及化学湿法腐蚀工艺造成的一致性差的问题。该光电探测器的制作方法制作工艺简单，由该制作方法制作的光电探测器具有台型结构，且一致性好，可靠性高。

Description

一种光电探测器及其制作方法 【技术领域】
本发明涉及芯片制造技术领域，特别是涉及一种光电探测器及其制作方法。
【背景技术】
目前，光电探测器作为光接收芯片，被广泛应用于光通信系统中。大规模应用的4G移动通信中光网络的光电探测器速率需要达到10Gbit/s，未来5G移动通信中的光网络需要达到25Gbit/s以上。传统平面光电探测器受困于结电容太大一般只能满足10Gbit/s以下，而波导探测器受限于封装和成本因素难以大规模应用，因此，为达到较高的传输速率，高速光电探测器以垂直光入射台面结构为主。
台面光电探测器工艺的难点在于台型PN结制作，常用的有反应离子或者感应耦合等离子干法刻蚀工艺和选择性化学湿法腐蚀工艺。干法刻蚀工艺容易造成物理缺陷和反应离子污染，影响光电探测器的暗电流和可靠性；而化学湿法腐蚀工艺需要选择合适的腐蚀液，工艺一致性难以控制，影响成品率。
鉴于此，克服该现有技术所存在的缺陷是本技术领域亟待解决的问题。
【发明内容】
本发明实施例要解决的技术问题是：目前，一般采用干法刻蚀工艺和化学湿法腐蚀工艺形成台面光电探测器，以保证光电探测器具有较高的传输速率。但是由这两种工艺形成的光电探测器，均对应存在相应的问题，影响光电探测器的性能。采用干法刻蚀工艺形成台面光电探测器时，容易造成物理缺陷和反应离子污染，影响光电探测器的暗电流和可靠性；采用化学湿法腐蚀工艺形成台面光电探测器时，工艺一致性难以控制，影响成品率。
本发明实施例采用如下技术方案：
第一方面，提供一种光电探测器的制作方法，所述光电探测器的制作方法包括：
在衬底1上依次生长第一半导体接触层2和介质层3；
去除部分所述介质层3，形成沿靠近所述第一半导体接触层2方向延展的开孔31，以限定外延层4的生长区域，其中，所述开孔31贯穿所述介质层3；
根据所述外延层4的生长区域，采用沉积的方式在所述第一半导体接触层2上选择性生长台型形状的外延层4；
去除所述第一半导体接触层2上剩余的所述介质层3，并在所述衬底1上形成接触金属层。
优选地，所述根据所述外延层4的生长区域，采用沉积的方式在所述第一半导体接触层2上选择性生长台型形状的外延层4包括：
根据所述外延层4的生长区域，采用金属气相有机气相沉积或分子束沉积的方式在所述第一半导体接触层2上依次选择性生长台型形状的下过渡层41、吸收层42、上过渡层43以及第二半导体接触层44，从而形成台型形状的外延层4。
优选地，所述外延层4包括层叠设置的下过渡层41、吸收层42、上过渡层43以及第二半导体接触层44；
所述去除所述第一半导体接触层2上剩余的所述介质层3，并在所述衬底1上形成接触金属层包括：
采用腐蚀液去除所述第一半导体接触层2上剩余的所述介质层3；
通过光刻和湿法腐蚀工艺去除位于所述衬底1边缘的部分所述第一半导体接触层2；
在所述衬底1上、所述第一半导体接触层2上以及所述外延层4表面形成钝化层5；
刻蚀位于所述第一半导体接触层2上的部分所述钝化层5得到第一电极接触区域21，刻蚀位于所述第二半导体接触层44上的所述钝化层5，以裸露所述第二半导体接触层44；
在所述第二半导体接触层44上，形成光敏层6以及第二电极接触区域441；
在位于衬底1左侧的所述钝化层5上以及所述第一电极接触区域21上形成第一接触金属层7，在位于衬底1右侧的所述钝化层5上以及所述第二电极接触区域441上形成第二接触金属层8。
优选地，所述光电探测器的制作方法还包括：
采用电子束蒸发和剥离工艺，在位于所述衬底1左侧的所述钝化层5上形成第一电极焊盘71，在位于所述衬底1右侧的所述钝化层5上形成第二电极焊盘81；
其中，所述第一电极焊盘71与所述第一接触金属层7连接，所述第二电极焊盘81与所述第二接触金属层8连接。
优选地，所述光电探测器的制作方法还包括：
采用减薄抛光工艺将所述外延层4减薄到预设的尺寸；
对所述外延层4进行解理得到光电探测器芯片。
优选地，所述第一半导体接触层2为N型InP接触层，所述第二半导体接触层44为P型InP接触层，所述下过渡层41为InGaAsP过渡层，所述吸收层42为I型InGaAs吸收层，所述上过渡层43为I型InGaAsP过渡层。
优选地，所述去除部分所述介质层3，形成沿靠近所述第一半导体接触层2方向延展的开孔31，以限定外延层4的生长区域包括：
采用光刻工艺定义开孔图案；
采用腐蚀或刻蚀工艺，去除所述开孔图案对应的介质层3，从而形成沿靠近所述第一半导体接触层2方向延展的开孔31，以限定外延层4的生长区域。
优选地，在衬底1上依次生长第一半导体接触层2和介质层3包括：
在衬底1上，通过金属气相有机气相沉积或者分子束沉积的方式生长第一半导体接触层2；
在所述第一半导体接触层2上，通过等离子增强化学气相沉积的方式生长介质层3。
优选地，所述介质层3的组成成分包括二氧化硅或氮化硅。
第二方面，提供一种光电探测器，所述光电探测器由如第一方面所述的光电探测器的制作方法制作而成。
与现有技术相比，本发明实施例的有益效果在于：本发明的光电探测器的制作方法首先限定外延层的生长区域，然后采用沉积的方法基于外延层的生长区域形成台型形状的外延层，从而形成台型PN结。本发明的光电探测器可以有效解决干法刻蚀造成物理缺陷和反应离子污染的问题以及化学湿法腐蚀工艺造成的一致性差的问题。同时，该光电探测器的制作方法不仅制作工艺简单，适用于批量生产，且由该制作方法制作的台型光电探测器的一致性好，可靠性高，可以有效提高光电探测器的性能。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本发明实施例提供的一种光电探测器的制作方法的流程示意图；
图2是步骤104的具体流程示意图；
图3是步骤101之后形成的光电探测器的结构示意图；
图4是步骤102之后形成的光电探测器的结构示意图；
图5是步骤103之后形成的光电探测器的结构示意图；
图6是步骤1041之后形成的光电探测器的结构示意图；
图7是步骤1042之后形成的光电探测器的结构示意图；
图8是步骤1043之后形成的光电探测器的结构示意图；
图9是步骤1044之后形成的光电探测器的结构示意图；
图10是步骤1045之后形成的光电探测器的结构示意图；
图11是步骤1046之后形成的光电探测器的结构示意图；
图12是本发明实施例提供的一种光电探测器的俯视示意图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本发明的描述中，术语“内”、“外”、“纵向”、“横向”、“上”、“下”、“顶”、“底”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明而不是要求本发明必须以特定的方位构造和操作，因此不应当理解为对本发明的限制。
此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
在实际应用场景中，为了提高光电探测器的传输速率，光电探测器以垂直光入射台面结构为主，目前，一般采用反应离子或者感应耦合等离子干法刻蚀工艺和选择性化学湿法腐蚀工艺形成台型PN结。但是干法刻蚀容易造成物理缺陷和反应离子污染，影响光电探测器的暗电流和可靠性；而化学湿法腐蚀工艺需要选择合适的腐蚀液，工艺一致性难以控制，影响成品率。
为了解决上述问题，本发明提出一种光电探测器的制作方法，该光电探测器的制作方法首先限定外延层的生长区域，然后采用沉积的方法基于外延层的生长区域形成台型形状的外延层，从而形成台型PN结。可以有效解决干法刻蚀造成物理缺陷和反应离子污染的问题以及化学湿法腐蚀工艺造成的一致性差的问题。下面结合图1～图12，本发明的光电探测器的制作方法具体包括如下步骤：
步骤101：在衬底1上依次生长第一半导体接触层2和介质层3。
在本实施例中，提供一衬底1，其中，衬底1可以为InP掺Fe半绝缘衬底。在衬底1上通过金属气相有机气相沉积MOCVD(Metal-organic Chemical Vapor Deposition，简写为MOCVD)或者分子束沉积MBE(Molecular Beam Epitaxy，简写为MBE)的方式生长第一半导体接触层2。第一半导体接触层2为N型InP接触层，其中，第一半导体接触层2的厚度为0.3μm～0.5μm，N型掺杂浓度大于 3e18cm -3。
然后，通过等离子增强化学气相沉积PECVD(Plasma Enhanced Chemical Vapor Deposition，简写为PECVD)的方式在第一半导体接触层2上生长介质层3。在优选的实施例中，介质层3的组成成分包括二氧化硅，介质层3的厚度为2μm～2.5μm。在其他实施例中，介质层3的组成成分包括氮化硅。由于二氧化硅更容易被沉积，可以制作更厚的介质层3，在实际制作过程中，大多采用二氧化硅形成介质层3。
步骤102：去除部分所述介质层3，形成沿靠近所述第一半导体接触层2方向延展的开孔31，以限定外延层4的生长区域，其中，所述开孔31贯穿所述介质层3。
在形成介质层3后，去除部分所述介质层3，形成沿靠近所述第一半导体接触层2方向延展的开孔31，以限定外延层4的生长区域，其中，所述开孔31贯穿所述生长介质层3，所述介质层3的厚度不小于外延层4的厚度。
在实际应用场景中，通过光刻和腐蚀工艺形成预设尺寸的开孔31。具体而言，首先采用光刻定义开孔图案，然后采用腐蚀或刻蚀工艺去除开孔图案对应的介质层3，其中，腐蚀或刻蚀的深度等于介质层3厚度，从而形成沿靠近所述第一半导体接触层2方向延展的开孔31。其中，开孔图案对应的形状可以为方形或圆形等，开孔图案的尺寸也可依据实际情况而定。
在本实施例中，介质层3厚度要大于外延层4厚度，由于孔径的大小直接影响到光电探测器的质量以及性能，孔径太小外延层4质量无法得到保证，孔径太大光电二极管电容超过100fF，3dB带宽无法满足25G应用，因此，需要合理设计孔径的大小，在优选的实施例中，孔径为12μm～18μm。
在本实施例中，在介质层3上形成的开孔31限定了后续外延层4的生长区域，在后续生长外延层4的工艺中，由于开孔31的中间区域在水平方向上接触面积较大，因此在沉积外延层4时，沉积速度较快；而在靠近开孔31的边缘区域(位于衬底1左右两侧未被去除的介质层3相对的侧面形成的区域)的垂直面上接触面积较小，在沉积外延层4时，沉积速度较慢。因此，在沉积外延层4 时，会形成如图5所示的台型结构的外延层4。另一方面，由于介质层3的材料属性与外延层4的材料属性存在较大差异，晶格不匹配，因此，在沉积外延层4时，沿着靠近介质层3的方向上，沉积的速度越来越慢，进一步促成在沉积外延层4时，会形成如图5所示的台型结构的外延层4。由前述分析可知，接触面积以及晶格等因素使得由沉积工艺形成的外延层4具有如图5所示的台型结构。
步骤103：根据所述外延层4的生长区域，采用沉积的方式在所述第一半导体接触层2上选择性生长台型形状的外延层4。
在本实施例中，根据所述外延层4的生长区域，采用沉积的方式在所述第一半导体接触层2选择性生长台型形状的外延层4。
具体而言，根据所述外延层4的生长区域，采用金属气相有机气相沉积MOCVD或分子束沉积MBE的方式在所述第一半导体接触层2上依次选择性生长台型形状的下过渡层41、吸收层42、上过渡层43以及第二半导体接触层44，从而形成台型形状的外延层4。
在一实际应用场景中，下过渡层41为I型InGaAsP过渡层，厚度为0.017μm～0.019μm，较优的厚度取值为0.018μm；吸收层42为I型InGaAs吸收层，其厚度为0.8μm～1.0μm；上过渡层43为I型InGaAsP过渡层，厚度为0.017μm～0.019μm，较优的厚度取值为0.018μm；第二半导体接触层44为P型InP接触层，其厚度为0.3μm～0.5μm，I型掺杂浓度低于5e15cm -3，P型掺杂浓度大于3e18cm -3。
步骤104：去除所述第一半导体接触层2上剩余的所述介质层3，并在所述衬底1上形成接触金属层。
在本实施例中，介质层3只用于中间制作工艺，以形成由开孔31限定的外延层4的生长区域，从而辅助制作台型的外延层4。在基于外延层4的生长区域形成台型的外延层4后，需要将剩余的介质层3去除，然后再制作其他层状结构。其中，剩余的介质层3为步骤102中未被去除的介质层3。
下面参阅图2具体说明步骤104的具体制作流程。
步骤1041：采用腐蚀液去除所述第一半导体接触层2上剩余的所述介质层 3。
首先，采用腐蚀液去除所述第一半导体接触层2上剩余的所述介质层3，例如，介质层3为二氧化硅介质层时，可以利用缓冲氢氟酸溶液(BOE)去除介质层3。具体结构如图6所示。
步骤1042：通过光刻和湿法腐蚀工艺，去除位于所述衬底1边缘的部分所述第一半导体接触层2。
然后，通过光刻和湿法腐蚀工艺去除位于所述衬底1边缘的部分所述第一半导体接触层2。例如，先通过光刻定义腐蚀区域图形，然后依据腐蚀区域图形通过湿法腐蚀工艺去除腐蚀区域图形对应的第一半导体接触层2以形成第一半导体接触层台。其中，第一半导体接触层2为N型InP接触层，湿法腐蚀工艺中可以采用氢溴酸：饱和溴水：水(1:1:1)的腐蚀液腐蚀N型InP接触层。具体结构如图7所示。
步骤1043：在所述衬底1上、所述第一半导体接触层2上以及所述外延层4表面形成钝化层5。
进一步地，在所述衬底1上、所述第一半导体接触层2上以及所述外延层4表面旋涂光敏BCB以形成钝化层5，其中，钝化层5厚度为2μm～3μm。具体结构如图8所示。
步骤1044：刻蚀位于所述第一半导体接触层2上的部分所述钝化层5得到第一电极接触区域21，刻蚀位于所述第二半导体接触层44上的所述钝化层5，以裸露所述第二半导体接触层44。
在本实施例中，刻蚀位于所述第一半导体接触层2上的部分所述钝化层5得到第一电极接触区域21，位于衬底1左侧上的部分钝化层5被去除，并裸露出部分第一半导体接触层2；刻蚀位于所述第二半导体接触层44上的所述钝化层5以裸露出第二半导体接触层44。具体结构如图9所示。
步骤1045：在所述第二半导体接触层44上，形成光敏层6以及第二电极接触区域441。
然后，在300℃氮气气氛下进行钝化30分钟，再通过等离子增强化学气相 沉积(PECVD)的方式生长1500诶氮化硅，利用光刻和刻蚀工艺在第二半导体接触层44上形成氮化硅光敏层6和第二电极接触区域441。具体结构如图10所示。
步骤1046：在位于衬底1左侧的所述钝化层5上以及所述第一电极接触区域21上形成第一接触金属层7，在位于衬底1右侧的所述钝化层5上以及所述第二电极接触区域441上形成第二接触金属层8。
在本实施例中，采用电子束蒸发和剥离工艺，在位于衬底1左侧的所述钝化层5上以及所述第一电极接触区域21上形成第一接触金属层7，在位于衬底1右侧的所述钝化层5上以及所述第二电极接触区域441上形成第二接触金属层8。具体结构如图11所示。
进一步地，参阅图12，采用电子束蒸发和剥离工艺在位于所述衬底1左侧的所述钝化层5上形成第一电极焊盘71，采用电子束蒸发和剥离工艺在位于所述衬底1右侧的所述钝化层5上形成第二电极焊盘81；其中，所述第一电极焊盘71与所述第一接触金属层7连接，从而使得第一电极焊盘71与第一半导体接触层2连接；所述第二电极焊盘81与所述第二接触金属层8连接，从而使得第二电极焊盘81与第二半导体接触层44连接。
然后，采用减薄抛光工艺将所述外延层4减薄到预设的尺寸，对所述外延层4进行解理得到光电探测器芯片。其中，预设的尺寸依据实际情况而定，例如，可以为140μm～150μm。
区别于现有技术，本发明光电探测器的制作方法首先限定外延层的生长区域，然后采用沉积的方法基于外延层的生长区域形成台型形状的外延层，从而形成台型PN结。本发明的光电探测器可以有效解决干法刻蚀造成物理缺陷和反应离子污染的问题以及化学湿法腐蚀工艺造成的一致性差的问题。同时，该光电探测器的制作方法不仅制作工艺简单，适用于批量生产，且由该制作方法制作的光电探测器的一致性好，可靠性高，可以有效提高光电探测器的性能。
实施例2：
本实施例提供一种光电探测器，该光电探测器可以由实施例1中的光电探 测器的制作方法制成。
结合图3～图12，本实施例的光电探测器包括衬底1，层叠设置在衬底1上的第一半导体接触层2以及外延层4，其中，外延层4包括下过渡层41、吸收层42、上过渡层43以及第二半导体接触层44。其中，所述下过渡层41、所述吸收层42、所述上过渡层43以及所述第二半导体接触层44的截面均呈台型形状，即外延层4的截面呈台型形状。在外延层4的周围覆盖有钝化层5，外延层4和覆盖在其周围的钝化层5形成沟道，其中，位于衬底1右侧的沟道覆盖有稍薄的钝化层5，该钝化层5上设置有第二接触金属层8以及第二电极焊盘81；位于衬底1左侧的沟道底部的设置有第一电极接触区域21，位于衬底1左侧的钝化层5以及第一电极接触区域21上设置有第一接触金属层7，在位于衬底1左侧的钝化层5上还设置有第一电极焊盘71。
在一具体应用场景中，第一半导体接触层2为N型InP接触层，厚度为0.3μm～0.5μm；下过渡层41为I型InGaAsP过渡层，厚度为0.017μm～0.019μm，较优的厚度取值为0.018μm；吸收层42为I型InGaAs吸收层，其厚度为0.8μm～1.0μm；上过渡层43为I型InGaAsP过渡层，厚度为0.017μm～0.019μm，较优的厚度取值为0.018μm；第二半导体接触层44为P型InP接触层，其厚度为0.3μm～0.5μm，I型掺杂浓度低于5e15cm -3，P型掺杂浓度大于3e18cm -3。
关于形成该光电探测器的具体制作过程，请参阅实施例1，在此不再赘述。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种光电探测器的制作方法，其特征在于，所述光电探测器的制作方法包括：
    在衬底(1)上依次生长第一半导体接触层(2)和介质层(3)；
    去除部分所述介质层(3)，形成沿靠近所述第一半导体接触层(2)方向延展的开孔(31)，以限定外延层(4)的生长区域，其中，所述开孔(31)贯穿所述介质层(3)；
    根据所述外延层(4)的生长区域，采用沉积的方式在所述第一半导体接触层(2)上选择性生长台型形状的外延层(4)；
    去除所述第一半导体接触层(2)上剩余的所述介质层(3)，并在所述衬底(1)上形成接触金属层。
  2. 根据权利要求1所述的光电探测器的制作方法，其特征在于，所述根据所述外延层(4)的生长区域，采用沉积的方式在所述第一半导体接触层(2)上选择性生长台型形状的外延层(4)包括：
    根据所述外延层(4)的生长区域，采用金属气相有机气相沉积或分子束沉积的方式，在所述第一半导体接触层(2)上依次选择性生长台型形状的下过渡层(41)、吸收层(42)、上过渡层(43)以及第二半导体接触层(44)，从而形成台型形状的外延层(4)。
  3. 根据权利要求1所述的光电探测器的制作方法，其特征在于，所述外延层(4)包括层叠设置的下过渡层(41)、吸收层(42)、上过渡层(43)以及第二半导体接触层(44)；
    所述去除所述第一半导体接触层(2)上剩余的所述介质层(3)，并在所述衬底(1)上形成接触金属层包括：
    采用腐蚀液去除所述第一半导体接触层(2)上剩余的所述介质层(3)；
    通过光刻和湿法腐蚀工艺去除位于所述衬底(1)边缘的部分所述第一半导 体接触层(2)；
    在所述衬底(1)上、所述第一半导体接触层(2)上以及所述外延层(4)表面形成钝化层(5)；
    刻蚀位于所述第一半导体接触层(2)上的部分所述钝化层(5)，得到第一电极接触区域(21)，刻蚀位于所述第二半导体接触层(44)上的所述钝化层(5)，以裸露所述第二半导体接触层(44)；
    在所述第二半导体接触层(44)上，形成光敏层(6)以及第二电极接触区域(441)；
    在位于衬底(1)左侧的所述钝化层(5)上以及所述第一电极接触区域(21)上形成第一接触金属层(7)，在位于衬底(1)右侧的所述钝化层(5)上以及所述第二电极接触区域(441)上形成第二接触金属层(8)。
  4. 根据权利要求3所述的光电探测器的制作方法，其特征在于，所述光电探测器的制作方法还包括：
    采用电子束蒸发和剥离工艺，在位于所述衬底(1)左侧的所述钝化层(5)上形成第一电极焊盘(71)，在位于所述衬底(1)右侧的所述钝化层(5)上形成第二电极焊盘(81)；
    其中，所述第一电极焊盘(71)与所述第一接触金属层(7)连接，所述第二电极焊盘(81)与所述第二接触金属层(8)连接。
  5. 根据权利要求4所述的光电探测器的制作方法，其特征在于，所述光电探测器的制作方法还包括：
    采用减薄抛光工艺将所述外延层(4)减薄到预设的尺寸；
    对所述外延层(4)进行解理得到光电探测器芯片。
  6. 根据权利要求2～5任一项所述的光电探测器的制作方法，其特征在于，所述第一半导体接触层(2)为N型InP接触层，所述第二半导体接触层(44) 为P型InP接触层，所述下过渡层(41)为InGaAsP过渡层，所述吸收层(42)为I型InGaAs吸收层，所述上过渡层(43)为I型InGaAsP过渡层。
  7. 根据权利要求1所述的光电探测器的制作方法，其特征在于，所述去除部分所述介质层(3)，形成沿靠近所述第一半导体接触层(2)方向延展的开孔(31)，以限定外延层(4)的生长区域包括：
    采用光刻工艺定义开孔图案；
    采用腐蚀或刻蚀工艺，去除所述开孔图案对应的介质层(3)，从而形成沿靠近所述第一半导体接触层(2)方向延展的开孔(31)，以限定外延层(4)的生长区域。
  8. 根据权利要求1所述的光电探测器的制作方法，其特征在于，所述在衬底(1)上依次生长第一半导体接触层(2)和介质层(3)包括：
    在衬底(1)上，通过金属气相有机气相沉积或者分子束沉积的方式生长第一半导体接触层(2)；
    在所述第一半导体接触层(2)上，通过等离子增强化学气相沉积的方式生长介质层(3)。
  9. 根据权利要求1所述的光电探测器的制作方法，其特征在于，所述介质层(3)的组成成分包括二氧化硅或氮化硅。
  10. 一种光电探测器，其特征在于，所述光电探测器由如权利要求1～9所述的光电探测器的制作方法制作而成。
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