WO2020042244A1 - 液晶显示面板及具有该液晶显示面板的液晶显示装置 - Google Patents

液晶显示面板及具有该液晶显示面板的液晶显示装置 Download PDF

Info

Publication number
WO2020042244A1
WO2020042244A1 PCT/CN2018/106186 CN2018106186W WO2020042244A1 WO 2020042244 A1 WO2020042244 A1 WO 2020042244A1 CN 2018106186 W CN2018106186 W CN 2018106186W WO 2020042244 A1 WO2020042244 A1 WO 2020042244A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
data
video data
circuit
timing controller
Prior art date
Application number
PCT/CN2018/106186
Other languages
English (en)
French (fr)
Inventor
肖光星
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US16/304,018 priority Critical patent/US10937375B2/en
Publication of WO2020042244A1 publication Critical patent/WO2020042244A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3644—Control of matrices with row and column drivers using a passive matrix with the matrix divided into sections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/02—Handling of images in compressed format, e.g. JPEG, MPEG
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication

Definitions

  • the present invention relates to the technical field of liquid crystal display, in particular to a liquid crystal display panel and a liquid crystal display device having the liquid crystal display panel.
  • Liquid crystal displays have the advantages of light weight, thinness, shortness, energy saving, and radiation indicators that are generally lower than those of cathode ray tubes (CRT) displays, which have gradually replaced CRT displays to achieve the realization of various electronic products (such as mobile phones, Tablet, etc.).
  • CTR cathode ray tubes
  • the liquid crystal display panel is usually provided with multiple timing controllers working at the same time, and each timing controller controls a corresponding area correspondingly, that is, each timing controller can only obtain and process Corresponding data (such as video data).
  • Corresponding data such as video data.
  • the image processing algorithms such as color shift compensation algorithm, visual compensation algorithm, etc.
  • the timing controller of the liquid crystal display panel are not ideal for image processing, resulting in the display effect of the liquid crystal display panel. Meet viewing requirements.
  • An embodiment of the present invention provides a liquid crystal display panel and a liquid crystal display device having the liquid crystal display panel.
  • a timing controller provided in a display sub-region can acquire and process edge video data displayed in an edge region of an adjacent display sub-region. This makes each image processing algorithm at the boundary of the display sub-region process the image better.
  • An embodiment of the present invention provides a liquid crystal display panel, which includes a non-display area and a display area, the non-display area is provided around a peripheral side of the display area; the non-display area is provided with a system on a chip, and the display area Including at least two display sub-areas, each of which is provided with a corresponding timing controller, and any two of the timing controllers are electrically connected; the system on chip is electrically connected to each of the timing controllers And sending edge video data displayed in an edge region of an adjacent display sub-region to each of the timing controllers, the timing controller receiving and processing the edge video data; wherein the adjacent display sub-regions are connected with The display sub-areas corresponding to the timing controller are adjacent to each other, and the edge area of the adjacent display sub-area corresponds to the display sub-area corresponding to the timing controller in the adjacent display sub-area. Contiguous area.
  • the display area includes at least a first display sub-area and a second display sub-area.
  • the first display sub-area is provided with a first timing controller
  • the second display sub-area is provided with a second timing controller.
  • the first display sub-region and the second display sub-region are disposed adjacent to each other, and the system on a chip is electrically connected to the first timing controller and the second timing controller.
  • the frame period field video effective area and field blanking area of the liquid crystal display panel is a scanning time between when an electron gun starts scanning a frame image and after scanning the frame image, the field blanking The area is the preparation time between when the electron gun scans one frame of image and when the next frame of image is scanned; the on-chip system sends the edge video to the timing controller through the V-by-one interface in the field blanking area data.
  • the system on chip includes a data reading circuit, a data recombination circuit, and a data sending circuit; the data reading circuit reads edge video data stored in the system on chip; the data reconfiguration circuit and the data reading The circuit is electrically connected, and the edge video data read by the data reading circuit is recombined to obtain recombined edge video data.
  • the recombined edge video data has the V-by-one interface required.
  • Data format; the data sending circuit is electrically connected to the data recombination circuit, and sends the recombined edge video data to the timing controller through the V-by-one interface.
  • the timing controller includes a data receiving circuit, a data decoding circuit, a data importing circuit, and an importing algorithm circuit; the data receiving circuit is configured to receive, through the V-by-one interface, the reorganized data sent by the on-chip system.
  • Edge video data the data decoding circuit is electrically connected to the data receiving circuit, and decodes the reconstructed edge video data received by the data receiving circuit to obtain decoded edge video data, and the decoded
  • the edge video data has a data format required by the timing controller;
  • the data import circuit is electrically connected to the data decoding circuit, and sends the decoded edge video data to the import algorithm circuit;
  • the import The algorithm circuit is electrically connected to the data decoding circuit, receives the decoded edge video data sent by the data import circuit, and processes the decoded edge video data according to a preset image processing algorithm.
  • the preset image processing algorithm includes a color shift compensation algorithm and / or a visual compensation algorithm.
  • the system-on-chip also sends to the timing controllers all video data displayed in the display sub-region corresponding to the timing controller, and the timing controller also receives and processes all the video data.
  • the system-on-chip sends the entire video data to the timing controller through the V-by-one interface in the field video valid area.
  • the field blanking area includes a front shoulder, a field synchronization area, and a back shoulder.
  • the field synchronization area is the duration of the field synchronization signal, and the field synchronization signal controls the electron gun to scan the next frame of image.
  • the front shoulder is the time between when the electron gun scans a frame of image and the start of the field synchronization signal
  • the back shoulder is the time between the end of the field synchronization signal and the electron gun starts scanning the next frame of image. time.
  • an embodiment of the present invention further provides a liquid crystal display device, which includes the liquid crystal display panel described above.
  • the edge data displayed in the edge area of the adjacent display sub-area is sent to the timing controller through the system on a chip, and the timing The controller can acquire and process the edge video data displayed in the edge region of the adjacent display sub-region, so that each image processing algorithm at the boundary of the display sub-region has a better processing effect on the image.
  • FIG. 1 is a schematic circuit structure diagram of a liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 2 is a timing diagram of video transmission performed by the liquid crystal display panel shown in FIG. 1.
  • FIG. 3 is a schematic diagram of a system on a chip shown in FIG. 1.
  • FIG. 4 is a frame schematic diagram of the timing controller shown in FIG. 1.
  • An embodiment of the present invention provides a liquid crystal display panel.
  • a timing controller provided in a display sub-region of the liquid crystal display panel can acquire and process edge video data displayed in an edge region of an adjacent display sub-region, so that the Each image processing algorithm at the junction has a better effect on image processing.
  • a liquid crystal display panel and a liquid crystal display device having the liquid crystal display panel provided by embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4.
  • FIG. 1 is a schematic diagram of a circuit structure of a liquid crystal display panel according to an embodiment of the present invention.
  • the liquid crystal display panel 100 includes a non-display area 10 and a display area 20, wherein the non-display area 10 is located at an edge position of the liquid crystal display panel 100 and surrounds the display area 20
  • the peripheral side is provided, that is, the display area 20 is located inside the non-display area 10.
  • the non-display area 10 is provided with a system on chip (SoC) 30, and the display area 20 is provided with a timing controller (Tcon) 40, and the timing controller 40 and the system on chip 30 Electrical connection.
  • the display area 20 includes at least two display sub-areas, and each display sub-area is provided with a corresponding timing controller 40, and any two of the timing controllers 40 are electrically connected.
  • the system on chip 30 is configured to send video data to each of the timing controllers 40, and the timing controller 40 is configured to receive and process the video data.
  • the video data includes all video data displayed in a display sub-region corresponding to the timing controller 40 and edge video data displayed in an edge region of an adjacent display sub-region.
  • the adjacent display subregion is a display subregion adjacent to the display subregion corresponding to the timing controller 40, and an edge region of the adjacent display subregion is in the adjacent display subregion.
  • the interaction process between the on-chip system 30 and the timing controller 40 is schematically described with the display area 20 including two display sub-areas.
  • the display area 20 includes a first display sub-area 201 and a second display sub-area 202.
  • the first display sub-area 201 is provided with a first timing controller 41 and the second display sub-area.
  • 202 is provided with a second timing controller 42.
  • the first display sub-region 201 and the second display sub-region 202 are disposed adjacent to each other, that is, the first display sub-region 201 and the second display sub-region 202 are adjacent display sub-regions to each other.
  • the system on chip 30 is electrically connected to the first timing controller 41 and the second timing controller 42, and the first timing controller 41 is electrically connected to the second timing controller 42.
  • the system on chip 30 sends first video data and second video data to the first timing controller 41 and the second timing controller 42, respectively.
  • a timing controller 41 is configured to receive and process the first video data
  • a second timing controller 42 is configured to receive and process the second video data.
  • the first video data includes all video data displayed in the first display sub-region 201 and edge video data displayed in an edge region of the second display sub-region 202;
  • the second video data includes All video data displayed in the second display sub-region 202 and edge video data displayed in an edge region of the first display sub-region 201.
  • FIG. 2 is a timing diagram of video transmission performed by the liquid crystal display panel shown in FIG. 1.
  • the video screen is composed of a frame-by-frame image switched display on the liquid crystal display panel 100.
  • the frame period of the liquid crystal display panel 100 includes a vertical video active area and a vertical blanking (VBlank) area.
  • the field video effective area is the scanning time between when the electron gun starts scanning one frame of image and the frame image is scanned, and the field blanking area is between the electron gun scanning one frame of image and the next frame of image. Preparation time.
  • the field blanking area includes a vertical shoulder (VFP), a vertical synchronization (VSync) area, and a vertical back shoulder (VBP).
  • the field synchronization area is the duration of the field synchronization signal, and the field synchronization signal is used to control the electron gun to scan the next frame of image; the front shoulder of the field is that the electron gun has scanned a frame of image to the field synchronization signal.
  • the time between the start; the shoulder behind the field is the time between the end of the field synchronization signal and the start of the electron gun to scan the next frame of image.
  • the system-on-chip 30 sends all the information displayed in the first display sub-region 201 to the timing controller 41 through the V-by-one interface in the field video effective area.
  • Video data The system-on-chip 30 sends all video data displayed in the second display sub-region 202 to the second timing controller 42 through the V-by-one interface in the field video valid area.
  • the system-on-chip 30 sends edge video data displayed in the edge area of the second display sub-region 202 to the timing controller 41 through the V-by-one interface in the field blanking area.
  • the system-on-chip 30 sends edge video data displayed in the edge region of the first display sub-region 201 to the second timing controller 42 through the V-by-one interface in the field blanking area.
  • the V-by-One interface is a digital interface standard developed for image transmission, and the input and output levels of the signals are Low-Voltage Differential Signaling (LVDS).
  • FIG. 3 is a schematic diagram of a frame of the system on a chip shown in FIG. 1.
  • the on-chip system 30 includes a data reading circuit 301, a data recombination circuit 302, and a data transmitting circuit 303.
  • the data reading circuit 301 is configured to read edge video data stored in the on-chip system 30.
  • the edge video data may be stored in a memory of the system on chip 30, and the memory may be a double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), as described in Second-generation double-rate synchronous dynamic random access memory (DDR2SDRAM) or third-generation double-rate synchronous dynamic random-access memory (DDR3SDRAM).
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • DDR2SDRAM Second-generation double-rate synchronous dynamic random access memory
  • DDR3SDRAM third-generation double-rate synchronous dynamic random-access memory
  • the edge video data includes edge video data displayed in an edge region of the first display sub-region 201 and edge video data displayed in an edge region of the second display sub-region 202.
  • the data recombination circuit 302 is electrically connected to the data reading circuit 301, and is configured to recompose the edge video data read by the data reading circuit 301 to obtain the recombined edge video data.
  • the recombined edge video data has a data format required by the V-by-one interface, so that the recombined edge video data can be transmitted through the V-by-one interface.
  • the data recombination circuit 302 performs recombination processing on the edge video data displayed in the edge region of the first display sub-region 201 to obtain a recombined image on the first display sub-region.
  • the edge video data displayed in the edge region of the sub-region 202 is displayed.
  • the data sending circuit 303 is electrically connected to the data recombination circuit 302 and is configured to send the recombined edge video data to the timing controller 40 through the V-by-one interface. Specifically, the data sending circuit 303 sends the reconstructed edge video data displayed in the edge region of any display sub-region to the timing controller 40 corresponding to the adjacent display sub-region through the V-by-one interface. .
  • the data sending circuit 303 sends the reconstructed edge video data displayed in the edge area of the second display sub-region 202 to the first through the V-by-one interface.
  • FIG. 4 is a schematic diagram of a timing controller shown in FIG. 1.
  • the timing controller 40 includes a data receiving circuit 401, a data decoding circuit 402, a data import circuit 403, and an import algorithm circuit 404.
  • the data receiving circuit 401 is configured to receive, through the V-by-one interface, the reconstructed edge video data sent by the system on chip 30.
  • the reconstructed edge video data includes edge video data displayed in an edge region of an adjacent display sub-region.
  • the data decoding circuit 402 is electrically connected to the data receiving circuit 401, and is configured to decode the reconstructed edge video data received by the data receiving circuit 401 to obtain decoded edge video data.
  • the decoded edge video data has a data format required by the timing controller 40.
  • the data import circuit 403 is electrically connected to the data decoding circuit 402, and is configured to send the decoded edge video data to the import algorithm circuit 404.
  • the importing algorithm circuit 404 is electrically connected to the data importing circuit 403, and is configured to receive the decoded edge video data sent by the data importing circuit 403, and to decode the decoded edge video according to a preset image processing algorithm. Data is processed.
  • the preset image processing algorithm may include a color shift compensation algorithm, a visual compensation algorithm, and the like.
  • an embodiment of the present invention further provides a liquid crystal display device, which includes the liquid crystal display panel 100 shown in FIG. 1 described above.
  • the liquid crystal display device may include, but is not limited to, a mobile phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a mobile Internet device (MID), and a personal digital assistant (Personal Digital Assistant) with a liquid crystal display panel 100 PDA), laptops, televisions, electronic paper, digital photo frames, etc.
  • each timing controller can only acquire and process the video data displayed in its corresponding display sub-region, so each image processing algorithm at the boundary of the display sub-region has an unsatisfactory processing effect on the image.
  • the timing controller 40 of the liquid crystal display panel 100 described in the above embodiments of the present invention can not only acquire and process all video data displayed in its corresponding display sub-region, but also acquire and process edge regions of adjacent display sub-regions.
  • the displayed edge video data that is, the video data displayed at the boundary of the display sub-region can be shared among multiple display sub-regions, so that each image processing algorithm at the boundary of the display sub-region has a better processing effect on the image.

Abstract

一种液晶显示面板（100），其包括非显示区域（10）和显示区域（20），非显示区域（10）设置有片上系统（30），显示区域（20）包括至少两个显示子区域，每一显示子区域设置有一个对应的时序控制器（40）；片上系统（30）与各时序控制器（40）电性连接，并向各时序控制器（40）发送在相邻显示子区域的边缘区域显示的边缘视频数据，时序控制器（40）接收并处理边缘视频数据；相邻显示子区域为与时序控制器（40）对应的显示子区域相邻接设置的显示子区域。液晶显示面板（100）中时序控制器（40）可以获取并处理在相邻显示子区域的边缘区域显示的边缘视频数据，使得在显示子区域的交界处各图像处理算法对图像的处理效果较好。一种液晶显示装置，其具有上述液晶显示面板（100）。

Description

液晶显示面板及具有该液晶显示面板的液晶显示装置
本发明要求2018年8月31日递交的发明名称为“液晶显示面板及具有该液晶显示面板的液晶显示装置”的申请号2018110103017的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种液晶显示面板及一种具有该液晶显示面板的液晶显示装置。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有轻薄短小、节能、辐射指标普遍低于阴极射线管(Cathode Ray Tube，CRT)显示器等优点，使之逐渐代替CRT显示器实现在各类电子产品(如手机、平板电脑等)中的广泛应用。
为了更好地保证液晶显示面板的显示效果，液晶显示面板中通常设置有多个时序控制器同时工作，每个时序控制器对应控制一个相应的区域，即每个时序控制器只能获取并处理与其对应区域内的资料(如视频数据)。但是，在上述区域的交界处，液晶显示面板的时序控制器里的图像处理算法(如色偏补偿算法、视觉补偿算法等)对图像的处理效果并不理想，导致液晶显示面板的显示效果不能满足观看要求。
发明内容
本发明实施例提供一种液晶显示面板及具有该液晶显示面板的液晶显示装置，其显示子区域中设置的时序控制器可以获取并处理在相邻显示子区域的边缘区域显示的边缘视频数据，使得在显示子区域的交界处各图像处理算法对图像的处理效果较好。
本发明实施例提供了一种液晶显示面板，其包括非显示区域和显示区域，所述非显示区域围绕所述显示区域的周侧设置；所述非显示区域设置有片上系 统，所述显示区域包括至少两个显示子区域，每一所述显示子区域设置有一个对应的时序控制器，任意两个所述时序控制器电性连接；所述片上系统与各个所述时序控制器电性连接，并向各个所述时序控制器发送在相邻显示子区域的边缘区域显示的边缘视频数据，所述时序控制器接收并处理所述边缘视频数据；其中，所述相邻显示子区域为与所述时序控制器对应的显示子区域相邻接设置的显示子区域，所述相邻显示子区域的边缘区域为所述相邻显示子区域中与所述时序控制器对应的显示子区域相邻接的部分区域。
其中，所述显示区域至少包括第一显示子区域和第二显示子区域，所述第一显示子区域设置有第一时序控制器，所述第二显示子区域设置有第二时序控制器；其中，所述第一显示子区域与所述第二显示子区域相邻接设置，所述片上系统与所述第一时序控制器以及所述第二时序控制器电性连接。
其中，所述液晶显示面板的帧周期场视频有效区和场消隐区，所述场视频有效区为电子枪开始扫描一帧图像到扫描完该帧图像之间的扫描时间，所述场消隐区为电子枪扫描完一帧图像到开始扫描下一帧图像之间的准备时间；所述片上系统在所述场消隐区通过V-by-one接口向所述时序控制器发送所述边缘视频数据。
其中，所述片上系统包括数据读取电路、数据重组电路和数据发送电路；所述数据读取电路读取存储在所述片上系统中的边缘视频数据；所述数据重组电路与所述数据读取电路电性连接，将所述数据读取电路读取的边缘视频数据进行重组处理，得到重组后的边缘视频数据，所述重组后的边缘视频数据具有所述V-by-one接口所需的数据格式；所述数据发送电路与所述数据重组电路电性连接，将所述重组后的边缘视频数据通过所述V-by-one接口发送给所述时序控制器。
其中，所述时序控制器包括数据接收电路、数据解码电路、数据导入电路和导入算法电路；所述数据接收电路用于通过所述V-by-one接口接收所述片上系统发送的重组后的边缘视频数据；所述数据解码电路与所述数据接收电路电性连接，对所述数据接收电路接收的重组后的边缘视频数据进行解码处理，得到解码后的边缘视频数据，所述解码后的边缘视频数据具有所述时序控制器所需的数据格式；所述数据导入电路与所述数据解码电路电性连接，将所述解码 后的边缘视频数据发送给所述导入算法电路；所述导入算法电路与所述数据解码电路电性连接，接收所述数据导入电路发送的解码后的边缘视频数据，并根据预设图像处理算法对所述解码后的边缘视频数据进行处理。
其中，所述预设图像处理算法包括色偏补偿算法和/或视觉补偿算法。
其中，所述片上系统还向各个所述时序控制器发送在所述时序控制器对应的显示子区域显示的全部视频数据，所述时序控制器还接收并处理所述全部视频数据。
其中，所述片上系统在所述场视频有效区通过所述V-by-one接口向所述时序控制器发送所述全部视频数据。
其中，所述场消隐区包括场前肩、场同步区和场后肩；所述场同步区为场同步信号的持续时间，所述场同步信号控制所述电子枪扫描下一帧图像，所述场前肩为所述电子枪扫描完一帧图像到所述场同步信号开始之间的时间，所述场后肩为所述场同步信号结束到所述电子枪开始扫描下一帧图像之间的时间。
相应地，本发明实施例还提供了一种液晶显示装置，其包括上述的液晶显示面板。
综上所述，在本发明实施例提供的液晶显示面板及具有该液晶显示面板的液晶显示装置中，通过片上系统向时序控制器发送在相邻显示子区域的边缘区域显示的边缘数据，时序控制器可以获取并处理在相邻显示子区域的边缘区域显示的边缘视频数据，使得在显示子区域的交界处各图像处理算法对图像的处理效果较好。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种液晶显示面板的电路结构示意图。
图2为图1所示的液晶显示面板进行视频传输的时序图。
图3为图1所示的片上系统的框架示意图。
图4为图1所示的时序控制器的框架示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。显然，所描述的实施方式是本发明的一部分实施方式，而不是全部实施方式。基在本发明中的实施方式，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施方式，都应属在本发明保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语，其不仅是指独立的工序，在与其它工序无法明确区别时，只要能实现所述工序所预期的作用则也包括在本用语中。另外，本说明书中用“～”表示的数值范围是指将“～”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的单元用相同的标号表示。
本发明实施例提供一种液晶显示面板，该液晶显示面板的显示子区域中设置的时序控制器可以获取并处理在相邻显示子区域的边缘区域显示的边缘视频数据，使得在显示子区域的交界处各图像处理算法对图像的处理效果较好。下面将结合图1至图4对本发明实施例提供的一种液晶显示面板及具有该液晶 显示面板的液晶显示装置进行具体描述。
请参见图1，图1为本发明实施例提供的一种液晶显示面板的电路结构示意图。如图1所示，所述液晶显示面板100包括非显示区域10和显示区域20，其中，所述非显示区域10位于所述液晶显示面板100的边缘位置处，且其围绕所述显示区域20的周侧设置，即所述显示区域20位于所述非显示区域10的内侧。所述非显示区域10设置有片上系统(System on a Chip，SoC)30，所述显示区域20设置有时序控制器(Timing Controller，Tcon)40，所述时序控制器40与所述片上系统30电性连接。具体地，所述显示区域20包括至少两个显示子区域，每一显示子区域设置有一个对应的时序控制器40，任意两个所述时序控制器40电性连接。
在本发明的实施例中，所述片上系统30用于向各个所述时序控制器40发送视频资料，所述时序控制器40用于接收并处理所述视频资料。其中，所述视频资料包括在所述时序控制器40对应的显示子区域显示的全部视频数据以及在相邻显示子区域的边缘区域显示的边缘视频数据。其中，所述相邻显示子区域为与所述时序控制器40对应的显示子区域相邻接设置的显示子区域，所述相邻显示子区域的边缘区域为所述相邻显示子区域中与所述时序控制器40对应的显示子区域相邻接的部分区域。
需要说明的是，本发明实施例以所述显示区域20包括两个显示子区域的情况下对所述片上系统30和所述时序控制器40的交互过程进行示意性说明。从图1中可见，所述显示区域20包括第一显示子区域201和第二显示子区域202，所述第一显示子区域201设置有第一时序控制器41，所述第二显示子区域202设置有第二时序控制器42。具体为，所述第一显示子区域201与所述第二显示子区域202相邻接设置，即所述第一显示子区域201与所述第二显示子区域202互为相邻显示子区域，所述片上系统30与所述第一时序控制器41以及所述第二时序控制器42电性连接，所述第一时序控制器41与所述第二时序控制器42电性连接。
基于如图1所示的液晶显示面板100，所述片上系统30分别向所述第一时序控制器41和所述第二时序控制器42发送第一视频资料和第二视频资料，所述第一时序控制器41用于接收并处理所述第一视频资料，所述第二时序控制器42 用于接收并处理所述第二视频资料。
其中，所述第一视频资料包括在所述第一显示子区域201显示的全部视频数据以及在所述第二显示子区域202的边缘区域显示的边缘视频数据；所述第二视频资料包括在所述第二显示子区域202显示的全部视频数据以及在所述第一显示子区域201的边缘区域显示的边缘视频数据。
请参见图2，图2为图1所示的液晶显示面板进行视频传输的时序图。在所述液晶显示面板100的视频画面显示过程中，视频画面是由一帧一帧的图像在所述液晶显示面板100上切换显示构成的。如图2所示，所述液晶显示面板100的帧周期包括场视频有效(Vertical Active Video)区和场消隐(Vertical Blanking，VBlank)区。其中，所述场视频有效区为电子枪开始扫描一帧图像到扫描完该帧图像之间的扫描时间，所述场消隐区为电子枪扫描完一帧图像到开始扫描下一帧图像之间的准备时间。
其中，所述场消隐区包括场前肩(Vertical Front Porch，VFP)、场同步(Vertical Synchronization，VSync)区和场后肩(Vertical Back Porch，VBP)。其中，所述场同步区为场同步信号的持续时间，所述场同步信号用于控制电子枪扫描下一帧图像；所述场前肩为所述电子枪扫描完一帧图像到所述场同步信号开始之间的时间；所述场后肩为所述场同步信号结束到所述电子枪开始扫描下一帧图像之间的时间。
具体地，在本发明的实施例中，所述片上系统30在所述场视频有效区通过V-by-one接口向所述时序控制器41发送在所述第一显示子区域201显示的全部视频数据。所述片上系统30在所述场视频有效区通过V-by-one接口向所述第二时序控制器42发送在所述第二显示子区域202显示的全部视频数据。
此外，所述片上系统30在所述场消隐区通过V-by-one接口向所述时序控制器41发送在所述第二显示子区域202的边缘区域显示的边缘视频数据。所述片上系统30在所述场消隐区通过V-by-one接口向所述第二时序控制器42发送在所述第一显示子区域201的边缘区域显示的边缘视频数据。其中，所述V-by-One接口是用于图像传输开发出的数字接口标准，其信号的输入输出水平采用低电压差动信号(Low-Voltage Differential Signaling，LVDS)。
请参见图3，图3为图1所示的片上系统的框架示意图。如图3所示，所述片 上系统30包括数据读取电路301、数据重组电路302和数据发送电路303。
其中，所述数据读取电路301用于读取存储在所述片上系统30中的边缘视频数据。具体地，所述边缘视频数据可以存储在所述片上系统30的存储器中，所述存储器可以为双倍速率同步动态随机存取存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDR SDRAM)，如第二代双倍速率同步动态随机存取存储器(DDR2SDRAM)或第三代双倍速率同步动态随机存取存储器(DDR3SDRAM)。
在本发明的实施例中，所述边缘视频数据包括在所述第一显示子区域201的边缘区域显示的边缘视频数据以及在所述第二显示子区域202的边缘区域显示的边缘视频数据。
所述数据重组电路302与所述数据读取电路301电性连接，用于将所述数据读取电路301读取的边缘视频数据进行重组处理，得到重组后的边缘视频数据。其中，所述重组后的边缘视频数据具有V-by-one接口所需的数据格式，以使所述重组后的边缘视频数据可以通过所述V-by-one接口传输。
具体地，在本发明的实施例中，所述数据重组电路302将在所述第一显示子区域201的边缘区域显示的边缘视频数据进行重组处理，得到重组后的在所述第一显示子区域201的边缘区域显示的边缘视频数据；所述数据重组电路302还可以将在所述第二显示子区域202的边缘区域显示的边缘视频数据进行重组处理，得到重组后的在所述第二显示子区域202的边缘区域显示的边缘视频数据。
所述数据发送电路303与所述数据重组电路302电性连接，用于将所述重组后的边缘视频数据通过所述V-by-one接口发送给所述时序控制器40。具体地，所述数据发送电路303将重组后的在任一显示子区域的边缘区域显示的边缘视频数据通过所述V-by-one接口发送给与相邻显示子区域对应设置的时序控制器40。
在本发明的实施例中，所述数据发送电路303将重组后的在所述第二显示子区域202的边缘区域显示的边缘视频数据通过所述V-by-one接口发送给所述第一时序控制器41；所述数据发送电路303将重组后的在所述第一显示子区域201的边缘区域显示的边缘视频数据通过所述V-by-one接口发送给所述第二时 序控制器42。
请参见图4，图4为图1所示的时序控制器的框架示意图。如图4所示，所述时序控制器40包括数据接收电路401、数据解码电路402、数据导入电路403和导入算法电路404。
其中，所述数据接收电路401，用于通过所述V-by-one接口接收所述片上系统30发送的重组后的边缘视频数据。所述重组后的边缘视频数据包括在相邻显示子区域的边缘区域显示的边缘视频数据。
所述数据解码电路402与所述数据接收电路401电性连接，用于对所述数据接收电路401接收的重组后的边缘视频数据进行解码处理，得到解码后的边缘视频数据。其中，所述解码后的边缘视频数据具有所述时序控制器40所需的数据格式。
所述数据导入电路403与所述数据解码电路402电性连接，用于将所述解码后的边缘视频数据发送给所述导入算法电路404。
所述导入算法电路404与所述数据导入电路403电性连接，用于接收所述数据导入电路403发送的解码后的边缘视频数据，并根据预设图像处理算法对所述解码后的边缘视频数据进行处理。
其中，所述预设图像处理算法可以包括色偏补偿算法、视觉补偿算法等。
相应地，本发明实施例还提供了一种液晶显示装置，其包括上述图1所示的液晶显示面板100。例如，该液晶显示装置可以包括但不限于具有液晶显示面板100的手机(如Android手机、iOS手机等)、平板电脑、移动互联网设备(Mobile Internet Devices，MID)、个人数字助理(Personal Digital Assistant，PDA)、笔记本电脑、电视机、电子纸、数码相框等等。
在现有技术中，每个时序控制器仅能获取并处理在其对应的显示子区域显示的视频数据，因此在显示子区域的交界处各图像处理算法对图像的处理效果并不理想。而本发明上述实施例中所述液晶显示面板100的时序控制器40不仅可以获取并处理在其对应的显示子区域显示的全部视频数据，还可以获取并处理在相邻显示子区域的边缘区域显示的边缘视频数据，即在显示子区域的交界处显示的视频数据可以在多个显示子区域共享，使得在显示子区域的交界处各图像处理算法对图像的处理效果较好。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含在本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上对本发明实施例所提供的液晶显示面板及具有该液晶显示面板的液晶显示装置进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (18)

  1. 一种液晶显示面板，其中，包括非显示区域和显示区域，所述非显示区域围绕所述显示区域的周侧设置；所述非显示区域设置有片上系统，所述显示区域包括至少两个显示子区域，每一所述显示子区域设置有一个对应的时序控制器；所述片上系统与各个所述时序控制器电性连接，并向各个所述时序控制器发送在相邻显示子区域的边缘区域显示的边缘视频数据，所述时序控制器接收并处理所述边缘视频数据；其中，所述相邻显示子区域为与所述时序控制器对应的显示子区域相邻接设置的显示子区域，所述相邻显示子区域的边缘区域为所述相邻显示子区域中与所述时序控制器对应的显示子区域相邻接的部分区域。
  2. 如权利要求1所述的液晶显示面板，其中，所述显示区域至少包括第一显示子区域和第二显示子区域，所述第一显示子区域设置有第一时序控制器，所述第二显示子区域设置有第二时序控制器；其中，所述第一显示子区域与所述第二显示子区域相邻接设置，所述片上系统与所述第一时序控制器以及所述第二时序控制器电性连接。
  3. 如权利要求1所述的液晶显示面板，其中，所述液晶显示面板的帧周期包括场视频有效区和场消隐区，所述场视频有效区为电子枪开始扫描一帧图像到扫描完该帧图像之间的扫描时间，所述场消隐区为电子枪扫描完一帧图像到开始扫描下一帧图像之间的准备时间；所述片上系统在所述场消隐区通过V-by-one接口向所述时序控制器发送所述边缘视频数据。
  4. 如权利要求3所述的液晶显示面板，其中，所述片上系统包括数据读取电路、数据重组电路和数据发送电路；
    所述数据读取电路读取存储在所述片上系统中的边缘视频数据；
    所述数据重组电路与所述数据读取电路电性连接，将所述数据读取电路读取的边缘视频数据进行重组处理，得到重组后的边缘视频数据，所述重组后的 边缘视频数据具有所述V-by-one接口所需的数据格式；
    所述数据发送电路与所述数据重组电路电性连接，将所述重组后的边缘视频数据通过所述V-by-one接口发送给所述时序控制器。
  5. 如权利要求4所述的液晶显示面板，其中，所述时序控制器包括数据接收电路、数据解码电路、数据导入电路和导入算法电路；
    所述数据接收电路用于通过所述V-by-one接口接收所述片上系统发送的重组后的边缘视频数据；
    所述数据解码电路与所述数据接收电路电性连接，对所述数据接收电路接收的重组后的边缘视频数据进行解码处理，得到解码后的边缘视频数据，所述解码后的边缘视频数据具有所述时序控制器所需的数据格式；
    所述数据导入电路与所述数据解码电路电性连接，将所述解码后的边缘视频数据发送给所述导入算法电路；
    所述导入算法电路与所述数据解码电路电性连接，接收所述数据导入电路发送的解码后的边缘视频数据，并根据预设图像处理算法对所述解码后的边缘视频数据进行处理。
  6. 如权利要求5所述的液晶显示面板，其中，所述预设图像处理算法包括色偏补偿算法和/或视觉补偿算法。
  7. 如权利要求3所述的液晶显示面板，其中，所述片上系统还向各个所述时序控制器发送在所述时序控制器对应的显示子区域显示的全部视频数据，所述时序控制器还接收并处理所述全部视频数据。
  8. 如权利要求7所述的液晶显示面板，其中，所述片上系统在所述场视频有效区通过所述V-by-one接口向所述时序控制器发送所述全部视频数据。
  9. 如权利要求3所述的液晶显示面板，其中，所述场消隐区包括场前肩、场同步区和场后肩；其中，所述场同步区为场同步信号的持续时间，所述场同 步信号控制所述电子枪扫描下一帧图像，所述场前肩为所述电子枪扫描完一帧图像到所述场同步信号开始之间的时间，所述场后肩为所述场同步信号结束到所述电子枪开始扫描下一帧图像之间的时间。
  10. 一种液晶显示装置，其中，包括液晶显示面板，所述液晶显示面板包括非显示区域和显示区域，所述非显示区域围绕所述显示区域的周侧设置；所述非显示区域设置有片上系统，所述显示区域包括至少两个显示子区域，每一所述显示子区域设置有一个对应的时序控制器；所述片上系统与各个所述时序控制器电性连接，并向各个所述时序控制器发送在相邻显示子区域的边缘区域显示的边缘视频数据，所述时序控制器接收并处理所述边缘视频数据；其中，所述相邻显示子区域为与所述时序控制器对应的显示子区域相邻接设置的显示子区域，所述相邻显示子区域的边缘区域为所述相邻显示子区域中与所述时序控制器对应的显示子区域相邻接的部分区域。
  11. 如权利要求10所述的液晶显示装置，其中，所述显示区域至少包括第一显示子区域和第二显示子区域，所述第一显示子区域设置有第一时序控制器，所述第二显示子区域设置有第二时序控制器；其中，所述第一显示子区域与所述第二显示子区域相邻接设置，所述片上系统与所述第一时序控制器以及所述第二时序控制器电性连接。
  12. 如权利要求10所述的液晶显示装置，其中，所述液晶显示面板的帧周期包括场视频有效区和场消隐区，所述场视频有效区为电子枪开始扫描一帧图像到扫描完该帧图像之间的扫描时间，所述场消隐区为电子枪扫描完一帧图像到开始扫描下一帧图像之间的准备时间；所述片上系统在所述场消隐区通过V-by-one接口向所述时序控制器发送所述边缘视频数据。
  13. 如权利要求12所述的液晶显示装置，其中，所述片上系统包括数据读取电路、数据重组电路和数据发送电路；
    所述数据读取电路读取存储在所述片上系统中的边缘视频数据；
    所述数据重组电路与所述数据读取电路电性连接，将所述数据读取电路读取的边缘视频数据进行重组处理，得到重组后的边缘视频数据，所述重组后的边缘视频数据具有所述V-by-one接口所需的数据格式；
    所述数据发送电路与所述数据重组电路电性连接，将所述重组后的边缘视频数据通过所述V-by-one接口发送给所述时序控制器。
  14. 如权利要求13所述的液晶显示装置，其中，所述时序控制器包括数据接收电路、数据解码电路、数据导入电路和导入算法电路；
    所述数据接收电路用于通过所述V-by-one接口接收所述片上系统发送的重组后的边缘视频数据；
    所述数据解码电路与所述数据接收电路电性连接，对所述数据接收电路接收的重组后的边缘视频数据进行解码处理，得到解码后的边缘视频数据，所述解码后的边缘视频数据具有所述时序控制器所需的数据格式；
    所述数据导入电路与所述数据解码电路电性连接，将所述解码后的边缘视频数据发送给所述导入算法电路；
    所述导入算法电路与所述数据解码电路电性连接，接收所述数据导入电路发送的解码后的边缘视频数据，并根据预设图像处理算法对所述解码后的边缘视频数据进行处理。
  15. 如权利要求14所述的液晶显示装置，其中，所述预设图像处理算法包括色偏补偿算法和/或视觉补偿算法。
  16. 如权利要求12所述的液晶显示装置，其中，所述片上系统还向各个所述时序控制器发送在所述时序控制器对应的显示子区域显示的全部视频数据，所述时序控制器还接收并处理所述全部视频数据。
  17. 如权利要求16所述的液晶显示装置，其中，所述片上系统在所述场视频有效区通过所述V-by-one接口向所述时序控制器发送所述全部视频数据。
  18. 如权利要求12所述的液晶显示装置，其中，所述场消隐区包括场前肩、场同步区和场后肩；其中，所述场同步区为场同步信号的持续时间，所述场同步信号控制所述电子枪扫描下一帧图像，所述场前肩为所述电子枪扫描完一帧图像到所述场同步信号开始之间的时间，所述场后肩为所述场同步信号结束到所述电子枪开始扫描下一帧图像之间的时间。
PCT/CN2018/106186 2018-08-31 2018-09-18 液晶显示面板及具有该液晶显示面板的液晶显示装置 WO2020042244A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/304,018 US10937375B2 (en) 2018-08-31 2018-09-18 Liquid crystal display panel and liquid crystal display device having the liquid crystal display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811010301.7A CN109064987A (zh) 2018-08-31 2018-08-31 液晶显示面板及具有该液晶显示面板的液晶显示装置
CN201811010301.7 2018-08-31

Publications (1)

Publication Number Publication Date
WO2020042244A1 true WO2020042244A1 (zh) 2020-03-05

Family

ID=64758893

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/106186 WO2020042244A1 (zh) 2018-08-31 2018-09-18 液晶显示面板及具有该液晶显示面板的液晶显示装置

Country Status (3)

Country Link
US (1) US10937375B2 (zh)
CN (1) CN109064987A (zh)
WO (1) WO2020042244A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7224637B2 (ja) * 2019-03-28 2023-02-20 ザインエレクトロニクス株式会社 送信装置、受信装置、送受信装置および送受信システム
CN110189696A (zh) * 2019-06-24 2019-08-30 昆山国显光电有限公司 一种显示装置及其驱动方法
CN110415661B (zh) * 2019-07-02 2020-12-08 深圳市华星光电技术有限公司 液晶显示装置及其驱动方法
CN110890049B (zh) * 2019-11-21 2023-11-28 Tcl华星光电技术有限公司 显示装置的驱动系统及其驱动方法
CN111179883B (zh) * 2020-01-03 2022-06-03 云谷（固安）科技有限公司 图像显示方法和装置、移动终端、计算机设备、存储介质
CN111554245B (zh) * 2020-05-22 2021-10-08 Tcl华星光电技术有限公司 显示装置的驱动方法和显示装置
CN112530351B (zh) * 2020-12-23 2024-04-09 厦门天马微电子有限公司 显示面板的驱动方法、显示面板和显示装置
CN113571023B (zh) * 2021-08-03 2022-08-05 深圳市视显光电技术有限公司 一种基于fpga的背光多分区亮度统计方法及装置
CN114822433B (zh) * 2022-04-07 2023-06-30 Tcl华星光电技术有限公司 液晶显示器、存储介质、图像显示处理方法及相关装置
EP4343750A1 (en) * 2022-09-26 2024-03-27 LG Electronics Inc. Display device and operating method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160125845A1 (en) * 2014-11-04 2016-05-05 Samsung Display Co., Ltd. Display apparatus and method of operating display apparatus
CN106409249A (zh) * 2015-07-31 2017-02-15 乐金显示有限公司 显示面板及使用该显示面板的多屏显示装置
CN106415697A (zh) * 2014-05-21 2017-02-15 三星电子株式会社 显示装置、包括该显示装置的电子设备以及操作该电子设备的方法
CN107633795A (zh) * 2016-08-19 2018-01-26 京东方科技集团股份有限公司 显示装置和显示面板的驱动方法
CN107665666A (zh) * 2017-10-31 2018-02-06 京东方科技集团股份有限公司 显示模组的伽马电压校正方法及系统

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101330433B1 (ko) * 2006-06-30 2013-11-15 엘지디스플레이 주식회사 시야각 제어 가능한 액정 표시 장치
US8164600B2 (en) * 2007-12-06 2012-04-24 Barco Nv Method and system for combining images generated by separate sources
JP2009216815A (ja) * 2008-03-07 2009-09-24 Sanyo Electric Co Ltd 投写型映像表示装置
CN101667389B (zh) * 2009-10-09 2011-12-07 友达光电股份有限公司 像素数据的补偿方法、时序控制器以及液晶显示器
JP5756594B2 (ja) * 2009-11-20 2015-07-29 セイコーエプソン株式会社 画像処理装置、画像処理方法
JP2014032314A (ja) * 2012-08-03 2014-02-20 Sharp Corp マルチディスプレイ装置
CN103824550B (zh) * 2014-02-24 2016-04-13 华南理工大学 一种基于分时复用技术的液晶屏显示系统及方法
KR102154190B1 (ko) * 2014-05-08 2020-09-09 삼성전자 주식회사 멀티칩으로 구성된 드라이버 집적 회로 및 이의 구동 방법
KR20160065556A (ko) * 2014-12-01 2016-06-09 삼성전자주식회사 디스플레이 구동 집적 회로 및 이를 포함하는 디스플레이 장치
CN105096753A (zh) * 2015-09-01 2015-11-25 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN105487313A (zh) * 2016-01-04 2016-04-13 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及其驱动方法
CN105867867B (zh) * 2016-04-19 2019-04-26 京东方科技集团股份有限公司 显示控制方法、装置及系统
KR102526613B1 (ko) * 2016-07-29 2023-04-28 엘지디스플레이 주식회사 타이밍 제어부, 이를 이용한 표시장치 및 이의 구동방법
KR102421443B1 (ko) * 2017-11-13 2022-07-18 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106415697A (zh) * 2014-05-21 2017-02-15 三星电子株式会社 显示装置、包括该显示装置的电子设备以及操作该电子设备的方法
US20160125845A1 (en) * 2014-11-04 2016-05-05 Samsung Display Co., Ltd. Display apparatus and method of operating display apparatus
CN106409249A (zh) * 2015-07-31 2017-02-15 乐金显示有限公司 显示面板及使用该显示面板的多屏显示装置
CN107633795A (zh) * 2016-08-19 2018-01-26 京东方科技集团股份有限公司 显示装置和显示面板的驱动方法
CN107665666A (zh) * 2017-10-31 2018-02-06 京东方科技集团股份有限公司 显示模组的伽马电压校正方法及系统

Also Published As

Publication number Publication date
US20200365096A1 (en) 2020-11-19
CN109064987A (zh) 2018-12-21
US10937375B2 (en) 2021-03-02

Similar Documents

Publication Publication Date Title
WO2020042244A1 (zh) 液晶显示面板及具有该液晶显示面板的液晶显示装置
US10097803B2 (en) Display processing apparatus, device and method
US20070070258A1 (en) Techniques to switch between video display modes
TW200521941A (en) Display device and driving method thereof
WO2017181937A1 (zh) 显示控制方法、显示控制装置及显示控制系统
KR101493905B1 (ko) 영상처리장치 및 영상처리방법
US20210233459A1 (en) Display controller, display control method, display control system, display apparatus
US20200105180A1 (en) Display device and driving method
CN102724458B (zh) 视频画面全屏显示的字幕处理方法及视频终端
US9666159B2 (en) Display, display system and data processing method
WO2020156007A1 (zh) 驱动方法、驱动电路和显示装置
CN104052978A (zh) 信号处理方法、信号处理系统和显示设备
WO2013152591A1 (zh) 显示装置的驱动方法及显示装置
CN102572463A (zh) 视频信号处理装置、视频信号处理方法和计算机程序
JP2007206356A (ja) 映像表示システム
CN101115129B (zh) 具多通道数据传输界面的平面显示器及其影像传输方法
US9418631B2 (en) Display control apparatus and method and image processing method
EP2741279A2 (en) Array substrate, 3D display device and driving method for the same
JP2013152338A (ja) 画像処理装置、画像表示システム、および画像表示方法
TWI419043B (zh) 同時在雙螢幕及外接螢幕上正確顯示畫面的方法、雙螢幕電子裝置及其顯示晶片
TWI397896B (zh) 使用單一資料致能訊號來控制顯示器時序之方法及相關時序控制電路
JP2007251723A (ja) 投写型映像表示装置
CN107613361A (zh) 一种过扫描图像处理方法及一种存储设备
CN113724663B (zh) 图像处理系统及显示装置
CN113963650B (zh) 驱动装置以及显示设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18931363

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18931363

Country of ref document: EP

Kind code of ref document: A1