WO2020029254A1 - 一种SoC芯片及总线访问控制方法 - Google Patents

一种SoC芯片及总线访问控制方法 Download PDF

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Publication number
WO2020029254A1
WO2020029254A1 PCT/CN2018/099983 CN2018099983W WO2020029254A1 WO 2020029254 A1 WO2020029254 A1 WO 2020029254A1 CN 2018099983 W CN2018099983 W CN 2018099983W WO 2020029254 A1 WO2020029254 A1 WO 2020029254A1
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WIPO (PCT)
Prior art keywords
bus
access control
control information
mpu
otp memory
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PCT/CN2018/099983
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English (en)
French (fr)
Inventor
王东格
韦健
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2018/099983 priority Critical patent/WO2020029254A1/zh
Priority to EP18917575.5A priority patent/EP3637253B1/en
Priority to CN201880001174.6A priority patent/CN111295645B/zh
Priority to US16/686,014 priority patent/US11048648B2/en
Publication of WO2020029254A1 publication Critical patent/WO2020029254A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/16—Memory access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating

Definitions

  • the present application relates to the technical field of SoC chips, and in particular, to a SoC chip and a bus access control method.
  • SoC (System-on-a-Chip) chip as an integrated circuit chip, can effectively reduce the development cost of electronic / information system products, shorten the development cycle, and improve the competitiveness of the product. It is widely used in today's society.
  • the bus system is a channel for the master device and the slave device to transmit information on the chip, and plays an important role.
  • a single bus system is used, that is, all master devices share a bus, and only one master device is allowed to have access rights on the bus at the same time. With the increasing scale and complexity of SoC chips, the traditional single bus system can no longer meet the application requirements.
  • the current bus structure has gradually changed from a single bus to a multi-layer bus structure, that is, multiple master devices can An access request is sent to the slave device on the layer bus.
  • This multi-layer bus structure improves the performance of the system, so that the access request of one bus master device does not block other master devices, and improves the bus efficiency.
  • each master device can only access the address space that it is allowed to access. For example, for external communication interface devices, it only Can access the storage area in the system used to exchange data with the outside, and cannot control and access other resources in the system.
  • the existing bus permission configuration method lacks flexibility, and the access permission information of the master device cannot be modified. Therefore, this configuration method usually can only meet one application scenario and cannot meet the requirements of the SoC chip application environment diversity.
  • the purpose of some embodiments of the present application is to provide a SoC chip and a bus access control method, which can set different bus access control information according to different application scenarios, thereby adapting to different application scenarios and improving the flexibility of configuration methods.
  • An embodiment of the present application provides a SoC chip, including: a bus mechanism including at least one MPU; an OTP memory for storing bus access control information; a mode configuration module connected to the at least one MPU and the OTP memory
  • the mode configuration module is configured to read the bus access control information from the OTP memory when the SoC chip is in a startup mode, and configure the MPU by using the bus access control information, the mode configuration
  • the module is further configured to enable the MPU and switch the SoC chip to a user mode after the MPU is configured.
  • An embodiment of the present application further provides a bus access control method, which is applied to a SoC chip.
  • the SoC chip includes a mode configuration module, an OTP memory, and a bus mechanism; the mode configuration module is respectively connected to the OTP memory and the bus mechanism MPU; the method includes: the mode configuration module reads bus access control information from the OTP memory when the SoC chip is in a boot mode; and the mode configuration module configures the bus access control information using the bus access control information MPU in a bus mechanism; the mode configuration module enables the MPU after the MPU is configured, and switches the SoC chip to a user mode.
  • the embodiments of the present application utilize OTP memory to store bus access control information, so that corresponding bus access control information can be written into OTP memory according to the requirements of different application scenarios, thereby adapting to different application scenarios.
  • the mode configuration module implemented by hardware is used to control the process of reading and configuring the bus access control information, so that the process cannot be controlled and tampered externally, which is beneficial to improving the security of the bus access control information.
  • an encryption module is provided in the OTP memory, and the encryption module is configured to encrypt the bus access control information written in the OTP memory by using a key preset by the hardware;
  • the SoC chip further includes A decryption module, the decryption module is respectively connected to the mode configuration module and the OTP memory;
  • the mode configuration module is further configured to call the decryption module to use the key preset by the hardware to read the bus
  • the access control information is decrypted, and the decrypted bus access control information is written into the MPU. Encryption and decryption using a key preset by the hardware is helpful to prevent the bus access control information from being illegally modified.
  • the mode configuration module is further configured to: after the encryption module encrypts the bus access control information, calculate verification information corresponding to the encrypted bus access control information, and write the verification information Into the OTP memory; the mode configuration module is further configured to read the verification information from the OTP memory, and facilitate the access to the currently read encrypted bus access control by the verification information The information is verified, and when the verification is successful, the decryption module is called to decrypt the read bus access control information.
  • the bus access control information is saved, the check information is saved, which is helpful to prevent an attacker from illegally modifying the bus access control information.
  • the mode configuration module is further configured to control the overall reset of the SoC chip when the verification fails. It helps to avoid potential dangers caused by illegal modification.
  • the bus mechanism includes a multi-layer bus, and each layer of the bus is connected to one MPU, at least one master device, and at least one slave device; one end of the MPU is connected to the master device, and the other end is connected to the slave device. device.
  • a specific structure of a bus mechanism is provided.
  • the master device when the SoC chip is in the user mode, the master device is configured to send an access request through a bus of a layer in which the SoC is located; and the MPU is configured to determine a bus passing the layer in which the SoC is located according to the bus access control information
  • the validity of the sent access request and output the valid access request to the slave device corresponding to the access request.
  • Using the MPU to verify the legitimacy of the access request, and then output the legitimate access request to the corresponding slave device, is beneficial to avoid illegal access and improve the security of the SoC chip.
  • the MPU is further configured to intercept the illegal access request sent through the bus of the layer where the MPU is located, return error information to the master device corresponding to the illegal access request, and save the illegal access request.
  • the intercepted illegal access request is saved, so that the user can view the illegal access request.
  • an address decoding module is connected to the bus of each layer, and one end of the MPU is connected to the master device through the address decoding module; the address decoding module is configured to receive a transmission from the master device.
  • the access request is received, determine the slave device corresponding to the access request according to the address information of the slave device in the access request, and output the access request that the corresponding slave device has determined to Said MPU.
  • a method for determining a slave device corresponding to an access request is provided.
  • each layer of the bus is also connected with a first arbitration module; the address decoding module is connected to the master device through the first arbitration module; and the first arbitration module is used to receive at least the same time
  • control of the bus of the layer where the first arbitration module is located is assigned to one of the master devices, and output is obtained.
  • the bus mechanism further includes a first gating circuit corresponding to the slave device one to one; the other end of each MPU is connected to the slave device through the first gating circuit; the first The gating circuit is configured to, when receiving the access requests sent by at least two of the MPUs at the same time, determine the access request currently to be responded by the slave device according to a second preset policy, and turn on the access request.
  • the slave device corresponds to the master device corresponding to the determined access request.
  • a specific processing method is provided for a scenario in which a slave device simultaneously receives an access request from a master device on a multi-layer bus.
  • the bus mechanism further includes a second gating circuit corresponding to the MPU one by one; each of the MPUs is also connected to the master device through the second gating circuit; the MPU is further configured to receive all The response information sent by the slave device; the second gating circuit is configured to determine the slave device corresponding to the response information according to the response information, and conduct the determined slave device and obtain the current The master device that controls the bus of the layer where the second gating circuit is located.
  • a method for receiving response information from a slave device is provided.
  • the mode configuration module is further configured to switch the SoC chip to a test mode for the designated master device when the SoC chip is in a startup mode and a mode control word of the OTP memory is an initial value.
  • Write the bus access control information into the OTP memory Provide a scenario for writing bus access control information into OTP memory.
  • FIG. 1 is a schematic structural diagram of an SoC chip according to a first embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a bus mechanism according to a first embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a second selective energization according to the first embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an SoC chip according to a second embodiment of the present application.
  • FIG. 5 is a specific flowchart of a bus access control method according to a fourth embodiment of the present application.
  • FIG. 6 is a specific flowchart of a bus access control method according to a fifth embodiment of the present application.
  • FIG. 7 is a specific flowchart of a bus access control method according to a sixth embodiment of the present application.
  • the first embodiment of the present application relates to a SoC chip.
  • the SoC chip includes a mode configuration module 1, an OTP (One Time Programmable) memory 2 and a bus mechanism 3.
  • the OTP memory 2 is used to store bus access control information
  • the bus mechanism 3 includes At least one MPU (Memory Protection Unit) 31 (see FIG. 2), and the mode configuration module 1 is connected to the OTP memory 2 and the at least one MPU 31, respectively.
  • MPU Memory Protection Unit
  • the bus mechanism 3 may include a multi-layer bus, and each layer of the bus may be connected to one MPU31, at least one master device 4, and at least one slave device 5; one end of the MPU31 is connected to the master device 4 through the bus, and the other end is connected to the bus through From device 5.
  • the master device 4 connected to the MPU31 is the master device on the bus of the layer in which it resides, and the slave device 5 connected to the MPU31 includes both the slave devices on the bus of the layer and slave devices on the bus of other layers.
  • the master device 4 may include an MCU, a DMA (Direct Memory Access) module, an external communication interface module, a debugging interface module, an encryption / decryption module, and the like; the slave device 5 may include a RAM (random access memory, random access memory), ROM (Read-Only Memory, Read-Only Memory), Flash (Flash), EEPROM (Electrically Erasable, Programmable, Read-Only Memory, and Erasable Programmable Read-Only Memory) and other function modules (function modules are usually connected to the bus through a register interface ).
  • Figure 2 illustrates the bus mechanism 3 including a three-layer bus as an example.
  • the master device 4 on the first layer bus is an MCU, JTAG (System Test Interface Module); the master device 4 on the second layer bus is a USB, SPIM0 (serial peripheral interface M0), SPIM2 (serial peripheral interface M2); the master device 4 on the third layer bus is AES (Advanced Encryption Standard Module), SHA (Secure Hash Algorithm Module), SPIM1 (string Line peripheral interface M1), DMA (direct memory access module).
  • Slave devices 5 are IRAM (Internal Random Access Memory), DRAM (Dynamic Random Access Memory), BRAM (Block Random Access Memory), APB RegRegs ( Peripheral register space).
  • the OTP memory 2 can be connected to one of the layers of the bus; the mode configuration module 1 can be connected to one of the layers of the bus.
  • the connection of the MPU31 may not be connected to any layer of the bus, but may be connected to the OTP memory 2 and the MPU31 on each layer of the bus through other lines, which is not limited in this embodiment.
  • the OTP memory 2 is used to store bus access control information.
  • the bus access control information may include information of the master device 4 connected to each layer of the bus (such as the number of the master device), and information of the slave device 5 (such as the address information of the slave device, which may include the start address of the slave device, the slave The address range of the device, etc.) and the access right of the master device 4 to the slave device 5.
  • the mode configuration module 1 is configured to read the bus access control information from the OTP memory 2 and configure the MPU 31 using the bus access control information when the SoC chip is in a boot mode (Boot mode).
  • the SoC chip After the SoC chip is reset or powered on, the SoC chip enters the startup mode. At this time, the multi-layer bus in the bus mechanism is controlled by the mode configuration module 1, and the master device 4 on the bus cannot initiate an access request through the bus. In this mode, the mode configuration module 1 reads the mode control word of the OTP memory 2. If the mode control word is the initial value of the OTP memory 2, it indicates that the bus access control information is not written in the OTP memory 2. At this time, the mode The configuration module 1 will switch the SoC chip to a test mode for a designated master device 4 (such as a test interface device) to write bus access control information to the OTP memory 2.
  • a test mode for a designated master device 4 (such as a test interface device) to write bus access control information to the OTP memory 2.
  • the mode control word of the OTP memory 2 is updated to a preset value. After that, the SoC chip is powered on and reset again, and enters the boot mode again. If the mode control word of the OTP memory 2 read by the mode configuration module 1 is a preset value, it indicates that the bus access control information has been written into the OTP memory 2. At this time, the mode configuration module 1 can directly read the bus access control information from the OTP memory 2 and write the bus access control information into the MPU31 to realize the configuration of the MPU31.
  • the mode configuration module 1 is also used to enable the MPU31 and switch the SoC chip to the user mode after the MPU31 is configured. At this time, the mode configuration module 1 transfers control of the bus to the master device 4 for the master device 4 to send an access request through the bus.
  • the master device 4 When the SoC chip is in the user mode, the master device 4 is used to send an access request through the bus of the layer in which it is located, and the MPU 31 is used to judge the legitimacy of the access request sent through the bus of this layer according to the bus access control information.
  • the access request carries information of the corresponding master device 4 (such as the number of the master device), information of the slave device 5 to be accessed (such as the address information of the slave device), and the like.
  • the MPU31 receives the access request sent through the bus of its layer, it can first determine which slave device 5 the current master device 4 wants to access (that is, determine the slave device 5 corresponding to the access request), and then according to the bus access control information, Access to determine if the access is legitimate.
  • the MPU31 will output the access request to the slave device corresponding to the access request. If it is illegal, the MPU 31 will intercept the illegal access request, return an error message to the master device 4 corresponding to the illegal access request, and save the illegal access request for the user to view at any time.
  • an address decoding module 34 is further connected to each layer of the bus, and the MPU 31 is connected to the master device 4 on the bus of the layer where the MPU 31 is located through the address decoding module 34.
  • the address decoding module 34 is configured to, when receiving an access request sent by the master device 4, determine the slave device 5 corresponding to the access request according to the address information of the slave device 5 included in the access request. After the slave device 5 is determined, the address decoding module 34 can output the access request determined by the corresponding slave device to the MPU 31.
  • the MPU 31 receives the access request output by the address decoding module 34, it can directly determine which slave device 5 the current master device 4 wants to access from the access request.
  • a first arbitration module 32 is further connected to each layer of the bus.
  • the address decoding module 34 is connected to the master device 4 on the bus where the MPU 31 is located through the first arbitration module 32.
  • the first arbitration module 32 is configured to assign control of the bus of the layer where the first arbitration module 32 is located to one of the masters when receiving access requests sent by at least two masters 4 at the same time.
  • the device 4 outputs an access request from the master device 4 that has obtained control of the bus of the layer where the first arbitration module 32 is located.
  • the first preset policy may be the priority of the master device, that is, the control right of the bus is allocated according to the priority of each master device that sends the access request.
  • the first preset policy may also be a polling policy, which is not limited in this embodiment.
  • the first arbitration module 32 also buffers an access request of a master device that has not currently obtained control of the bus of its layer. When the bus of its layer is idle (control of the bus is released), the first arbitration module 32 may The control right of the bus is allocated to the master device corresponding to the currently cached access request according to the first preset policy.
  • the bus mechanism 3 further includes a first gating circuit 33 corresponding to the slave device 5 in a one-to-one manner, and the MPU 31 is connected to the slave device 5 through the first gating circuit 33.
  • the MPU 31 receives the access request output by the first arbitration module 32 and determines that the access request is a legitimate access request, it will output the access request to the first gating circuit 33 corresponding to the corresponding slave device 5. If the first gating circuit 33 receives only the access request sent by one MPU 31 at the same time, it will turn on the corresponding slave device 5 and the master device 4 corresponding to the access request to send the received access request to the slave device. 5.
  • the first gating circuit 33 can determine the access request currently to be responded by the slave device according to the second preset policy, and conduct the slave device and the determined access Request the corresponding master device.
  • the second preset policy may be the priority of the master device or a polling policy, which is not limited in this embodiment.
  • the first gating circuit 33 may include an output module, a first data selector (that is, MUX1 in FIG. 2), and a second arbitration module.
  • the output module includes a plurality of first connection terminals and a second connection terminal. Each first connection end can be correspondingly connected to one MPU31, and the second connection end is connected to the first data selector; the first data selector is also connected to the second arbitration module and the slave device 5.
  • the output module is configured to receive the access request sent by the connected MPU31, and the second arbitration module is configured to receive the access request sent by at least two MPU31 at the same time according to the second preset policy, Determines which access request the slave device is currently responding to.
  • the first data selector is used to turn on the master device 4 corresponding to the determined access request to the slave device 5 to send the determined access request to the slave device 5 (the remaining access requests can be buffered in the output module).
  • the bus mechanism 3 may further include a second gating circuit corresponding to the MPU 31 on a one-to-one basis; the MPU 31 is also connected to the master device 4 on the bus of this layer through the corresponding second gating circuit.
  • the slave device 5 responds to the access request and outputs response information.
  • the response information may carry information of the slave device and information of the master device.
  • the second gating circuit receives the response information fed back from the slave device 5, the second gating circuit determines the corresponding slave device 5 according to the response information, and conducts the determined corresponding slave device 5 and the layer where the second gating circuit is currently obtained.
  • the master device that controls the bus is configured to send the response information to the master device that obtains control of the bus of the layer where the second gating circuit is located.
  • the second gating circuit may be composed of a second data selector (ie, MUX2 in FIG. 3) 35 and an address decoding module 34.
  • the second data selector 35 is connected to the host device 4 and the address. Between the decoding modules 34.
  • the address decoding module 34 is used to determine the corresponding slave device 5 according to the response information, and the second data selector 35 is used to conduct control of the bus of the layer where the determined slave device 5 and the second data selector 35 are currently obtained.
  • this embodiment uses the OTP memory to store the bus access control information, so that the corresponding bus access control information can be written into the OTP memory according to the needs of different application scenarios, thereby adapting to different application scenarios. High flexibility.
  • the mode configuration module implemented by hardware is used to control the process of reading and configuring the bus access control information, so that the process cannot be controlled and tampered externally, which is beneficial to improving the security of the bus access control information.
  • the second embodiment of the present application relates to a SoC chip.
  • This embodiment is a further improvement based on the first embodiment.
  • the main improvement is that this embodiment also encrypts the bus access control information stored in the OTP memory to improve the security of the bus access control information. Sex.
  • an encryption module is provided in the OTP memory 2; the encryption module is used to encrypt the bus access control information written in the OTP memory 2. After the bus access control information is encrypted by the encryption module, it will be stored in the OTP memory 2 in the form of ciphertext. In practical applications, the encryption module can encrypt the bus access control information with a key preset by hardware that is not visible from the outside (that is, a key generated by hardware outside the OTP memory). After being encrypted by the encryption module, in the startup mode, the bus access control information read by the mode configuration module 1 from the OTP memory 2 is the encrypted bus access control information.
  • the SoC chip further includes a decryption module 6, and the decryption module 6 is connected to the mode configuration module 1 and the OTP memory 2 respectively.
  • the mode configuration module 1 can call the decryption module 6 to decrypt the read bus access control information, and write the decrypted bus access control information into the MPU31 to implement the configuration of the MPU31.
  • the decryption module 6 may adopt a public or private symmetric cryptographic algorithm, and use the same key as the encryption module (that is, a key preset by the hardware) for decryption.
  • this embodiment is described by using an encryption module provided in the OTP memory 2 as an example, but in an actual application, the encryption module may also be provided outside the OTP memory 2.
  • the encryption module can detect the interface of the OTP memory 2.
  • the encryption module detects that the designated master device writes bus access control information to the OTP memory 2, the encryption module is The bus access control information written in the OTP memory 2 can be encrypted.
  • this embodiment uses a key preset by hardware to encrypt and decrypt the bus access control information stored in the OTP memory.
  • the key preset by the hardware is an externally invisible key. This makes it impossible for an attacker to obtain the plaintext of the bus access control information, thereby improving the security of the bus access control information.
  • the third embodiment of the present application relates to a SoC chip.
  • This embodiment is a further improvement on the basis of the second embodiment.
  • the main improvement is that this embodiment encrypts the bus access control information stored in the OTP memory and also encrypts the bus access.
  • the verification information corresponding to the control information is stored in the OTP memory.
  • the mode configuration module 1 is further configured to calculate the verification information corresponding to the encrypted bus access control information after the encryption module encrypts the bus access control information, and write the verification information into OTP memory 2.
  • the mode configuration module 1 When the mode configuration module 1 reads the encrypted bus access control information from the OTP memory 2, it reads the verification information at the same time, and uses the verification information to calibrate the currently read encrypted bus access control information. Check. If the verification is successful, it indicates that the currently read bus access control information has not been modified. At this time, the mode configuration module 1 may call the decryption module 6 to decrypt the read bus access control information; if the verification fails, it indicates that the current bus access control information is not modified. The read bus access control information has been illegally modified. At this time, the mode configuration module 1 can trigger a safety alarm signal to reset the chip as a whole. In practical applications, the check information is used to check the currently read encrypted bus access control information, and methods such as CRC (Cyclic Redundancy Check, cyclic redundancy check) or parity check can be used.
  • CRC Cyclic Redundancy Check, cyclic redundancy check
  • parity check can be used.
  • this embodiment encrypts the bus access control information stored in the OTP memory, and also stores the verification information corresponding to the encrypted bus access control information in the OTP memory. It is beneficial to further prevent attackers from being unable to illegally modify the bus access control information, and improve the security of the SoC chip.
  • the fourth embodiment of the present application relates to a bus access control method. This method is applied to the SoC chip of the first embodiment, and the specific process is shown in FIG. 5.
  • Step 501 The mode configuration module reads the mode control word of the OTP memory after the SOC chip enters the startup mode.
  • Step 502 The mode configuration module determines whether the mode control word is an initial value of the OTP memory. If yes, go to step 503; if no, go to step 504.
  • Step 503 The mode configuration module switches the SoC chip to a test mode for the designated master device to write the bus access control information to the OTP memory.
  • the mode configuration module transfers control of the bus to a designated master device (test interface device), and the designated master device can write the bus access control information to the OTP memory through the bus. After writing the bus access control information, the designated master device can update the mode control word of the OTP memory to a preset value. After that, the SoC chip will be reset after power-on.
  • Step 504 The mode configuration module reads the bus access control information from the OTP memory.
  • Step 505 The mode configuration module uses the bus access control information to configure the MPU in the bus mechanism.
  • the mode configuration module can write the bus access control information into the MPUs on each layer of the bus to implement the MPU configuration.
  • Step 506 After the configuration of the MPU is completed, the mode configuration module enables the MPU and switches the SOC chip to the user mode.
  • the mode configuration module controls the SoC chip to enter the user mode.
  • the control of the bus is transferred to the master device, and the master device can send an access request through the bus.
  • the bus mechanism is a multi-layer bus interconnection structure, all bus masters are arranged in a hierarchical order, and each layer has an independent MPU.
  • the MPU can determine which slave device the current master device wants to access according to the slave device information in the bus access control information, and determine whether the access is legal according to the access authority in the bus access control information.
  • the MPU will intercept the access; for each intercepted access request, the MPU will generate a corresponding interrupt signal (return an error message to the master device corresponding to the illegal access request), and save the illegal access request.
  • the first embodiment corresponds to this embodiment, this embodiment can be implemented in cooperation with the first embodiment.
  • the related technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, details are not repeated here. Accordingly, the related technical details mentioned in this embodiment can also be applied in the first embodiment.
  • this embodiment uses the OTP memory to store the bus access control information, so that the corresponding bus access control information can be written into the OTP memory according to the needs of different application scenarios, thereby adapting to different application scenarios. High flexibility.
  • the mode configuration module implemented by hardware is used to control the process of reading and configuring the bus access control information, so that the process cannot be controlled and tampered externally, which is beneficial to improving the security of the bus access control information.
  • the fifth embodiment of the present application relates to a bus access control method.
  • This embodiment is a further improvement based on the fourth embodiment.
  • the main improvement is that this embodiment also encrypts the bus access control information stored in the OTP memory.
  • the specific process is shown in Figure 6. .
  • Steps 601 to 604 and 606 are the same as steps 501 to 504 and 506, which are not described in this embodiment.
  • Step 605 The mode configuration module calls the decryption module to decrypt the read bus access control information, and configures the MPU by using the decrypted bus access control information.
  • an encryption module is provided in the OTP memory; the encryption module encrypts the bus access control information written in the OTP memory. Therefore, in this embodiment, the bus access control information read by the mode configuration module from the OTP memory is encrypted bus access control information. Therefore, after the MPU is configured with the read bus access control information, the mode configuration module can call a decryption module to decrypt the read bus access control information, and then write the decrypted bus access control information into the MPU to implement Configuration of MPU.
  • the decryption module may use a public or private symmetric cryptographic algorithm and use the same key as the encryption module for decryption.
  • This key can be a preset key for externally invisible hardware.
  • the second embodiment corresponds to this embodiment, this embodiment can be implemented in cooperation with the second embodiment.
  • the relevant technical details mentioned in the second embodiment are still valid in this embodiment, and the technical effects that can be achieved in the second embodiment can also be achieved in this embodiment. In order to reduce repetition, details are not repeated here. Accordingly, the related technical details mentioned in this embodiment can also be applied in the second embodiment.
  • this embodiment uses a key preset by hardware to encrypt and decrypt the bus access control information stored in the OTP memory, so that an attacker cannot obtain the hardware key, and therefore cannot obtain the bus access control.
  • the clear text of the information improves the security of the bus access control information.
  • the sixth embodiment of the present application relates to a bus access control method.
  • This embodiment is a further improvement on the basis of the fifth embodiment.
  • the main improvement is that this embodiment encrypts the bus access control information stored in the OTP memory, and also encrypts the bus access.
  • the verification information corresponding to the control information is stored in the OTP memory, and the specific process is shown in FIG. 7.
  • Steps 701 to 703 and 708 are the same as steps 601 to 603 and 606, which are not described in this embodiment.
  • Step 704 The mode configuration module reads the bus access control information and the verification information from the OTP memory.
  • the mode configuration module calculates verification information corresponding to the encrypted bus access control information, and writes the verification information into the OTP memory.
  • Step 705 The mode configuration module uses the verification information to verify the currently read encrypted bus access control information, and determines whether the verification is successful. If yes, go to step 707; if no, go to step 706.
  • the check information is used to check the currently read encrypted bus access control information, and methods such as CRC or parity can be used.
  • Step 706 The mode configuration module controls the overall reset of the chip.
  • the mode configuration module can trigger a safety alarm signal to reset the chip as a whole.
  • Step 707 The mode configuration module calls the decryption module to decrypt the read bus access control information, and configures the MPU by using the decrypted bus access control information.
  • the mode configuration module can call the decryption module to decrypt the read bus access control information and write the decrypted bus access control information to the MPU. in.
  • the third embodiment corresponds to this embodiment, while the bus access control information stored in the OTP memory is encrypted, the verification information corresponding to the encrypted bus access control information is also stored in the OTP memory. It is beneficial to further prevent attackers from being unable to illegally modify the bus access control information, and improve the security of the SoC chip.

Abstract

本申请SoC芯片技术领域，提供了一种SoC芯片及总线访问控制方法。SoC芯片包括：总线机构，其包括至少一个MPU；OTP存储器，其用于存储总线访问控制信息；模式配置模块，连接至至少一个MPU及OTP存储器，模式配置模块用于在SoC芯片处于启动模式下，从OTP存储器中读取总线访问控制信息，并利用总线访问控制信息配置MPU，模式配置模块还用于在对MPU配置完成后，使能MPU，并将SoC芯片切换至用户模式。本申请，利用OTP存储器存储总线访问控制信息，使得可根据不同应用场景的需求，往OTP存储器中写入对应的总线访问控制信息，从而适应不同的应用场景，具有高度的灵活性。

Description

一种SoC芯片及总线访问控制方法 技术领域
本申请涉及SoC芯片技术领域，特别涉及一种SoC芯片及总线访问控制方法。
背景技术
SoC(System-on-a-Chip)芯片作为集成电路的芯片，其可有效地降低电子/信息系统产品的开发成本、缩短开发周期、提高产品的竞争力，在当今社会得到了广泛的应用。在SoC芯片中，总线系统是芯片上主设备与从设备传送信息的通道，具有重要的作用。在传统的SoC芯片架构中，采用的是单一总线系统，即所有的主设备共用一条总线，在同一时刻总线上只允许一个主设备具有访问权限。而随着SoC芯片的规模和复杂度日益提高，传统的单一总线系统已经无法满足应用需求，目前的总线结构由单一总线逐渐变为多层总线结构，即在同一时刻多个主设备可以在多层总线上向从设备发出访问请求，这种多层总线的结构提高了系统的性能，使得一个总线主设备的访问请求不会阻塞其他主设备，提高了总线效率。
在多个主设备和从设备相连的总线系统中，需要对总线上的每个主设备定义访问权限，每个主设备只能访问其允许访问的地址空间，例如对于外部通信接口设备，它只能访问系统中用于与外部交换数据的存储区域，不能控制和 访问系统中的其他资源。但现有的总线权限的配置方式欠缺灵活性，定义主设备的访问权限信息无法修改，因此这种配置方式通常只能满足一种应用场景，无法满足SoC芯片应用环境多样性的需求。
发明内容
本申请部分实施例的目的在于提供一种SoC芯片及总线访问控制方法，可根据不同的应用场景，设置不同的总线访问控制信息，从而适应不同的应用场景，提高配置方式的灵活性。
本申请实施例提供了一种SoC芯片，包括：总线机构，其包括至少一个MPU；OTP存储器，其用于存储总线访问控制信息；模式配置模块，连接至所述至少一个MPU及所述OTP存储器，所述模式配置模块用于在所述SoC芯片处于启动模式下，从所述OTP存储器中读取所述总线访问控制信息，并利用所述总线访问控制信息配置所述MPU，所述模式配置模块还用于在对所述MPU配置完成后，使能所述MPU，并将所述SoC芯片切换至用户模式。
本申请实施例还提供了一种总线访问控制方法，应用于SoC芯片，所述SoC芯片包括模式配置模块、OTP存储器及总线机构；所述模式配置模块分别连接所述OTP存储器及所述总线机构中的MPU；所述方法包括：所述模式配置模块在所述SoC芯片处于启动模式下，从所述OTP存储器中读取总线访问控制信息；所述模式配置模块利用所述总线访问控制信息配置总线机构中的MPU；所述模式配置模块在对所述MPU配置完成后，使能所述MPU，并将所述SoC芯片切换至用户模式。
本申请实施例相对于现有技术而言，利用OTP存储器存储总线访问控制 信息，使得可根据不同应用场景的需求，往OTP存储器中写入对应的总线访问控制信息，从而适应不同的应用场景，具有高度的灵活性。同时，本申请实施例利用通过硬件实现的模式配置模块控制总线访问控制信息的读取和配置过程，使得外部无法控制和篡改该过程，有利于提高总线访问控制信息的安全性。
另外，所述OTP存储器中设有加密模块，所述加密模块用于利用硬件预设的密钥，对写入所述OTP存储器中的所述总线访问控制信息进行加密；所述SoC芯片还包括解密模块，所述解密模块分别连接所述模式配置模块及所述OTP存储器；所述模式配置模块还用于调用所述解密模块利用所述硬件预设的密钥，对读取的所述总线访问控制信息进行解密，并将解密后的所述总线访问控制信息写入所述MPU中。使用硬件预设的密钥进行加密、解密，有利于避免防止总线访问控制信息被非法修改。
另外，所述模式配置模块还用于在所述加密模块对所述总线访问控制信息进行加密后，计算加密后的所述总线访问控制信息对应的校验信息，并将所述校验信息写入所述OTP存储器中；所述模式配置模块还用于从所述OTP存储器中读取所述校验信息，并利在所述校验信息对当前读取的加密后的所述总线访问控制信息进行校验，并在校验成功时，调用所述解密模块对读取的所述总线访问控制信息进行解密。在保存总线访问控制信息的同时，保存其校验信息，有利于避免攻击者非法修改总线访问控制信息。
另外，所述模式配置模块还用于在校验失败时，控制所述SoC芯片整体复位。有利于避免因非法修改而造成的潜在危险。
另外，所述总线机构包括多层总线，每层所述总线上连接一个所述MPU、至少一个主设备及至少一个从设备；所述MPU的一端连接所述主设备，另一 端连接所述从设备。提供一种总线机构的具体结构。
另外，在所述SoC芯片处于所述用户模式下，所述主设备用于通过其所在层的总线发送访问请求；所述MPU用于根据所述总线访问控制信息，判断通过其所在层的总线发送的所述访问请求的合法性，并将合法的所述访问请求输出给所述访问请求对应的所述从设备。利用MPU先验证访问请求的合法性，再将合法的访问请求输出给对应的从设备，有利于避免非法访问，提高SoC芯片的安全性。
另外，所述MPU还用于拦截通过其所在层的总线发送的非法的所述访问请求，向非法的所述访问请求对应的所述主设备返回错误信息，并保存非法的所述访问请求。对拦截的非法的访问请求进行保存，使的用户可查看到非法的访问请求。
另外，每层所述总线上还连接一地址译码模块，所述MPU的一端通过所述地址译码模块连接所述主设备；所述地址译码模块用于在接收到所述主设备发送的所述访问请求时，根据所述访问请求中的所述从设备的地址信息，确定所述访问请求对应的所述从设备，并输出对应的所述从设备已确定的所述访问请求至所述述MPU。提供一种确定访问请求对应的从设备的方法。
另外，每层所述总线上还连接一第一仲裁模块；所述地址译码模块通过所述第一仲裁模块连接所述主设备；所述第一仲裁模块用于在同一时间内接收到至少两个所述主设备发送的所述访问请求时，根据第一预设策略，将所述第一仲裁模块所在层的总线的控制权分配给其中一个所述主设备，并输出获得所述第一仲裁模块所在层的总线的控制权的所述主设备的所述访问请求。针对同层总线上多个主设备同时发送访问请求的场景，提供了一种具体的处理方法。
另外，所述总线机构还包括与所述从设备一一对应的第一选通电路；每个所述MPU的另一端通过所述第一选通电路连接至所述从设备；所述第一选通电路用于在同一时间内接收到至少两个所述MPU发送的所述访问请求时，根据第二预设策略，确定所述从设备当前待响应的所述访问请求，并导通所述从设备与确定的所述访问请求对应的所述主设备。针对从设备同时接收到多层总线上的主设备的访问请求的场景，提供了一种具体的处理方法。
另外，所述总线机构还包括与所述MPU一一对应的第二选通电路；每个所述MPU还通过所述第二选通电路连接所述主设备；所述MPU还用于接收所述从设备的发送的响应信息；所述第二选通电路用于根据所述响应信息，确定所述响应信息对应的所述从设备，并导通确定的所述从设备与当前获得所述第二选通电路所在层的总线的控制权的所述主设备。提供一种接收从设备的响应信息的方法。
另外，所述模式配置模块还用于在所述SoC芯片处于启动模式下，且所述OTP存储器的模式控制字为初始值时，将所述SoC芯片切换至测试模式，以供指定的主设备向所述OTP存储器中写入所述总线访问控制信息。提供一种向OTP存储器中写入总线访问控制信息的场景。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例中的SoC芯片的结构示意图；
图2是根据本申请第一实施例中的总线机构的结构示意图；
图3是根据本申请第一实施例中的第二选通电中的结构示意图；
图4是根据本申请第二实施例中的SoC芯片的结构示意图；
图5是根据本申请第四实施例中的总线访问控制方法的具体流程图；
图6是根据本申请第五实施例中的总线访问控制方法的具体流程图；
图7是根据本申请第六实施例中的总线访问控制方法的具体流程图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种SoC芯片。如图1所示，该SoC芯片包括模式配置模块1、OTP(One Time Programable，一次性可编程)存储器2及总线机构3；其中，OTP存储器2用于存储总线访问控制信息，总线机构3包括至少一个MPU(Memory Protection Unit，存储器保护单元)31(参见图2)，模式配置模块1分别连接OTP存储器2及该至少一个MPU31。
具体而言，总线机构3可包括多层总线，每层总线可连接一个MPU31、至少一个主设备4及至少一个从设备5；MPU31的一端通过总线连接至主设备4，另一端通过总线连接至从设备5。在实际应用中，MPU31连接的主设备4为所在层的总线上的主设备，MPU31连接的从设备5既包括所在层的总线上的从设备，也可包括其他层的总线上的从设备。主设备4可包括MCU、DMA(Direct Memory Access，直接存储器访问)模块、外部通信接口模块、调试接口模块、 加解密模块等；从设备5可包括RAM(random access memory，随机存取存储器)、ROM(Read-Only Memory，只读存储器)、Flash(闪存)、EEPROM(Electrically Erasable Programmable read only memory，带电可擦可编程只读存储器)以及其他功能模块(功能模块通常通过寄存器接口连接在总线上)。图2是以总线机构3包括三层总线为例进行示意的，其中第一层总线上的主设备4为MCU、JTAG(系统测试接口模块)；第二层总线上的主设备4为USB、SPIM0(串行外设接口M0)、SPIM2(串行外设接口M2)；第三层总线上的主设备4为AES(高级加密标准模块)、SHA(安全散列算法模块)、SPIM1(串行外设接口M1)、DMA(直接存储器访问模块)。从设备5分别为IRAM(Internal Random Access Memory，内部随机存取存储器)、DRAM(Dynamic Random Access Memory，动态随机存取存储器)、BRAM(Block Random Access Memory，块随机存取存储器)、APB Regs(外设的寄存器空间)。
值得一提的是，在实际应用中，OTP存储器2可连接在其中一层总线上；模式配置模块1既可连接在其中一层总线上，通过总线实现与OTP存储器2及各层总线上的MPU31的连接，也可不连接在任意一层总线上，而通过其他线路，实现与OTP存储器2及各层总线上的MPU31的连接，本实施例对此不做限制。
本实施例中，OTP存储器2用于存储总线访问控制信息。该总线访问控制信息可包括各层总线上连接的主设备4的信息(如主设备的编号)、从设备5的信息(如从设备的地址信息，其可包括从设备的起始地址、从设备的地址范围等)以及主设备4对从设备5的访问权限。访问权限主要分为四种，即：RW(可以读可以写)、WO(只可写)、RO(只可读)、NA(不可读不可写)， 参见表一。
表一：
Figure PCTCN2018099983-appb-000001
模式配置模块1用于在SoC芯片处于启动模式(Boot模式)下，从OTP存储器2中读取总线访问控制信息，并利用总线访问控制信息对MPU31进行配置。
具体而言，当SoC芯片复位或上电之后，SoC芯片会进入启动模式，此时，总线机构中的多层总线由模式配置模块1控制，总线上的主设备4不能通过总线发起访问请求。在该模式下，模式配置模块1读取OTP存储器2的模式控制字，若该模式控制字为OTP存储器2的初始值，则表明OTP存储器2中未写入总线访问控制信息，此时，模式配置模块1会将SoC芯片切换至测试模式，以供指定的主设备4(如测试接口设备)向OTP存储器2中写入总线访问控制信息。该指定的主设备4在写入总线访问控制信息后，会将OTP存储器2的模式控制字更新为预设值，此后，SoC芯片会重新上电复位，再次进入启动模式。若模式配置模块1读取的OTP存储器2的模式控制字为预设值，则表明OTP存储器2中已写入总线访问控制信息。此时，模式配置模块1可直接从OTP存储器2中读取总线访问控制信息，并将总线访问控制信息写入MPU31 中，以实现对MPU31的配置。
模式配置模块1还用于在对MPU31配置完成后，使能MPU31，并将SoC芯片切换至用户模式。此时，模式配置模块1会将总线的控制权转移给主设备4，以供主设备4通过总线发送访问请求。
在SoC芯片处于用户模式下，主设备4用于通过其所在层的总线发送访问请求，MPU31用于根据总线访问控制信息，判断通过本层总线发送的访问请求的合法性。具体而言，访问请求中会携带对应的主设备4的信息(如主设备的编号)、要访问的从设备5的信息(如从设备的地址信息)等。MPU31在接收到通过其所在层的总线发送的访问请求时，可先确定当前的主设备4要访问哪一个从设备5(即确定访问请求对应的从设备5)，然后根据总线访问控制信息中的访问权限判断该访问是否合法。若合法，MPU31会将该访问请求输出给该访问请求对应的从设备。若不合法，MPU31会拦截该非法的访问请求，向非法的访问请求对应的主设备4返回错误信息，并保存该非法的访问请求，以供用户随时查看。
优选地，本实施例中，每层总线上还连接一个地址译码模块34，MPU31通过该地址译码模块34连接MPU31所在层的总线上的主设备4。地址译码模块34用于在接收到主设备4发送的访问请求时，根据访问请求包含的从设备5的地址信息，确定该访问请求对应的从设备5。确定好从设备5之后，地址译码模块34就可输出对应的从设备已确定的访问请求至MPU31。MPU31在接收到地址译码模块34输出的访问请求时，就可直接从该访问请求中确定出当前的主设备4要访问哪一个从设备5。
优选地，本实施例中，每层总线上还连接一个第一仲裁模块32。地址译 码模块34通过该第一仲裁模块32连接MPU31所在层的总线上的主设备4。第一仲裁模块32用于在同一时间内接收到至少两个主设备4发送的访问请求时，根据第一预设策略，将第一仲裁模块32所在层的总线的控制权分配给其中一个主设备4，并输出获得第一仲裁模块32所在层的总线的控制权的主设备4的访问请求。该第一预设策略可以是主设备的优先级，即根据发送访问请求的各主设备的优先级的高低分配总线的控制权。该第一预设策略也可以是轮询策略，本实施例对此不做限制。第一仲裁模块32还会缓存当前未获得其所在层的总线的控制权的主设备的访问请求，待其所在层的总线空闲(总线的控制权被释放)时，第一仲裁模块32可再按照第一预设策略将总线的控制权分配给当前缓存的访问请求对应的主设备。
优选地，总线机构3还包括与从设备5一一对应的第一选通电路33，MPU31通过第一选通电路33连接至从设备5。具体而言，MPU31接收到第一仲裁模块32输出的访问请求，并判定该访问请求为合法的访问请求时，会将该访问请求输出给相应的从设备5对应的第一选通电路33。若第一选通电路33在同一时间内仅接收到一个MPU31发送的访问请求，则会导通对应的从设备5与该访问请求对应的主设备4，以将接收到访问请求发送给从设备5。若第一选通电路33在同一时间内接收到至少两个MPU31发送的访问请求，则可根据第二预设策略，确定从设备当前待响应的访问请求，并导通从设备与确定的访问请求对应的主设备。该第二预设策略可以是主设备的优先级，也可以是轮询策略，本实施例对此不做限制。
该第一选通电路33可包括：输出模块、第一数据选择器(即图2中的MUX1)及第二仲裁模块；其中，输出模块包括多个第一连接端，及一个第二 连接端，每个第一连接端可对应连接一个MPU31，第二连接端连接第一数据选择器；第一数据选择器还连接第二仲裁模块及从设备5。其中，输出模块用于接收其所连接的MPU31所发送的访问请求，第二仲裁模块用于在输出模块在同一时间内接收到至少两个MPU31发送的访问请求时，根据第二预设策略，确定从设备当前待响应的访问请求。第一数据选择器则用于导通从设备5与确定的访问请求对应的主设备4，以将确定的访问请求发送给从设备5(剩下的访问请求可缓存在输出模块中)。
值得一提的是，总线机构3还可包括与MPU31一一对应的第二选通电路；MPU31还通过对应的第二选通电路连接本层总线上的主设备4。具体而言，从设备5接收到第一选通电路33发送的访问请求后，会对该访问请求进行响应，并输出响应信息。该响应信息中可携带从设备的信息及主设备的信息。第二选通电路在MPU31接收到从设备5反馈的响应信息时，会根据该响应信息确定对应的从设备5，并导通确定的对应从设备5与当前获得第二选通电路所在层的总线的控制权的主设备，以将该响应信息发送给该获得第二选通电路所在层的总线的控制权的主设备。
如图3所示，该第二选通电路可由第二数据选择器(即图3中的MUX2)35及地址译码模块34组成，其中，第二数据选择器35连接在主设备4与地址译码模块34之间。其中，地址译码模块34用于根据该响应信息确定对应的从设备5，第二数据选择器35用于导通确定的从设备5与当前获得第二数据选择器35所在层的总线的控制权的主设备4。
本实施例相对于现有技术而言，利用OTP存储器存储总线访问控制信息，使得可根据不同应用场景的需求，往OTP存储器中写入对应的总线访问控制信 息，从而适应不同的应用场景，具有高度的灵活性。同时，本申请实施例利用通过硬件实现的模式配置模块控制总线访问控制信息的读取和配置过程，使得外部无法控制和篡改该过程，有利于提高总线访问控制信息的安全性。
本申请第二实施例涉及一种SoC芯片。本实施例是在第一实施例的基础上做的进一步改进，主要改进之处在于：本实施例还会对存储在OTP存储器中的总线访问控制信息进行加密，以提高总线访问控制信息的安全性。
本实施例中，OTP存储器2中设有加密模块；加密模块用于对写入OTP存储器2中的总线访问控制信息进行加密。总线访问控制信息经加密模块加密之后，会对密文的形式存储于OTP存储器2中。在实际应用中，加密模块可用外部不可见的硬件预设的密钥(即OTP存储器外部的硬件产生的密钥)对总线访问控制信息进行加密。经加密模块加密之后，在启动模式下，模式配置模块1从OTP存储器2中读取的总线访问控制信息就是加密后的总线访问控制信息。
本实施例中，如4所示，SoC芯片还包括解密模块6，该解密模块6分别连接模式配置模块1及OTP存储器2。模式配置模块1可调用解密模块6对读取的总线访问控制信息进行解密，并将解密后的总线访问控制信息写入MPU31中，以实现对MPU31的配置。解密模块6可采用公开或私有的对称密码算法，使用与加密模块相同的密钥(即该硬件预设的密钥)进行解密。
值得一提的是，本实施例是以加密模块设置于OTP存储器2中为例进行说明的，但在实际应用中，加密模块也可以设置于OTP存储器2外。当加密模块设置于OTP存储器2外时，该加密模块可对OTP存储器2的接口进行检测，当加密模块检测到指定的主设备向OTP存储器2中写入总线访问控制信息时， 该加密模块即可对写入OTP存储器2中的总线访问控制信息进行加密。
本实施例相对于第一实施例而言，使用硬件预设的密钥对存储在OTP存储器中的总线访问控制信息进行加密、解密，该硬件预设的密钥为外部不可见的密钥，使得攻击者无法获取，因此无法得到总线访问控制信息的明文，提高了总线访问控制信息的安全性。
本申请第三实施例涉及一种SoC芯片。本实施例是在第二实施例的基础上做的进一步改进，主要改进之处在于：本实施例在对存储于OTP存储器中的总线访问控制信息进行加密的同时，还将加密后的总线访问控制信息对应的校验信息存储于OTP存储器中。
具体而言，本实施例中，模式配置模块1还用于在加密模块对总线访问控制信息进行加密后，计算加密后的总线访问控制信息对应的校验信息，并将该校验信息写入OTP存储器2中。
模式配置模块1在从OTP存储器2中读取加密后的总线访问控制信息时，会同时读取该校验信息，并利用该校验信息对当前读取的加密后的总线访问控制信息进行校验。若校验成功，则表明当前读取的总线访问控制信息未被修改，此时，模式配置模块1可调用解密模块6对读取的总线访问控制信息进行解密；若校验失败，则表明当前读取的总线访问控制信息已被非法修改。此时，模式配置模块1可触发安全报警信号使芯片整体复位。在实际应用中，利用校验信息对当前读取的加密后的总线访问控制信息进行校验，可使用CRC(Cyclic Redundancy Check，循环冗余校验)或奇偶校验等方法。
本实施例相对于第二实施例而言，在对存储于OTP存储器中的总线访问 控制信息进行加密的同时，还将加密后的总线访问控制信息对应的校验信息存储于OTP存储器中，有利于进一步防止攻击者无法非法修改总线访问控制信息，提高SoC芯片的安全性。
本申请第四实施例涉及一种总线访问控制方法。该方法应用于第一实施例的SoC芯片，其具体流程如图5所示。
步骤501：模式配置模块在SOC芯片进入启动模式后，读取OTP存储器的模式控制字。
步骤502：模式配置模块判断该模式控制字是否为OTP存储器的初始值。若是，则进入步骤503；若否，则进入步骤504。
步骤503：模式配置模块将SoC芯片切换至测试模式，以供指定的主设备向OTP存储器中写入总线访问控制信息。
在测试模式下，模式配置模块将总线的控制权转移给指定的主设备(测试接口设备)，该指定的主设备就可通过总线向OTP存储器中写入总线访问控制信息。写完总线访问控制信息，该指定的主设备就可将OTP存储器的模式控制字更新为预设值。此后，SoC芯片会重新上电复位。
步骤504：模式配置模块从OTP存储器中读取总线访问控制信息。
步骤505：模式配置模块利用总线访问控制信息配置总线机构中的MPU。
从OTP存储器中读取总线访问控制信息后，模式配置模块可将总线访问控制信息写入各层总线上的MPU中，以实现对MPU的配置。
步骤506：模式配置模块在对MPU配置完成后，使能MPU，并将SOC芯片切换至用户模式。
完成对MPU的配置后，模式配置模块控制SoC芯片进入用户模式，此时，总线的控制权会转移至主设备，主设备可通过总线发送访问请求。
值得一提的是，本实施例中，总线机构是一个多层的总线互联结构，所有的总线主设备按照分层顺序排列，每一层上有一个独立的MPU。主设备通过总线发送访问请求时，MPU可根据总线访问控制信息中的从设备的信息判断当前的主设备要访问哪一个从设备，并根据总线访问控制信息中的访问权限判断该访问是否合法。对于非法的访问请求，MPU会拦截该次访问；针对每次被拦截的访问请求，MPU都会产生对应的中断信号(向非法的访问请求对应的主设备返回错误信息)，并保存该非法的访问请求。
由于第一实施例与本实施例相互对应，因此本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
本实施例相对于现有技术而言，利用OTP存储器存储总线访问控制信息，使得可根据不同应用场景的需求，往OTP存储器中写入对应的总线访问控制信息，从而适应不同的应用场景，具有高度的灵活性。同时，本申请实施例利用通过硬件实现的模式配置模块控制总线访问控制信息的读取和配置过程，使得外部无法控制和篡改该过程，有利于提高总线访问控制信息的安全性。
本申请第五实施例涉及一种总线访问控制方法。本实施例是在第四实施例的基础上做的进一步改进，主要改进之处在于：本实施例还会对存储在OTP 存储器中的总线访问控制信息进行加密，其具体流程如图6所示。
其中，步骤601至604、606与步骤501至504、506相同，本实施例不再赘述。
步骤605：模式配置模块调用解密模块对读取的总线访问控制信息进行解密，并利用解密后的总线访问控制信息配置MPU。
本实施例中，OTP存储器中设有加密模块；该加密模块会对写入OTP存储器中的总线访问控制信息进行加密。因此，本实施例中，模式配置模块从OTP存储器中读取的总线访问控制信息为加密的总线访问控制信息。因此，在利用读取的总线访问控制信息配置MPU之后，模式配置模块可调用解密模块对读取的总线访问控制信息进行解密，然后再将解密后的总线访问控制信息写入MPU中，以实现对MPU的配置。
值得一提的是，本实施例中解密模块可采用公开或私有的对称密码算法，使用与加密模块相同的密钥进行解密。该密钥可为外部不可见的硬件预设的密钥。
由于第二实施例与本实施例相互对应，因此本实施例可与第二实施例互相配合实施。第二实施例中提到的相关技术细节在本实施例中依然有效，在第二实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第二实施例中。
本实施例相对于第四实施例而言，使用硬件预设的密钥对存储在OTP存储器中的总线访问控制信息进行加密、解密，使得攻击者无法获得硬件密钥，因此无法得到总线访问控制信息的明文，提高了总线访问控制信息的安全性。
本申请第六实施例涉及一种总线访问控制方法。本实施例是在第五实施例的基础上做的进一步改进，主要改进之处在于：本实施例在对存储于OTP存储器中的总线访问控制信息进行加密的同时，还将加密后的总线访问控制信息对应的校验信息存储于OTP存储器中，其具体流程如图7所示。
其中，步骤701至703、708与步骤601至603、606相同，本实施例不再赘述。
步骤704：模式配置模块从OTP存储器中读取总线访问控制信息，以及校验信息。
本实施例中，模式配置模块还在加密模块对总线访问控制信息进行加密后，计算加密后的总线访问控制信息对应的校验信息，并将该校验信息写入OTP存储器中。
步骤705：模式配置模块利用该校验信息对当前读取的加密后的总线访问控制信息进行校验，并判断是否校验成功。若是，则进入步骤707；若否，则进入步骤706。
在实际应用中，利用校验信息对当前读取的加密后的总线访问控制信息进行校验，可使用CRC或奇偶校验等方法。
步骤706：模式配置模块控制芯片整体复位。
若校验失败，则表明当前的总线访问控制信息已被非法修改。此时，模式配置模块可触发安全报警信号使芯片整体复位。
步骤707：模式配置模块调用解密模块对读取的总线访问控制信息进行解密，并利用解密后的总线访问控制信息配置MPU。
若校验成功，则表明当前的总线访问控制信息未被修改，此时，模式配置模块可调用解密模块对读取的总线访问控制信息进行解密，并将解密后的总线访问控制信息写入MPU中。
由于第三实施例与本实施例相互对应，在对存储于OTP存储器中的总线访问控制信息进行加密的同时，还将加密后的总线访问控制信息对应的校验信息存储于OTP存储器中，有利于进一步防止攻击者无法非法修改总线访问控制信息，提高SoC芯片的安全性。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (17)

  1. 一种SoC芯片，其特征在于，包括：
    总线机构，其包括至少一个MPU；
    OTP存储器，其用于存储总线访问控制信息；
    模式配置模块，连接至所述至少一个MPU及所述OTP存储器，
    所述模式配置模块用于在所述SoC芯片处于启动模式下，从所述OTP存储器中读取所述总线访问控制信息，并利用所述总线访问控制信息配置所述MPU，所述模式配置模块还用于在对所述MPU配置完成后，使能所述MPU，并将所述SoC芯片切换至用户模式。
  2. 根据权利要求1所述的SoC芯片，其中，所述OTP存储器中设有加密模块，所述加密模块用于利用硬件预设的密钥，对写入所述OTP存储器中的所述总线访问控制信息进行加密；
    所述SoC芯片还包括解密模块，所述解密模块分别连接所述模式配置模块及所述OTP存储器；
    所述模式配置模块还用于调用所述解密模块利用所述硬件预设的密钥，对读取的所述总线访问控制信息进行解密，并将解密后的所述总线访问控制信息写入所述MPU中。
  3. 根据权利要求2所述的SoC芯片，其中，
    所述模式配置模块还用于在所述加密模块对所述总线访问控制信息进行加密后，计算加密后的所述总线访问控制信息对应的校验信息，并将所述校验信息写入所述OTP存储器中；
    所述模式配置模块还用于从所述OTP存储器中读取所述校验信息，并利在所述校验信息对当前读取的加密后的所述总线访问控制信息进行校验，并在校验成功时，调用所述解密模块对读取的所述总线访问控制信息进行解密。
  4. 根据权利要求3所述的SoC芯片，其中，所述模式配置模块还用于在校验失败时，控制所述SoC芯片整体复位。
  5. 根据权利要求1所述的SoC芯片，其中，所述总线机构包括多层总线，每层所述总线连接一个所述MPU、至少一个主设备及至少一个从设备；其中，所述MPU的一端连接所述主设备，另一端连接所述从设备。
  6. 根据权利要求5所述的SoC芯片，其中，
    在所述SoC芯片处于所述用户模式下，
    所述主设备用于通过其所在层的总线发送访问请求；
    所述MPU用于根据所述总线访问控制信息，判断通过其所在层的总线发送的所述访问请求的合法性，并将合法的所述访问请求输出给所述访问请求对应的所述从设备。
  7. 根据权利要求6所述的SoC芯片，其中，所述MPU还用于拦截通过其所在层的总线发送的非法的所述访问请求，向非法的所述访问请求对应的所述主设备返回错误信息，并保存非法的所述访问请求。
  8. 根据权利要求5所述的SoC芯片，其中，每层所述总线上还连接一地址译码模块，所述MPU的一端通过所述地址译码模块连接所述主设备；
    所述地址译码模块用于在接收到所述主设备发送的所述访问请求时，根据所述访问请求中的所述从设备的地址信息，确定所述访问请求对应的所述从设备，并输出对应的所述从设备已确定的所述访问请求至所述MPU。
  9. 根据权利要求8所述的SoC芯片，其中，每层所述总线上还连接一第一仲裁模块；所述地址译码模块通过所述第一仲裁模块连接所述主设备；
    所述第一仲裁模块用于在同一时间内接收到至少两个所述主设备发送的所述访问请求时，根据第一预设策略，将所述第一仲裁模块所在层的总线的控制权分配给其中一个所述主设备，并输出获得所述第一仲裁模块所在层的总线的控制权的所述主设备的所述访问请求。
  10. 根据权利要求5所述的SoC芯片，其中，所述总线机构还包括与所述从设备一一对应的第一选通电路；每个所述MPU的另一端通过所述第一选通电路连接至所述从设备；
    所述第一选通电路用于在同一时间内接收到至少两个所述MPU发送的所述访问请求时，根据第二预设策略，确定所述从设备当前待响应的所述访问请求，并导通所述从设备与确定的所述访问请求对应的所述主设备。
  11. 根据权利要5所述的SoC芯片，其中，所述总线机构还包括与所述MPU一一对应的第二选通电路；每个所述MPU还通过所述第二选通电路连接所述主设备；
    所述MPU还用于接收所述从设备的发送的响应信息；
    所述第二选通电路用于根据所述响应信息，确定所述响应信息对应的所述从设备，并导通确定的所述从设备与当前获得所述第二选通电路所在层的总线的控制权的所述主设备。
  12. 根据权利要求1所述的SoC芯片，其中，所述模式配置模块还用于在所述SoC芯片处于所述启动模式下，且所述OTP存储器的模式控制字为初始值 时，将所述SoC芯片切换至测试模式，以供指定的主设备向所述OTP存储器中写入所述总线访问控制信息。
  13. 一种总线访问控制方法，其特征在于，应用于SoC芯片，所述SoC芯片包括：
    总线机构，其包括至少一个MPU；
    OTP存储器，其用于存储总线访问控制信息；
    模式配置模块，连接至所述至少一个MPU及所述OTP存储器；
    所述方法包括：
    所述模式配置模块在所述SoC芯片处于启动模式下，从所述OTP存储器中读取所述总线访问控制信息；
    所述模式配置模块利用所述总线访问控制信息配置所述MPU；
    所述模式配置模块在对所述MPU配置完成后，使能所述MPU，并将所述SoC芯片切换至用户模式。
  14. 根据权利要求13所述的总线访问控制方法，其中，所述OTP存储器中设有加密模块；所述加密模块用于利用硬件预设的密钥，对写入所述OTP存储器中的所述总线访问控制信息进行加密；
    所述模式配置模块利用所述总线访问控制信息配置所述MPU，具体包括：
    所述模式配置模块调用解密模块利用所述硬件预设的密钥，对读取的所述总线访问控制信息进行解密，并将解密后的所述总线访问控制信息写入所述MPU中。
  15. 根据权利要求14所述的总线访问控制方法，其中，在所述调用解密模块利用所述硬件预设的密钥，对读取的所述总线访问控制信息进行解密之前，所述方法还包括：
    从所述OTP存储器中读取校验信息；其中，所述模式配置模块在所述加密模块对所述总线访问控制信息进行加密后，计算加密后的所述总线访问控制信息对应的所述校验信息，并将所述校验信息写入所述OTP存储器；
    利用所述校验信息对当前读取的加密后的所述总线访问控制信息进行校验；
    在校验成功时，执行所述调用解密模块对读取的所述总线访问控制信息进行解密。
  16. 根据权利要求15所述的总线访问控制方法，其中，在校验失败时，所述方法还包括：
    控制所述SoC芯片整体复位。
  17. 根据权利要求13所述的总线访问控制方法，其中，在所述从OTP存储器中读取总线访问控制信息之前，所述方法还包括：
    读取当前所述OTP存储器的模式控制字；
    判断所述模式控制字是否为所述OTP存储器的初始值；
    若是，则将所述SoC芯片切换至测试模式，以供指定的主设备向所述OTP存储器中写入所述总线访问控制信息；
    若否，则执行所述读取所述总线访问控制信息。
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