WO2020024985A1 - 移位寄存器、栅极驱动电路、显示装置和栅极驱动方法 - Google Patents

移位寄存器、栅极驱动电路、显示装置和栅极驱动方法 Download PDF

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Publication number
WO2020024985A1
WO2020024985A1 PCT/CN2019/098612 CN2019098612W WO2020024985A1 WO 2020024985 A1 WO2020024985 A1 WO 2020024985A1 CN 2019098612 W CN2019098612 W CN 2019098612W WO 2020024985 A1 WO2020024985 A1 WO 2020024985A1
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Prior art keywords
transistor
terminal
signal
sensing
circuit
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PCT/CN2019/098612
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/633,082 priority Critical patent/US11081061B2/en
Priority to EP19836777.3A priority patent/EP3832635B1/en
Publication of WO2020024985A1 publication Critical patent/WO2020024985A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register, a gate driving circuit, a display device, and a gate driving method.
  • a gate driving circuit ie, a gate driver-on-array (GOA) circuit integrated on an array substrate.
  • the gate driving circuit includes a cascaded multi-stage shift register for generating a plurality of driving signals to perform progressive scanning through a plurality of gate lines. This is an effective way to drive a thin film transistor-based pixel array in a display panel to display image frames one by one on the display panel.
  • the present disclosure provides a shift register including an input circuit, an inversion circuit, and an output circuit.
  • the input circuit is connected to the pull-up node with the inversion circuit and the output circuit, and the output circuit and
  • the reverse circuit is connected to a pull-down node, wherein the input circuit is configured to control a voltage of the pull-up node in response to an input signal, and the reverse circuit is configured to perform a voltage control of the pull-up node.
  • Reverse processing, and outputting the voltage after the reverse processing to the pull-down node, and the output circuit is configured to continue for one frame under the control of the voltage of the pull-up node and the voltage of the pull-down node Multiple pulse signals are output in time.
  • the input circuit includes: a display precharge reset circuit, a sensing cascade circuit, and a sensing precharge reset circuit;
  • the sensing cascade circuit and the sensing precharge reset circuit are connected to a sensing cascade node, and the display precharge reset circuit, the sensing precharge reset circuit, and the output circuit are connected to the above. Pull node
  • the display precharge reset circuit is connected to a first signal input terminal, a reset signal terminal, a first power terminal, and a second power terminal, and is configured to respond to the first signal input terminal provided during the display precharge stage. Control of a first input signal, writing a first working voltage in an active level state provided by a first power terminal to the pull-up node, and responding to a reset signal provided by the reset signal terminal in a display reset phase Control, writing a second working voltage in a non-active level state provided by a second power supply terminal to the pull-up node;
  • the sensing cascade circuit is connected to the second signal input terminal and the second clock signal terminal, and is configured to respond to the control of the second clock signal provided by the second clock signal terminal during the sensing cascade stage, and Writing a second input signal in a valid level state provided by a second signal input terminal to the sensing cascade node;
  • the sensing precharge reset circuit is connected to the first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the second power supply terminal, and is configured to respond to the The control of sensing the voltage of the cascade node and the first clock signal provided by the first clock signal terminal, and writing the third clock signal provided by the third clock signal terminal in an active level state to the The pull-up node, and in response to the control of the second clock signal provided by the second clock signal terminal during the sensing reset phase, write the second working voltage in the inactive level state provided by the second power terminal Access to the pull-up node;
  • the output circuit is connected to at least one signal output terminal
  • the output circuit includes: at least one output sub-circuit corresponding to the at least one signal output terminal, and the output sub-circuit in the at least one output sub-circuit Connected to the pull-up node, the pull-down node, a corresponding signal output terminal, a corresponding driving clock signal terminal, and a corresponding reset power terminal
  • the output sub-circuit is configured to respond in the display output stage and the sensing output stage
  • the driving clock signal provided by the corresponding driving clock signal terminal is written to the corresponding signal output terminal, and is configured to be in a display reset stage And in the sensing reset phase, in response to control of the voltage of the pull-down node in an active level state, writing a reset operating voltage in a non-active level state provided by the corresponding reset power supply terminal to the corresponding Signal output.
  • the display precharge reset circuit includes: a first display transistor and a second display transistor;
  • a control electrode of the first display transistor is connected to the first signal input terminal, a first electrode of the first display transistor is connected to the first power supply terminal, and a second electrode of the first display transistor is connected to the first signal transistor. Said pull-up node connection;
  • a control pole of the second display transistor is connected to the reset signal terminal, a first pole of the second display transistor is connected to the pull-up node, and a second pole of the second display transistor is connected to the second Connect the power supply.
  • the shift register further includes: an anti-leakage circuit
  • the leakage prevention circuit includes a first leakage prevention transistor and a second leakage prevention transistor, and a second pole of the second display transistor is connected to the second power supply terminal through the second leakage prevention transistor;
  • a control electrode of the first leakage prevention transistor is connected to one of the at least one signal output terminal, and a first pole of the first leakage prevention transistor is connected to a second pole of the second display transistor.
  • the first pole of the second leakage preventing transistor is connected, and the second pole of the first leakage preventing transistor is connected to one of the at least one signal output terminal;
  • the control electrode of the second leakage prevention transistor is connected to the control electrode of the second display transistor, the first electrode of the second leakage prevention transistor is connected to the second electrode of the second display transistor, and the second The second pole of the anti-leakage transistor is connected to the second power terminal.
  • the reverse circuit includes: a third display transistor, a fourth display transistor, and a fifth display transistor;
  • a control electrode of the third display transistor is connected to a third power terminal, a first electrode of the third display transistor is connected to the third power terminal, and a second electrode of the third display transistor is connected to the pull-down node. connection;
  • a control electrode of the fourth display transistor is connected to a fourth power terminal, a first electrode of the fourth display transistor is connected to the fourth power terminal, and a second electrode of the fourth display transistor is connected to the pull-down node. connection;
  • a control electrode of the fifth display transistor is connected to the pull-up node, a first electrode of the fifth display transistor is connected to the pull-down node, and a second electrode of the fifth display transistor is connected to the second power source.
  • the third operating voltage provided by the third power supply terminal and the fourth operating voltage provided by the fourth power supply terminal are switched between an active level state and an inactive level state every preset period, and at any time At one time, one of the third working voltage and the fourth working voltage is in an active level state, and the other is in an inactive level state.
  • the output sub-circuit includes: a sixth display transistor and a seventh display transistor;
  • a control electrode of the sixth display transistor is connected to the pull-up node, a first electrode of the sixth display transistor is connected to the corresponding driving clock signal terminal, and a second electrode of the sixth display transistor is connected to the Said corresponding signal output terminal connection;
  • the control electrode of the seventh display transistor is connected to the pull-down node, the first electrode of the seventh display transistor is connected to the corresponding signal output terminal, and the second electrode of the seventh display transistor is connected to the corresponding one.
  • the reset power terminal is connected.
  • the shift register further includes: a first capacitor
  • a first terminal of the first capacitor is connected to the pull-up node, and a second terminal of the first capacitor is connected to a signal output terminal of the at least one signal output terminal.
  • the number of the at least one signal output terminal is 1-4.
  • the shift register further includes: a noise reduction circuit, the noise reduction circuit includes: an eighth display transistor;
  • the control electrode of the eighth display transistor is connected to the pull-down node, the first electrode of the eighth display transistor is connected to the pull-up node, and the second electrode of the eighth display transistor is connected to the second power source. ⁇ ⁇ End connection.
  • the shift register further includes: an anti-leakage circuit
  • the leakage prevention circuit includes a first leakage prevention transistor and a third leakage prevention transistor, and a second pole of the eighth display transistor is connected to the second power supply terminal through the third leakage prevention transistor;
  • a control electrode of the first leakage prevention transistor is connected to one of the at least one signal output terminal, and a first pole of the first leakage prevention transistor is connected to a second pole of the eighth display transistor.
  • the first pole of the third leakage prevention transistor is connected, and the second pole of the first leakage prevention transistor is connected to one of the at least one signal output terminal;
  • the control electrode of the third leakage prevention transistor is connected to the control electrode of the eighth display transistor, the first electrode of the third leakage prevention transistor is connected to the second electrode of the eighth display transistor, and the third The second pole of the anti-leakage transistor is connected to the second power terminal.
  • the sensing cascade circuit includes: a first sensing transistor
  • a control electrode of the first sensing transistor is connected to the second clock signal terminal, a first electrode of the first sensing transistor is connected to the second signal input terminal, and a first electrode of the first sensing transistor is connected to the second clock signal terminal.
  • a dipole is connected to the sensing cascade node.
  • the shift register further includes: a second capacitor
  • a first terminal of the second capacitor is connected to the sensing cascade node, and a second terminal of the second capacitor is connected to a fifth power supply terminal.
  • the sensing precharge reset circuit includes: a second sensing transistor, a third sensing transistor, and a fourth sensing transistor;
  • a control pole of the second sensing transistor is connected to the sensing cascade node, a first pole of the second sensing transistor is connected to the third clock signal terminal, and a second pole of the second sensing transistor A second pole is connected to a first pole of the third sensing transistor;
  • a control electrode of the third sensing transistor is connected to the first clock signal terminal, and a second electrode of the third sensing transistor is connected to the pull-up node;
  • a control pole of the fourth sensing transistor is connected to the second clock signal terminal, a first pole of the fourth sensing transistor is connected to the pull-up node, and a second pole of the fourth sensing transistor Connected to the second power terminal.
  • the shift register further includes: an anti-leakage circuit
  • the leakage prevention circuit includes a first leakage prevention transistor, a fourth leakage prevention transistor, and a fifth leakage prevention transistor.
  • a first pole of the third sensing transistor passes the fourth leakage prevention transistor and the second sense transistor.
  • a second pole of the sensing transistor is connected, and a second pole of the fourth sensing transistor is connected to the second power supply terminal through the fifth leakage preventing transistor;
  • a control electrode of the first leakage prevention transistor is connected to one of the at least one signal output terminal, a first pole of the first leakage prevention transistor and a first pole of the third sensing transistor, The second pole of the fourth leakage prevention transistor, the second pole of the fourth sensing transistor, and the first pole of the fifth leakage prevention transistor are connected, and the second pole of the first leakage prevention transistor is connected to all One of the at least one signal output terminal is connected;
  • the control electrode of the fourth leakage prevention transistor is connected to the control electrode of the third sensing transistor, and the first electrode of the fourth leakage prevention transistor is connected to the second electrode of the second sensing transistor.
  • the second pole of the fourth leakage preventing transistor is connected to the first pole of the third sensing transistor;
  • the control electrode of the fifth leakage prevention transistor is connected to the control electrode of the fourth sensing transistor, and the first electrode of the fifth leakage prevention transistor is connected to the second electrode of the fourth sensing transistor.
  • a second pole of the fifth leakage preventing transistor is connected to the second power terminal.
  • the one signal output terminal connected to the control electrode of the first leakage prevention transistor and the one signal output terminal connected to the second electrode of the first leakage prevention transistor are the same signal. Output.
  • the one signal output terminal connected to the control electrode of the first leakage prevention transistor and the one signal output terminal connected to the second electrode of the first leakage prevention transistor are different signals. Output.
  • the output circuit includes a first signal output terminal and a second signal output terminal, and the first signal output terminal is configured to provide a cascaded signal to the second shift register or to a gate connected thereto.
  • the line provides a driving signal
  • the second signal output terminal is configured to provide a driving signal to a gate line connected thereto.
  • the output circuit includes a first signal output terminal, a second signal output terminal, and a third signal output terminal.
  • the first signal output terminal is configured to provide a cascaded signal to a second shift register
  • the second signal output terminal is configured to provide a cascaded signal to the third shift register or is configured to provide a driving signal to a first gate line connected thereto;
  • the third signal output terminal is configured to provide a driving signal to a second gate line connected thereto.
  • the output circuit includes a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal.
  • the first signal output terminal is configured to provide a cascaded signal to the second shift register
  • the second signal output terminal is configured to provide a cascaded signal to the third shift register
  • the third signal output terminal is configured to provide a driving signal to a first gate line connected thereto, and
  • the fourth signal output terminal is configured to provide a driving signal to a second gate line connected thereto.
  • the present disclosure also provides a gate driving circuit, including: cascaded N shift registers, the N shift registers adopt any of the shift registers described herein;
  • the first signal input terminal of the shift register at the first and second stages is connected to the frame start signal input terminal, and the first signal input terminal of the shift register at the i-th stage is connected to the shift at the i-2 stage.
  • a signal output terminal of the register is connected, where 3 ⁇ i ⁇ N, and i is a positive integer;
  • the second signal input terminal of the shift register at the first stage is connected to the sensing start signal input terminal, and the second signal input terminal of the shift register at the j-th stage is connected to one of the j-1 shift registers.
  • Signal output terminals are connected, where 2 ⁇ j ⁇ N, and j is a positive integer;
  • the reset signal terminal of the shift register located at the N-2th to Nth stages is connected to the frame reset signal terminal, and the reset signal terminal of the kth stage is connected to a signal output terminal of the k + 3th stage shift register, where 1 ⁇ k ⁇ N-3, and k is a positive integer.
  • the shift registers at each level are connected to three corresponding signal output terminals, which are a first cascade signal output terminal, a second cascade signal output terminal, and a first drive signal output terminal;
  • the first signal input terminal of the shift register located at the i-th stage is connected to the first cascade signal output terminal of the shift register at the i-2 stage;
  • the second signal input terminal of the j-th shift register is connected to the second cascade signal output terminal of the j-1th shift register;
  • the reset signal terminal of the shift register at the k-th stage is connected to the first cascade signal output terminal of the shift register at the k + 3 stage;
  • the first driving signal output terminals of the shift registers of each stage are connected to corresponding row gate lines.
  • the present disclosure also provides a display device including any of the gate driving circuits described herein.
  • the present disclosure also provides a gate driving method.
  • the gate driving method is based on a shift register.
  • the shift register adopts any one of the shift registers described herein.
  • the gate driving method includes :
  • the sensing cascade circuit responds to the control of the second clock signal provided by the second clock signal terminal, and inputs the second input signal in the active level state provided by the second signal input terminal. Write to the sensing cascade node;
  • the display precharge reset circuit responds to the control of the first input signal provided by the first signal input terminal, and writes the first working voltage in the active level state provided by the first power terminal. Access to the pull-up node;
  • the output sub-circuit writes the driving clock signal provided by the corresponding driving clock signal terminal to the corresponding driving clock in response to the voltage control of the pull-up node in an active level state.
  • the display precharge reset circuit responds to the control of the reset signal provided by the reset signal terminal, and writes the second working voltage provided by the second power supply terminal in an inactive level state to the display.
  • a pull-up node in response to the voltage control of the pull-down node in an active-level state, the output sub-circuit writes a reset operating voltage in a non-active-level state provided by the corresponding reset power terminal to all Mentioned corresponding signal output;
  • the sensing pre-charging circuit responds to the voltage of the sensing cascade node and the control of the first clock signal provided by the first clock signal terminal to the third clock signal terminal. Writing the provided third clock signal in an active level state to the pull-up node;
  • the output sub-circuit writes the driving clock signal provided by the corresponding driving clock signal end to the corresponding driving circuit in response to the voltage control of the pull-up node in an active level state.
  • the sensing pre-charging reset circuit responds to the control of the second clock signal provided by the second clock signal terminal, and changes the first voltage provided by the second power terminal in an inactive level state.
  • Two working voltages are written to the pull-up node; the output sub-circuit responds to the voltage control of the pull-down node in an active-level state, and puts the corresponding reset power supply terminal in an inactive-level state
  • the reset operating voltage is written to the corresponding signal output terminal.
  • FIG. 1 is a schematic circuit structure diagram of a pixel circuit in an organic light emitting diode display panel.
  • FIG. 2 is an operation timing diagram of the pixel circuit shown in FIG. 1.
  • FIG. 3 is a schematic structural diagram of a gate driving sub-circuit in the related art.
  • FIG. 4 is a schematic diagram of a circuit structure of a shift register according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of a circuit structure of another shift register according to some embodiments of the present disclosure.
  • FIG. 6 is a timing diagram of a third operating voltage provided by a third power source terminal and a fourth operating voltage provided by a fourth power source terminal according to some embodiments of the present disclosure.
  • FIG. 7 is an operation timing diagram of the shift register shown in FIG. 5.
  • FIG. 8 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 10 is a timing diagram when two driving clock signal terminals in FIG. 9 provide different clock signals.
  • FIG. 11 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 12 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 14 is an operation timing diagram of the gate driving circuit shown in FIG. 13.
  • FIG. 15 is a flowchart of a gate driving method according to some embodiments of the present disclosure.
  • the transistor in the present disclosure may be a thin film transistor or a field effect transistor or other switching devices with the same characteristics.
  • a transistor generally includes three poles: a gate, a source, and a drain.
  • the source and drain in the transistor are symmetrical in structure, and the two can be interchanged as required.
  • a control electrode refers to a gate of a transistor, and one of the first and second electrodes is a source and the other is a drain.
  • the transistor can be divided into an N-type transistor and a P-type transistor; when the transistor is an N-type transistor, its on-voltage is a high-level voltage and its off-voltage is a low-level voltage; when the transistor is a P-type transistor When a transistor is used, its on-voltage is a low-level voltage and its off-voltage is a high-level voltage.
  • the “active level” in the present disclosure refers to a voltage capable of controlling the corresponding transistor to be turned on, and the “inactive level” refers to a voltage capable of controlling the corresponding transistor to be turned off; therefore, when the transistor is an N-type transistor, the effective level is Refers to high level, inactive level refers to low level; when the transistor is a P-type transistor, active level refers to low level, and inactive level refers to high level.
  • each transistor is taken as an example for example.
  • the active level refers to a high level
  • the inactive level refers to a low level.
  • TFTs thin film field effect transistors
  • GOA gate drive ICs
  • each gate driving sub-circuit in the gate driving circuit requires each gate driving sub-circuit in the gate driving circuit (consisting of a plurality of cascaded gate driving sub-circuits) not only can output control the display switching transistor during the display driving stage
  • the driving signal that is turned on can also output a driving signal that controls the conduction of the sensing switch transistor during the sensing stage, that is, the gate driving sub-circuit must have the function of outputting double pulses.
  • the existing shift register can only output a single pulse signal, the existing gate driving sub-circuit including only one shift register (Shift register) cannot meet the driving requirements.
  • a gate driving sub-circuit which has two shift registers and a signal combining circuit.
  • This gate driving sub-circuit has a function of outputting double pulses.
  • the gate driving sub-circuit includes a design scheme of two shift registers and a signal combining circuit. The number of TFTs it needs to set is large, which is not conducive to the implementation of a narrow frame.
  • a frame can be divided into two phases: the display driving phase and the sensing phase; in the display driving phase, each row of pixel units in the display panel completes the display Driving; in the sensing stage, a certain row of pixel units in the display panel completes current extraction (ie, sensing).
  • OLED organic light emitting diode
  • FIG. 1 is a schematic circuit structure diagram of a pixel circuit in an organic light emitting diode display panel
  • FIG. 2 is a working timing diagram of the pixel circuit shown in FIG. 1.
  • the pixel circuit includes a display switching transistor QTFT (its control electrode is connected to the gate line G1), a driving transistor DTFT, a sensing switching transistor STFT (its control electrode is connected to the gate line G2), and a capacitor Cst.
  • the pixel circuit includes at least the following two phases in the working process: a pixel driving phase (including a data voltage writing process) and a pixel sensing phase (including a current reading process).
  • the data voltage Vdata in the data line Data needs to be written to the pixel unit; in the pixel sensing stage, a test voltage Vsense needs to be written into the pixel unit through the data line Data, and the switching transistor STFT is sensed The electric signal at the drain of the driving transistor is read to the signal read line Sense.
  • an effective level voltage needs to be written to the gate of the sensing switch transistor STFT through the corresponding gate line G2.
  • the gate driving sub-circuit Since the duration of the data writing process is longer than the duration of the current reading process, for the gate line G2 connected to the gate of the sensing switch transistor STFT, it needs to output a double pulse signal within one frame time, which corresponds to the current
  • the pulse width of the reading process is larger than the pulse corresponding to the data writing process. Therefore, this requires that the gate driving sub-circuit has the function of outputting two pulses and two pulse widths different.
  • FIG. 3 is a schematic structural diagram of a gate driving sub-circuit in the related art.
  • a related art uses a first shift register, a second shift register, and a signal combining circuit to form a gate driving sub-circuit.
  • first shift registers in each gate driving sub-circuit are cascaded, and second shift registers in each gate driving sub-circuit are cascaded.
  • the first shift register is used for During the display driving stage, a driving signal for driving the sensing switch transistor is output.
  • the second shift register is used for outputting a driving signal for driving the sensing switch transistor during the sensing stage.
  • the signal merging circuit will be located on the same gate driver.
  • the driving signals output by the two shift registers in the circuit are combined, and a double pulse signal is output through the signal output terminal OUTPUT to meet the driving demand.
  • the present disclosure particularly provides a shift register, a gate driving circuit, a display device, and a gate driving method, which substantially avoid one or more of the problems due to the limitations and restrictions of the related art.
  • the shift register provided by the technical solution of the present disclosure has a function of outputting double pulses, which can meet the driving requirements of the pixel circuit in the pixel driving stage and the pixel sensing stage. Therefore, the shift register according to the present disclosure can be used as a gate driver alone. Circuit to use. Compared with the technical solution of the gate driving sub-circuit in the related art including two shift registers and one signal combining circuit, the technical solution of the present disclosure can greatly reduce the number of TFTs in the gate driving sub-circuit, which is beneficial to the realization of a narrow frame.
  • the present disclosure provides a shift register including an input circuit, an inversion circuit, and an output circuit.
  • the input circuit is connected to the pull-up node with the inversion circuit and the output circuit, and the output circuit and
  • the reverse circuit is connected to a pull-down node, wherein the input circuit is configured to control a voltage of the pull-up node in response to an input signal, and the reverse circuit is configured to perform a voltage control of the pull-up node.
  • Reverse processing, and outputting the voltage after the reverse processing to the pull-down node, and the output circuit is configured to continue for one frame under the control of the voltage of the pull-up node and the voltage of the pull-down node Multiple pulse signals are output in time.
  • FIG. 4 is a schematic diagram of a circuit structure of a shift register according to some embodiments of the present disclosure.
  • the shift register includes: an input circuit (which includes a display precharge reset circuit 3, a sensing cascade circuit 1, a sensing precharge reset circuit 2), and a reverse circuit 4 And output circuit.
  • the sensing cascade circuit 1 and the sensing precharge reset circuit 2 are connected to the sensing cascade node H, and the display precharge reset circuit 3, the sensing precharge reset circuit 2, and the output circuit are connected to the pull-up node PU, and the reverse circuit 4 and the output circuit are connected to the pull-down node PD.
  • the display precharge reset circuit 3 is connected to the first signal input terminal STU1, the reset signal terminal STD, the first power terminal, and the second power terminal, and is configured to respond to the first signal input during the display precharge stage. Control of the first input signal provided by the terminal STU1, writing the first working voltage in the active level state provided by the first power terminal to the pull-up node PU, and in response to the reset signal terminal STD provided in the display reset stage The control of the reset signal writes the second working voltage provided by the second power terminal in an inactive level state to the pull-up node PU.
  • the sensing cascade circuit 1 is connected to the second signal input terminal STU2 and the second clock signal terminal CLKB, and is configured to respond to the second clock provided by the second clock signal terminal CLKB during the sensing cascade stage.
  • the second input signal in the active level state provided by the second signal input terminal STU2 is written to the sensing cascade node H.
  • the sensing precharge reset circuit 2 is connected to the first clock signal terminal CLKA, the second clock signal terminal CLKB, the third clock signal terminal CLKC, and the second power terminal, and is configured to be in the sensing precharge stage.
  • the third clock signal provided by the third clock signal terminal CLKC in an active level state is written to the pull-up node PU, and in response to the control of the second clock signal provided by the second clock signal terminal CLKB in the sensing reset phase, write the second working voltage provided by the second power terminal in an inactive level state to the pull-up node PU .
  • the reverse circuit 4 is configured to reversely process the voltage of the pull-up node PU, and output the reverse-processed voltage to the pull-down node PD.
  • the output circuit is connected to at least one signal output terminal OUT, and the output circuit includes: at least one output sub-circuit 5 corresponding to the at least one signal output terminal OUT one-to-one.
  • the output sub-circuit 5 is connected to the pull-up node PU, the pull-down node PD, the corresponding signal output terminal OUT, the corresponding driving clock signal terminal CLKD, and the corresponding reset power terminal, and the output sub-circuit 5 is configured to display and sense in the display output stage.
  • the output phase responds to the voltage control of the pull-up node PU in the active level state, writes the driving clock signal provided by the corresponding driving clock signal terminal CLKD to the corresponding signal output terminal OUT, and is configured to be in the display reset phase
  • the reset operating voltage in the non-active level state provided by the corresponding reset power terminal is written to the corresponding signal output terminal OUT.
  • the number of the at least one signal output terminal OUT is 1-4. It should be noted that FIG. 4 only exemplarily illustrates one signal output terminal OUT, and this situation does not limit the technical solution of the present disclosure.
  • the display precharge reset circuit 3 and the sensing precharge reset circuit 2 can share one reverse circuit 4 and one output circuit.
  • the first shift register configured to output a driving signal for driving the display switching transistor during the display driving stage includes at least: a display precharge reset circuit 3, an inverter circuit 4 and an output circuit;
  • the second shift register is a second shift register that outputs a driving signal for driving the sensing switch transistor during the sensing stage.
  • the second shift register includes at least: a sensing cascade circuit 1, a sensing precharge reset circuit 2, a reverse circuit 4 and a Output circuit.
  • the existing gate drive sub-circuit includes at least: a display precharge reset circuit 3, a sensing cascade circuit 1, a sensing precharge reset circuit 2, two reverse circuits 4, and two outputs Circuit and a signal combining circuit.
  • the shift register provided by the present disclosure can constitute a gate driving sub-circuit by itself. Therefore, the gate driving sub-circuit in the present disclosure includes: a display precharge reset circuit 3, a sensing cascade circuit 1, A sensing precharge reset circuit 2, a reverse circuit 4, and an output circuit. It can be seen that, compared with the existing gate driving sub-circuit, the technical solution of the present disclosure can save one inverting circuit 4 and one output circuit by sharing the inverting circuit 4 and the output circuit; at the same time, the present invention There is no need to provide a signal combining circuit in the publicly provided shift register.
  • the gate driving subcircuit composed of the shift register provided by the present disclosure can omit an inverting circuit 4, an output circuit and a signal combination. Circuit, the technical solution of the present disclosure can reduce the number of TFTs in the gate driving sub-circuit, which is beneficial to the realization of a narrow frame.
  • FIG. 5 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure.
  • the shift register shown in FIG. 5 is a specific configuration of a shift register based on the shift register shown in FIG. 4.
  • the display precharge reset circuit 3 includes a first display transistor M1 and a second display transistor M2.
  • the control electrode of the first display transistor M1 is connected to the first signal input terminal STU1, the first electrode of the first display transistor M1 is connected to the first power terminal, and the second electrode of the first display transistor M1 is connected to the pull-up node PU;
  • the control electrode of the two display transistors M2 is connected to the reset signal terminal STD, the first electrode of the second display transistor M2 is connected to the pull-up node PU, and the second electrode of the second display transistor M2 is connected to the second power terminal.
  • the inversion circuit 4 includes a third display transistor M3, a fourth display transistor M4, and a fifth display transistor M5.
  • the control electrode of the third display transistor M3 is connected to the third power terminal, the first electrode of the third display transistor M3 is connected to the third power terminal, and the second electrode of the third display transistor M3 is connected to the pull-down node PD.
  • the control electrode of the fourth display transistor M4 is connected to the fourth power supply terminal, the first electrode of the fourth display transistor M4 is connected to the fourth power supply terminal, and the second electrode of the fourth display transistor M4 is connected to the pull-down node PD.
  • the control electrode of the fifth display transistor M5 is connected to the pull-up node PU, the first electrode of the fifth display transistor M5 is connected to the pull-down node PD, and the second electrode of the fifth display transistor M5 is connected to the second power terminal.
  • FIG. 6 is a timing diagram of a third operating voltage and a fourth operating voltage in some embodiments according to the present disclosure.
  • the third power supply terminal provides a third operating voltage
  • the fourth power supply terminal provides a fourth operating voltage.
  • the flat state and the inactive level state are switched once, and at any time one of the third working voltage and the fourth working voltage is in an active level state, and the other is in an inactive level state.
  • the range of the preset period T includes: 1s to 3s.
  • the present disclosure is not limited to this, and the value of the preset period T may be designed and adjusted according to actual needs.
  • the inverting circuit 4 includes the third display transistor M3, the fourth display transistor M4, and the fifth display transistor M5, and the third operating voltage and the fourth operating voltage are in an active level state every preset period T and Switch between inactive level states once. Since the third operating voltage and the fourth operating voltage are switched between the active level state and the inactive level state at intervals, the first poles of the third display transistor M3 and the fourth display transistor M4 are not changed. Always in a constant voltage state, which can effectively prevent the third display transistor M3 and the fourth display transistor M4 from shifting their threshold voltage due to constant voltage, thereby ensuring the electrical properties of the third display transistor M3 and the fourth display transistor M4. Stable characteristics.
  • the inverting circuit 4 may also adopt other circuit structures capable of performing 180 ° inverse processing of the voltage signal, and specific cases are not described here one by one.
  • the output sub-circuit 5 includes a sixth display transistor M6 and a seventh display transistor M7.
  • the control electrode of the sixth display transistor M6 is connected to the pull-up node PU, the first electrode of the sixth display transistor M6 is connected to the driving clock signal terminal CLKD, and the second electrode of the sixth display transistor M6 is connected to the signal output terminal OUT.
  • the control electrode of the seventh display transistor M7 is connected to the pull-down node PD, the first electrode of the seventh display transistor M7 is connected to the corresponding signal output terminal OUT, and the second electrode of the seventh display transistor M7 is connected to the reset power terminal.
  • the shift register further includes: a first capacitor C1, a first terminal of the first capacitor C1 is connected to the pull-up node PU, and a second terminal of the first capacitor C1 is connected to the signal output terminal OUT.
  • the first capacitor C1 may be configured to ensure that the voltage of the pull-up node PU is always in an active level state during the display output stage and the sensing output stage.
  • the sensing cascade circuit 1 includes: a first sensing transistor T1; a control electrode of the first sensing transistor T1 is connected to a second clock signal terminal CLKB, and a first electrode of the first sensing transistor T1 and The second signal input terminal STU2 is connected, and the second pole of the first sensing transistor T1 is connected to the sensing cascade node H.
  • the shift register further includes: a second capacitor C2, a first terminal of the second capacitor C2 is connected to the sensing cascade node H, a second terminal of the second capacitor C2 is connected to a fifth power source terminal, The second capacitor C2 is configured to maintain a stable voltage of the sensing cascade node H when the first sensing transistor T1 is in an off state.
  • the sensing precharge reset circuit 2 includes a second sensing transistor T2, a third sensing transistor T3, and a fourth sensing transistor T4.
  • the control electrode of the second sensing transistor T2 is connected to the sensing cascade node H, the first electrode of the second sensing transistor T2 is connected to the third clock signal terminal CLKC, and the second electrode of the second sensing transistor T2 is connected to the third The first pole of the sense transistor T3 is connected.
  • the control electrode of the third sensing transistor T3 is connected to the first clock signal terminal CLKA, and the second electrode of the third sensing transistor T3 is connected to the pull-up node PU.
  • the control electrode of the fourth sensing transistor T4 is connected to the second clock signal terminal CLKB, the first electrode of the fourth sensing transistor T4 is connected to the pull-up node PU, and the second electrode of the fourth sensing transistor T4 is connected to the second power terminal. connection.
  • the working process of the shift register shown in FIG. 5 will be described in detail with reference to the drawings.
  • the first working voltage provided by the first power terminal is a high-level working voltage VGH
  • the second working voltage provided by the second power terminal is a low-level working voltage VGL1
  • the third working voltage provided by the third power terminal is high-voltage.
  • Flat operating voltage VGH the fourth operating voltage provided by the fourth power supply terminal is a low-level operating voltage VGL
  • the fifth operating voltage provided by the fifth power supply terminal is a low-level operating voltage VGL2
  • the reset operating voltage provided by the reset power terminal is Low-level operating voltage VGL2.
  • FIG. 7 is an operation timing diagram of the shift register shown in FIG. 5. The following describes the working process of the shift register shown in FIG. 5 in detail with reference to FIG. 7. As shown in FIG. 7, the working process of the shift register includes the following 7 stages t0 to t6.
  • the first input signal provided by the first signal input terminal STU1 is in a low-level state
  • the second input signal provided by the second signal input terminal STU2 is in the In a high state
  • the reset signal provided by the reset signal terminal STD is in a low state
  • the first clock signal provided by the first clock signal terminal CLKA is in a low state
  • the second clock signal provided by the second clock signal terminal CLKB is in In a high-level state
  • the third clock signal provided by the third clock signal terminal CLKC is in a low-level state
  • the driving clock signal provided by the driving clock signal terminal CLKD is in a high-level state.
  • the second clock signal is in a high-level state
  • the first sensing transistor T1 and the fourth sensing transistor are turned on.
  • the second input signal in the high-level state is written to the sense through the first sensing transistor T1.
  • the cascade node H is measured, the voltage of the cascade node H is sensed as a high level state, the second sensing transistor T2 is turned on, and the third clock signal can be written to the third sensing transistor T3 through the second sensing transistor T2.
  • the third sensing transistor T3 is turned off, and the third clock signal cannot be written to the pull-up node PU.
  • the fourth sensing transistor T4 is turned on, the second operating voltage VGL1 is written to the pull-up node PU through the fourth sensing transistor T4.
  • both the first input signal and the reset signal are in a low-level state, both the first display transistor M1 and the second display transistor M2 are turned off.
  • both the fifth display transistor M5 and the sixth display transistor M6 are turned off; in the inverting circuit 4, the third operating voltage VGH is written to the pull-down through the third display transistor M3 The voltage of the node PD and the pull-down node PD is high.
  • the seventh display transistor M7 is turned on, and the reset working voltage VGL2 is written to the signal output terminal OUT through the seventh display transistor M7, that is, the signal output terminal OUT outputs a low voltage.
  • Flat signal
  • the first input signal provided by the first signal input terminal STU1 is in a high-level state
  • the second input signal provided by the second signal input terminal STU2 is first in a low-level state and switched to a high-voltage state after a period of time.
  • the reset signal provided by the reset signal terminal STD is in a low state
  • the first clock signal provided by the first clock signal terminal CLKA is in a low state
  • the second clock signal provided by the second clock signal terminal CLKB is in a low power state.
  • the third clock signal provided by the third clock signal terminal CLKC is in a low-level state
  • the driving clock signal provided by the driving clock signal terminal CLKD is in a low-level state.
  • both the first sensing transistor T1 and the fourth sensing transistor T4 are turned off, the sensing cascade node H is in a floating state, and the voltage of the cascade node H is sensed The high state of the previous stage is maintained. It should be noted that, because the first sensing transistor T1 is turned off, no matter whether the second input signal is in a high-level state or a low-level state, the voltage of the sensing cascade node H will not be affected.
  • the second capacitor C2 in the present disclosure can maintain the voltage stability of the sensing cascade node H after the sensing cascade phase t0 ends and the sensing cascade node H is in a floating state; since the first clock signal is still In the low-level state, the third sensing transistor T3 remains off.
  • the first display transistor M1 Since the first input signal is in a high-level state and the reset signal is in a low-level state, the first display transistor M1 is turned on and the second display transistor M2 is turned off, and the first operating voltage VGH can be written on through the first display transistor M1 Pull the node PU, and the voltage of the pull-up node PU is high.
  • the fifth display transistor M5 and the sixth display transistor M6 are turned on, and the second operating voltage VGL1 is written to the pull-down node PD through the fifth display transistor M5.
  • the display transistor M3 is equivalent to a resistor, the voltage of the pull-down node PD is a low-level state, and the seventh display transistor M7 is turned off.
  • the driving clock signal is written to the corresponding signal output terminal OUT through the sixth display transistor M6, and because the driving clock signal is in a low-level state, the signal output terminal OUT outputs a low-level signal.
  • the first input signal provided by the first signal input terminal STU1 is in a low state
  • the second input signal provided by the second signal input terminal STU2 is in a high state and switched to a low level after a period of time.
  • the reset signal provided by the reset signal terminal STD is at a low state
  • the first clock signal provided by the first clock signal terminal CLKA is at a low state
  • the second clock signal provided by the second clock signal terminal CLKB is at a low level
  • the third clock signal provided by the third clock signal terminal CLKC is in a low-level state
  • the driving clock signal provided by the driving clock signal terminal CLKD is in a high-level state and switched to a low-level state after a period of time.
  • both the first sensing transistor T1 and the fourth sensing transistor T4 are turned off, the sensing cascade node H is in a floating state, and the voltage of the cascade node H is sensed Maintain the high state of the previous stage (the second input signal will not affect the voltage of the sensing cascade node H); because the first clock signal is still in the low state, the third sensing transistor T3 remains off .
  • both the first input signal and the reset signal are in a low-level state
  • the first display transistor M1 and the second display transistor M2 are both turned off
  • the pull-up node PU is in a floating state
  • the high-level state of the previous stage is maintained.
  • the fifth display transistor M5 and the sixth display transistor M6 remain on
  • the pull-down node PD maintains a low state (the seventh display transistor M7 is off)
  • the driving clock signal is written to the corresponding signal output through the sixth display transistor M6. Terminal OUT.
  • the driving clock signal is switched from a low state to a high state, and the signal output terminal OUT outputs a high level signal.
  • the voltage of the pull-up node PU is pulled up to a higher state.
  • VGH the voltage corresponding to each clock signal in the high-level state
  • VGL the voltage corresponding to the low-level state
  • the voltage of the PU is approximately VGH, and at the initial time of the display driving phase t2, the voltage of the pull-up node PU may be pulled up to approximately 2 ⁇ VGH.
  • the driving clock signal is switched from a high level to a low level, and the signal output terminal OUT outputs a low level signal; at the same time, under the bootstrapping effect of the first capacitor C1, the pull-up of the node PU The voltage drops to a level at the initial moment of the display driving stage t2, that is, to VGH, at this time, the pull-up node PU is still in a high-level state.
  • the first input signal provided by the first signal input terminal STU1 is at a low state
  • the second input signal provided by the second signal input terminal STU2 is at a low state
  • the reset signal provided by the reset signal terminal STD is at In a high state
  • the first clock signal provided by the first clock signal terminal CLKA is in a low state
  • the second clock signal provided by the second clock signal terminal CLKB is in a low state
  • the first clock signal provided by the third clock signal terminal CLKC is The three clock signals are in a low state
  • the driving clock signal provided by the driving clock signal terminal CLKD is first in a low state and switches to a high state after a period of time.
  • both the first sensing transistor T1 and the fourth sensing transistor T4 are turned off, the sensing cascade node H is in a floating state, and the voltage of the cascade node H is sensed The high-level state of the previous stage is maintained; since the first clock signal is still in a low-level state, the third sensing transistor T3 remains off.
  • the first display transistor M1 Since the first input signal is in a low state and the reset signal is in a high state, the first display transistor M1 is turned off and the second display transistor M2 is turned on, and the second operating voltage VGL1 can be written to the upper through the second display transistor M2 The node PU is pulled, and the voltage of the pull-up node PU is in a low state.
  • both the fifth display transistor M5 and the sixth display transistor M6 are turned off. Since the sixth display transistor M6 is turned off, the driving clock signal cannot be written to the signal output terminal OUT, and therefore it will not affect the voltage of the signal output terminal OUT.
  • the third operating voltage VGH is written to the pull-down node PD through the third display transistor M3, and the voltage of the pull-down node PD is high level.
  • the seventh display transistor M7 is turned on and the working voltage VGL2 is reset.
  • the seventh display transistor M7 writes to the signal output terminal OUT, that is, the signal output terminal OUT outputs a low-level signal.
  • the first input signal provided by the first signal input terminal STU1 is in a low state
  • the second input signal provided by the second signal input terminal STU2 is in a low state
  • the reset provided by the reset signal terminal STD is reset.
  • the signal is in a low state
  • the first clock signal provided by the first clock signal terminal CLKA is in a high state
  • the second clock signal provided by the second clock signal terminal CLKB is in a low state
  • the third clock signal terminal CLKC is provided
  • the third clock signal is in a high-level state
  • the driving clock signal provided by the driving clock signal terminal CLKD is in a low-level state.
  • both the first sensing transistor T1 and the fourth sensing transistor T4 are turned off, the sensing cascade node H is in a floating state, and the voltage of the cascade node H is sensed
  • the high-level state of the previous stage is maintained, and accordingly the second sensing transistor T2 maintains the on-state.
  • the third sensing transistor T3 is turned on, and the third clock signal in the high-level state passes the second sensing transistor T2 and the third sensing transistor in order. T3 is written to the pull-up node PU, and the voltage of the pull-up node PU is high.
  • both the first display transistor M1 and the second display transistor M2 are turned off.
  • the fifth display transistor M5 and the sixth display transistor M6 are turned on, and the second operating voltage VGL1 is written to the pull-down node PD through the fifth display transistor M5.
  • the display transistor M3 is equivalent to a resistor
  • the voltage of the pull-down node PD is a low-level state
  • the seventh display transistor M7 is turned off.
  • the driving clock signal is written to the corresponding signal output terminal OUT through the sixth display transistor M6, and because the driving clock signal is in a low level state, the signal output terminal OUT outputs a low level signal.
  • the first input signal provided by the first signal input terminal STU1 is in a low state
  • the second input signal provided by the second signal input terminal STU2 is in a low state
  • the reset signal provided by the reset signal terminal STD is In the low state
  • the first clock signal provided by the first clock signal terminal CLKA is in the low state
  • the second clock signal provided by the second clock signal terminal CLKB is in the low state
  • the third clock signal terminal CLKC is provided
  • the third clock signal is first in the high-level state and switched to the low-level state after a period of time
  • the driving clock signal provided by the driving clock signal terminal CLKD is first in the high-level state and after a period of time is in the low-level state.
  • both the first sensing transistor T1 and the fourth sensing transistor T4 are turned off, and the voltage of the sensing cascade node H maintains the high-level state of the previous stage, and the second sensing The transistor T2 remains on; since the first clock signal is in a low-level state, the third sensing transistor T3 is turned off, and the third clock signal does not affect the voltage of the pull-up node PU.
  • both the first input signal and the reset signal are in a low-level state
  • the first display transistor M1 and the second display transistor M2 are both turned off
  • the pull-up node PU is in a floating state
  • the high-level state of the previous stage is maintained.
  • the fifth display transistor M5 and the sixth display transistor M6 remain on
  • the pull-down node PD maintains a low state (the seventh display transistor M7 is off)
  • the driving clock signal is written to the corresponding signal output through the sixth display transistor M6. Terminal OUT.
  • the driving clock signal is switched from a low state to a high state, and the signal output terminal OUT outputs a high level signal.
  • the voltage of the pull-up node PU is pulled up to a higher state.
  • VGH the corresponding voltage when each clock signal is at a high level
  • VGL the corresponding voltage when it is at a low state
  • the voltage of is approximately VGH, and at the initial moment of the sensing driving phase t5, the voltage of the pull-up node PU can be pulled up to approximately 2 ⁇ VGH.
  • the driving clock signal is switched from a high level to a low level, and the signal output terminal OUT outputs a low level signal; at the same time, under the bootstrapping effect of the first capacitor C1, the pull-up of the node PU
  • the voltage drops to a level at the initial moment of the sensing driving period t5, that is, to VGH, at this time, the pull-up node PU is still in a high-level state.
  • the first input signal provided by the first signal input terminal STU1 is in a low state
  • the second input signal provided by the second signal input terminal STU2 is in a low state
  • the reset signal provided by the reset signal terminal STD is In the low state
  • the first clock signal provided by the first clock signal terminal CLKA is in the low state
  • the second clock signal provided by the second clock signal terminal CLKB is in the high state
  • the third clock signal terminal CLKC is provided
  • the third clock signal is in a low state
  • the driving clock signal provided by the driving clock signal terminal CLKD is in a low state.
  • both the first sensing transistor T1 and the fourth sensing transistor T4 are turned on, and the second input signal in the low-level state is written to the sense through the first sensing transistor T1.
  • the cascade node H is measured, the voltage of the cascade node H is sensed as a low-level state, and the second sensing transistor T2 is turned off. Since the first clock signal is in a low-level state, the third sensing transistor T3 is turned off.
  • the fourth sensing transistor M4 Since the fourth sensing transistor M4 is turned on, the second operating voltage VGL1 is written to the pull-up node PU through the fourth display transistor M4, and the voltage of the pull-up node PU is in a low-level state.
  • both the first display transistor M1 and the second display transistor M2 are turned off.
  • both the fifth display transistor M5 and the sixth display transistor M6 are turned off; in the inverting circuit 4, the third operating voltage VGH is written to the pull-down through the third display transistor M3 The voltage of the node PD and the pull-down node PD is high.
  • the seventh display transistor M7 is turned on, and the reset working voltage VGL2 is written to the signal output terminal OUT through the seventh display transistor M7, that is, the signal output terminal OUT outputs a low voltage.
  • Flat signal
  • the above-mentioned shift register can output a high-level (active-level) signal in the display driving phase and the sensing phase in one frame, respectively, to meet the driving requirements of the corresponding row of pixel units.
  • the shift register further includes: a noise reduction circuit 6, and the noise reduction circuit 6 is configured to apply a voltage to the pull-up node PU when the voltage of the pull-up node PU is in an inactive level state. Noise reduction is performed to maintain a stable voltage at the pull-up node PU.
  • the noise reduction circuit 6 includes: an eighth display transistor M8; a control electrode of the eighth display transistor M8 is connected to the pull-down node PD; a first electrode of the eighth display transistor M8 is connected to the pull-up node PU; The second electrode of the display transistor M8 is connected to a second power terminal.
  • the inverting circuit 4 and the eighth display transistor M8 can form a positive feedback loop at this time to strengthen the voltage at the pull-up node PU.
  • the reverse circuit 4 controls the voltage of the pull-down node PD in a high-level state.
  • the eighth display transistor M8 is turned on, and the second operating voltage VGL1 is displayed through the eighth display.
  • the transistor M8 is written to the pull-up node PU to strengthen the voltage of the pull-up node PU to be in a low-level state (the voltage is VGL1) to achieve the purpose of noise reduction.
  • FIG. 8 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure.
  • the shift register shown in FIG. 8 further includes: an anti-leakage circuit 7, which can be used to prevent the second display transistor M2 and the eighth display transistor.
  • M8 the third sensing transistor T3, and the fourth sensing transistor T4 generate a leakage current in the display output stage and the sensing output stage.
  • the leakage prevention circuit 7 includes a first leakage prevention transistor S1.
  • a second leakage prevention transistor S2 is provided in the leakage prevention circuit 7 in order.
  • the second electrode of the second electrode is connected to the second power terminal through the third leakage preventing transistor S3, and the first electrode of the third sensing transistor T3 is connected to the second electrode of the second sensing transistor T2 through the fourth leakage preventing transistor S4.
  • the second pole of the sensing transistor T4 is connected to the second power terminal through a fifth leakage preventing transistor S5.
  • the control pole of the first leakage prevention transistor S1 is connected to a signal output terminal OUT
  • the second pole of the first leakage prevention transistor S1 is connected to a signal output terminal OUT
  • the first pole of the first leakage prevention transistor S1 is connected to the second leakage prevention
  • the first pole of the transistor S2, the first pole of the third leakage prevention transistor S3, the second pole of the fourth leakage prevention transistor S4, and the first pole of the fifth leakage prevention transistor S5 are connected.
  • the control electrode of the second leakage prevention transistor S2 is connected to the control electrode of the second display transistor M2.
  • the first electrode of the second leakage prevention transistor S2 is connected to the second electrode of the second display transistor M2.
  • the second pole is connected to the second power terminal.
  • the control electrode of the third leakage prevention transistor S3 is connected to the control electrode of the eighth display transistor M8.
  • the first electrode of the third leakage prevention transistor S3 is connected to the second electrode of the eighth display transistor M8.
  • the second pole is connected to the second power terminal.
  • the control pole of the fourth leakage prevention transistor S4 is connected to the control pole of the third sensing transistor T3, the first pole of the fourth leakage prevention transistor S4 is connected to the second pole of the second sensing transistor T2, and the fourth leakage prevention transistor S4 Is connected to the first pole of the third sensing transistor T3.
  • the control pole of the fifth leakage prevention transistor S5 is connected to the control pole of the fourth sensing transistor T4, the first pole of the fifth leakage prevention transistor S5 is connected to the second pole of the fourth sensing transistor T4, and the fifth leakage prevention transistor S5
  • the second pole is connected to the second power terminal.
  • the working process of the shift register shown in FIG. 8 can refer to the content described with reference to FIG. 5 and FIG. 6, which will not be repeated here.
  • the working process of each transistor in the leakage prevention circuit 7 will be described in detail below.
  • the first leakage prevention transistor S1 is turned off due to the low-level signal output from the signal output terminal OUT. .
  • a high-level signal is output to the control electrode of the first leakage prevention transistor S1.
  • the first leakage prevention transistor S1 is turned on. At this time, the high-level signal (the voltage is VGH) output from the signal output terminal OUT connected to the second pole of the first leakage prevention transistor S1 will be written by the first leakage prevention transistor S1.
  • the second leakage prevention transistor S2 (the second pole of the second display transistor M2), the first pole of the third leakage prevention transistor S3 (the second pole of the eighth display transistor M8), and the fourth leakage prevention
  • the second pole of the transistor S4 (the first pole of the third sensing transistor T3) and the first pole of the fifth leakage prevention transistor S5 (the second pole of the fourth sensing transistor T4).
  • the second display transistor M2 The source-drain voltage difference between the eighth display transistor M8, the third sensing transistor T3, and the fourth sensing transistor T4 is relatively small (approximately VGH), so that the above four transistors can be prevented from being in a saturated conduction state, thereby preventing leakage.
  • the generation of current ensures the stability of the voltage at the pull-up node PU.
  • FIG. 9 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure.
  • the number of signal output terminals is two (OUT / OUT ′), and accordingly, the number of output sub-circuits 5 is two.
  • the sixth display transistors M6 / M6 'in each output sub-circuit 5 are turned on or turned off simultaneously, and the seventh display transistors M7 / M7' in each output sub-circuit 5 are turned on or turned off simultaneously.
  • the driving clock signals provided by the driving clock signal terminals CLKD / CLKD ′ connected to the two output sub-circuits 5 may be the same or different.
  • the driving clock signals provided by the driving clock signal terminals CLKD / CLKD 'connected to the two output sub-circuits 5 are the same. At this time, one of the two signal output terminals OUT / OUT' is used as a The other shift registers in the gate driving circuit provide cascade signals (see the following content), and the other is used to provide a driving signal to the gate line G2 connected to the control electrode of the sensing switch transistor STFT in the corresponding row of pixel units.
  • the load on the signal output terminal providing the driving signal can be reduced, and the shift register can be ensured to the corresponding row gate line.
  • the stability of the output drive signal by separating the signal output terminal providing the cascade signal from the signal output terminal providing the driving signal, the load on the signal output terminal providing the driving signal can be reduced, and the shift register can be ensured to the corresponding row gate line.
  • the driving clock signals provided by the driving clock signal terminals CLKD / CLKD ′ connected to the two output sub-circuits 5 are different.
  • FIG. 10 is a timing diagram when two driving clock signal terminals in FIG. 9 provide different clock signals.
  • the two driving clock signal terminals CLKD / CLKD ' provide the same driving clock signal in the display driving stage, but the driving clock signals provided in the sensing stage are different;
  • the driving clock signal provided by the driving clock signal terminal CLKD Corresponds to the driving signal required for the gate line G2 connected to the control electrode of the switching transistor STFT in the pixel unit.
  • the driving clock signal provided by the driving clock signal terminal CLKD ' corresponds to the gate line G1 connected to the control electrode of the display switching transistor QTFT. Required drive signals.
  • one of the two signal output terminals OUT / OUT '(the signal output terminal OUT in FIG. 9) is used to provide cascaded signals to other shift registers in the gate driving circuit and simultaneously to the corresponding row pixel units.
  • the gate line G2 connected to the control electrode of the sensing switching transistor STFT provides a driving signal
  • the other (the signal output terminal OUT 'in FIG. 9) is used as a gate connected to the control electrode of the display switching transistor QTFT in the corresponding row of pixel units.
  • Line G1 provides a drive signal.
  • one shift register can simultaneously provide driving signals to two gate lines connected to the pixel unit, so there is no need to additionally set a shift register for the gate line G1 connected to the control electrode of the display switching transistor QTFT. Effectively reduce the number of shift registers in the display panel, which is conducive to narrow frame design.
  • FIG. 11 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure. Different from the above embodiment, the number of signal output terminals in the embodiment shown in FIG. 11 is three (OUT / OUT ′ / OUT ”), and accordingly, the number of output sub-circuits 5 is three. Each output sub-circuit The sixth display transistor M6 / M6 '/ M6 "in the circuit 5 is turned on or off at the same time, and the seventh display transistor M7 / M7' / M7" in each output sub-circuit 5 is turned on or off at the same time.
  • one of the three signal output terminals OUT / OUT '/ OUT ” is used to provide cascaded signals to other shift registers in the gate driving circuit, and the other two are used to provide pixel units to corresponding rows.
  • the gate line G1 connected to the control electrode of the internal display switching transistor QTFT, and the gate line G2 connected to the control electrode of the sensing switching transistor STFT provide a driving signal (the driving clock signal corresponding to the driving clock signal terminal corresponding to the two signal output terminals). (See Figure 10 for the timing of operation).
  • one of the three signal output terminals OUT / OUT '/ OUT " is used to provide a driving signal to the gate line G2 connected to the control electrode of the sensing switch transistor STFT in the corresponding row of pixel units, and the other two Both are used to provide cascaded signals to other shift registers in the gate driving circuit (the driving timing of the driving clock signals in the three driving clock signal terminals CLKD can be the same).
  • FIG. 12 is a schematic circuit structure diagram of another shift register according to some embodiments of the present disclosure. Different from the above embodiment, the number of signal output terminals in the embodiment shown in FIG. 12 is four (OUT / OUT '/ OUT ”/ OUT”'), and accordingly, the number of output sub-circuits 5 is four. .
  • the sixth display transistor M6 / M6 '/ M6 "/ M6"' in each output sub-circuit 5 is turned on or off at the same time, and the seventh display transistor M7 / M7 '/ M7 "/ M7"' in each output sub-circuit 5 Turn on or off at the same time.
  • two of the four signal outputs OUT / OUT '/ OUT "/ OUT"' are used to provide cascaded signals to other shift registers in the gate drive circuit (the two signal outputs The corresponding driving clock signal in the corresponding driving clock signal terminal CLKD may be the same.)
  • the other two are used as the gate line G1 connected to the control electrode of the display switching transistor QTFT in the corresponding row pixel unit, and the control electrode of the sensing switching transistor STFT.
  • the connected gate line G2 provides a driving signal (refer to FIG. 10 for the working timing of the driving clock signal in the driving clock signal terminal CLKD corresponding to the two signal output terminals).
  • FIG. 13 is a schematic structural diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • the gate driving circuit includes: cascaded N shift registers A1 / A2 / A3 / A4, and the shift registers A1 / A2 / A3 / A4 adopt the above embodiments. Any one of the shift registers.
  • the first signal input terminal STU1 of the shift registers A1 / A2 located at the first and second stages is connected to the frame start signal input terminal STV1, and the first signal of the shift register located at the i-th stage
  • the input terminal STU1 is connected to a signal output terminal of the shift register at the i-2 stage, where 3 ⁇ i ⁇ N, and i is a positive integer.
  • the second signal input terminal STU2 of the shift register A1 in the first stage is connected to the sensing start signal input terminal STV2, and the second signal input terminal STU2 of the shift register in the j stage is connected to A signal output terminal of the j-1 stage shift register is connected, where 2 ⁇ j ⁇ N, and j is a positive integer.
  • the reset signal terminal STD of the shift register located at the N-2th stage to the Nth stage is connected to the frame reset signal terminal (not shown), and the reset signal terminal STD of the kth stage is connected to the k + th stage.
  • a signal output terminal of the 3-stage shift register is connected, where 1 ⁇ k ⁇ N-3, and k is a positive integer.
  • the first clock signal terminal CLKA to the third clock signal terminal CLKC of the shift register in the gate driving circuit three corresponding clock signal lines CK1 / CK2 / CK3 can be set.
  • the first clock signal terminal CLKA of each shift register is connected to the first clock signal line CK1, and the second clock signal terminal CLKB of the shift register located at the odd-numbered stage is connected to the second clock signal line CK2.
  • the third clock signal terminal CLKC of the bit register is connected to the third clock signal line CK3, and the second clock signal terminal CLKB of the shift register located at the even-numbered stage is connected to the third clock signal line CK3.
  • the three clock signal terminal CLKC is connected to the second clock signal line CK2.
  • the drive clock signal terminal CLKD of the shift register at the 4m-3 stage is connected to the first drive clock signal line CKD1, and the drive clock signal terminal CLKD of the shift register at the 4m-2 stage is connected to the second drive clock signal.
  • the line CKD2 is connected, and the driving clock signal terminal CLKD of the shift register at the 4m-1 stage is connected to the third driving clock signal line CKD3.
  • the driving clock signal terminal CLKD of the shift register at the 4m stage is connected to the fourth driving clock signal.
  • Line CKD4 is connected, 1 ⁇ m ⁇ N, and m is a positive integer.
  • three levels of shift registers A1 / A2 / A3 / A4 are connected to corresponding three signal output terminals CR1 / CR2 / OUT, which are respectively the first cascaded signal output terminal CR1 (used as a gate drive).
  • the other shift registers in the circuit provide cascaded signals), the second cascaded signal output terminal CR2 (for providing cascaded signals to other shift registers in the gate drive circuit), and the first drive signal output terminal OUT (for It is used to provide a driving signal to the gate line G2 connected to the control electrode of the sensing switch transistor STFT in the corresponding pixel unit); wherein the first signal input terminal STU1 of the shift register located at the i-th stage and the i-2 stage The first cascade signal output terminal CR1 of the shift register is connected; the second signal input terminal STU2 of the shift register located at the j-th stage is connected to the second cascade signal output terminal CR2 of the j-1 shift register; The reset signal terminal STD in the k-th stage shift register is connected to the first cascade signal output terminal CR1 in the k + 3-th stage shift register.
  • the first driving signal output terminals OUT of the shift registers of each stage are connected to the corresponding row gate lines Gate1 / Gate2 / Gate3
  • the low-level operating voltage VGL2 provided by the second power supply terminal connected to the output sub-circuit 5 corresponding to the second cascade signal output terminal CR2 is greater than that of the second clock signal line (third clock signal line).
  • the corresponding voltage VGL1 in the level state At this time, it can be ensured that when the control electrode of the first sensing transistor T1 in each shift register is at VGL1, the gate-source voltage difference of the first sensing transistor T1 is always less than 0, and the first sensing transistor T1 will not be turned on incorrectly. phenomenon.
  • FIG. 14 is an operation timing diagram of the gate driving circuit shown in FIG. 13.
  • the shift registers A1 / A2 / A3 / A4 at each level sequentially output driving signals to the corresponding row gate lines Gate1 / Gate2 / Gate3 / Gate4 for display panel to perform.
  • the overlapping ratio (Overlap) of the driving signals of the adjacent row gate lines can be controlled.
  • the present disclosure also provides a display device.
  • the display device includes: a gate driving circuit, and the gate driving circuit may adopt any one of the gate driving circuits described herein.
  • FIG. 15 is a flowchart of a gate driving method according to some embodiments of the present disclosure.
  • the gate driving method is based on a shift register that employs any of the shift registers described herein. As shown in FIG. 15, the gate driving method may include steps S0 to S6.
  • step S0 in the sensing cascade stage, the sensing cascade circuit responds to the control of the second clock signal provided by the second clock signal terminal, and inputs the second input signal provided by the second signal input terminal in a valid level state. Write to the sensing cascade node.
  • step S1 in the display precharge stage, the display precharge reset circuit responds to the control of the first input signal provided by the first signal input terminal, and writes the first working voltage provided by the first power terminal in an active level state. Enter the pull-up node.
  • step S2 in the display output stage, the output sub-circuit responds to the voltage control of the pull-up node in the active level state, and writes the driving clock signal provided by the driving clock signal terminal to the corresponding signal output terminal.
  • step S3 in the display reset phase, the display precharge reset circuit responds to the control of the reset signal provided by the reset signal terminal, and writes the second working voltage provided by the second power terminal in an inactive level state to the pull-up node. ;
  • the output sub-circuit responds to the voltage control of the pull-down node in the active level state, and writes the reset operating voltage in the non-active level state provided by the reset power terminal to the signal output terminal.
  • step S4 in the sensing pre-charging phase, the sensing pre-charging circuit responds to the control of the voltage of the cascade node and the control of the first clock signal provided by the first clock signal terminal, and makes the third clock signal terminal effective.
  • the third clock signal in the level state is written to the pull-up node.
  • step S5 in the sensing output phase, the output sub-circuit writes the driving clock signal provided by the driving clock signal terminal to the corresponding signal output terminal in response to the voltage control of the pull-up node in the active level state.
  • step S6 in the sensing reset phase, the sensing pre-charging reset circuit responds to the control of the second clock signal provided by the second clock signal terminal, and switches the second work provided by the second power terminal in an inactive level state.
  • the voltage is written to the pull-up node; the output subcircuit responds to the voltage control of the pull-down node in the active level state, and writes the reset operating voltage in the non-active level state provided by the reset power terminal to the signal output terminal.

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Abstract

本申请提供了移位寄存器、栅极驱动电路、显示装置和栅极驱动方法。移位寄存器包括：输入电路、反向电路和输出电路。所述输入电路与所述反向电路和所述输出电路连接于上拉节点，所述输出电路与所述反向电路连接于下拉节点。所述输入电路配置为响应于输入信号，对所述上拉节点的电压进行控制。所述反向电路配置为将所述上拉节点的电压进行反向处理，并将反向处理后的电压输出至所述下拉节点。所述输出电路配置为在所述上拉节点的电压和所述下拉节点的电压的控制下，在一帧画面的持续时间内输出多脉冲信号。

Description

移位寄存器、栅极驱动电路、显示装置和栅极驱动方法
相关申请的交叉引用
本申请要求于2018年8月1日提交的中国专利申请No.201810862311.7的优先权，其全部内容以引用方式并入本文。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器、栅极驱动电路、显示装置和栅极驱动方法。
背景技术
为了实现显示装置的窄边框化，开发了集成在阵列基板上的栅极驱动电路(即，GOA(Gate driver-on-array)电路)。所述栅极驱动电路包括级联的多级移位寄存器，用于产生多个驱动信号，以通过多条栅线进行逐行扫描。这是驱动显示面板中的基于薄膜晶体管的像素阵列以在显示面板上一个接一个地显示图像帧的有效方式。
发明内容
一方面，本公开提供了一种移位寄存器，包括输入电路、反向电路和输出电路，所述输入电路与所述反向电路和所述输出电路连接于上拉节点，所述输出电路与所述反向电路连接于下拉节点，其中，所述输入电路配置为响应于输入信号，对所述上拉节点的电压进行控制，所述反向电路配置为将所述上拉节点的电压进行反向处理，并将反向处理后的电压输出至所述下拉节点，所述输出电路配置为在所述上拉节点的电压和所述下拉节点的电压的控制下，在一帧画面的持续时间内输出多脉冲信号。
在一些实施例中，所述输入电路包括：显示预充复位电路、感测级联电路和感测预充复位电路；
所述感测级联电路与所述感测预充复位电路连接于感测级联节点，所述显示预充复位电路、所述感测预充复位电路、所述输出电路 连接于所述上拉节点；
所述显示预充复位电路，与第一信号输入端、复位信号端、第一电源端、第二电源端连接，并且配置为在显示预充阶段响应于所述第一信号输入端所提供的第一输入信号的控制，将第一电源端提供的处于有效电平状态的第一工作电压写入至所述上拉节点，以及在显示复位阶段响应于所述复位信号端所提供的复位信号的控制，将第二电源端提供的处于非有效电平状态的第二工作电压写入至所述上拉节点；
所述感测级联电路，与第二信号输入端、第二时钟信号端连接，并且配置为在感测级联阶段响应于所述第二时钟信号端提供的第二时钟信号的控制，将第二信号输入端提供的处于有效电平状态的第二输入信号写入至所述感测级联节点；
所述感测预充复位电路，与所述第一时钟信号端、第二时钟信号端、第三时钟信号端、所述第二电源端连接，并且配置为在感测预充阶段响应于所述感测级联节点的电压、所述第一时钟信号端提供的第一时钟信号的控制，将所述第三时钟信号端提供的处于有效电平状态的第三时钟信号写入至所述上拉节点，以及在感测复位阶段响应于所述第二时钟信号端所提供的第二时钟信号的控制，将所述第二电源端提供的处于非有效电平状态的第二工作电压写入至所述上拉节点；
其中，所述输出电路连接有至少一个信号输出端，所述输出电路包括：与所述至少一个信号输出端一一对应的至少一个输出子电路，所述至少一个输出子电路中的输出子电路与所述上拉节点、所述下拉节点、对应的信号输出端、对应的驱动时钟信号端、对应的复位电源端连接，并且所述输出子电路配置为在显示输出阶段和感测输出阶段响应于处于有效电平状态的所述上拉节点的电压的控制，将所述对应的驱动时钟信号端所提供的驱动时钟信号写入至所述对应的信号输出端，以及配置为在显示复位阶段和所述感测复位阶段响应于处于有效电平状态的所述下拉节点的电压的控制，将所述对应的复位电源端提供的处于非有效电平状态的复位工作电压写入至所述对应的信号输出端。
在一些实施例中，所述显示预充复位电路包括：第一显示晶体管和第二显示晶体管；
所述第一显示晶体管的控制极与所述第一信号输入端连接，所述第一显示晶体管的第一极与所述第一电源端连接，所述第一显示晶体管的第二极与所述上拉节点连接；
所述第二显示晶体管的控制极与所述复位信号端连接，所述第二显示晶体管的第一极与所述上拉节点连接，所述第二显示晶体管的第二极与所述第二电源端连接。
在一些实施例中，所述移位寄存器还包括：防漏电电路；
所述防漏电电路包括：第一防漏电晶体管和第二防漏电晶体管，所述第二显示晶体管的第二极通过所述第二防漏电晶体管与所述第二电源端连接；
所述第一防漏电晶体管的控制极与所述至少一个信号输出端中的一个信号输出端连接，所述第一防漏电晶体管的第一极与所述第二显示晶体管的第二极、所述第二防漏电晶体管的第一极连接，所述第一防漏电晶体管的第二极与所述至少一个信号输出端中的一个信号输出端连接；
所述第二防漏电晶体管的控制极与所述第二显示晶体管的控制极连接，所述第二防漏电晶体管的第一极与所述第二显示晶体管的第二极连接，所述第二防漏电晶体管的第二极与所述第二电源端连接。
在一些实施例中，所述反向电路包括：第三显示晶体管、第四显示晶体管和第五显示晶体管；
所述第三显示晶体管的控制极与第三电源端连接，所述第三显示晶体管的第一极与所述第三电源端连接，所述第三显示晶体管的第二极与所述下拉节点连接；
所述第四显示晶体管的控制极与第四电源端连接，所述第四显示晶体管的第一极与所述第四电源端连接，所述第四显示晶体管的第二极与所述下拉节点连接；
所述第五显示晶体管的控制极与所述上拉节点连接，所述第五显示晶体管的第一极与所述下拉节点连接，所述第五显示晶体管的第 二极与所述第二电源端连接；
所述第三电源端提供的第三工作电压和所述第四电源端提供的第四工作电压均每隔预设周期在有效电平状态和非有效电平状态之间切换一次，且在任意时刻所述第三工作电压和所述第四工作电压中的一者处于有效电平状态，另一者处于非有效电平状态。
在一些实施例中，所述输出子电路包括：第六显示晶体管和第七显示晶体管；
所述第六显示晶体管的控制极与所述上拉节点连接，所述第六显示晶体管的第一极与所述对应的驱动时钟信号端连接，所述第六显示晶体管的第二极与所述对应的信号输出端连接；
所述第七显示晶体管的控制极与所述下拉节点连接，所述第七显示晶体管的第一极与所述对应的信号输出端连接，所述第七显示晶体管的第二极与所述对应的复位电源端连接。
在一些实施例中，所述移位寄存器还包括：第一电容器；
所述第一电容器的第一端与所述上拉节点连接，所述第一电容器的第二端与所述至少一个信号输出端中的信号输出端连接。
在一些实施例中，所述至少一个信号输出端的数量为1～4个。
在一些实施例中，所述移位寄存器还包括：降噪电路，所述降噪电路包括：第八显示晶体管；
所述第八显示晶体管的控制极与所述下拉节点连接，所述第八显示晶体管的第一极与所述上拉节点连接，所述第八显示晶体管的第二极与所述第二电源端连接。
在一些实施例中，所述移位寄存器还包括：防漏电电路；
所述防漏电电路包括：第一防漏电晶体管和第三防漏电晶体管，所述第八显示晶体管的第二极通过所述第三防漏电晶体管与所述第二电源端连接；
所述第一防漏电晶体管的控制极与所述至少一个信号输出端中的一个信号输出端连接，所述第一防漏电晶体管的第一极与所述第八显示晶体管的第二极、所述第三防漏电晶体管的第一极连接，所述第一防漏电晶体管的第二极与所述至少一个信号输出端中的一个信号 输出端连接；
所述第三防漏电晶体管的控制极与所述第八显示晶体管的控制极连接，所述第三防漏电晶体管的第一极与所述第八显示晶体管的第二极连接，所述第三防漏电晶体管的第二极与所述第二电源端连接。
在一些实施例中，所述感测级联电路包括：第一感测晶体管；
所述第一感测晶体管的控制极与所述第二时钟信号端连接，所述第一感测晶体管的第一极与所述第二信号输入端连接，所述第一感测晶体管的第二极与所述感测级联节点连接。
在一些实施例中，所述移位寄存器还包括：第二电容器；
所述第二电容器的第一端与所述感测级联节点连接，所述第二电容器的第二端与第五电源端连接。
在一些实施例中，所述感测预充复位电路包括：第二感测晶体管、第三感测晶体管和第四感测晶体管；
所述第二感测晶体管的控制极与所述感测级联节点连接，所述第二感测晶体管的第一极与所述第三时钟信号端连接，所述第二感测晶体管的第二极与所述第三感测晶体管的第一极连接；
所述第三感测晶体管的控制极与所述第一时钟信号端连接，所述第三感测晶体管的第二极与所述上拉节点连接；
所述第四感测晶体管的控制极与所述第二时钟信号端连接，所述第四感测晶体管的第一极与所述上拉节点连接，所述第四感测晶体管的第二极与所述第二电源端连接。
在一些实施例中，所述移位寄存器还包括：防漏电电路；
所述防漏电路包括：第一防漏电晶体管、第四防漏电晶体管和第五防漏电晶体管，所述第三感测晶体管的第一极通过所述第四防漏电晶体管与所述第二感测晶体管的第二极连接，所述第四感测晶体管的第二极通过所述第五防漏电晶体管与所述第二电源端连接；
所述第一防漏电晶体管的控制极与所述至少一个信号输出端中的一个信号输出端连接，所述第一防漏电晶体管的第一极与所述第三感测晶体管的第一极、所述第四防漏电晶体管的第二极、所述第四感测晶体管的第二极、所述第五防漏电晶体管的第一极连接，所述第一 防漏电晶体管的第二极与所述至少一个信号输出端中的一个信号输出端连接；
所述第四防漏电晶体管的控制极与所述第三感测晶体管的控制极连接，所述第四防漏电晶体管的第一极与所述第二感测晶体管的第二极连接，所述第四防漏电晶体管的第二极与所述第三感测晶体管的第一极连接；
所述第五防漏电晶体管的控制极与所述第四感测晶体管的控制极连接，所述第五防漏电晶体管的第一极与所述第四感测晶体管的第二极连接，所述第五防漏电晶体管的第二极与所述第二电源端连接。
在一些实施例中，与所述第一防漏电晶体管的控制极连接的所述一个信号输出端和与所述第一防漏电晶体管的第二极连接的所述一个信号输出端是同一个信号输出端。
在一些实施例中，与所述第一防漏电晶体管的控制极连接的所述一个信号输出端和与所述第一防漏电晶体管的第二极连接的所述一个信号输出端是不同的信号输出端。
在一些实施例中，所述输出电路包括第一信号输出端和第二信号输出端，所述第一信号输出端配置为向第二移位寄存器提供级联信号或者配置为向与其连接的栅线提供驱动信号，并且所述第二信号输出端配置为向与其连接的栅线提供驱动信号。
在一些实施例中，所述输出电路包括第一信号输出端、第二信号输出端和第三信号输出端，
所述第一信号输出端配置为向第二移位寄存器提供级联信号；
所述第二信号输出端配置为向第三移位寄存器提供级联信号或者配置为向与其连接的第一栅线提供驱动信号；并且
所述第三信号输出端配置为向与其连接的第二栅线提供驱动信号。
在一些实施例中，所述输出电路包括第一信号输出端、第二信号输出端、第三信号输出端和第四信号输出端，
所述第一信号输出端配置为向第二移位寄存器提供级联信号，
所述第二信号输出端配置为向第三移位寄存器提供级联信号，
所述第三信号输出端配置为向与其连接的第一栅线提供驱动信号，并且
所述第四信号输出端配置为向与其连接的第二栅线提供驱动信号。
另一方面，本公开还提供了一种栅极驱动电路，包括：级联的N个移位寄存器，所述N个移位寄存器采用本文所述的任一移位寄存器；
位于第1级和第2级的移位寄存器的第一信号输入端与帧起始信号输入端连接，位于第i级的移位寄存器的第一信号输入端与位于第i-2级移位寄存器的一个信号输出端连接，其中3≤i≤N，且i为正整数；
位于第1级的移位寄存器的第二信号输入端与感测起始信号输入端连接，位于第j级的移位寄存器的第二信号输入端与位于第j-1级移位寄存器的一个信号输出端连接，其中2≤j≤N，且j为正整数；
位于第N-2级至第N的移位寄存器的复位信号端与帧复位信号端连接，位于第k级的复位信号端与位于第k+3级移位寄存器的一个信号输出端连接，其中1≤k≤N-3，且k为正整数。
在一些实施例中，各级所述移位寄存器连接有对应的三个信号输出端，分别为第一级联信号输出端、第二级联信号输出端和第一驱动信号输出端；
其中，位于第i级的移位寄存器的第一信号输入端与位于第i-2级移位寄存器的第一级联信号输出端连接；
位于第j级的移位寄存器的第二信号输入端与位于第j-1级移位寄存器的第二级联信号输出端连接；
位于第k级的移位寄存器的复位信号端与位于第k+3级移位寄存器的第一级联信号输出端连接；
各级移位寄存器的所述第一驱动信号输出端与对应行栅线连接。
另一方面，本公开还提供了一种显示装置，包括本文所述的任一栅极驱动电路。
另一方面，本公开还提供了一种栅极驱动方法，所述栅极驱动方法基于移位寄存器，所述移位寄存器采用本文所述的任一移位寄存 器，所述栅极驱动方法包括：
在感测级联阶段，所述感测级联电路响应于所述第二时钟信号端提供的第二时钟信号的控制，将第二信号输入端提供的处于有效电平状态的第二输入信号写入至所述感测级联节点；
在显示预充阶段，所述显示预充复位电路响应于所述第一信号输入端所提供的第一输入信号的控制，将第一电源端提供的处于有效电平状态的第一工作电压写入至所述上拉节点；
在显示输出阶段，所述输出子电路响应于处于有效电平状态的所述上拉节点的电压的控制，将所述对应的驱动时钟信号端所提供的驱动时钟信号写入至所述对应的信号输出端；
在显示复位阶段，所述显示预充复位电路响应于所述复位信号端所提供的复位信号的控制，将第二电源端提供的处于非有效电平状态的第二工作电压写入至所述上拉节点；所述输出子电路响应于处于有效电平状态的所述下拉节点的电压的控制，将所述对应的复位电源端提供的处于非有效电平状态的复位工作电压写入至所述对应的信号输出端；
在感测预充阶段，所述感测预充电路响应于所述感测级联节点的电压、所述第一时钟信号端提供的第一时钟信号的控制，将所述第三时钟信号端提供的处于有效电平状态的第三时钟信号写入至所述上拉节点；
在感测输出阶段，所述输出子电路响应于处于有效电平状态的所述上拉节点的电压的控制，将所述对应的驱动时钟信号端所提供的驱动时钟信号写入至所述对应的信号输出端；
在感测复位阶段，所述感测预充复位电路响应于所述第二时钟信号端所提供的第二时钟信号的控制，将所述第二电源端提供的处于非有效电平状态的第二工作电压写入至所述上拉节点；所述输出子电路响应于处于有效电平状态的所述下拉节点的电压的控制，将所述对应的复位电源端提供的处于非有效电平状态的复位工作电压写入至所述对应的信号输出端。
附图说明
图1为有机发光二极管显示面板内的像素电路的电路结构示意图。
图2为图1所示像素电路的工作时序图。
图3为相关技术中的一种栅极驱动子电路的结构示意图。
图4为根据本公开的一些实施例的一种移位寄存器的电路结构示意图。
图5为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。
图6为根据本公开的一些实施例的第三电源端提供的第三工作电压和第四电源端提供的第四工作电压的时序图。
图7为图5所示移位寄存器的工作时序图。
图8为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。
图9为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。
图10为图9中两个驱动时钟信号端提供不同时钟信号时的时序图。
图11为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。
图12为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。
图13为根据本公开的一些实施例的一种栅极驱动电路的结构示意图。
图14为图13所示栅极驱动电路的工作时序图。
图15为根据本公开的一些实施例的一种栅极驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的移位寄存器、栅极驱动电路、显示装置和栅极 驱动方法进行详细描述。
需要说明的是，本公开中的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。晶体管一般包括三个极：栅极、源极和漏极，晶体管中的源极和漏极在结构上是对称的，根据需要两者是可以互换的。在本公开中，控制极是指晶体管的栅极，第一极和第二极中的一者为源极，另一者为漏极。
此外，按照晶体管特性，可将晶体管分为N型晶体管和P型晶体管；当晶体管为N型晶体管时，其导通电压为高电平电压，截止电压为低电平电压；当晶体管为P型晶体管时，其导通电压为低电平电压，截止电压为高电平电压。本公开中的“有效电平”是指能够控制相应晶体管导通的电压，“非有效电平”是指能够控制相应晶体管截止的电压；因此，当晶体管为N型晶体管时，有效电平是指高电平，非有效电平是指低电平；当晶体管为P型晶体管时，有效电平是指低电平，非有效电平是指高电平。
在下面各实施例的描述中，以各晶体管均为N型晶体管为例进行示例性说明。此时，有效电平是指高电平，非有效电平是指低电平。本领域技术人员应该知晓的是，下述实施例中的各晶体管还可替换为P型晶体管，而不脱离本公开的精神和范围。
在相关技术中，采用GOA技术将薄膜场效应晶体管(Thin Film Transistor，简称TFT)集成在阵列基板上，用以对显示面板中的栅线进行扫描驱动，从而可以省掉栅极驱动IC(集成电路)，有利于窄边框的实现。
对于具有外部补偿功能的显示面板而言，其需要栅极驱动电路(由级联的多个栅极驱动子电路构成)中的各栅极驱动子电路不仅能在显示驱动阶段输出控制显示开关晶体管导通的驱动信号，还能在感测阶段输出控制感测开关晶体管导通的驱动信号，即栅极驱动子电路需具备输出双脉冲的功能。然而，由于现有的移位寄存器只能输出单脉冲信号，因此仅包括一个移位寄存器(Shift Register)的现有的栅极驱动子电路无法满足驱动需求。
相关技术中，还提出了一种栅极驱动子电路，其具有两个移位 寄存器和一个信号合并电路。该栅极驱动子电路具备输出双脉冲的功能。然而，栅极驱动子电路包括两个移位寄存器和一个信号合并电路的设计方案，其所需要设置的TFT的数量较多，不利于窄边框实现。
对于具有外部补偿功能的有机发光二极管(OLED)显示面板而言，一帧画面可划分为两个阶段：显示驱动阶段和感测阶段；在显示驱动阶段中，显示面板中的各行像素单元完成显示驱动；在感测阶段，显示面板中的某一行像素单元完成电流抽取(即感测)。
图1为有机发光二极管显示面板内的像素电路的电路结构示意图，图2为图1所示像素电路的工作时序图。如图1和图2所示，该像素电路包括显示开关晶体管QTFT(其控制极连栅线G1)、驱动晶体管DTFT、感测开关晶体管STFT(其控制极连栅线G2)和一个电容器Cst。在该像素电路仅需外部补偿时，该像素电路在工作过程中至少包括如下两个阶段：像素驱动阶段(包括数据电压写入过程)和像素感测阶段(包括电流读取过程)。
在像素驱动阶段，需要将数据线Data中的数据电压Vdata写入至像素单元；在像素感测阶段，需要通过数据线Data将一个测试电压Vsense写入至像素单元，并通过感测开关晶体管STFT将驱动晶体管的漏极处的电信号读取至信号读取线Sense。其中，在数据写入过程和电流读取过程中，均需要通过对应的栅线G2向感测开关晶体管STFT的栅极写入有效电平电压。
需要说明的是，对OLED显示面板中的像素单元进行外部补偿，其过程属于本领域的常规技术，具体补偿过程和原理，此处不再赘述。
由于数据写入过程的时长大于电流读取过程的时长，因此对于连接感测开关晶体管STFT的栅极的栅线G2而言，其需要在一帧时间内输出一个双脉冲信号，且对应于电流读取过程的脉冲宽度大于对应于数据写入过程的脉冲。因此，这就要求栅极驱动子电路具有输出双脉冲且两个脉冲宽度不同的功能。
图3为相关技术中的一种栅极驱动子电路的结构示意图。如图3所示，为实现栅极驱动子电路能够输出双脉冲信号，相关技术中利用一个第一移位寄存器、一个第二移位寄存器和一个信号合并电路以构 成一个栅极驱动子电路。在栅极驱动电路中，各栅极驱动子电路内的第一移位寄存器之间级联，各栅极驱动子电路内的第二移位寄存器之间级联，第一移位寄存器用于在显示驱动阶段输出用以驱动感测开关晶体管的驱动信号，第二移位寄存器用于在感测阶段输出用以驱动感测开关晶体管的驱动信号，信号合并电路将与其位于同一栅极驱动子电路内的两个移位寄存器所输出的驱动信号进行合并，并通过信号输出端OUTPUT输出一个双脉冲信号，以满足驱动需求。
上述由两个移位寄存器和一个信号合并电路以构成栅极驱动子电路的技术方案，虽能满足驱动需求，但是其结构复杂且所需设置的晶体管数量较多，不利于窄边框设计。
因此，本公开特别提供了移位寄存器、栅极驱动电路、显示装置和栅极驱动方法，其实质上避免了由于相关技术的局限和限制所导致的问题中的一个或多个。
本公开的技术方案提供的移位寄存器具备输出双脉冲的功能，可满足像素电路在像素驱动阶段和像素感测阶段的驱动需求，因此根据本公开的移位寄存器可独自作为一个栅极驱动子电路来使用。与相关技术中栅极驱动子电路包括两个移位寄存器和一个信号合并电路技术方案相比，本公开的技术方案可大大减少栅极驱动子电路中TFT的数量，有利于窄边框的实现。
一方面，本公开提供了一种移位寄存器，包括输入电路、反向电路和输出电路，所述输入电路与所述反向电路和所述输出电路连接于上拉节点，所述输出电路与所述反向电路连接于下拉节点，其中，所述输入电路配置为响应于输入信号，对所述上拉节点的电压进行控制，所述反向电路配置为将所述上拉节点的电压进行反向处理，并将反向处理后的电压输出至所述下拉节点，所述输出电路配置为在所述上拉节点的电压和所述下拉节点的电压的控制下，在一帧画面的持续时间内输出多脉冲信号。
图4为根据本公开的一些实施例的一种移位寄存器的电路结构示意图。如图4所示，在一些实施例中，该移位寄存器包括：输入电路(其包括显示预充复位电路3、感测级联电路1、感测预充复位电 路2)、反向电路4和输出电路。感测级联电路1与感测预充复位电路2连接于感测级联节点H，显示预充复位电路3、感测预充复位电路2、输出电路连接于上拉节点PU，反向电路4和输出电路连接于下拉节点PD。
在一个实施例中，显示预充复位电路3与第一信号输入端STU1、复位信号端STD、第一电源端、第二电源端连接，并且配置为在显示预充阶段响应于第一信号输入端STU1所提供的第一输入信号的控制，将第一电源端提供的处于有效电平状态的第一工作电压写入至上拉节点PU，以及在显示复位阶段响应于复位信号端STD所提供的复位信号的控制，将第二电源端提供的处于非有效电平状态的第二工作电压写入至上拉节点PU。
在一个实施例中，感测级联电路1与第二信号输入端STU2、第二时钟信号端CLKB连接，并且配置为在感测级联阶段响应于第二时钟信号端CLKB提供的第二时钟信号的控制，将第二信号输入端STU2提供的处于有效电平状态的第二输入信号写入至感测级联节点H。
在一个实施例中，感测预充复位电路2与第一时钟信号端CLKA、第二时钟信号端CLKB、第三时钟信号端CLKC、第二电源端连接，并且配置为在感测预充阶段响应于感测级联节点H的电压、第一时钟信号端CLKA提供的第一时钟信号的控制，将第三时钟信号端CLKC提供的处于有效电平状态的第三时钟信号写入至上拉节点PU，以及在感测复位阶段响应于第二时钟信号端CLKB所提供的第二时钟信号的控制，将第二电源端提供的处于非有效电平状态的第二工作电压写入至上拉节点PU。
在一个实施例中，反向电路4配置为对上拉节点PU的电压进行反向处理，并将反向处理后的电压输出至下拉节点PD。
在一个实施例中，输出电路连接有至少一个信号输出端OUT，并且输出电路包括：与所述至少一个信号输出端OUT一一对应的至少一个输出子电路5。输出子电路5与上拉节点PU、下拉节点PD、对应的信号输出端OUT、对应的驱动时钟信号端CLKD、对应的复位电源端连接，并且输出子电路5配置为在显示输出阶段和感测输出阶段响应 于处于有效电平状态的上拉节点PU的电压的控制，将对应的驱动时钟信号端CLKD所提供的驱动时钟信号写入至对应的信号输出端OUT，以及配置为在显示复位阶段和感测复位阶段响应于处于有效电平状态的下拉节点PD的电压的控制，将对应的复位电源端提供的处于非有效电平状态的复位工作电压写入至对应的信号输出端OUT。
在一些实施例中，所述至少一个信号输出端OUT的数量为1～4个。需要说明的是，附图4仅示例性画出了1个信号输出端OUT，该情况不会对本公开的技术方案产生限制。
通过上述内容可见，在本公开中，显示预充复位电路3和感测预充复位电路2可共用一个反向电路4和共用一个输出电路。
在相关技术中，配置为在显示驱动阶段输出用以驱动显示开关晶体管的驱动信号的第一移位寄存器其至少包括：一个显示预充复位电路3、一个反向电路4和一个输出电路；配置为在感测阶段输出用以驱动感测开关晶体管的驱动信号的第二移位寄存器其至少包括：一个感测级联电路1、一个感测预充复位电路2、一个反向电路4和一个输出电路。由此可见，现有的栅极驱动子电路至少包括：一个显示预充复位电路3、一个感测级联电路1、一个感测预充复位电路2、两个反向电路4、两个输出电路和一个信号合并电路。
在本公开中，本公开提供的移位寄存器可独自构成一个栅极驱动子电路，因此本公开中的栅极驱动子电路包括：一个显示预充复位电路3、一个感测级联电路1、一个感测预充复位电路2、一个反向电路4、一个输出电路。由此可见，相较于现有的栅极驱动子电路，本公开的技术方案通过共用反向电路4和输出电路，从而可省去一个反向电路4和一个输出电路；与此同时，本公开提供的移位寄存器中无需设置信号合并电路。
由此可见，相较于相关技术提供的栅极驱动子电路，由本公开所提供的移位寄存器构成的栅极驱动子电路，其可省去一个反向电路4、一个输出电路和一个信号合并电路，因此本公开的技术方案可减少栅极驱动子电路中TFT的数量，有利于窄边框的实现。
图5为根据本公开的一些实施例中的另一种移位寄存器的电路 结构示意图。图5所示移位寄存器为基于图4所示移位寄存器的一种移位寄存器的具体配置。
在一些实施例中，显示预充复位电路3包括：第一显示晶体管M1和第二显示晶体管M2。
第一显示晶体管M1的控制极与第一信号输入端STU1连接，第一显示晶体管M1的第一极与第一电源端连接，第一显示晶体管M1的第二极与上拉节点PU连接；第二显示晶体管M2的控制极与复位信号端STD连接，第二显示晶体管M2的第一极与上拉节点PU连接，第二显示晶体管M2的第二极与第二电源端连接。
在一些实施例中，反向电路4包括：第三显示晶体管M3、第四显示晶体管M4和第五显示晶体管M5。
第三显示晶体管M3的控制极与第三电源端连接，第三显示晶体管M3的第一极与第三电源端连接，第三显示晶体管M3的第二极与下拉节点PD连接。
第四显示晶体管M4的控制极与第四电源端连接，第四显示晶体管M4的第一极与第四电源端连接，第四显示晶体管M4的第二极与下拉节点PD连接。
第五显示晶体管M5的控制极与上拉节点PU连接，第五显示晶体管M5的第一极与下拉节点PD连接，第五显示晶体管M5的第二极与第二电源端连接。
图6为根据本公开的一些实施例中的第三工作电压和第四工作电压的时序图。如图6所示，在本公开中，第三电源端提供第三工作电压，第四电源端提供第四工作电压，第三工作电压和第四工作电压均每隔预设周期T在有效电平状态和非有效电平状态之间切换一次，且在任意时刻第三工作电压和第四工作电压中的一者处于有效电平状态，另一者处于非有效电平状态。
在一个实施例中，预设周期T的范围包括：1s～3s。但是本公开不限于此，可根据实际需要来对预设周期T的取值进行设计、调整。
从上述描述可知，反向电路4包括第三显示晶体管M3、第四显示晶体管M4和第五显示晶体管M5，并且第三工作电压和第四工作电 压每隔预设周期T在有效电平状态和非有效电平状态之间切换一次。由于第三工作电压和第四工作电压每隔一段时间便在有效电平状态和非有效电平状态之间进行一次切换，因此第三显示晶体管M3和第四显示晶体管M4的第一极不会始终处于恒压状态，从而能有效防止第三显示晶体管M3和第四显示晶体管M4因受到恒压而导致自身阈值电压发生偏移，进而保证了第三显示晶体管M3和第四显示晶体管M4的电学特性的稳定。
在本公开中，反向电路4还可采用其他能够实现将电压信号进行180°反向处理的电路结构，具体情况此处不再一一举例说明。
在一实施例中，输出子电路5包括：第六显示晶体管M6和第七显示晶体管M7。
第六显示晶体管M6的控制极与上拉节点PU连接，第六显示晶体管M6的第一极与驱动时钟信号端CLKD连接，第六显示晶体管M6的第二极与信号输出端OUT连接。
第七显示晶体管M7的控制极与下拉节点PD连接，第七显示晶体管M7的第一极与对应的信号输出端OUT连接，第七显示晶体管M7的第二极与复位电源端连接。
在一些实施例中，该移位寄存器还包括：第一电容器C1，第一电容C1器的第一端与上拉节点PU连接，第一电容器C1的第二端与信号输出端OUT连接。第一电容器C1可配置为在显示输出阶段和感测输出阶段保证上拉节点PU的电压始终处于有效电平状态。
在一些实施例中，感测级联电路1包括：第一感测晶体管T1；第一感测晶体管T1的控制极与第二时钟信号端CLKB连接，第一感测晶体管T1的第一极与第二信号输入端STU2连接，第一感测晶体管T1的第二极与感测级联节点H连接。
在一些实施例中，该移位寄存器还包括：第二电容器C2，第二电容器C2的第一端与感测级联节点H连接，第二电容器C2的第二端与第五电源端连接，第二电容器C2配置为在第一感测晶体管T1处于截止状态时，维持感测级联节点H的电压的稳定。
在一些实施例中，感测预充复位电路2包括：第二感测晶体管 T2、第三感测晶体管T3和第四感测晶体管T4。
第二感测晶体管T2的控制极与感测级联节点H连接，第二感测晶体管T2的第一极与第三时钟信号端CLKC连接，第二感测晶体管T2的第二极与第三感测晶体管T3的第一极连接。
第三感测晶体管T3的控制极与第一时钟信号端CLKA连接，第三感测晶体管T3的第二极与上拉节点PU连接。
第四感测晶体管T4的控制极与第二时钟信号端CLKB连接，第四感测晶体管T4的第一极与上拉节点PU连接，第四感测晶体管T4的第二极与第二电源端连接。
下面，将结合附图来对图5所示移位寄存器的工作过程进行详细描述。假定第一电源端提供的第一工作电压为高电平工作电压VGH，第二电源端提供的第二工作电压为低电平工作电压VGL1，第三电源端提供的第三工作电压为高电平工作电压VGH，第四电源端提供的第四工作电压为低电平工作电压VGL，第五电源端提供的第五工作电压为低电平工作电压VGL2，复位电源端提供的复位工作电压为低电平工作电压VGL2。
图7为图5所示移位寄存器的工作时序图。下面参照图7对图5所示的移位寄存器的工作过程进行详细描述。如图7所示，该移位寄存器的工作过程包括如下7个阶段t0至t6。
感测级联阶段t0(位于前一帧画面的感测阶段中)，第一信号输入端STU1提供的第一输入信号处于低电平状态，第二信号输入端STU2提供的第二输入信号处于高电平状态，复位信号端STD提供的复位信号处于低电平状态，第一时钟信号端CLKA提供的第一时钟信号处于低电平状态，第二时钟信号端CLKB提供的第二时钟信号处于高电平状态，第三时钟信号端CLKC提供的第三时钟信号处于低电平状态，驱动时钟信号端CLKD提供的驱动时钟信号处于高电平状态。
由于第二时钟信号处于高电平状态，则第一感测晶体管T1和第四感测晶体管导通，此时处于高电平状态的第二输入信号通过第一感测晶体管T1写入至感测级联节点H，感测级联节点H的电压为高电平状态，第二感测晶体管T2导通，第三时钟信号可通过第二感测晶 体管T2写入至第三感测晶体管T3的第一极，但由于第一时钟信号处于低电平状态，则第三感测晶体管T3截止，第三时钟信号无法写入至上拉节点PU。又因为第四感测晶体管T4导通，则第二工作电压VGL1通过第四感测晶体管T4写入至上拉节点PU。
由于第一输入信号和复位信号均处于低电平状态，则第一显示晶体管M1和第二显示晶体管M2均截止。
由于上拉节点PU的电压处于低电平状态，则第五显示晶体管M5和第六显示晶体管M6均截止；在反向电路4内，第三工作电压VGH通过第三显示晶体管M3写入至下拉节点PD，下拉节点PD的电压为高电平状态，此时第七显示晶体管M7导通，复位工作电压VGL2通过第七显示晶体管M7写入至信号输出端OUT，即信号输出端OUT输出低电平信号。
显示预充阶段t1，第一信号输入端STU1提供的第一输入信号处于高电平状态，第二信号输入端STU2提供的第二输入信号先处于低电平状态并经过一段时间后切换至高电平状态，复位信号端STD提供的复位信号处于低电平状态，第一时钟信号端CLKA提供的第一时钟信号处于低电平状态，第二时钟信号端CLKB提供的第二时钟信号处于低电平状态，第三时钟信号端CLKC提供的第三时钟信号处于低电平状态，驱动时钟信号端CLKD提供的驱动时钟信号处于低电平状态。
由于第二时钟信号处于低电平状态，则第一感测晶体管T1和第四感测晶体管T4均截止，感测级联节点H处于浮接(Floating)状态，感测级联节点H的电压维持前一阶段的高电平状态。需要说明的是，由于第一感测晶体管T1截止，因此第二输入信号无论是处于高电平状态还是处于低电平状态，均不会对感测级联节点H的电压产生影响。
此外，本公开中的第二电容器C2可在感测级联阶段t0结束之后且感测级联节点H处于浮接状态时维持感测级联节点H的电压的稳定；由于第一时钟信号仍处于低电平状态，则第三感测晶体管T3维持截止。
由于第一输入信号处于高电平状态，复位信号处于低电平状态， 则第一显示晶体管M1导通且第二显示晶体管M2截止，第一工作电压VGH可通过第一显示晶体管M1写入至上拉节点PU，上拉节点PU的电压为高电平状态。
由于上拉节点PU的电压为高电平状态，则第五显示晶体管M5和第六显示晶体管M6导通，第二工作电压VGL1通过第五显示晶体管M5写入至下拉节点PD，此时第三显示晶体管M3等同于一个电阻，下拉节点PD的电压为低电平状态，第七显示晶体管M7截止。与此同时，驱动时钟信号通过第六显示晶体管M6写入至对应的信号输出端OUT，又由于驱动时钟信号处于低电平状态，信号输出端OUT输出低电平信号。
显示输出阶段t2，第一信号输入端STU1提供的第一输入信号处于低电平状态，第二信号输入端STU2提供的第二输入信号处于高电平状态并经过一段时间后切换至低电平状态，复位信号端STD提供的复位信号处于低电平状态，第一时钟信号端CLKA提供的第一时钟信号处于低电平状态，第二时钟信号端CLKB提供的第二时钟信号处于低电平状态，第三时钟信号端CLKC提供的第三时钟信号处于低电平状态，驱动时钟信号端CLKD提供的驱动时钟信号先处于高电平状态并经过一段时间后切换至低电平状态。
由于第二时钟信号处于低电平状态，则第一感测晶体管T1和第四感测晶体管T4均截止，感测级联节点H处于浮接(Floating)状态，感测级联节点H的电压维持前一阶段的高电平状态(第二输入信号不会对感测级联节点H的电压产生影响)；由于第一时钟信号仍处于低电平状态，则第三感测晶体管T3维持截止。
由于第一输入信号和复位信号均处于低电平状态，则第一显示晶体管M1和第二显示晶体管M2均截止，上拉节点PU处于浮接状态，并维持前一阶段的高电平状态，此时第五显示晶体管M5和第六显示晶体管M6维持导通，下拉节点PD维持低电平状态(第七显示晶体管M7截止)，驱动时钟信号通过第六显示晶体管M6写入至对应的信号输出端OUT。
在显示驱动阶段t2的初始时刻，驱动时钟信号由低电平状态切 换至高电平状态，则信号输出端OUT输出高电平信号。与此同时，在第一电容器C1的自举作用下，上拉节点PU的电压被上拉至更高状态。本实施例中，假定各时钟信号处于高电平状态时对应的电压为VGH、处于低电平状态时对应的电压为VGL(近似为0V)，则在显示预充阶段t1时，上拉节点PU的电压近似为VGH，而在显示驱动阶段t2的初始时刻时，上拉节点PU的电压可被上拉至近似2×VGH。经过一段时间后，驱动时钟信号由高电平切换至低电平状态，则信号输出端OUT输出低电平信号；与此同时，在第一电容器C1的自举作用下，上拉节点PU的电压下降至在显示驱动阶段t2的初始时刻的水平，即下降至VGH，此时上拉节点PU仍处于高电平状态。
显示复位阶段t3，第一信号输入端STU1提供的第一输入信号处于低电平状态，第二信号输入端STU2提供的第二输入信号处于低电平状态，复位信号端STD提供的复位信号处于高电平状态，第一时钟信号端CLKA提供的第一时钟信号处于低电平状态，第二时钟信号端CLKB提供的第二时钟信号处于低电平状态，第三时钟信号端CLKC提供的第三时钟信号处于低电平状态，驱动时钟信号端CLKD提供的驱动时钟信号先处于低电平状态并经过一段时间后切换至高电平状态。
由于第二时钟信号处于低电平状态，则第一感测晶体管T1和第四感测晶体管T4均截止，感测级联节点H处于浮接(Floating)状态，感测级联节点H的电压维持前一阶段的高电平状态；由于第一时钟信号仍处于低电平状态，则第三感测晶体管T3维持截止。
由于第一输入信号处于低电平状态，复位信号处于高电平状态，则第一显示晶体管M1截止且第二显示晶体管M2导通，第二工作电压VGL1可通过第二显示晶体管M2写入至上拉节点PU，上拉节点PU的电压为低电平状态。
由于上拉节点PU的电压为低电平状态，则第五显示晶体管M5和第六显示晶体管M6均截止。由于第六显示晶体管M6截止，则驱动时钟信号无法写入至信号输出端OUT，因而不会对信号输出端OUT的电压产生影响。在反向电路4内，第三工作电压VGH通过第三显示晶体管M3写入至下拉节点PD，下拉节点PD的电压为高电平状态，此 时第七显示晶体管M7导通，复位工作电压VGL2通过第七显示晶体管M7写入至信号输出端OUT，即信号输出端OUT输出低电平信号。
感测预充阶段t4，第一信号输入端STU1提供的第一输入信号处于低电平状态，第二信号输入端STU2提供的第二输入信号处于低电平状态，复位信号端STD提供的复位信号处于低电平状态，第一时钟信号端CLKA提供的第一时钟信号处于高电平状态，第二时钟信号端CLKB提供的第二时钟信号处于低电平状态，第三时钟信号端CLKC提供的第三时钟信号处于高电平状态，驱动时钟信号端CLKD提供的驱动时钟信号处于低电平状态。
由于第二时钟信号处于低电平状态，则第一感测晶体管T1和第四感测晶体管T4均截止，感测级联节点H处于浮接(Floating)状态，感测级联节点H的电压维持前一阶段的高电平状态，相应地第二感测晶体管T2维持导通状态。与此同时，由于第一时钟信号仍处于高电平状态，则第三感测晶体管T3导通，处于高电平状态的第三时钟信号依次通过第二感测晶体管T2、第三感测晶体管T3写入至上拉节点PU，上拉节点PU的电压为高电平状态。
由于第一输入信号处于低电平状态，复位信号处于低电平状态，则第一显示晶体管M1和第二显示晶体管M2均截止。
由于上拉节点PU的电压为高电平状态，则第五显示晶体管M5和第六显示晶体管M6导通，第二工作电压VGL1通过第五显示晶体管M5写入至下拉节点PD，此时第三显示晶体管M3等同于一个电阻，下拉节点PD的电压为低电平状态，第七显示晶体管M7截止。与此同时，驱动时钟信号通过第六显示晶体管M6写入至对应的信号输出端OUT，又由于驱动时钟信号处于低电平状态，则信号输出端OUT输出低电平信号。
感测输出阶段t5，第一信号输入端STU1提供的第一输入信号处于低电平状态，第二信号输入端STU2提供的第二输入信号处于低电平状态，复位信号端STD提供的复位信号处于低电平状态，第一时钟信号端CLKA提供的第一时钟信号处于低电平状态，第二时钟信号端CLKB提供的第二时钟信号处于低电平状态，第三时钟信号端CLKC提 供的第三时钟信号先处于高电平状态并经过一段时间后切换至低电平状态，驱动时钟信号端CLKD提供的驱动时钟信号先处于高电平状态并经过一段时间后处于低电平状态。
由于第二时钟信号处于低电平状态，则第一感测晶体管T1和第四感测晶体管T4均截止，感测级联节点H的电压维持前一阶段的高电平状态，第二感测晶体管T2维持导通；由于第一时钟信号处于低电平状态，则第三感测晶体管T3截止，第三时钟信号不会对上拉节点PU的电压造成影响。
由于第一输入信号和复位信号均处于低电平状态，则第一显示晶体管M1和第二显示晶体管M2均截止，上拉节点PU处于浮接状态，并维持前一阶段的高电平状态，此时第五显示晶体管M5和第六显示晶体管M6维持导通，下拉节点PD维持低电平状态(第七显示晶体管M7截止)，驱动时钟信号通过第六显示晶体管M6写入至对应的信号输出端OUT。
在感测驱动阶段t5的初始时刻，驱动时钟信号由低电平状态切换至高电平状态，则信号输出端OUT输出高电平信号。与此同时，在第一电容器C1的自举作用下，上拉节点PU的电压被上拉至更高状态。本实施例中，假定各时钟信号处于高电平时对应的电压为VGH、处于低电平状态时对应的电压为VGL(近似为0V)，则在感测预充阶段t4时，上拉节点PU的电压近似为VGH，而在感测驱动阶段t5的初始时刻时，上拉节点PU的电压可被上拉至近似2×VGH。经过一段时间后，驱动时钟信号由高电平切换至低电平状态，则信号输出端OUT输出低电平信号；与此同时，在第一电容器C1的自举作用下，上拉节点PU的电压下降至在感测驱动阶段t5的初始时刻的水平，即下降至VGH，此时上拉节点PU仍处于高电平状态。
感测复位阶段t6，第一信号输入端STU1提供的第一输入信号处于低电平状态，第二信号输入端STU2提供的第二输入信号处于低电平状态，复位信号端STD提供的复位信号处于低电平状态，第一时钟信号端CLKA提供的第一时钟信号处于低电平状态，第二时钟信号端CLKB提供的第二时钟信号处于高电平状态，第三时钟信号端CLKC提 供的第三时钟信号处于低电平状态，驱动时钟信号端CLKD提供的驱动时钟信号处于低电平状态。
由于第二时钟信号处于高电平状态，则第一感测晶体管T1和第四感测晶体管T4均导通，处于低电平状态的第二输入信号通过第一感测晶体管T1写入至感测级联节点H，感测级联节点H的电压为低电平状态，第二感测晶体管T2截止。由于第一时钟信号处于低电平状态，则第三感测晶体管T3截止。
由于第四感测晶体管M4导通，则第二工作电压VGL1通过第四显示晶体管M4写入至上拉节点PU，上拉节点PU的电压处于低电平状态。
由于第一输入信号处于低电平状态，复位信号处于低电平状态，则第一显示晶体管M1和第二显示晶体管M2均截止。
由于上拉节点PU的电压处于低电平状态，则第五显示晶体管M5和第六显示晶体管M6均截止；在反向电路4内，第三工作电压VGH通过第三显示晶体管M3写入至下拉节点PD，下拉节点PD的电压为高电平状态，此时第七显示晶体管M7导通，复位工作电压VGL2通过第七显示晶体管M7写入至信号输出端OUT，即信号输出端OUT输出低电平信号。
由此可见，上述移位寄存器可在一帧中的显示驱动阶段和感测阶段分别输出高电平(有效电平)信号，以满足对应行像素单元的驱动需求。
在一些实施例中，如图5所示，该移位寄存器还包括：降噪电路6，降噪电路6用于在上拉节点PU的电压处于非有效电平状态时对上拉节点PU处进行降噪，以维持上拉节点PU处电压的稳定。在一个实施例中，降噪电路6包括：第八显示晶体管M8；第八显示晶体管M8的控制极与下拉节点PD连接，第八显示晶体管M8的第一极与上拉节点PU连接，第八显示晶体管M8的第二极与第二电源端连接。
在显示复位阶段t3结束至感测预充阶段t4开始之间的时间段内，需保持上拉节点PU的电压处于低电平(非有效电平)状态。通过设置上述第八显示晶体管M8，此时反向电路4与第八显示晶体管 M8可构成正反馈环，以强化上拉节点PU处的电压。例如，当上拉节点PU的电压处于低电平状态，反向电路4控制下拉节点PD的电压处于高电平状态，此时第八显示晶体管M8导通，第二工作电压VGL1通过第八显示晶体管M8写入至上拉节点PU，以强化上拉节点PU的电压处于低电平状态(电压大小为VGL1)，达到降噪的目的。
在实际应用中发现，图5所示移位寄存器在显示输出阶段t2和感测输出阶段t5且信号输出端OUT输出有效电平时，上拉节点PU的电压会被第一电容器C1上拉至较高(约2×VGH)状态，此时第二显示晶体管M2、第八显示晶体管M8、第三感测晶体管T3、第四感测晶体管T4的源漏电压差(约为2×VGH)较大，该四个晶体管容易进入饱和导通状态而产生漏电流，从而导致上拉节点PU处的电压漂移，移位寄存器工作异常。
基于图5所示的移位寄存器，本公开还提供了一种移位寄存器。图8为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。在一些实施例中，相较于图5所示移位寄存器，图8所示的移位寄存器还包括：防漏电电路7，防漏电电路7可用于防止第二显示晶体管M2、第八显示晶体管M8、第三感测晶体管T3、第四感测晶体管T4在显示输出阶段和感测输出阶段产生漏电流。
在一个实施例中，防漏电电路7包括：第一防漏电晶体管S1。此外，针对第二显示晶体管M2、第八显示晶体管M8、第三感测晶体管T3、第四感测晶体管T4四处的漏电流问题，防漏电电路7中内依次对应设置有第二防漏电晶体管S2、第三防漏电晶体管S3、第四防漏电晶体管S4和第五防漏电晶体管S5，第二显示晶体管M2的第二极通过第二防漏电晶体管S2与第二电源端连接，第八显示晶体管M8的第二极通过第三防漏电晶体管S3与第二电源端连接，第三感测晶体管T3的第一极通过第四防漏电晶体管S4与第二感测晶体管T2的第二极连接，第四感测晶体管T4的第二极通过第五防漏电晶体管S5与第二电源端连接。
第一防漏电晶体管S1的控制极与一个信号输出端OUT连接，第一防漏电晶体管S1的第二极与一个信号输出端OUT连接，第一防漏 电晶体管S1的第一极与第二防漏电晶体管S2的第一极、第三防漏电晶体管S3的第一极、第四防漏电晶体管S4的第二极、第五防漏电晶体管S5的第一极连接。
需要说明的是，附图中仅示例性给出了第一防漏电晶体管S1的控制极和第二极连接同一信号输出端OUT的情况，其不会对本公开的技术方案产生限制，本领域技术人员应知晓的是，当信号输出端OUT的数量为2个或多个时，第一防漏电晶体管S1的控制极和第二极可分别连接至不同的信号输出端OUT(例如图11、12中所示)。
第二防漏电晶体管S2的控制极与第二显示晶体管M2的控制极连接，第二防漏电晶体管S2的第一极与第二显示晶体管M2的第二极连接，第二防漏电晶体管S2的第二极与第二电源端连接。
第三防漏电晶体管S3的控制极与第八显示晶体管M8的控制极连接，第三防漏电晶体管S3的第一极与第八显示晶体管M8的第二极连接，第三防漏电晶体管S3的第二极与第二电源端连接。
第四防漏电晶体管S4的控制极与第三感测晶体管T3的控制极连接，第四防漏电晶体管S4的第一极与第二感测晶体管T2的第二极连接，第四防漏电晶体管S4的第二极与第三感测晶体管T3的第一极连接。
第五防漏电晶体管S5的控制极与第四感测晶体管T4的控制极连接，第五防漏电晶体管S5的第一极与第四感测晶体管T4的第二极连接，第五防漏电晶体管S5的第二极与第二电源端连接。
图8所示移位寄存器的工作过程可参见参照图5和图6描述的内容，此处不再赘述，下面仅对防漏电电路7中各晶体管的工作过程进行详细描述。
在感测级联阶段、显示预充阶段、显示复位阶段、感测预充阶段、感测复位阶段中，由于信号输出端OUT输出的低电平信号，则第一防漏电晶体管S1处于截止状态。
在感测输出阶段和显示输出阶段中且信号输出端OUT输出高电平信号时，向第一防漏电晶体管S1的控制极输出高电平信号。第一防漏电晶体管S1导通，此时与第一防漏电晶体管S1的第二极连接的 信号输出端OUT所输出的高电平信号(电压为VGH)，会通过第一防漏电晶体管S1写入至第二防漏电晶体管S2的第一极(第二显示晶体管M2的第二极)、第三防漏电晶体管S3的第一极(第八显示晶体管M8的第二极)、第四防漏电晶体管S4的第二极(第三感测晶体管T3的第一极)、第五防漏电晶体管S5的第一极(第四感测晶体管T4的第二极)，此时第二显示晶体管M2、第八显示晶体管M8、第三感测晶体管T3、第四感测晶体管T4的源漏电压差相对较小(约为VGH)，从而可避免上述四个晶体管处于饱和导通状态，进而可避免漏电流的产生，保障了上拉节点PU处电压的稳定。
图9为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。与上述移位寄存器相比，如图9所示，在一些实施例中，信号输出端的数量为两个(OUT/OUT')，相应地，输出子电路5的数量为两个。各输出子电路5中的第六显示晶体管M6/M6'同时导通或同时截止，各输出子电路5中的第七显示晶体管M7/M7'同时导通或同时截止。
该两个输出子电路5所连接的驱动时钟信号端CLKD/CLKD'所提供的驱动时钟信号可以相同也可以不同。
在一些实施例中，该两个输出子电路5所连接的驱动时钟信号端CLKD/CLKD'所提供的驱动时钟信号相同，此时，两个信号输出端OUT/OUT'中的一个用作向栅极驱动电路中的其他移位寄存器提供级联信号(参见后续内容)，另一个用作向对应行像素单元内感测开关晶体管STFT的控制极所连接的栅线G2提供驱动信号。
在上述方案中，通过将提供级联信号的信号输出端与提供驱动信号的信号输出端分离，从而可降低提供驱动信号的信号输出端上的负载，进而能保证移位寄存器向对应行栅线所输出的驱动信号的稳定性。
在一些实施例中，该两个输出子电路5所连接的驱动时钟信号端CLKD/CLKD'所提供的驱动时钟信号不同。图10为图9中两个驱动时钟信号端提供不同时钟信号时的时序图。如图10所示，该两个驱动时钟信号端CLKD/CLKD'在显示驱动阶段提供的驱动时钟信号相同， 但在感测阶段提供的驱动时钟信号不同；驱动时钟信号端CLKD提供的驱动时钟信号对应像素单元内感测开关晶体管STFT的控制极所连接的栅线G2所需的驱动信号，驱动时钟信号端CLKD'提供的驱动时钟信号对应显示开关晶体管QTFT的控制极所连接的栅线G1所需的驱动信号。
此时，两个信号输出端OUT/OUT'中的一个(图9中的信号输出端OUT)用作向栅极驱动电路中的其他移位寄存器提供级联信号以及同时向对应行像素单元内感测开关晶体管STFT的控制极所连接的栅线G2提供驱动信号，另一个(图9中的信号输出端OUT')用作向对应行像素单元内显示开关晶体管QTFT的控制极所连接的栅线G1提供驱动信号。
在上述方案中，一个移位寄存器可同时向像素单元所连接的两条栅线分别提供驱动信号，因而无需再针对显示开关晶体管QTFT的控制极所连接的栅线G1额外设置移位寄存器，可有效减少显示面板中移位寄存器的数量，有利于窄边框设计。
图11为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。与上述实施例不同的是，图11示出的实施例中的信号输出端的数量为三个(OUT/OUT'/OUT”)，相应地，输出子电路5的数量为三个。各输出子电路5中的第六显示晶体管M6/M6'/M6”同时导通或截止，各输出子电路5中的第七显示晶体管M7/M7'/M7”同时导通或截止。
在一些实施例中，三个信号输出端OUT/OUT'/OUT”中的一个用作向栅极驱动电路中的其他移位寄存器提供级联信号，另外两个分别用作向对应行像素单元内显示开关晶体管QTFT的控制极所连接的栅线G1、感测开关晶体管STFT的控制极所连接的栅线G2提供驱动信号(该两个信号输出端所对应的驱动时钟信号端内驱动时钟信号的工作时序可参见图10所示)。
在一些实施例中，三个信号输出端OUT/OUT'/OUT”中的一个用作向对应行像素单元内感测开关晶体管STFT的控制极所连接的栅线G2提供驱动信号，另外两个均用作向栅极驱动电路中的其他移位寄 存器提供级联信号(三个驱动时钟信号端CLKD内驱动时钟信号的工作时序可相同)。
图12为根据本公开的一些实施例的另一种移位寄存器的电路结构示意图。与上述实施例不同的是，图12示出的实施例中的信号输出端的数量为四个(OUT/OUT'/OUT”/OUT”')，相应地，输出子电路5的数量为四个。各输出子电路5中的第六显示晶体管M6/M6'/M6”/M6”'同时导通或截止，各输出子电路5中的第七显示晶体管M7/M7'/M7”/M7”'同时导通或截止。
在一些实施例中，四个信号输出端OUT/OUT'/OUT”/OUT”'中的两个用作向栅极驱动电路中的其他移位寄存器提供级联信号(该两个信号输出端所对应的驱动时钟信号端CLKD内驱动时钟信号可相同)，另外两个分别用作向对应行像素单元内显示开关晶体管QTFT的控制极所连接的栅线G1、感测开关晶体管STFT的控制极所连接的栅线G2提供驱动信号(该两个信号输出端所对应的驱动时钟信号端CLKD内驱动时钟信号的工作时序可参见图10所示)。
另一方面，本公开还提供了一种栅极驱动电路。图13为根据本公开的一些实施例中的一种栅极驱动电路的结构示意图。如图13所示，在一些实施例中，该栅极驱动电路包括：级联的N个移位寄存器A1/A2/A3/A4，移位寄存器A1/A2/A3/A4采用上述实施例中所述的移位寄存器中的任一个。
需要说明的是，附图中仅示例性给出了前4级移位寄存器的示意图。
如图13所示，位于第1级和第2级的移位寄存器A1/A2的第一信号输入端STU1与帧起始信号输入端STV1连接，位于第i级的移位寄存器的第一信号输入端STU1与位于第i-2级移位寄存器的一个信号输出端连接，其中3≤i≤N，且i为正整数。
如图13所示，位于第1级的移位寄存器A1的第二信号输入端STU2与感测起始信号输入端STV2连接，位于第j级的移位寄存器的第二信号输入端STU2与位于第j-1级移位寄存器的一个信号输出端连接，其中2≤j≤N，且j为正整数。
如图13所示，位于第N-2级至第N的移位寄存器的复位信号端STD与帧复位信号端(未示出)连接，位于第k级的复位信号端STD与位于第k+3级移位寄存器的一个信号输出端连接，其中1≤k≤N-3，且k为正整数。
针对该栅极驱动电路中移位寄存器的第一时钟信号端CLKA～第三时钟信号端CLKC，可设置对应的三条时钟信号线CK1/CK2/CK3。其中，各移位寄存器的第一时钟信号端CLKA与第一时钟信号线CK1连接，位于奇数级的移位寄存器的第二时钟信号端CLKB与第二时钟信号线CK2连接，位于奇数级的移位寄存器的第三时钟信号端CLKC与第三时钟信号线CK3连接，位于偶数级的移位寄存器的第二时钟信号端CLKB与第三时钟信号线CK3连接，位于偶数级的移位寄存器的第三时钟信号端CLKC与第二时钟信号线CK2连接。
针对该栅极驱动电路中驱动时钟信号端CLKD，可设置对应的四条驱动时钟信号线CKD1/CKD2/CKD3/CKD4。其中，位于第4m-3级的移位寄存器的驱动时钟信号端CLKD与第一驱动时钟信号线CKD1连接，位于第4m-2级的移位寄存器的驱动时钟信号端CLKD与第二驱动时钟信号线CKD2连接，位于第4m-1级的移位寄存器的驱动时钟信号端CLKD与第三驱动时钟信号线CKD3连接，位于第4m级的移位寄存器的驱动时钟信号端CLKD与第四驱动时钟信号线CKD4连接，1≤m≤N，且m为正整数。
在一些实施例中，各级移位寄存器A1/A2/A3/A4连接有对应的三个信号输出端CR1/CR2/OUT，分别为第一级联信号输出端CR1(用作向栅极驱动电路中的其他移位寄存器提供级联信号)、第二级联信号输出端CR2(用作向栅极驱动电路中的其他移位寄存器提供级联信号)和第一驱动信号输出端OUT(用作向对应行像素单元内感测开关晶体管STFT的控制极所连接的栅线G2提供驱动信号)；其中，位于第i级的移位寄存器的第一信号输入端STU1与位于第i-2级移位寄存器的第一级联信号输出端CR1连接；位于第j级的移位寄存器的第二信号输入端STU2与位于第j-1级移位寄存器的第二级联信号输出端CR2连接；位于第k级移位寄存器的复位信号端STD与位于第k+3 级移位寄存器的第一级联信号输出端CR1连接。各级移位寄存器的第一驱动信号输出端OUT与对应行栅线Gate1/Gate2/Gate3/Gate4连接。
在一些实施例中，第二级联信号输出端CR2所对应的输出子电路5连接的第二电源端提供的低电平工作电压VGL2大于第二时钟信号线(第三时钟信号线)处于低电平状态时对应的电压VGL1。此时，可保证各移位寄存器中第一感测晶体管T1的控制极处于VGL1时，第一感测晶体管T1的栅源电压差恒小于0，第一感测晶体管T1不会出现误导通的现象。
图14为图13所示栅极驱动电路的工作时序图。如图14所示，在每一帧的显示驱动阶段，各级移位寄存器A1/A2/A3/A4依次向对应的行栅线Gate1/Gate2/Gate3/Gate4输出驱动信号，以供显示面板进行画面显示；在每一帧的感测阶段，仅一级移位寄存器输出驱动信号以对对应行像素单元内的显示器件或驱动晶体管进行电流感测，以供进行外部补偿；各行像素单元逐帧进行外部补偿。
需要说明的是，通过控制各驱动时钟信号端CKD1～CKD4所提供的驱动时钟信号的重叠占比，可对相邻行栅线的驱动信号的重叠占比(Overlap)进行控制。
另一方面，本公开还提供了一种显示装置。在一些实施例中，该显示装置包括：栅极驱动电路，该栅极驱动电路可采用本文所述的任一栅极驱动电路。
另一方面，本公开还提供了一种栅极驱动方法。图15为根据本公开的一些实施例的一种栅极驱动方法的流程图。该栅极驱动方法基于移位寄存器，该移位寄存器采用本文所述的任一移位寄存器。如图15所示，该栅极驱动方法可以包括步骤S0至S6。
在步骤S0，在感测级联阶段，感测级联电路响应于第二时钟信号端提供的第二时钟信号的控制，将第二信号输入端提供的处于有效电平状态的第二输入信号写入至感测级联节点。
在步骤S1，在显示预充阶段，显示预充复位电路响应于第一信号输入端所提供的第一输入信号的控制，将第一电源端提供的处于有 效电平状态的第一工作电压写入至上拉节点。
在步骤S2，在显示输出阶段，输出子电路响应于处于有效电平状态的上拉节点的电压的控制，将驱动时钟信号端所提供的驱动时钟信号写入至对应的信号输出端。
在步骤S3，在显示复位阶段，显示预充复位电路响应于复位信号端所提供的复位信号的控制，将第二电源端提供的处于非有效电平状态的第二工作电压写入至上拉节点；输出子电路响应于处于有效电平状态的下拉节点的电压的控制，将复位电源端提供的处于非有效电平状态的复位工作电压写入至信号输出端。
在步骤S4，在感测预充阶段，感测预充电路响应于感测级联节点的电压、第一时钟信号端提供的第一时钟信号的控制，将第三时钟信号端提供的处于有效电平状态的第三时钟信号写入至上拉节点。
在步骤S5，在感测输出阶段，输出子电路响应于处于有效电平状态的上拉节点的电压的控制，将驱动时钟信号端所提供的驱动时钟信号写入至对应的信号输出端。
在步骤S6，在感测复位阶段，感测预充复位电路响应于第二时钟信号端所提供的第二时钟信号的控制，将第二电源端提供的处于非有效电平状态的第二工作电压写入至上拉节点；输出子电路响应于处于有效电平状态的下拉节点的电压的控制，将复位电源端提供的处于非有效电平状态的复位工作电压写入至信号输出端。
对于上述步骤S1～步骤S6的具体描述，可参见前述实施例中内容，此处不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (23)

  1. 一种移位寄存器，包括输入电路、反向电路和输出电路，所述输入电路与所述反向电路和所述输出电路连接于上拉节点，所述输出电路与所述反向电路连接于下拉节点，其中，
    所述输入电路配置为响应于输入信号，对所述上拉节点的电压进行控制，
    所述反向电路配置为将所述上拉节点的电压进行反向处理，并将反向处理后的电压输出至所述下拉节点，
    所述输出电路配置为在所述上拉节点的电压和所述下拉节点的电压的控制下，在一帧画面的持续时间内输出多脉冲信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述输入电路包括：显示预充复位电路、感测级联电路和感测预充复位电路；
    所述感测级联电路与所述感测预充复位电路连接于感测级联节点，所述显示预充复位电路、所述感测预充复位电路、所述输出电路连接于所述上拉节点；
    所述显示预充复位电路，与第一信号输入端、复位信号端、第一电源端、第二电源端连接，并且配置为在显示预充阶段响应于所述第一信号输入端所提供的第一输入信号的控制，将第一电源端提供的处于有效电平状态的第一工作电压写入至所述上拉节点，以及在显示复位阶段响应于所述复位信号端所提供的复位信号的控制，将第二电源端提供的处于非有效电平状态的第二工作电压写入至所述上拉节点；
    所述感测级联电路，与第二信号输入端、第二时钟信号端连接，并且配置为在感测级联阶段响应于所述第二时钟信号端提供的第二时钟信号的控制，将第二信号输入端提供的处于有效电平状态的第二输入信号写入至所述感测级联节点；
    所述感测预充复位电路，与所述第一时钟信号端、第二时钟信号端、第三时钟信号端、所述第二电源端连接，并且配置为在感测预 充阶段响应于所述感测级联节点的电压、所述第一时钟信号端提供的第一时钟信号的控制，将所述第三时钟信号端提供的处于有效电平状态的第三时钟信号写入至所述上拉节点，以及在感测复位阶段响应于所述第二时钟信号端所提供的第二时钟信号的控制，将所述第二电源端提供的处于非有效电平状态的第二工作电压写入至所述上拉节点；
    其中，所述输出电路连接有至少一个信号输出端，所述输出电路包括：与所述至少一个信号输出端一一对应的至少一个输出子电路，所述至少一个输出子电路中的输出子电路与所述上拉节点、所述下拉节点、对应的信号输出端、对应的驱动时钟信号端、对应的复位电源端连接，并且所述输出子电路配置为在显示输出阶段和感测输出阶段响应于处于有效电平状态的所述上拉节点的电压的控制，将所述对应的驱动时钟信号端所提供的驱动时钟信号写入至所述对应的信号输出端，以及配置为在显示复位阶段和所述感测复位阶段响应于处于有效电平状态的所述下拉节点的电压的控制，将所述对应的复位电源端提供的处于非有效电平状态的复位工作电压写入至所述对应的信号输出端。
  3. 根据权利要求2所述的移位寄存器，其中，所述显示预充复位电路包括：第一显示晶体管和第二显示晶体管；
    所述第一显示晶体管的控制极与所述第一信号输入端连接，所述第一显示晶体管的第一极与所述第一电源端连接，所述第一显示晶体管的第二极与所述上拉节点连接；
    所述第二显示晶体管的控制极与所述复位信号端连接，所述第二显示晶体管的第一极与所述上拉节点连接，所述第二显示晶体管的第二极与所述第二电源端连接。
  4. 根据权利要求2或3所述的移位寄存器，其中，所述反向电路包括：第三显示晶体管、第四显示晶体管和第五显示晶体管；
    所述第三显示晶体管的控制极与第三电源端连接，所述第三显示晶体管的第一极与所述第三电源端连接，所述第三显示晶体管的第 二极与所述下拉节点连接；
    所述第四显示晶体管的控制极与第四电源端连接，所述第四显示晶体管的第一极与所述第四电源端连接，所述第四显示晶体管的第二极与所述下拉节点连接；
    所述第五显示晶体管的控制极与所述上拉节点连接，所述第五显示晶体管的第一极与所述下拉节点连接，所述第五显示晶体管的第二极与所述第二电源端连接；
    所述第三电源端提供的第三工作电压和所述第四电源端提供的第四工作电压均每隔预设周期在有效电平状态和非有效电平状态之间切换一次，且在任意时刻所述第三工作电压和所述第四工作电压中的一者处于有效电平状态，另一者处于非有效电平状态。
  5. 根据权利要求2至4中任一项所述的移位寄存器，其中，所述输出子电路包括：第六显示晶体管和第七显示晶体管；
    所述第六显示晶体管的控制极与所述上拉节点连接，所述第六显示晶体管的第一极与所述对应的驱动时钟信号端连接，所述第六显示晶体管的第二极与所述对应的信号输出端连接；
    所述第七显示晶体管的控制极与所述下拉节点连接，所述第七显示晶体管的第一极与所述对应的信号输出端连接，所述第七显示晶体管的第二极与所述对应的复位电源端连接。
  6. 根据权利要求2至5中任一项所述的移位寄存器，还包括：第一电容器；
    所述第一电容器的第一端与所述上拉节点连接，所述第一电容器的第二端与所述至少一个信号输出端中的信号输出端连接。
  7. 根据权利要求2至6中任一项所述的移位寄存器，其中，所述至少一个信号输出端的数量为1～4个。
  8. 根据权利要求2至7中任一项所述的移位寄存器，还包括： 降噪电路，所述降噪电路包括：第八显示晶体管；
    所述第八显示晶体管的控制极与所述下拉节点连接，所述第八显示晶体管的第一极与所述上拉节点连接，所述第八显示晶体管的第二极与所述第二电源端连接。
  9. 根据权利要求2至8中任一项所述的移位寄存器，其中，所述感测级联电路包括：第一感测晶体管；
    所述第一感测晶体管的控制极与所述第二时钟信号端连接，所述第一感测晶体管的第一极与所述第二信号输入端连接，所述第一感测晶体管的第二极与所述感测级联节点连接。
  10. 根据权利要求2至9中任一项所述的移位寄存器，还包括：第二电容器；
    所述第二电容器的第一端与所述感测级联节点连接，所述第二电容器的第二端与第五电源端连接。
  11. 根据权利要求2至10中任一项所述的移位寄存器，其中，所述感测预充复位电路包括：第二感测晶体管、第三感测晶体管和第四感测晶体管；
    所述第二感测晶体管的控制极与所述感测级联节点连接，所述第二感测晶体管的第一极与所述第三时钟信号端连接，所述第二感测晶体管的第二极与所述第三感测晶体管的第一极连接；
    所述第三感测晶体管的控制极与所述第一时钟信号端连接，所述第三感测晶体管的第二极与所述上拉节点连接；
    所述第四感测晶体管的控制极与所述第二时钟信号端连接，所述第四感测晶体管的第一极与所述上拉节点连接，所述第四感测晶体管的第二极与所述第二电源端连接。
  12. 根据权利要求3所述的移位寄存器，还包括：防漏电电路；
    所述防漏电电路包括：第一防漏电晶体管和第二防漏电晶体管， 所述第二显示晶体管的第二极通过所述第二防漏电晶体管与所述第二电源端连接；
    所述第一防漏电晶体管的控制极与所述至少一个信号输出端中的一个信号输出端连接，所述第一防漏电晶体管的第一极与所述第二显示晶体管的第二极、所述第二防漏电晶体管的第一极连接，所述第一防漏电晶体管的第二极与所述至少一个信号输出端中的一个信号输出端连接；
    所述第二防漏电晶体管的控制极与所述第二显示晶体管的控制极连接，所述第二防漏电晶体管的第一极与所述第二显示晶体管的第二极连接，所述第二防漏电晶体管的第二极与所述第二电源端连接。
  13. 根据权利要求8所述的移位寄存器，还包括：防漏电电路；
    所述防漏电电路包括：第一防漏电晶体管和第三防漏电晶体管，所述第八显示晶体管的第二极通过所述第三防漏电晶体管与所述第二电源端连接；
    所述第一防漏电晶体管的控制极与所述至少一个信号输出端中的一个信号输出端连接，所述第一防漏电晶体管的第一极与所述第八显示晶体管的第二极、所述第三防漏电晶体管的第一极连接，所述第一防漏电晶体管的第二极与所述至少一个信号输出端中的一个信号输出端连接；
    所述第三防漏电晶体管的控制极与所述第八显示晶体管的控制极连接，所述第三防漏电晶体管的第一极与所述第八显示晶体管的第二极连接，所述第三防漏电晶体管的第二极与所述第二电源端连接。
  14. 根据权利要求11所述的移位寄存器，还包括：防漏电电路；
    所述防漏电路包括：第一防漏电晶体管、第四防漏电晶体管和第五防漏电晶体管，所述第三感测晶体管的第一极通过所述第四防漏电晶体管与所述第二感测晶体管的第二极连接，所述第四感测晶体管的第二极通过所述第五防漏电晶体管与所述第二电源端连接；
    所述第一防漏电晶体管的控制极与所述至少一个信号输出端中 的一个信号输出端连接，所述第一防漏电晶体管的第一极与所述第三感测晶体管的第一极、所述第四防漏电晶体管的第二极、所述第四感测晶体管的第二极、所述第五防漏电晶体管的第一极连接，所述第一防漏电晶体管的第二极与所述至少一个信号输出端中的一个信号输出端连接；
    所述第四防漏电晶体管的控制极与所述第三感测晶体管的控制极连接，所述第四防漏电晶体管的第一极与所述第二感测晶体管的第二极连接，所述第四防漏电晶体管的第二极与所述第三感测晶体管的第一极连接；
    所述第五防漏电晶体管的控制极与所述第四感测晶体管的控制极连接，所述第五防漏电晶体管的第一极与所述第四感测晶体管的第二极连接，所述第五防漏电晶体管的第二极与所述第二电源端连接。
  15. 根据权利要求12至14中任一项所述的移位寄存器，其中，与所述第一防漏电晶体管的控制极连接的所述一个信号输出端和与所述第一防漏电晶体管的第二极连接的所述一个信号输出端是同一个信号输出端。
  16. 根据权利要求12至14中任一项所述的移位寄存器，其中，与所述第一防漏电晶体管的控制极连接的所述一个信号输出端和与所述第一防漏电晶体管的第二极连接的所述一个信号输出端是不同的信号输出端。
  17. 根据权利要求1所述的移位寄存器，其中，所述输出电路包括第一信号输出端和第二信号输出端，所述第一信号输出端配置为向第二移位寄存器提供级联信号或者配置为向与其连接的栅线提供驱动信号，并且所述第二信号输出端配置为向与其连接的栅线提供驱动信号。
  18. 根据权利要求1所述的移位寄存器，其中，所述输出电路包 括第一信号输出端、第二信号输出端和第三信号输出端，
    所述第一信号输出端配置为向第二移位寄存器提供级联信号；
    所述第二信号输出端配置为向第三移位寄存器提供级联信号或者配置为向与其连接的第一栅线提供驱动信号；并且
    所述第三信号输出端配置为向与其连接的第二栅线提供驱动信号。
  19. 根据权利要求1所述的移位寄存器，其中，所述输出电路包括第一信号输出端、第二信号输出端、第三信号输出端和第四信号输出端，
    所述第一信号输出端配置为向第二移位寄存器提供级联信号，
    所述第二信号输出端配置为向第三移位寄存器提供级联信号，
    所述第三信号输出端配置为向与其连接的第一栅线提供驱动信号，并且
    所述第四信号输出端配置为向与其连接的第二栅线提供驱动信号。
  20. 一种栅极驱动电路，包括：级联的N个移位寄存器，所述N个移位寄存器中的每一个采用根据权利要求1-19中任一所述的移位寄存器；其中，
    位于第1级和第2级的移位寄存器的第一信号输入端与帧起始信号输入端连接，位于第i级的移位寄存器的第一信号输入端与位于第i-2级移位寄存器的一个信号输出端连接，其中3≤i≤N，且i为正整数；
    位于第1级的移位寄存器的第二信号输入端与感测起始信号输入端连接，位于第j级的移位寄存器的第二信号输入端与位于第j-1级移位寄存器的一个信号输出端连接，其中2≤j≤N，且j为正整数；
    位于第N-2级至第N的移位寄存器的复位信号端与帧复位信号端连接，位于第k级的复位信号端与位于第k+3级移位寄存器的一个信号输出端连接，其中1≤k≤N-3，且k为正整数。
  21. 根据权利要求20所述的栅极驱动电路，其中，各级所述移位寄存器连接有对应的三个信号输出端，分别为第一级联信号输出端、第二级联信号输出端和第一驱动信号输出端；
    其中，位于第i级的移位寄存器的第一信号输入端与位于第i-2级移位寄存器的第一级联信号输出端连接；
    位于第j级的移位寄存器的第二信号输入端与位于第j-1级移位寄存器的第二级联信号输出端连接；
    位于第k级的移位寄存器的复位信号端与位于第k+3级移位寄存器的第一级联信号输出端连接；
    各级移位寄存器的所述第一驱动信号输出端与对应行栅线连接。
  22. 一种显示装置，包括：根据权利要求20或21所述的栅极驱动电路。
  23. 一种栅极驱动方法，所述栅极驱动方法基于移位寄存器，所述移位寄存器采用根据权利要求2-16中任一所述的移位寄存器，所述栅极驱动方法包括：
    在感测级联阶段，所述感测级联电路响应于所述第二时钟信号端提供的第二时钟信号的控制，将第二信号输入端提供的处于有效电平状态的第二输入信号写入至所述感测级联节点；
    在显示预充阶段，所述显示预充复位电路响应于所述第一信号输入端所提供的第一输入信号的控制，将第一电源端提供的处于有效电平状态的第一工作电压写入至所述上拉节点；
    在显示输出阶段，所述输出子电路响应于处于有效电平状态的所述上拉节点的电压的控制，将所述对应的驱动时钟信号端所提供的驱动时钟信号写入至所述对应的信号输出端；
    在显示复位阶段，所述显示预充复位电路响应于所述复位信号端所提供的复位信号的控制，将第二电源端提供的处于非有效电平状态的第二工作电压写入至所述上拉节点；所述输出子电路响应于处于 有效电平状态的所述下拉节点的电压的控制，将所述对应的复位电源端提供的处于非有效电平状态的复位工作电压写入至所述对应的信号输出端；
    在感测预充阶段，所述感测预充电路响应于所述感测级联节点的电压、所述第一时钟信号端提供的第一时钟信号的控制，将所述第三时钟信号端提供的处于有效电平状态的第三时钟信号写入至所述上拉节点；
    在感测输出阶段，所述输出子电路响应于处于有效电平状态的所述上拉节点的电压的控制，将所述对应的驱动时钟信号端所提供的驱动时钟信号写入至所述对应的信号输出端；
    在感测复位阶段，所述感测预充复位电路响应于所述第二时钟信号端所提供的第二时钟信号的控制，将所述第二电源端提供的处于非有效电平状态的第二工作电压写入至所述上拉节点；所述输出子电路响应于处于有效电平状态的所述下拉节点的电压的控制，将所述对应的复位电源端提供的处于非有效电平状态的复位工作电压写入至所述对应的信号输出端。
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US20210065630A1 (en) 2021-03-04
EP3832635A4 (en) 2022-04-27
EP3832635A1 (en) 2021-06-09
CN109949749B (zh) 2021-01-26
CN109949749A (zh) 2019-06-28
US11081061B2 (en) 2021-08-03

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