WO2020015397A1 - 显示装置及移位暂存电路 - Google Patents

显示装置及移位暂存电路 Download PDF

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Publication number
WO2020015397A1
WO2020015397A1 PCT/CN2019/082287 CN2019082287W WO2020015397A1 WO 2020015397 A1 WO2020015397 A1 WO 2020015397A1 CN 2019082287 W CN2019082287 W CN 2019082287W WO 2020015397 A1 WO2020015397 A1 WO 2020015397A1
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Prior art keywords
switch
signal
terminal
electrically coupled
shift register
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PCT/CN2019/082287
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English (en)
French (fr)
Inventor
单剑锋
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present application relates to the technical field of display panels, and in particular to a display device having an array substrate gate driving circuit and a shift temporary storage circuit thereof.
  • liquid crystal displays Liquid Crystal Display, LCD
  • LCD Liquid Crystal Display
  • a gate driver chip (1C) is mainly used to implement it. Since the gate driving chip needs to be connected to a display panel through a connector, and a plurality of gate driving chips are used in one liquid crystal display, the manufacturing cost of the liquid crystal display is still relatively high.
  • the array substrate gate driving technology is a process of exposing and developing a gate driving integrated circuit directly on the surface of an active switching array substrate, thereby eliminating the need for an external gate driving chip. From the aspects of material cost and process steps, the array substrate gate driving technology can greatly reduce the cost of the product, and can further reduce the power consumption of the liquid crystal display panel.
  • a typical gate drive circuit of an array substrate has a multi-stage shift register.
  • each shift register scans and drives a gate signal line
  • its gate voltage point will receive a pre-charge signal to the gate.
  • the pole voltage point is precharged, so that the voltage at this point reaches the high voltage level under the action of the clock signal, so that the thin-film transistor (Thin-Film Transistor, TFT) of the control output is turned on, and the signal is smoothly transmitted to drive the panel gate.
  • TFT Thi-Film Transistor
  • the present application proposes a display device and a shift temporary storage circuit thereof, which can accurately and smoothly output a gate scan signal, and can improve the tailing phenomenon of the gate scan signal, thereby improving the picture quality of the display device.
  • the present application proposes a shift register circuit, including a multi-stage shift register, in which any stage of the shift register includes: an input module that inputs a stage transfer signal of a previous stage shift register to a booster Node to increase the voltage signal Qn of the boost node to a first level; a coupling pull-up module, coupled to the boost node, for generating a first pull-up signal and a second pull-up signal, The first pull-up signal can be electrically coupled to pull the voltage signal Qn from the first level coupling to a second level; the output module receives a clock signal CKn, and The clock signal CKn couples the voltage signal Qn from the second level to a third level, and the output module is controlled by the voltage signal Qn at the third level and passes through an output terminal.
  • Output a gate scan signal, wherein when the pulse of the clock signal CKn ends, the coupling pull-up module generates the second pull-up signal, and maintains the voltage signal Qn at The second level; and a feedback module, receiving a feedback signal, The voltage signal Qn and the gate scan signal coupled to the boost node are pulled down to a preset low level.
  • the shift register of any stage further includes a sub-pull-down module for maintaining the voltage signal Qn at the preset low level; and a sub-pull-down control module for controlling Operation of the sub-pull-down module.
  • the sub-pull-down module is electrically coupled to the boost node, the gate scan signal, and the preset low potential.
  • the output module includes a first switch, a control terminal of the first switch is electrically coupled to the boost node, and a first terminal of the first switch is configured to receive the first switch.
  • the clock signal CKn a second terminal of the first switch is electrically coupled to the output terminal for outputting the gate scan signal, and when the voltage signal Qn coupling of the boost node is increased to the first At three levels, the first switch is turned on and outputs the gate scan signal.
  • the input module includes a second switch, and a control terminal of the second switch is electrically coupled to a first terminal of the second switch and a first terminal of the second switch. The two ends are used to output the cascaded signal.
  • the feedback module includes a third switch, a control terminal of the third switch is electrically coupled to a feedback signal, and a first terminal of the third switch is electrically coupled. At the output terminal, a second terminal of the third switch is electrically coupled to the preset low level, wherein the third switch is turned on in response to the feedback signal, and the third switch is turned on.
  • the first terminal and the second terminal of the switch pull the gate scan signal to the preset low level; and a fourth switch, a control terminal of the fourth switch is electrically coupled Connected to the feedback signal, a first terminal of the fourth switch is electrically coupled to the boost node, and a second terminal of the fourth switch is electrically coupled to the preset low level Wherein the fourth switch is turned on in response to the feedback signal, and the first terminal and the second terminal of the fourth switch are turned on to pull the voltage signal Qn to the preset low Level.
  • the coupling pull-up module includes a fifth switch, and a control terminal of the fifth switch is electrically coupled to the clock signal CK (n-1) of the previous stage shift register, A first terminal of the fifth switch is electrically coupled to the clock signal CK (n-2) of the front-stage shift register, wherein the fifth switch is responsive to the previous-stage shift register.
  • the clock signal CK (n-1) of the fifth switch is turned on, and the first terminal and a second terminal of the fifth switch are turned on, and the clock signal CK (n-2) of the first-stage shift register is turned on.
  • a sixth switch a control end of the sixth switch is electrically coupled to the voltage signal Q (n-1) of the previous stage shift register A first terminal of the sixth switch is electrically coupled to the second terminal of the fifth switch, and a second terminal of the sixth switch is electrically coupled to the boost node, wherein the The sixth switch is turned on in response to the voltage signal Q (n-1) of the previous stage shift register, turns on the first end and the second end of the sixth switch, and outputs all Said first pull-up signal; a seventh switch, said A control terminal of the seven switches is electrically coupled to the clock signal CK (n + 1) of the first stage shift register, and a first terminal of the seventh switch is electrically coupled to the second stage shift register.
  • Clock signal CK (n + 2) wherein the seventh switch is turned on in response to the clock signal CK (n + 1) of the subsequent stage shift register, and the seventh switch is turned on.
  • a first terminal and a second terminal transmitting the clock signal CK (n + 2) of the second-stage shift register to the second terminal of the seventh switch; and an eighth switch, so A control terminal of the eighth switch is electrically coupled to the voltage signal Q (n + 1) of the subsequent stage shift register, and a first terminal of the eighth switch is electrically coupled to the seventh switch.
  • the second terminal and a second terminal of the eighth switch are electrically coupled to the boost node, wherein the eighth switch is responsive to the voltage signal Q (n +1) is turned on, the first terminal and the second terminal of the eighth switch are turned on, and the second pull-up signal is output.
  • the second terminal of the sixth switch is electrically coupled to the second terminal of the eighth switch.
  • the coupling pull-up module further includes a ninth switch, a control terminal of the ninth switch is electrically coupled to the boost node, and a first terminal of the ninth switch is electrically coupled Connected to the second terminal of the sixth switch and the second terminal of the eighth switch, a second terminal of the ninth switch is electrically coupled to the preset low level, wherein The ninth switch is turned on in response to the voltage signal, and the first terminal and the second terminal of the ninth switch are turned on.
  • the coupling pull-up module further includes a ninth switch, a control end of the ninth switch is electrically coupled to the boost node, and a first end of the ninth switch is used for Receiving the first pull-up signal and the second pull-up signal, a second terminal of the ninth switch is electrically coupled to the preset low level, and the ninth switch is responsive to the The voltage signal is turned on, and the first terminal and the second terminal of the ninth switch are turned on.
  • the coupled pull-up module is controlled by the voltage signal Q (n-1) of the previous stage shift register to generate the first pull-up signal, and the voltage signal Qn is determined by The first level coupling is pulled up to the second level, and is controlled by the voltage signal Q (n + 1) of the subsequent stage shift register to generate the second pull-up signal, which is electrically coupled.
  • the voltage signal Qn is maintained at the second level.
  • the coupled pull-up module generates the first pull-up signal according to the clock signal CK (n-1) of the previous stage shift register, and converts the voltage signal Qn from the first A level coupling is pulled up to the second level, and the second pull-up signal is generated according to the clock signal CK (n + 2) of the second-stage shift register, which is electrically coupled to the boost Node to maintain the voltage signal Qn at the second level.
  • the display device includes an active switch array substrate and a pair of substrates.
  • the display device is disposed opposite to the active switch array substrate, and an array substrate grid is fabricated on the active switch array substrate.
  • a driving circuit, and the gate driving circuit of the array substrate includes the shift register circuit described in the above various embodiments, the shift register circuit includes a multi-stage shift register, and any of the stages is shifted
  • the register includes: an input module for inputting a stage transfer signal of a previous stage shift register to a boost node; a coupling pull-up module coupled to the boost node for generating a first pull-up signal and a second A pull-up signal, wherein the first pull-up signal is electrically coupled to pull the voltage signal from a first level coupling to a second level; an output module receives a clock signal, and according to the clock The signal couples the voltage signal from the second level to a third level, the output module is controlled by the voltage signal of the third level, and outputs a gate scan signal through an output terminal, where
  • the output module includes a first switch, a control terminal of the first switch is electrically coupled to the boost node, and a first terminal of the first switch is configured to receive the clock. Signal, a second terminal of the first switch is electrically coupled to the output terminal for outputting the gate scan signal, and when the voltage signal coupling of the boost node is increased to the third level , The first switch is turned on and outputs the gate scan signal.
  • the input module includes a second switch, a control terminal of the second switch is electrically coupled to the first terminal of the second switch, and the second terminal of the second switch is used for At the output stage signal.
  • the feedback module includes a third switch, a control terminal of the third switch is electrically coupled to the feedback signal, and a first terminal of the third switch is electrically coupled to The output terminal and a second terminal of the third switch are electrically coupled to the preset low level, wherein the third switch is turned on in response to the feedback signal, and the third switch is turned on. The first terminal and the second terminal pull the gate scan signal to the preset low level.
  • the feedback module includes a fourth switch, a control terminal of the fourth switch is electrically coupled to the feedback signal, and a first terminal of the fourth switch is electrically coupled to the In the boost node, a second terminal of the fourth switch is electrically coupled to the preset low level, wherein the fourth switch is turned on in response to the feedback signal, and the fourth switch is turned on.
  • the first terminal and the second terminal pull the voltage signal to the preset low level.
  • the coupling pull-up module includes a fifth switch, a control terminal of the fifth switch is electrically coupled to a clock signal of a previous stage shift register, and one of the fifth switch The first terminal is electrically coupled to the clock signal of the front-stage shift register, wherein the fifth switch is turned on in response to the clock signal of the previous-stage shift register, and the fifth switch is turned on.
  • the first end and a second end of the first and second ends transmit clock signals of the first two-stage shift register to the second end of the fifth switch; the sixth switch, the sixth switch A control terminal is electrically coupled to the voltage signal of the previous stage shift register, a first terminal of the sixth switch is electrically coupled to the second terminal of the fifth switch, and the sixth switch A second terminal of is electrically coupled to the boost node, wherein the sixth switch is turned on in response to a voltage signal of the previous stage shift register, and the first switch of the sixth switch is turned on.
  • One end is connected to the second end, and the first pull-up signal is output; a seventh switch, a control end of the seventh switch is electrically coupled after a stage shift A clock signal of a bit register, a first end of the seventh switch is electrically coupled to a clock signal of a second stage shift register, wherein the seventh switch is responsive to the second stage shift register
  • the clock signal of the register is turned on, the first end and a second end of the seventh switch are turned on, and the clock signal of the second-stage shift register is transmitted to the seventh switch.
  • a control terminal of the eighth switch is electrically coupled to the voltage signal of the stage shift register, and a first terminal of the eighth switch is electrically coupled to the The second terminal of the seventh switch, and a second terminal of the eighth switch are electrically coupled to the boost node, wherein the eighth switch is responsive to the The voltage signal is turned on, the first terminal and the second terminal of the eighth switch are turned on, and the second pull-up signal is output.
  • the coupling pull-up module further includes a ninth switch, a control end of the ninth switch is electrically coupled to the boost node, and a first end of the ninth switch is used for receiving The first pull-up signal and the second pull-up signal, a second terminal of the ninth switch is electrically coupled to the preset low level, and the ninth switch responds to the voltage The signal is turned on, and the first terminal and the second terminal of the ninth switch are turned on.
  • this application uses a coupling pull-up module, which indirectly acts on the boost node through electrical coupling, the voltage signal of the boost node can be pulled up to a higher level, so that the shift register can be accurate And smoothly output the gate scan signal.
  • the pull-up module since the pull-up module is coupled, when the pulse of the gate scan signal ends, a pull-up signal is also output, which indirectly acts on the boost node through electrical coupling and maintains the voltage signal of the boost node at a high level. Therefore, the gate scan signal can be accelerated to pull down, thereby improving the tailing phenomenon of the gate scan signal, thereby improving the quality of the display screen.
  • FIG. 1a is a schematic diagram of an exemplary display.
  • FIG. 1b is a schematic diagram of a display according to an embodiment of the present application.
  • FIG. 2a is a schematic diagram of an exemplary shift register circuit.
  • FIG. 2b is a schematic diagram of a voltage signal waveform of a boost node in an exemplary shift register circuit.
  • FIG. 2c is a working timing diagram of an exemplary shift register circuit.
  • FIG. 3a is a schematic structural diagram of a module of a shift temporary storage circuit in the first embodiment of the present application.
  • FIG. 3b is a schematic circuit structure diagram of a shift temporary storage circuit in the first embodiment of the present application.
  • FIG. 3c is a schematic structural diagram of a module of a shift temporary storage circuit in a second embodiment of the present application.
  • FIG. 3d is a schematic circuit structure diagram of a shift temporary storage circuit in the second embodiment of the present application.
  • 3e is a schematic diagram of a voltage signal waveform of a boosting node in a shift temporary storage circuit according to an embodiment of the present application.
  • FIG. 4 is a working timing diagram of a shift temporary storage circuit in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a display device according to an embodiment of the present application.
  • the display device may be, for example, a liquid crystal display device, an OLED display device, a QLED display device, a curved display device, or other display devices.
  • the liquid crystal display device includes an active switching array substrate, an opposite substrate, and a liquid crystal layer formed between the two substrates.
  • the TFT array and the color filter (CF) of the present application can also be formed on the same substrate.
  • the display device of the present application can also be manufactured as a curved display device.
  • FIG. 1a is a schematic diagram of an exemplary display device.
  • a display device 10 includes an active switch array substrate 101, a pair of opposing substrates 100 disposed opposite to the active switch array substrate 101, and a gate driving chip 102 for driving a circuit.
  • the gate driving chip 102 is externally connected to the right side of the active switch array substrate 101.
  • FIG. 1b is a schematic diagram of a display device according to an embodiment of the present application.
  • a display device 12 having an array substrate gate drive includes an active switch array substrate 121, a pair of opposing substrates 120 and the active switch array substrate 121 facing each other.
  • an array substrate gate driving circuit 122 wherein the array substrate gate driving circuit 122 is directly fabricated on the surface of the active switching array substrate 121 by a lithography process.
  • the gate driving circuits 122 of the array substrate are fabricated on the left and right surfaces of the active switching array substrate 121, respectively.
  • FIG. 2a is a schematic diagram of an exemplary shift temporary storage circuit. Please refer to FIG. 2a.
  • a shift register circuit includes a multi-stage shift register. Any shift register 2 includes a first switch T1, a second switch T2, a third switch T3, a The fourth switch T4, a sub pull-down control module (sub-pull controller) 21, and a sub pull-down module (sub-pull controller) 22.
  • the shift register circuit includes an n-stage shift register, where n is a positive integer, and the n-stage shift register 2 is shown in FIG. 2a.
  • a control terminal T1a of the first switch T1 is electrically coupled to a boost point BP, and a first terminal T1b of the first switch T1 is electrically coupled to a clock signal CK.
  • the first A second terminal T1c of the switch T1 is electrically coupled to an output terminal O to output a gate scan signal Gn.
  • the second switch T2 is electrically coupled to the stage transmission signal ST of the previous stage shift register, and is used to input the stage transmission signal ST to the boost node BP, so as to improve the boost node BP.
  • the level of the voltage signal Qn A control terminal T2a and a first terminal T2b of the second switch T2 are electrically coupled to the stage signal ST, and a second terminal T2c of the second switch T2 is electrically coupled to the boost node BP. .
  • a control terminal T3a of the third switch T3 is electrically coupled to a feedback signal FB, and a first terminal T3b of the third switch T3 is electrically coupled to a gate scan signal Gn of the output terminal O.
  • a second terminal T3c of the third switch T3 is electrically coupled to a preset low level Vss.
  • a control terminal T4a of the fourth switch T4 is electrically coupled to the feedback signal FB, a first terminal T4b of the fourth switch T4 is electrically coupled to the boost node BP, and the fourth switch T4 A second terminal T4c is electrically coupled to the preset low level Vss.
  • the sub-pull-down module 22 is electrically coupled to the boost node BP, the gate scan signal Gn, and the preset low potential Vss of the shift register 2 to maintain the voltage.
  • the signal Qn and the gate scan signal Gn are at the preset low level Vss.
  • the sub-pull-down control module 21 is electrically coupled to the low preset potential Vss of the shift register 2 and the sub-pull-down module 22, and is configured to control the sub-pull-down module 22 at a correct time. Do it. That is, the sub pull-down module 22 can eliminate the noise of the boost node BP and the output terminal O, and ensure that the voltage signal Qn and the gate scan signal Gn can be maintained at a preset low level Vss during non-operation time. Avoid malfunctions.
  • FIG. 2b is a waveform diagram of the voltage signal Qn of the boosting node BP in the exemplary shift register circuit. Please also refer to FIG. 2a.
  • the boost node BP When the stage signal ST of the previous stage shift register (n-1) in FIG. 2a is transmitted to the boost node BP, the boost node BP will be precharged. The voltage signal Qn is increased to a level A, as shown in FIG. 2b. Subsequently, when the clock signal CK is applied to the first terminal T1b of the first switch T1, electrical coupling is generated, so that the voltage signal Qn of the boosting node BP is further increased from the precharged level A to the level B, such as Figure 2b.
  • the coupled voltage signal Qn is applied to the control terminal T1a of the first switch T1, which will cause the first switch T1 to open, transmit the clock signal CK on the first terminal T1a to the second terminal T1b, and output through the output terminal O, and The gate scan signal Gn is generated. Subsequently, as shown in FIG. 2b, with the end of the clock signal CK, the voltage signal Qn of the boosting node BP decreases from the level B after coupling to the level A after precharging.
  • FIG. 2c is a working timing diagram of a shift temporary storage circuit according to an embodiment of the present application.
  • the shift temporary storage circuit uses eight sets of clock signals CK1-CK8 to control the operation.
  • the voltage signal Q4 of the shift register 2 at the boost node BP can be divided into three periods: t1 is the precharge time; t2 is the output gate scan signal time; t3 is the pull-down gate scan signal time .
  • the stage transmission signal ST transmitted from the previous stage shift register that is, the stage transmission signal ST of the third stage shift register is received to precharge the boost node BP, so the voltage Signal Q4 is raised to level A. That is, the second switch T2 will follow the pulse of the clock signal CK (n-2) of the previous two-stage shift register, that is, the pulse of the clock signal CK2 in FIG. 2c, and input the stage signal ST to the amplifier. Press the node BP to increase the voltage signal Q4 of the boost node BP to the level A.
  • the shift register 2 will receive the aforementioned feedback signal FB, discharge the boost node BP, and pull down the voltage signal Q4 from the level A to a preset low level.
  • FIG. 3a is a schematic structural diagram of a module of a shift temporary storage circuit in the first embodiment of the present application.
  • FIG. 3b is a schematic circuit structure diagram of a shift temporary storage circuit in the first embodiment of the present application.
  • FIG. 3e is a schematic diagram of a voltage signal waveform of a boosting node in a shift temporary storage circuit according to an embodiment of the present application.
  • a shift register circuit includes a multi-stage shift register.
  • a shift register 3 mainly includes an input module 31, a pull-up module 32, and an output module. 33.
  • the shift register circuit includes an n-stage shift register, where n is a positive integer, and the n-stage shift register 3 is shown in FIG. 3a.
  • the input module 31 is configured to input the stage transmission signal ST of the previous stage shift register to a boosting node BP.
  • the stage transmission signal ST of the previous stage shift register may be input to improve the The voltage signal Qn of the boosting node BP reaches a first level A ′, as shown in FIG. 3e.
  • the stage transmission signal ST of the previous stage shift register is input, but depending on the signal configuration, the first two stages, the first three stages, or It is the stage signal ST of other previous stage (nx) shift registers.
  • the pull-up module 32 is configured to output a first pull-up signal Pu1 to the boost node BP, and pull the voltage signal Qn from the first level A ′ to a second level B ′, And a second pull-up signal Pu2 is output to the boost node BP, so that the voltage signal Qn is maintained at the second level B ′, as shown in FIG. 3e.
  • the output module 33 receives a clock signal CKn and couples the voltage signal Qn from the second high level B ′ to the third high level C ′ according to the clock signal CKn, as shown in FIG. 3e .
  • the output module 33 is controlled by the coupled voltage signal Qn to turn on, and outputs a gate scan signal Gn through an output terminal O.
  • the pull-up module 32 outputs the second pull-up signal Pu2 to the boost node BP, so that the voltage signal Qn is maintained at the second level B '.
  • the feedback module 34 receives a feedback signal FB, and couples the voltage signal Qn and the gate scan signal Gn after coupling the boost node BP to a preset low level Vss.
  • the shift register 3 further includes a sub pull-down control module 35 and a sub pull-down module 36.
  • the sub-pull-down module 36 is configured to maintain the voltage signal Qn at the preset low level Vss.
  • the sub pull-down control module 35 it is used to control the operation of the sub pull-down module 36.
  • the output module 33 includes a switch T11.
  • a control terminal T11a of the switch T11 is electrically coupled to the boost node BP, a first terminal T11b of the switch T11 is used to receive the clock signal CKn, and a second terminal T11c of the switch T11 is electrically coupled Connected to the output terminal O for outputting the gate scan signal Gn.
  • the switch T11 is turned on and outputs the gate scan signal Gn.
  • the input module 31 includes a switch T12, a control terminal T12a of the switch T12 is electrically coupled to a first terminal T12b of the switch T12, and a second terminal T12c of the switch T12 is electrically coupled to the amplifier T12.
  • the voltage node BP is configured to output the stage transmission signal ST to the boost node BP, so as to increase the voltage signal Qn of the boost node BP to the first level A ′.
  • the feedback module 34 includes a switch T13 and a switch T14.
  • a control terminal T13a of the switch T13 is electrically coupled to a feedback signal FB
  • a first terminal T13b of the switch T13 is electrically coupled to the output terminal O
  • a second terminal T13c of the switch T13 Electrically coupled to the preset low level.
  • the switch T13 is turned on in response to the feedback signal FB, and the first terminal T13b and the second terminal T13c of the switch T13 are turned on to pull the gate scan signal Gn to the preset low level Vss.
  • a control terminal T14a of the switch T14 is electrically coupled to the feedback signal FB, a first terminal T14b of the switch T14 is electrically coupled to the boost node BP, and a second terminal of the switch T14 is The terminal T14c is electrically coupled to the preset low level Vss.
  • the switch T14 is turned on in response to the feedback signal FB, and the first terminal T14b and the second terminal T14c of the switch T14 are turned on to pull the voltage signal Qn to a preset low level Vss.
  • the pull-up module 32 includes a switch T15, a switch T16, a switch T17, and a switch T18.
  • a control terminal T15a of the switch T15 is electrically coupled to the clock signal CK (n-1) of the previous-stage shift register, and a first terminal T15b of the switch T15 is electrically coupled to the front-stage shift.
  • the switch T15 is turned on in response to the clock signal CK (n-1) of the previous stage shift register, and the first terminal T15b and the second terminal T15c of the switch T15 are turned on, and the first two The clock signal CK (n-2) of the stage shift register is transmitted to the second terminal T15c of the switch T15.
  • a control terminal T16a of the switch T16 is electrically coupled to the voltage signal Q (n-1) of the previous stage shift register, and a first terminal T16b of the switch T16 is electrically coupled to the switch T15.
  • the second terminal T15c and a second terminal T16c of the switch T16 are electrically coupled to the boost node BP.
  • the switch T16 is turned on in response to the voltage signal Q (n-1) of the previous stage shift register, turns on the first terminal T16b and the second terminal T16c of the switch T16, and outputs the first upper Pull signal Pu1 (n) to the boost node BP.
  • a control terminal T17a of the switch T17 is electrically coupled to the clock signal CK (n + 1) of the first stage shift register, and a first terminal T17b of the switch T17 is electrically coupled to the second stage shift.
  • the switch T17 is turned on in response to the clock signal CK (n + 1) of the subsequent stage shift register, and the first terminal T17b and a second terminal T17c of the switch T17 are turned on.
  • the clock signal CK (n + 2) of the rear two-stage shift register is transmitted to the second terminal T17c of the switch T17.
  • a control terminal T18a of the switch T18 is electrically coupled to the voltage signal Q (n + 1) of the post-stage shift register, and a first terminal T18b of the switch T18 is electrically coupled to the switch T17.
  • the second terminal T17c and a second terminal T18c of the switch T18 are electrically coupled to the boost node BP.
  • the switch T18 is turned on in response to the voltage signal Q (n + 1) of the subsequent stage shift register, and the first terminal T18b and the second terminal T18c of the switch T18 are turned on. And output the second pull-up signal Pu2 (n) to the boost node BP.
  • the pull-up module 32 is controlled by the voltage signal Q (n-1) of the previous stage shift register to output the first pull-up signal Pu1 and is subjected to the subsequent stage shift
  • the voltage signal Q (n + 1) of the register is controlled to output the second pull-up signal Pu2.
  • the pull-up module 32 outputs the first pull-up signal Pu1 according to the clock signal CK (n-1) of the previous stage shift register, and changes the voltage signal Qn from the first level A 'is pulled up to the second level B', and the second pull-up signal Pu2 is output according to the clock signal CK (n + 2) of the second-stage shift register, so that the voltage signal Qn is maintained At the second level B '.
  • the stage signal ST is input to the boost node BP according to the clock signal CK (n-2) of the previous two-stage shift register, so as to improve the boost node BP.
  • the voltage signal Qn to the first level A ′.
  • FIG. 3e is a waveform diagram of a voltage signal Qn of a boost node BP in an exemplary shift register circuit.
  • the boost node BP is precharged.
  • the voltage signal Qn is increased to a first level A ′, as shown in FIG. 3e.
  • the pull-up module 32 transmits the first pull-up signal Pu1 to the boost node BP, so that the voltage signal Qn of the boost node BP is changed from the first level A ′. Pull up to the second level B '.
  • the pull-up module 32 transmits the second pull-up signal Pu2 to the boost node BP, so that the voltage signal of the boost node BP can be continuously maintained at the second voltage.
  • Flat B ' When the pulse of the clock signal CK (n + 1) ends, the pull-up module will stop outputting the second pull-up signal Pu2. At this time, the voltage signal Qn of the boost node BP will be pulled down from the second level B 'to the first voltage.
  • the timing diagram of the operation of the register 3, and in order to facilitate comparison, also shows part of the operation timing of the above-mentioned fourth-stage shift register 2.
  • the shift temporary storage circuit uses eight sets of clock signals CK1-CK8 to control the operation.
  • the voltage signal Q4 'of the shift register 3 at the boost node BP can be divided into five periods: t1' is the pre-charging time of the step-up signal ST; t2 'is the time of the first pull-up signal Pu1. ; T3 'is the output gate scan signal Gn time; t4' is the second pull-up signal Pu2 action time; t5 'is the pull-down gate scan signal Gn time.
  • the stage transmission signal ST transmitted from the previous stage shift register that is, the stage transmission signal ST of the third stage shift register, performs pre-processing on the boost node BP.
  • the voltage signal Q4 ' will increase to the first level A'. That is, the switch T12 inputs the stage transmission signal ST to the boosting node BP according to the clock signal CK2.
  • the pull-up module 32 In the period t2 ', according to the clock signal CK3, the pull-up module 32 outputs the first pull-up signal Pu1, and pulls the voltage signal Q4' from the first level A 'to the second level. B ', the pulse of the first pull-up signal Pu1 will end with the pulse of the clock signal CK2.
  • the pulse of the clock signal CK4 ends, causing the voltage signal Q4' of the boost node BP to be pulled down from the third level C '.
  • the pull-up module 32 outputs the second pull-up signal Pu2, so that the voltage signal Q4 'can be maintained at the second level B'.
  • the pulse of the second pull-up signal Pu2 will end at the same time as the pulse of the clock signal CK5.
  • the shift register 3 will receive the aforementioned feedback signal FB, discharge the boost node BP, and pull down the voltage signal Q4' from the first level A 'to the pre- Set low.
  • the pull-up module 32 can generate the required first pull-up signal Pu1 and the second pull-up through different signal control modes in addition to the signal control mode shown in FIG. 3b. Signal Pu2.
  • the control terminal T15a of the switch T15 is electrically coupled to the clock signal CK (n-1) of the previous stage shift register, and the first terminal T15b is electrically coupled to the former stage two shift. Clock signal CK (n-2) of the register.
  • the control terminal T15a of the switch T15 can also be electrically coupled to the clock signal CK (n-2) of the previous two-stage shift register, and the first terminal T15b can be electrically coupled before Clock signal CK (n-1) of the first-stage shift register.
  • the switch T15 is turned on in response to the clock signal CK (n-2) of the previous two-stage shift register, and the first terminal T15b and the second terminal T15c of the switch T15 are turned on, and the previous one
  • the clock signal CK (n-1) of the stage shift register is transmitted to the second terminal T15c of the switch T15.
  • control terminal T17a of the switch T17 is electrically coupled to the clock signal CK (n + 1) of the first stage shift register, and the first terminal T17b is electrically coupled to the second stage shift register.
  • control terminal T17a of the switch T17 can also be electrically coupled to the clock signal CK (n + 2) of the second-stage shift register, while the first terminal T17b can be electrically coupled Clock signal CK (n + 1) of the first-stage shift register.
  • the switch T17 is turned on in response to the clock signal CK (n + 2) of the post-secondary shift register, and the first terminal T17b and the second terminal T17c of the switch T17 are turned on, and the The clock signal CK (n + 1) of the subsequent stage shift register is transmitted to the second terminal T17c of the switch T17.
  • a control terminal T16a of the switch T16 may also be electrically coupled to the voltage signal Q (n-2) of the front-stage shift register, and respond to the front-stage shift register.
  • the voltage signal Q (n-2) is turned on, and the first pull-up signal Pu1 (n) is output to the boost node BP.
  • a control terminal T18a of the switch T18 may also be electrically coupled to the voltage signal Q (n + 2) of the second stage shift register, and respond to the second stage shift register.
  • the voltage signal Q (n + 2) of the bit register is turned on, and the second pull-up signal Pu2 (n) is output to the boost node BP.
  • FIG. 3c is a schematic structural diagram of a module of a shift temporary storage circuit in a second embodiment of the present application.
  • FIG. 3d is a schematic circuit structure diagram of a shift temporary storage circuit in the second embodiment of the present application.
  • FIG. 3e is a schematic diagram of a voltage signal waveform of a boosting node in a shift temporary storage circuit according to an embodiment of the present application.
  • a shift element temporary storage circuit includes a multi-stage shift register.
  • a shift register 4 mainly includes an input module 41, a coupling pull-up module 42, An output module 43 and a feedback module 44.
  • the shift register circuit includes an n-stage shift register, where n is a positive integer, and the n-stage shift register 4 is shown in FIG. 3c.
  • the input module 41 is configured to input the stage transmission signal ST of the previous stage shift register to a boosting node BP.
  • the stage transmission signal ST of the previous stage shift register may be input to improve the The voltage signal Qn of the boosting node BP reaches a first level A ′, as shown in FIG. 3e. It should be particularly pointed out that although in this embodiment, the stage transmission signal ST of the previous stage shift register is input, but depending on the signal configuration, the first two stages, the first three stages, or It is the stage signal ST of other previous stage shift registers.
  • the coupled pull-up module 42 is coupled to the boost node BP and is used to generate a first pull-up signal Pu1 and a second pull-up signal Pu2.
  • the first pull-up signal Pu1 can indirectly act on the boosting node BP through electrical coupling, and couples the voltage signal Qn from the first level A ′ to the second level B.
  • the second pull-up signal Pu2 can indirectly act on the boosting node BP through electrical coupling and maintain the voltage signal Qn at the second level B', as shown in FIG. 3e.
  • the output module 43 receives a clock signal CKn and couples the voltage signal Qn from the second high level B ′ to the third high level C ′ according to the clock signal CKn, as shown in FIG. 3e .
  • the output module 43 is controlled and turned on by the coupled voltage signal Qn, and outputs a gate scan signal Gn through an output terminal O.
  • the coupling pull-up module 42 When the pulse of the clock signal CKn ends, the coupling pull-up module 42 generates the second pull-up signal Pu2 and indirectly acts on the boost node BP through electrical coupling, so that the voltage signal Qn is maintained At the second level B '.
  • the feedback module 44 receives a feedback signal FB, and couples the voltage signal Qn and the gate scan signal Gn after coupling the boost node BP to a preset low level Vss.
  • the shift register 4 further includes a sub-pull-down control module 45 and a sub-pull-down module 46.
  • the sub pull-down module 46 is configured to maintain the voltage signal Qn at the preset low level Vss.
  • the sub pull-down control module 45 it is used to control the operation of the sub pull-down module 46.
  • the output module 43 includes a switch T21.
  • a control terminal T21a of the switch T21 is electrically coupled to the boost node BP, a first terminal T21b of the switch T21 is used to receive the clock signal CKn, and a second terminal T21c of the switch T21 is electrically coupled Connected to the output terminal O for outputting the gate scan signal Gn.
  • the switch T21 is turned on and outputs the gate scan signal Gn.
  • the input module 41 includes a switch T22, a control terminal T22a of the switch T22 is electrically coupled to a first terminal T22b of the switch T22, and a second terminal T22c of the switch T22 is electrically coupled to the amplifier T22.
  • the voltage node BP is configured to output the stage transmission signal ST to the boost node BP, so as to increase the voltage signal Qn of the boost node BP to the first level A ′.
  • the feedback module 44 includes a switch T23 and a switch T24.
  • a control terminal T23a of the switch T23 is electrically coupled to a feedback signal FB
  • a first terminal T23b of the switch T23 is electrically coupled to the output terminal O
  • a second terminal T23c of the switch T23 Electrically coupled to the preset low level Vss.
  • the switch T23 is turned on in response to the feedback signal FB, and the first terminal T23b and the second terminal T23c of the switch T23 are turned on to pull the gate scan signal Gn to the preset low level Vss.
  • a control terminal T24a of the switch T24 is electrically coupled to the feedback signal FB, a first terminal T24b of the switch T24 is electrically coupled to the boost node BP, and a second terminal of the switch T24 is The terminal T24c is electrically coupled to the preset low level Vss.
  • the switch T24 is turned on in response to the feedback signal FB, and the first terminal T24b and the second terminal T24c of the switch T24 are turned on to pull the voltage signal Qn to a preset low level Vss.
  • the coupling pull-up module 42 includes a switch T25, a switch T26, a switch T27, a switch T28, and a switch T29.
  • a control terminal T25a of the switch T25 is electrically coupled to the clock signal CK (n-1) of the previous-stage shift register, and a first terminal T25b of the switch T25 is electrically coupled to the front-stage shift.
  • the switch T25 is turned on in response to the clock signal CK (n-1) of the previous stage shift register, and the first terminal T25b and the second terminal T25c of the switch T25 are turned on, and the first two The clock signal CK (n-2) of the stage shift register is transmitted to the second terminal T25c of the switch T25.
  • a control terminal T26a of the switch T26 is electrically coupled to the voltage signal Q (n-1) of the previous stage shift register, and a first terminal T26b of the switch T26 is electrically coupled to the switch T25.
  • the second terminal T25c, a second terminal T26c of the switch T26 is electrically coupled to a first terminal T29b of the switch T29, and is coupled to the boost node BP through the switch T29.
  • the switch T26 is turned on in response to the voltage signal Q (n-1) of the previous stage shift register, turns on the first terminal T26b and the second terminal T26c of the switch T26, and outputs the first upper Pull signal Pu1 (n).
  • a control terminal T27a of the switch T27 is electrically coupled to the clock signal CK (n + 1) of the first stage shift register, and a first terminal T27b of the switch T27 is electrically coupled to the second stage shift.
  • the switch T27 is turned on in response to the clock signal CK (n + 1) of the subsequent stage shift register, and the first terminal T27b and a second terminal T27c of the switch T27 are turned on.
  • the clock signal CK (n + 2) of the last two-stage shift register is transmitted to the second terminal T27c of the switch T27.
  • a control terminal T28a of the switch T28 is electrically coupled to the voltage signal Q (n + 1) of the post-stage shift register, and a first terminal T28b of the switch T28 is electrically coupled to the switch T27.
  • the second terminal T27c, a second terminal T28c of the switch T28 is electrically coupled to the first terminal T29b of the switch T29, and is coupled to the boost node BP through the switch T29.
  • the switch T28 is turned on in response to the voltage signal Q (n + 1) of the subsequent stage shift register, and the first terminal T28b and the second terminal T28c of the switch T28 are turned on. And output the second pull-up signal Pu2 (n).
  • a control terminal T29a of the switch T29 is electrically coupled to the boost node BP, and a first terminal T29b of the switch T29 is used to receive the first pull-up signal Pu1 and the second pull-up signal Pu2, A second terminal T29b of the switch T29 is electrically coupled to the preset low-level Vss, wherein the switch T29 is turned on in response to the voltage signal Qn and turns on the first of the switch T29.
  • the terminal T29b and the second terminal T29c is electrically coupled to the boost node BP, and a first terminal T29b of the switch T29 is used to receive the first pull-up signal Pu1 and the second pull-up signal Pu2, A second terminal T29b of the switch T29 is electrically coupled to the preset low-level Vss, wherein the switch T29 is turned on in response to the voltage signal Qn and turns on the first of the switch T29.
  • the first terminal T29b of the switch T29 receives the first pull-up signal Pu1
  • it is coupled to the control terminal T29a of the switch T29, and the voltage signal Qn of the boosting node BP is pulled up to the second level B '.
  • the second terminal T29c of the switch T29 receives the second pull-up signal Pu2
  • it is also coupled to the control terminal T29a of the switch T29, and the voltage signal Qn of the boost node BP is maintained at the second level B '.
  • the coupling pull-up module 42 is controlled by the voltage signal Q (n-1) of the previous stage shift register to generate the first pull-up signal Pu1, and convert the voltage signal Qn is coupled to the first level A ′ and pulled up to the second level B ′, and is controlled by the voltage signal Q (n + 1) of the subsequent stage shift register to generate the second
  • the pull-up signal Pu2 is electrically coupled to the boost node, so that the voltage signal Qn is maintained at the second level.
  • the coupling pull-up module 42 generates the first pull-up signal Pu1 according to the clock signal CK (n-1) of the previous stage shift register, and converts the voltage signal Qn from the first voltage Level A ′ is coupled up to the second level B ′, and the second pull-up signal Pu2 is generated according to the clock signal CK (n + 2) of the second-stage shift register, and is electrically coupled to the second level
  • the boosting node maintains the voltage signal Qn at the second level B ′.
  • the stage signal ST is input to the boost node BP according to the clock signal CK (n-2) of the previous two-stage shift register to improve the boost node BP.
  • the voltage signal Qn to the first level A ′.
  • FIG. 3e is a waveform diagram of a voltage signal Qn of a boost node BP in an exemplary shift register circuit.
  • the boost node BP is precharged.
  • the voltage signal Qn is increased to a first level A ′, as shown in FIG. 3e.
  • the coupling pull-up module 42 generates a first pull-up signal Pu1, and electrically couples the voltage signal Qn of the boosting node BP from the first level A ′ through electrical coupling.
  • the coupling is pulled up to a second level B '.
  • the coupling pull-up module 42 generates a second pull-up signal Pu2, and indirectly acts on the boost node BP through electrical coupling, so that the voltage of the boost node BP The signal can be continuously maintained at the second level B '.
  • the coupled pull-up module When the pulse of the clock signal CK (n + 1) ends, the coupled pull-up module will stop outputting the second pull-up signal Pu2, and the voltage signal Qn of the boost node BP will be pulled down from the second level B 'to the first Level A '.
  • the shift temporary storage circuit uses eight sets of clock signals CK1-CK8 to control the operation.
  • the voltage signal Q4 'of the shift register 4 at the boosting node BP can be divided into five periods: t1' is the pre-charging time of the stage signal ST; t2 'is the coupling effect of the first pull-up signal Pu1 Time; t3 'is the output gate scan signal Gn time; t4' is the second pull-up signal Pu2 coupling time; t5 'is the pull-down gate scan signal Gn time.
  • the stage transmission signal ST transmitted from the previous stage shift register that is, the stage transmission signal ST of the third stage shift register, performs pre-processing on the boost node BP.
  • the voltage signal Q4 ' will increase to the first level A'. That is, the switch T22 inputs the stage transmission signal ST to the boosting node BP according to the clock signal CK2.
  • the coupling pull-up module 42 In the period t2 ′, according to the clock signal CK3, the coupling pull-up module 42 generates the first pull-up signal Pu1, which is electrically coupled with the boost node BP, and the voltage signal Q4 ′ is changed from the first level A ′ is coupled up to the second level B ′, and the pulse of the first pull-up signal Pu1 will end with the pulse of the clock signal CK2.
  • the pulse of the clock signal CK4 ends, causing the voltage signal Q4' of the boost node BP to be pulled down from the third level C '.
  • the coupling pull-up module 42 generates the second pull-up signal Pu2, which is electrically coupled with the boost node BP, so that the voltage signal Q4 'can be maintained at the second level B. '.
  • the pulse of the second pull-up signal Pu2 will end at the same time as the pulse of the clock signal CK5.
  • the shift register 4 will receive the aforementioned feedback signal FB, discharge the boost node BP, and pull down the voltage signal Q4' from the first level A 'to the pre- Set low.
  • the coupled pull-up module 42 can generate the required first pull-up signal Pu1 and the second pull-up through different signal control modes in addition to the signal control mode shown in FIG. 3d. Pull signal Pu2.
  • the control terminal T25a of the switch T25 is electrically coupled to the clock signal CK (n-1) of the previous stage shift register, and the first terminal T25b is electrically coupled to the former stage two shift. Clock signal CK (n-2) of the register.
  • the control terminal T25a of the switch T25 can also be electrically coupled to the clock signal CK (n-2) of the former two-stage shift register, and the first terminal T25b can be electrically coupled before Clock signal CK (n-1) of the first-stage shift register.
  • the switch T25 is turned on in response to the clock signal CK (n-2) of the first-stage shift register, and the first terminal T25b and the second terminal T25c of the switch T25 are turned on, and the previous one
  • the clock signal CK (n-1) of the stage shift register is transmitted to the second terminal T25c of the switch T25.
  • control terminal T27a of the switch T27 is electrically coupled to the clock signal CK (n + 1) of the first stage shift register, and the first terminal T27b is electrically coupled to the second stage shift register.
  • control terminal T27a of the switch T27 can also be electrically coupled to the clock signal CK (n + 2) of the second-stage shift register, while the first terminal T27b can be electrically coupled Clock signal CK (n + 1) of the first-stage shift register.
  • the switch T27 is turned on in response to the clock signal CK (n + 2) of the post-secondary shift register, and the first terminal T27b and the second terminal T27c of the switch T27 are turned on, and the The clock signal CK (n + 1) of the subsequent stage shift register is transmitted to the second terminal T27c of the switch T27.
  • a control terminal T26a of the switch T26 may also be electrically coupled to the voltage signal Q (n-2) of the front-stage shift register, and respond to the front-stage shift register.
  • the voltage signal Q (n-2) of the device is turned on, and the first pull-up signal Pu1 (n) is output.
  • a control terminal T28a of the eighth switch T28 can also be electrically coupled to the voltage signal Q (n + 2) of the second stage shift register, and respond to the second stage shift register.
  • the voltage signal Q (n + 2) of the stage shift register is turned on, and the second pull-up signal Pu2 (n) is output.
  • FIG. 5 is a schematic diagram of a display device according to an embodiment of the present application.
  • the display device 12 includes an active switch array substrate 121, a pair of opposing substrates 120 disposed opposite to the active switch array substrate 121, and an array substrate gate driving circuit 122, wherein the array substrate gate
  • the pole driving circuit 122 is directly fabricated on the surface of the active switch array substrate 121 by a lithography process.
  • the gate driving circuit 122 of the array substrate includes a shift register circuit shown in FIG. 3c and FIG. 3d. That is, the gate driving circuit 110 of the array substrate has a plurality of shift registers 3 or 4.
  • This application uses a coupling pull-up module to output the first pull-up signal Pu1, which indirectly acts on the boost node through electrical coupling, so that the voltage signal of the boost node is pulled up to a higher level. Therefore, when the clock signal is electrically coupled with the output module, it can ensure that the switch is opened quickly, so that the shift register can accurately and smoothly output the gate scan signal.
  • a second pull-up signal Pu2 is also output, which indirectly acts on the boost node through electrical coupling to maintain the boost node. The voltage signal is at a high level, so the gate scan signal can be accelerated to pull down, thereby improving the tailing phenomenon of the gate scan signal, thereby improving the quality of the display screen.

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Abstract

一种显示装置及其移位暂存电路(4)，移位暂存电路(4)包括多级移位暂存器(4)，其中任一级移位暂存器(4)包括下列模块：输入模块(41)，输入级传信号(ST)至增压节点(BP)。耦合上拉模块(42)，产生第一上拉信号(Pu1)，将电压信号(Qn)由第一电平(A')耦合拉高至第二电平(B')。输出模块(43)，根据时钟信号(CKn)，将电压信号(Qn)从第二电平(B')耦合拉高至第三电平(C')，并经由输出端(O)输出栅极扫描信号(Gn)。当时钟信号(CKn)的脉冲结束时，耦合上拉模块(42)产生第二上拉信号(Pu2)，耦合作用于增压节点(BP)，将电压信号(Qn)维持于第二电平(B')。反馈模块(44)，接收反馈信号(FB)，将电压信号(Qn)以及栅极扫描信号(Gn)，拉低至预设低电平(Vss)。

Description

显示装置及移位暂存电路 技术领域
本申请涉及显示面板的技术领域，尤其涉及一种具有阵列基板栅极驱动电路的显示装置及其移位暂存电路。
背景技术
近年来，液晶显示器(Liquid Crystal Display，LCD)因其图像清晰精确、平面显示、厚度薄、重量轻、无辐射、低能耗、工作电压低等优点已被广泛的使用。传统的液晶显示器在进行栅极驱动时，主要采用栅极驱动芯片(Gate Driver 1C)来实现。由于栅极驱动芯片需要通过连接器与显示面板(Panel)连接，并且在一个液晶显示器中需要使用多个栅极驱动芯片，因此液晶显示器的制造成本仍然偏高。
随着新技术的开发，许多液晶显示面板已采用阵列基板栅极驱动(Gate Driver on Array,GOA)技术来取代外接的栅极驱动芯片。阵列基板栅极驱动技术，是透过曝光显影的制程，将栅极驱动集成电路直接制作在主动开关阵列基板表面，从而省掉外接的栅极驱动芯片。从材料成本和工艺步骤两个方面来看，阵列基板栅极驱动技术能大幅的降低产品的成本，并且还可使进一步降低液晶显示面板的功耗。
典型的阵列基板栅极驱动电路具有多级的移位暂存器，每一个移位暂存器在对栅极讯号线进行扫描驱动时，其栅极电压点将接收一个预充信号，对栅极电压点进行预充，使该点电压在时钟信号的作用下达到高电压准位，进而使得控制输出的薄膜晶体管(Thin-Film Transistor,TFT)打开，顺利的传递讯号，进而驱动面板栅极讯号线。因此，对于基板栅极驱动电路的移位暂存器来说，必需能稳定且精确的输出栅极驱动讯号，才不致于发生误动作造成噪声，从而影响了显示器的画质呈现。
发明内容
本申请提出了一种显示装置及其移位暂存电路，能准确且顺利的输出栅极扫描信号，并且能改善栅极扫描信号的拖尾现象，进而提升了显示装置的画质。
本申请提出一种移位暂存电路，包括多级移位暂存器，其中任一级移位暂存器包括：输入模块，输入前级移位暂存器的级传信号至一增压节点，以提高所述增压节点的电压信号Qn至第一电平；耦合上拉模块，耦接于所述增压节点，用于产生一第一上拉信号与一第二上拉信号，其中所述第一上拉信号，可透过电性耦合，将所述电压信号Qn由所述第一电平耦合拉高至第二电平；输出模块，接收一时钟信号CKn，并根据所述时钟信号CKn将所述电压信号Qn从所述第二电平耦合拉高至第三电平，所述输出模块受到所述第三电平的所述电压信号Qn控制，会经由一输出端输出一栅极扫描信号，其中当所述时钟信号CKn的脉冲结束时，所述耦合上拉模块会产生所述第二上拉信号，并透过电性耦合，将所述电压信号Qn维持于所述第二电平；以及反馈模块，接收一反馈信号，将所述增压节点耦合后的所述电压信号Qn以及所述栅极扫描信号，拉低至一预设低电平。
在一实施例中，所述任一级移位暂存器还包括一子下拉模块，用于维持所述电压信号Qn于所述预设低电平；以及一子下拉控制模块，用于控制所述子下拉模块的操作。
在一实施例中，所述子下拉模块电性耦接于所述增压节点、所述栅极扫描信号及所述预设低电位。
在一实施例中，所述输出模块包括一第一开关，所述第一开关的一控制端电性耦接所述增压节点，所述第一开关的一第一端用于接收所述时钟信号CKn，所述第一开关的一第二端电性耦接所述输出端，用于输出所述栅极扫描信号，其中当所述增压节点的电压信号Qn耦合提高至所述第三电平时，所述第一开关会开启并输出所述栅极扫描信号。
在一实施例中，所述输入模块包括一第二开关，所述第二开关的一控制端电性耦接所述所述第二开关的一第一端，所述第二开关的一第二端用于输出所述级传信号。
在一实施例中，所述反馈模块包括:一第三开关，所述第三开关的一控制端电性耦接于一反馈信号，所述第第三开关的一第一端电性耦接于所述输出端，所述第三开关的一第二端电性耦接于所述预设低电平，其中所述第三开关回应于所述反馈信号而开启，导通所述第三开关的所述第一端与所述第二端，将所述栅极扫描信号拉低至所述预设低电平；以及一第四开关，所述第四开关的一控制端电性耦接于所述反馈信号，所述第四开关的一第一端电性耦接于所述增压节点，所述第四开关的一第二端电性耦接于所述预设低电平，其中所述第四开关回应于所述反馈信号而开启，导通所述第四开关的所述第一端与所述第二端，将所述电压信号Qn拉低至所述预设低电平。
在一实施例中，所述耦合上拉模块包括:一第五开关，所述第五开关的一控制端电性耦接前一级移位暂存器的时钟信号CK(n-1)，所述第五开关的一第一端电性耦接前二级移位暂存器的时钟信号CK(n-2)，其中所述第五开关回应于所述前一级移位暂存器的时钟信号CK(n-1)而开启，导通所述第五开关的所述第一端与一第二端，将所述前二级移位暂存器的时钟信号CK(n-2)传送至所述第五开关的所述第二端；一第六开关，所述第六开关的一控制端电性耦接前一级移位暂存器的电压信号Q(n-1)，所述第六开关的一第一端电性耦接所述第五开关的所述第二端，所述第六开关的一第二端电性耦接所述增压节点，其中所述第六开关回应于所述前一级移位暂存器的电压信号Q(n-1)而开启，导通所述第六开关的所述第一端与所述第二端，并输出所述第一上拉信号；一第七开关，所述第七开关的一控制端电性耦接后一级移位暂存器的时钟信号CK(n+1)，所述第七开关的一第一端电性耦接后二级移位暂存器的时钟信号CK(n+2)，其中所述第七开关回应于所述后一级移位暂存器的时钟信号CK(n+1)而开启，导通所述第七开关的所述第一端与一第二端，将所述后二级移位暂存器的时钟信号CK(n+2)传送至所述第七开关的所述第二端；以及一第八开关，所述第八开关的一控制端电性耦接后一级移位暂存器的电压信号Q(n+1)，所述第八开关的一第一端电性耦接所述第七开关的所述第二端，所述第八开关的一第二端电性耦接所述增压节点，其中所述第八开关回应于所述后一级移位暂存器的电压信号Q(n+1)而开启，导通所述第八开关的所述第一端与所述第二端，并输出所述第二上拉信号。
在一实施例中，所述第六开关的所述第二端电性耦接所述第八开关的所述第二端。
在一实施例中，所述耦合上拉模块还包括第九开关，所述第九开关的一控制端电性耦接所述增压节点，所述第九开关的一第一端电性耦接所述第六开关的所述第二端以及所述第八开关的所述第二端，所述第九开关的一第二端电性耦接于所述预设低电平，其中所述第九开关回应于所述电压信号而开启，导通所述第九开关的所述第一端与所述第二端。
在一实施例中，所述耦合上拉模块还包括一第九开关，所述第九开关的一控制端电性耦接所述增压节点，所述第九开关的一第一端用于接收所述第一上拉信号与所述第二上拉信号，所述第九开关的一第二端电性耦接于所述预设低电平，其中所述第九开关回应于所述电压信号而开启，导通所述第九开关的所述第一端与所述第二端。
在一实施例中，所述耦合上拉模块是受到前一级移位暂存器的电压信号Q(n-1)控制而产生所述第一上拉信号，将所述电压信号Qn由所述第一电平耦合拉高至所述第二电平，并且是受到后一级移位暂存器的电压信号Q(n+1)控制而产生所述第二上拉信号，电性耦合至所述增压节点，使所述电压信号Qn维持于所述第二电平。
在一实施例中，所述耦合上拉模块是根据前一级移位暂存器的时钟信号CK(n-1)产生所述第一上拉信号，将所述电压信号Qn由所述第一电平耦合拉高至所述第二电平，并且根据后二级移位暂存器的时钟信号CK(n+2)产生所述第二上拉信号，电性耦合至所述增压节点，使所述电压信号Qn维持于所述第二电平。
本申请并提出一种显示装置，所述显示装置包括一主动开关阵列基板以及一对向基板，与 所述主动开关阵列基板对向设置，其中所述主动开关阵列基板上制作了阵列基板栅极驱动电路，且所述阵列基板栅极驱动电路包括上述各种实施例中所述的移位暂存电路，所述移位暂存电路包括多级移位暂存器，其中任一级移位暂存器包括：输入模块，输入前级移位暂存器的级传信号至增压节点；耦合上拉模块，耦接于所述增压节点，用于产生第一上拉信号与第二上拉信号，其中所述第一上拉信号，透过电性耦合，将所述电压信号由第一电平耦合拉高至第二电平；输出模块，接收时钟信号，并根据所述时钟信号将所述电压信号从所述第二电平耦合拉高至第三电平，所述输出模块受到所述第三电平的所述电压信号控制，经由输出端输出栅极扫描信号，其中当所述时钟信号的脉冲结束时，所述耦合上拉模块产生所述第二上拉信号，并透过电性耦合，将所述电压信号维持于所述第二电平；以及反馈模块，接收反馈信号，将所述增压节点的所述电压信号以及所述栅极扫描信号，拉低至预设低电平。
在一实施例中，所述输出模块包括第一开关，所述第一开关的一控制端电性耦接所述增压节点，所述第一开关的一第一端用于接收所述时钟信号，所述第一开关的一第二端电性耦接所述输出端，用于输出所述栅极扫描信号，其中当所述增压节点的电压信号耦合提高至所述第三电平时，所述第一开关开启并输出所述栅极扫描信号。
在一实施例中，所述输入模块包括第二开关，所述第二开关的一控制端电性耦接所述所述第二开关的第一端，所述第二开关的第二端用于输出所述级传信号。
在一实施例中，所述反馈模块包括第三开关，所述第三开关的一控制端电性耦接于所述反馈信号，所述第第三开关的一第一端电性耦接于所述输出端，所述第三开关的一第二端电性耦接于所述预设低电平，其中所述第三开关回应于所述反馈信号而开启，导通所述第三开关的所述第一端与所述第二端，将所述栅极扫描信号拉低至所述预设低电平。
在一实施例中，所述反馈模块包括第四开关，所述第四开关的一控制端电性耦接于所述反馈信号，所述第四开关的一第一端电性耦接于所述增压节点，所述第四开关的一第二端电性耦接于所述预设低电平，其中所述第四开关回应于所述反馈信号而开启，导通所述第四开关的所述第一端与所述第二端，将所述电压信号拉低至所述预设低电平。
在一实施例中，所述耦合上拉模块包括:第五开关，所述第五开关的一控制端电性耦接前一级移位暂存器的时钟信号，所述第五开关的一第一端电性耦接前二级移位暂存器的时钟信号，其中所述第五开关回应于所述前一级移位暂存器的时钟信号而开启，导通所述第五开关的所述第一端与一第二端，将所述前二级移位暂存器的时钟信号传送至所述第五开关的所述第二端；第六开关，所述第六开关的一控制端电性耦接前一级移位暂存器的电压信号，所述第六开关的一第一端电性耦接所述第五开关的所述第二端，所述第六开关的一第二端电性耦接所述增压节点，其中所述第六开关回应于所述前一级移位暂存器的电压信号而开启，导通所述第六开关的所述第一端与所述第二端，并输出所述第一上拉信号；第七开关，所述第七开关的一控制端电性耦接后一级移位暂存器的时钟信号，所述第七开关的一第一端电性耦接后二级移位暂存器的时钟信号，其中所述第七开关回应于所述后一级移位暂存器的时钟信号而开启，导通所述第七开关的所述第一端与一第二端，将所述后二级移位暂存器的时钟信号传送至所述第七开关的所述第二端；以及第八开关，所述第八开关的一控制端电性耦接后一级移位暂存器的电压信号，所述第八开关的一第一端电性耦接所述第七开关的所述第二端，所述第八开关的一第二端电性耦接所述增压节点，其中所述第八开关回应于所述后一级移位暂存器的电压信号而开启，导通所述第八开关的所述第一端与所述第二端，并输出所述第二上拉信号。
在一实施例中，所述耦合上拉模块还包括第九开关，所述第九开关的一控制端电性耦接所述增压节点，所述第九开关的一第一端用于接收所述第一上拉信号与所述第二上拉信号，所述第九开关的一第二端电性耦接于所述预设低电平，其中所述第九开关回应于所述电压信号而开启，导通所述第九开关的所述第一端与所述第二端。
本申请由于使用了一耦合上拉模块，透过电性耦合，间接作用于增压节点，因此可将增压 节点的电压信号上拉至更高的电平，使移位暂存器能准确且顺利的输出栅极扫描信号。并且，由于耦合上拉模块，在栅极扫描信号的脉冲结束时，还会输出上拉信号，透过电性耦合，间接作用于增压节点，维持增压节点的电压信号于一高电平，因此可加速下拉栅极扫描信号，进而改善栅极扫描信号的拖尾现象，从而提升显示画面的品质。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其他目的、特征和优点能够更明显易懂，以下特举具体实施例，并配合附图,详细说明如下。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1a是一示例性的显示器示意图。
图1b是本申請一实施例的显示器示意图。
图2a是一示例性的移位暂存电路示意图。
图2b是一示例性的移位暂存电路中增压节点的电压信号波形示意图。
图2c是一示例性的移位暂存电路的工作时序示意图。
图3a是本申請第一实施例中的移位暂存电路的模块结构示意图。
图3b是本申請第一实施例中的移位暂存电路的电路结构示意图。
图3c是本申請第二实施例中的移位暂存电路的模块结构示意图。
图3d是本申請第二实施例中的移位暂存电路的电路结构示意图。
图3e是本申請一实施例中移位暂存电路中增压节点的电压信号波形示意图。
图4是本申請一实施例中的移位暂存电路的工作时序示意图。
图5是本申請一实施例的显示装置示意图。
具体实施方式
这里所公开的具体电路结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“直向”、“横向”、“上”、“下”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“配置”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个组件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一条”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体实施例，对依据本申请提出的一种移位暂存电路及其波形产生方法与其应用的显示装置，其具体实施方式、结构、特征及其功效，详细说明如后。
在某些实施例中，显示装置可例如为液晶显示装置、OLED显示装置、QLED显示装置、曲面显示装置或其他显示装置。以液晶显示装置为例，液晶显示装置包括主动开关阵列基板(array glass substrate)、对向基板与形成于两基板间的液晶层。当然，随着需求上的不同，本申请的薄膜晶体管阵列(TFT array)及彩色滤光片(CF)也可形成于同一基板上。另外，本申请的显示装置也可制作为一曲面型的显示装置。
图1a为范例性的显示装置示意图。请参照图1a，一种显示装置10,包括一主动开关阵列基板101、一对向基板100与所述主动开关阵列基板101对向设置、以及栅极驱动芯片102用以驱动电路。如图1a所示，栅极驱动芯片102是以外接的方式连接于主动开关阵列基板101的右侧。
图1b为本申請一实施例的显示装置示意图。请参照图1b，在本申請一实施例中，一种具有阵列基板栅极驱动的显示装置12，包括一主动开关阵列基板121、一对向基板120与所述主动开关阵列基板121对向设置、以及阵列基板栅极驱动电路122,其中阵列基板栅极驱动电路122以微影制程直接制作在主动开关阵列基板121的表面上。如图1b所示，阵列基板栅极驱动电路122分别制作于主动开关阵列基板121左右两侧的表面上。
图2a为本申請一示例性的移位暂存电路示意图。请参图2a，一种移位暂存电路，包括多级移位暂存器，任一移位暂存器2包括一第一开关T1、—第二开关T2、—第三开关T3、一第四开关T4、一子下拉控制模块(sub pull down controller)21、以及一子下拉模块(sub pull down)22。在一实施例中，所述移位暂存电路包括了n级移位暂存器，其中n为正整数，图2a所显示的则为第n级移位暂存器2。
所述第一开关T1的一控制端T1a电性耦接一增压节点(boost point)BP，所述第一开关T1的一第一端T1b电性耦接一时钟讯号CK，所述第一开关T1的一第二端T1c电性耦接一输出端O，以输出栅极扫描信号Gn。
所述第二开关T2电性耦接前一级移位暂存器的级传(stage transmitting)信号ST，用于输入级传信号ST至所述增压节点BP，以提高增压节点BP的电压信号Qn的电平。所述第二开关T2的一控制端T2a与一第一端T2b电性耦接所述级传信号ST，所述第二开关T2的一第二端T2c电性耦接所述增压节点BP。
所述第三开关T3的一控制端T3a电性耦接一反馈信号FB，所述第三开关T3的一第一端T3b电性耦接所述输出端O的栅极扫描信号Gn，所述第三开关T3的一第二端T3c电性耦接一预设低电平Vss。
所述第四开关T4的一控制端T4a电性耦接所述反馈信号FB，所述第四开关T4的一第一端T4b电性耦接所述增压节点BP，所述第四开关T4的一第二端T4c电性耦接所述预设低电平Vss。
所述子下拉模块22，电性耦接于所述移位暂存器2的所述增压节点BP、所述栅极扫描信号Gn及所述预设低电位Vss，用于维持所述电压信号Qn与所述栅极扫描信号Gn于所述预设低电平Vss。
所述子下拉控制模块21，电性耦接于所述移位暂存器2的所述低预设电位Vss及所述子下拉模块22，用于控制所述子下拉模块22于正确的时间进行操作。亦即，透过子下拉模块22，可消除增压节点BP与输出端O的噪声，确保电压信号Qn以及栅极扫描信号Gn，在非操作时 间内能持续维持于预设低电平Vss，避免发生误动作。
图2b为示例性的移位暂存电路中增压节点BP的电压信号Qn波形示意图。请同时搭配参考图2a，当图2a中前一级移位暂存器(n-1)的级传信号ST，传送至所述增压节点BP时，会对增压节点BP进行预充电，将电压信号Qn提高至一电平A，如图2b所示。随后，当时钟信号CK施加于第一开关T1的第一端T1b时，会产生电性耦合，使增压节点BP的电压信号Qn从预充后的电平A进一步提高至电平B，如图2b所示。耦合后的电压信号Qn施加于第一开关T1的控制端T1a，会使第一开关T1打开，将第一端T1a上的时钟信号CK传送至第二端T1b，并经由输出端O输出，而产生所述的栅极扫描信号Gn。随后，如图2b所示，随着时钟信号CK的结束，增压节点BP的电压信号Qn从耦和后的电平B降低至预充后的电平A。
图2c为本申請一实施例中移位暂存电路的工作时序示意图。图2c用于显示一第4级(n＝4)移位暂存器2的工作时序图。如图2c所示，移位暂存电路使用了八组时钟信号CK1-CK8来控制操作。其中，移位暂存器2于增压节点BP处的电压信号Q4，可以分为三个时段:t1为预充电时间；t2为输出栅极扫描信号时间；t3则为下拉栅极扫描信号时间。
在时段t1，由于接收了由前一级移位暂存器传送过来的级传信号ST，即第3级移位暂存器的级传信号ST，对增压节点BP进行预充电，因此电压信号Q4会提高至电平A。亦即，第二开关T2会跟随前二级移位暂存器的时钟信号CK(n-2)的脉冲，即图2c中时钟信号CK2的脉冲，输入所述级传信号ST至所述增压节点BP，以提高所述增压节点BP的电压信号Q4至所述电平A。
在时段t2，由于时钟信号CK4，与增压节点BP产生电性耦合，因此电压信号Q4从电平A耦合提高至电平B，并且使图2a中的第一开关T1打开，而导通时钟信号CK4，并输出栅极扫描信号。
随后，在时段t3，由于时钟信号CK4的脉冲结束，因此增压节点BP的电压信号Q4，会从电平B下拉至电平A。其后，跟随时钟信号CK8的脉冲，移位暂存器2会接收前述的反馈信号FB，对增压节点BP进行放电，将电压信号Q4从电平A下拉至预设低电平。
接着，请参考图3a、图3b与图3e。图3a为本申請第一实施例中的移位暂存电路的模块结构示意图。图3b为本申請第一实施例中的移位暂存电路的电路结构示意图。图3e为本申請一实施例中移位暂存电路中增压节点的电压信号波形示意图。
请同时参考图3a与图3e，一种移位暂存电路，包括多级移位暂存器，其中一移位暂存器3主要包括一输入模块31、一上拉模块32、一输出模块33、一反馈模块34。在一实施例中，所述移位暂存电路包括了n级移位暂存器，其中n为正整数，图3a所显示的为第n级移位暂存器3。
所述输入模块31，用于输入前级移位暂存器的级传信号ST至一增压节点BP，例如，可输入前一级移位暂存器的级传信号ST，以提高所述增压节点BP的电压信号Qn至第一电平A’，如图3e所示。要特别指出的是，尽管此实施例中，输入的是前一级移位暂存器的级传信号ST，但是随着信号配置的不同，亦可选择输入前二级、前三级、或是其它前级(n-x)移位暂存器的级传信号ST。
所述上拉模块32，用于输出一第一上拉信号Pu1至所述增压节点BP，将所述电压信号Qn由所述第一电平A’拉高至第二电平B’，并且输出一第二上拉信号Pu2至所述增压节点BP，使所述电压信号Qn维持于所述第二电平B’，如图3e所示。
所述输出模块33，接收一时钟信号CKn，并根据所述时钟信号CKn将所述电压信号Qn从第二高电平B’耦合拉高至第三高电平C’，如图3e所示。并且，输出模块33会受到耦合后的电压信号Qn控制而开启，经由一输出端O输出一栅极扫描信号Gn。当所述时钟信号CKn的脉冲结束时，所述上拉模块32会输出所述第二上拉信号Pu2至所述增压节点BP，使所述电压信号Qn维持于第二电平B’。
所述反馈模块34，接收一反馈信号FB，将所述增压节点BP耦合后的电压信号Qn以及栅极扫描信号Gn，拉低至预设低电平Vss。
在一实施例中，所述移位暂存器3包括还包括一子下拉控制模块35以及一子下拉模块36。其中，子下拉模块36，用于维持所述电压信号Qn于所述预设低电平Vss。至于，子下拉控制模块35，则用于控制所述子下拉模块36的操作。
接着，请参考图3b，图3b显示了上述第n级移位暂存器3的详细电路结构。所述输出模块33包括开关T11。所述开关T11的一控制端T11a电性耦接所述增压节点BP，所述开关T11的第一端T11b用于接收所述时钟信号CKn，所述开关T11的第二端T11c电性耦接所述输出端O，用于输出所述栅极扫描信号Gn。其中，当所述增压节点BP的电压信号Qn耦合提高至所述第三电平C’时，所述开关T11会开启并输出所述栅极扫描信号Gn。
所述输入模块31包括开关T12，所述开关T12的一控制端T12a电性耦接所述所述开关T12的第一端T12b，所述开关T12的第二端T12c电性耦接所述增压节点BP，用于输出所述级传信号ST至所述增压节点BP，以提高增压节点BP其电压信号Qn至所述第一电平A’。
所述反馈模块34包括开关T13与开关T14。其中，所述开关T13的一控制端T13a电性耦接于一反馈信号FB，所述开关T13的第一端T13b电性耦接于所述输出端O，所述开关T13的第二端T13c电性耦接于所述预设低电平。其中，所述开关T13会响应于反馈信号FB而开启，导通开关T13的第一端T13b与第二端T13c，将所述栅极扫描信号Gn拉低至所述预设低电平Vss。
所述开关T14的一控制端T14a电性耦接于所述反馈信号FB，所述开关T14的一第一端T14b电性耦接于所述增压节点BP，所述开关T14的一第二端T14c电性耦接于所述预设低电平Vss。其中，开关T14响应于反馈信号FB而开启，导通所述开关T14的第一端T14b与第二端T14c，将所述电压信号Qn拉低至预设低电平Vss。
所述上拉模块32包括开关T15、开关T16、开关T17与开关T18。
所述开关T15的一控制端T15a电性耦接前一级移位暂存器的时钟信号CK(n-1)，所述开关T15的一第一端T15b电性耦接前二级移位暂存器的时钟信号CK(n-2)。其中，开关T15回应于所述前一级移位暂存器的时钟信号CK(n-1)而开启，导通所述开关T15的第一端T15b与第二端T15c，将所述前二级移位暂存器的时钟信号CK(n-2)传送至开关T15的第二端T15c。
所述开关T16的一控制端T16a电性耦接前一级移位暂存器的电压信号Q(n-1)，所述开关T16的一第一端T16b电性耦接所述开关T15的所述第二端T15c，所述开关T16的一第二端T16c电性耦接所述增压节点BP。其中，开关T16回应于前一级移位暂存器的电压信号Q(n-1)而开启，导通所述开关T16的第一端T16b与第二端T16c，并输出所述第一上拉信号Pu1(n)至所述增压节点BP。
所述开关T17的一控制端T17a电性耦接后一级移位暂存器的时钟信号CK(n+1)，所述开关T17的一第一端T17b电性耦接后二级移位暂存器的时钟信号CK(n+2)。其中，所述开关T17回应于所述后一级移位暂存器的时钟信号CK(n+1)而开启，导通所述开关T17的所述第一端T17b与一第二端T17c，将所述后二级移位暂存器的时钟信号CK(n+2)传送至所述开关T17的所述第二端T17c。
所述开关T18的一控制端T18a电性耦接后一级移位暂存器的电压信号Q(n+1)，所述开关T18的一第一端T18b电性耦接所述开关T17的所述第二端T17c，所述开关T18的一第二端T18c电性耦接所述增压节点BP。其中，所述开关T18回应于所述后一级移位暂存器的电压信号Q(n+1)而开启，导通所述开关T18的所述第一端T18b与所述第二端T18c，并输出所述第二上拉信号Pu2(n)至所述增压节点BP。
从上述的电路结构可以了解上拉模块32是受到前一级移位暂存器的电压信号Q(n-1)控制而输出所述第一上拉信号Pu1，并且是受到后一级移位暂存器的电压信号Q(n+1)控制而输出所 述第二上拉信号Pu2。
换言之，所述上拉模块32是根据前一级移位暂存器的时钟信号CK(n-1)输出所述第一上拉信号Pu1，将所述电压信号Qn由所述第一电平A’拉高至所述第二电平B’，并且根据后二级移位暂存器的时钟信号CK(n+2)输出所述第二上拉信号Pu2，使所述电压信号Qn维持于所述第二电平B’。
至于，所述输入模块31则是根据前二级移位暂存器的时钟信号CK(n-2)输入所述级传信号ST至所述增压节点BP，以提高所述增压节点BP的电压信号Qn至所述第一电平A’。
图3e为示例性的移位暂存电路中增压节点BP的电压信号Qn波形示意图。当图3b中前一级移位暂存器的级传信号ST，根据时钟信号CK(n-2)的脉冲，传送至所述增压节点BP时，会对增压节点BP进行预充电，将电压信号Qn提高至第一电平A’，如图3e所示。
接着，根据时钟信号CK(n-1)的脉冲，上拉模块32将第一上拉信号Pu1传送至所述增压节点BP，使增压节点BP的电压信号Qn由第一电平A’上拉至第二电平B’。
随后，当时钟信号CKn施加于开关T11的第一端T11b时，会产生电性耦合，使增压节点BP的电压信号Qn从预充后的第二电平B’进一步提高至第三电平C’，如图3e所示。耦合后的电压信号Qn施加于开关T11的控制端T11a，会使开关T11打开，将第一端T11a上的时钟信号CKn传送至第二端T11b，并经由输出端O输出，而产生所述的栅极扫描信号Gn。
随后，如图3e所示，随着时钟信号CKn的结束，增压节点BP的电压信号Qn从耦和后的第三电平C’向下降。此时，根据时钟信号CK(n+2)的脉冲，上拉模块32将第二上拉信号Pu2传送至所述增压节点BP，使增压节点BP的电压信号能持续维持于第二电平B’。当时钟信号CK(n+1)的脉冲结束时，上拉模块会停止输出第二上拉信号Pu2，此时增压节点BP的电压信号Qn会从第二电平B’下拉至第一电平A’。
请配合参考图3a、图3b、图3e与图4，图4为本申請一实施例中的移位暂存电路的工作时序示意图，用于显示第4级(n＝4)移位暂存器3的工作时序图，并且为了便于比对，也同时显示了上述第4级移位暂存器2的部分工作时序。
如图4所示，移位暂存电路使用了八组时钟信号CK1-CK8来控制操作。其中，移位暂存器3于增压节点BP处的电压信号Q4’，可以分为五个时段:t1’为级传信号ST进行预充电时间；t2’为第一上拉信号Pu1作用时间；t3’为输出栅极扫描信号Gn时间；t4’为第二上拉信号Pu2作用时间；t5’则为下拉栅极扫描信号Gn时间。
在时段t1’，根据时钟信号CK2，由前一级移位暂存器传送过来的级传信号ST，即第3级移位暂存器的级传信号ST，会对增压节点BP进行预充电，因此电压信号Q4’会提高至第一电平A’。亦即，开关T12会根据时钟信号CK2，输入所述级传信号ST至所述增压节点BP。
在时段t2’，根据时钟信号CK3,上拉模块32会输出所述第一上拉信号Pu1，将所述电压信号Q4’由所述第一电平A’拉高至所述第二电平B’，第一上拉信号Pu1的脉冲会跟随时钟信号CK2的脉冲结束。
在时段t3’，由于时钟信号CK4施加于开关T11的第一端T11b，并与增压节点BP产生电性耦合，因此电压信号Q4’从第二电平B’耦合提高至第三电平C’，并且使图3b中的开关T11打开，而导通时钟信号CK4，并输出栅极扫描信号。
随后，在时段t4’，时钟信号CK4的脉冲结束，导致增压节点BP的电压信号Q4’，会从第三电平C’下拉。但是，根据时钟信号CK6,上拉模块32会输出所述第二上拉信号Pu2，使所述电压信号Q4’可维持于所述第二电平B’。第二上拉信号Pu2的脉冲会跟随时钟信号CK5的脉冲同时结束。
在时段t5’，由于第二上拉信号Pu2的脉冲结束，所以电压信号Q4’会由所述第二电平B’下拉至第一电平A’。在时段t5’之后，伴随时钟信号CK8的脉冲，移位暂存器3会接收前述的反馈信号FB，对增压节点BP进行放电，将电压信号Q4’从第一电平A’下拉至预设低电平。
值得注意的是，所述上拉模块32除了以图3b中所显示的信号控制方式外，还能透过不同的信号控制方式，来产生所需的第一上拉信号Pu1与第二上拉信号Pu2。
例如，在图3b中，开关T15的控制端T15a电性耦接前一级移位暂存器的时钟信号CK(n-1)，第一端T15b则是电性耦接前二级移位暂存器的时钟信号CK(n-2)。但是，在一实施例中，开关T15的控制端T15a亦可电性耦接前二级移位暂存器的时钟信号CK(n-2)，至于第一端T15b则可电性耦接前一级移位暂存器的时钟信号CK(n-1)。其中，开关T15回应于所述前二级移位暂存器的时钟信号CK(n-2)而开启，导通所述开关T15的第一端T15b与第二端T15c，将所述前一级移位暂存器的时钟信号CK(n-1)传送至开关T15的第二端T15c。
此外，图3b中，开关T17的控制端T17a电性耦接后一级移位暂存器的时钟信号CK(n+1)，第一端T17b则电性耦接后二级移位暂存器的时钟信号CK(n+2)。但是，在一实施例中，开关T17的控制端T17a亦可电性耦接后二级移位暂存器的时钟信号CK(n+2)，至于第一端T17b则可电性耦接后一级移位暂存器的时钟信号CK(n+1)。如此，开关T17回应于所述后二级移位暂存器的时钟信号CK(n+2)而开启，导通所述开关T17的所述第一端T17b与第二端T17c，将所述后一级移位暂存器的时钟信号CK(n+1)传送至所述开关T17的第二端T17c。
在一实施例中，所述开关T16的一控制端T16a，亦可电性耦接前二级移位暂存器的电压信号Q(n-2)，并回应于前二级移位暂存器的电压信号Q(n-2)而开启，输出所述第一上拉信号Pu1(n)至所述增压节点BP。
在另一实施例中，所述开关T18的一控制端T18a，亦可电性耦接后二级移位暂存器的电压信号Q(n+2)，并回应于所述后二级移位暂存器的电压信号Q(n+2)而开启，输出所述第二上拉信号Pu2(n)至所述增压节点BP。
接着，请参考图3c、图3d与图3e。图3c为本申请第二实施例中的移位暂存电路的模块结构示意图。图3d为本申请第二实施例中的移位暂存电路的电路结构示意图。图3e为本申请一实施例中移位暂存电路中增压节点的电压信号波形示意图。
请同时参考图3c与图3e，一种移位元暂存电路，包括多级移位暂存器，其中一移位暂存器4主要包括一输入模块41、一耦合上拉模块42、一输出模块43、一反馈模块44。在一实施例中，所述移位暂存电路包括了n级移位暂存器，其中n为正整数，图3c所显示的为第n级移位暂存器4。
所述输入模块41，用于输入前级移位暂存器的级传信号ST至一增压节点BP，例如，可输入前一级移位暂存器的级传信号ST，以提高所述增压节点BP的电压信号Qn至第一电平A’，如图3e所示。要特别指出的是，尽管此实施例中，输入的是前一级移位暂存器的级传信号ST，但是随着信号配置的不同，亦可选择输入前二级、前三级、或是其它前级移位暂存器的级传信号ST。
所述耦合上拉模块42，耦接于所述增压节点BP，用于产生一第一上拉信号Pu1与一第二上拉信号Pu2。其中，所述第一上拉信号Pu1，可透过电性耦合，间接作用于增压节点BP，将所述电压信号Qn由所述第一电平A’耦合拉高至第二电平B’，所述第二上拉信号Pu2，则可透过电性耦合，间接作用于增压节点BP，将所述电压信号Qn维持于所述第二电平B’，如图3e所示。
所述输出模块43，接收一时钟信号CKn，并根据所述时钟信号CKn将所述电压信号Qn从第二高电平B’耦合拉高至第三高电平C’，如图3e所示。并且，输出模块43会受到耦合后的电压信号Qn控制而开启，经由一输出端O输出一栅极扫描信号Gn。当所述时钟信号CKn的脉冲结束时，所述耦合上拉模块42会产生所述第二上拉信号Pu2，并透过电性耦合间接作用于增压节点BP，使所述电压信号Qn维持于所述第二电平B’。
所述反馈模块44，接收一反馈信号FB，将所述增压节点BP耦合后的电压信号Qn以及栅极扫描信号Gn，拉低至一预设低电平Vss。
在一实施例中，所述移位暂存器4包括还包括一子下拉控制模块45以及一子下拉模块46。其中，子下拉模块46，用于维持所述电压信号Qn于所述预设低电平Vss。至于，子下拉控制模块45，则用于控制所述子下拉模块46的操作。
接着，请参考图3d，图3d显示了上述第n级移位暂存器4的详细电路结构。所述输出模块43包括开关T21。所述开关T21的一控制端T21a电性耦接所述增压节点BP，所述开关T21的第一端T21b用于接收所述时钟信号CKn，所述开关T21的第二端T21c电性耦接所述输出端O，用于输出所述栅极扫描信号Gn。其中，当所述增压节点BP的电压信号Qn耦合提高至所述第三电平C’时，所述开关T21会开启并输出所述栅极扫描信号Gn。
所述输入模块41包括开关T22，所述开关T22的一控制端T22a电性耦接所述所述开关T22的第一端T22b，所述开关T22的第二端T22c电性耦接所述增压节点BP，用于输出所述级传信号ST至所述增压节点BP，以提高增压节点BP其电压信号Qn至所述第一电平A’。
所述反馈模块44包括开关T23与开关T24。其中，所述开关T23的一控制端T23a电性耦接于一反馈信号FB，所述开关T23的第一端T23b电性耦接于所述输出端O，所述开关T23的第二端T23c电性耦接于所述预设低电平Vss。其中，所述开关T23会响应于反馈信号FB而开启，导通开关T23的第一端T23b与第二端T23c，将所述栅极扫描信号Gn拉低至所述预设低电平Vss。
所述开关T24的一控制端T24a电性耦接于所述反馈信号FB，所述开关T24的一第一端T24b电性耦接于所述增压节点BP，所述开关T24的一第二端T24c电性耦接于所述预设低电平Vss。其中，开关T24响应于反馈信号FB而开启，导通所述开关T24的第一端T24b与第二端T24c，将所述电压信号Qn拉低至预设低电平Vss。
所述耦合上拉模块42包括开关T25、开关T26、开关T27、开关T28、以及开关T29。
所述开关T25的一控制端T25a电性耦接前一级移位暂存器的时钟信号CK(n-1)，所述开关T25的一第一端T25b电性耦接前二级移位暂存器的时钟信号CK(n-2)。其中，开关T25回应于所述前一级移位暂存器的时钟信号CK(n-1)而开启，导通所述开关T25的第一端T25b与第二端T25c，将所述前二级移位暂存器的时钟信号CK(n-2)传送至开关T25的第二端T25c。
所述开关T26的一控制端T26a电性耦接前一级移位暂存器的电压信号Q(n-1)，所述开关T26的一第一端T26b电性耦接所述开关T25的所述第二端T25c，所述开关T26的一第二端T26c电性耦接所述开关T29的一第一端T29b，并经由所述开关T29耦接所述增压节点BP。其中，开关T26回应于前一级移位暂存器的电压信号Q(n-1)而开启，导通所述开关T26的第一端T26b与第二端T26c，并输出所述第一上拉信号Pu1(n)。
所述开关T27的一控制端T27a电性耦接后一级移位暂存器的时钟信号CK(n+1)，所述开关T27的一第一端T27b电性耦接后二级移位暂存器的时钟信号CK(n+2)。其中，所述开关T27回应于所述后一级移位暂存器的时钟信号CK(n+1)而开启，导通所述开关T27的所述第一端T27b与一第二端T27c，将所述后二级移位暂存器的时钟信号CK(n+2)传送至所述开关T27的所述第二端T27c。
所述开关T28的一控制端T28a电性耦接后一级移位暂存器的电压信号Q(n+1)，所述开关T28的一第一端T28b电性耦接所述开关T27的所述第二端T27c，所述开关T28的一第二端T28c电性耦接所述开关T29的第一端T29b，并经由所述开关T29耦接所述增压节点BP。其中，所述开关T28回应于所述后一级移位暂存器的电压信号Q(n+1)而开启，导通所述开关T28的所述第一端T28b与所述第二端T28c，并输出所述第二上拉信号Pu2(n)。
所述开关T29的一控制端T29a电性耦接所述增压节点BP，所述开关T29的第一端T29b用于接收所述第一上拉信号Pu1与所述第二上拉信号Pu2，所述开关T29的一第二端T29b电性耦接于所述预设低电平Vss，其中所述开关T29回应于所述电压信号Qn而开启，导通所述开关T29的所述第一端T29b与所述第二端T29c。
当所述开关T29的第一端T29b接收所述第一上拉信号Pu1时，会耦合至开关T29的控制端T29a，而上拉增压节点BP的电压信号Qn至第二电平B’。随后，当开关T29的第二端T29c接收所述第二上拉信号Pu2时，亦会耦合至开关T29的控制端T29a，而维持增压节点BP的电压信号Qn于第二电平B’。
此外，从上述的电路结构可以了解耦合上拉模块42是受到前一级移位暂存器的电压信号Q(n-1)控制而产生所述第一上拉信号Pu1，将所述电压信号Qn由所述第一电平A’耦合拉高至所述第二电平B’，并且是受到后一级移位暂存器的电压信号Q(n+1)控制而产生所述第二上拉信号Pu2，电性耦合至所述增压节点，使所述电压信号Qn维持于所述第二电平。
换言之，所述耦合上拉模块42是根据前一级移位暂存器的时钟信号CK(n-1)产生所述第一上拉信号Pu1，将所述电压信号Qn由所述第一电平A’耦合拉高至所述第二电平B’，并且根据后二级移位暂存器的时钟信号CK(n+2)产生所述第二上拉信号Pu2，电性耦合至所述增压节点，使所述电压信号Qn维持于所述第二电平B’。
至于，所述输入模块41则是根据前二级移位暂存器的时钟信号CK(n-2)输入所述级传信号ST至所述增压节点BP，以提高所述增压节点BP的电压信号Qn至所述第一电平A’。
图3e为示例性的移位暂存电路中增压节点BP的电压信号Qn波形示意图。当图3d中前一级移位暂存器的级传信号ST，根据时钟信号CK(n-2)的脉冲，传送至所述增压节点BP时，会对增压节点BP进行预充电，将电压信号Qn提高至第一电平A’，如图3e所示。
接着，根据时钟信号CK(n-1)的脉冲，耦合上拉模块42产生第一上拉信号Pu1，并透过电性耦合，使增压节点BP的电压信号Qn由第一电平A’耦合上拉至第二电平B’。
随后，当时钟信号CKn施加于开关T21的第一端T21b时，会产生电性耦合，使增压节点BP的电压信号Qn从预充后的第二电平B’进一步提高至第三电平C’，如图3e所示。耦合后的电压信号Qn施加于开关T21的控制端T21a，会使开关T21打开，将第一端T21a上的时钟信号CKn传送至第二端T21b，并经由输出端O输出，产生所述的栅极扫描信号Gn。
随后，如图3e所示，随着时钟信号CKn的结束，增压节点BP的电压信号Qn从耦和后的第三电平C’向下降。此时，根据时钟信号CK(n+2)的脉冲，耦合上拉模块42会产生第二上拉信号Pu2，并透过电性耦合间接作用于增压节点BP，使增压节点BP的电压信号能持续维持于第二电平B’。当时钟信号CK(n+1)的脉冲结束时，耦合上拉模块会停止输出第二上拉信号Pu2，此时增压节点BP的电压信号Qn会从第二电平B’下拉至第一电平A’。
以下参照图3c、图3d、图3e与图4进行说明。
如图4所示，移位暂存电路使用了八组时钟信号CK1-CK8来控制操作。其中，移位暂存器4于增压节点BP处的电压信号Q4’，可以分为五个时段:t1’为级传信号ST进行预充电时间；t2’为第一上拉信号Pu1耦合作用时间；t3’为输出栅极扫描信号Gn时间；t4’为第二上拉信号Pu2耦合作用时间；t5’则为下拉栅极扫描信号Gn时间。
在时段t1’，根据时钟信号CK2，由前一级移位暂存器传送过来的级传信号ST，即第3级移位暂存器的级传信号ST，会对增压节点BP进行预充电，因此电压信号Q4’会提高至第一电平A’。亦即，开关T22会根据时钟信号CK2，输入所述级传信号ST至所述增压节点BP。
在时段t2’，根据时钟信号CK3,耦合上拉模块42会产生所述第一上拉信号Pu1，与增压节点BP产生电性耦合，将所述电压信号Q4’由所述第一电平A’耦合拉高至所述第二电平B’，第一上拉信号Pu1的脉冲会跟随时钟信号CK2的脉冲结束。
在时段t3’，由于时钟信号CK4施加于开关T21的第一端T21b，并与增压节点BP产生电性耦合，因此电压信号Q4’从第二电平B’耦合提高至第三电平C’，并且使图3d中的开关T21打开，而导通时钟信号CK4，并输出栅极扫描信号。
随后，在时段t4’，时钟信号CK4的脉冲结束，导致增压节点BP的电压信号Q4’，会从第三电平C’下拉。但是，根据时钟信号CK6,耦合上拉模块42会产生所述第二上拉信号Pu2，与 增压节点BP产生电性耦合，使所述电压信号Q4’可维持于所述第二电平B’。第二上拉信号Pu2的脉冲会跟随时钟信号CK5的脉冲同时结束。
在时段t5’，由于第二上拉信号Pu2的脉冲结束，所以电压信号Q4’会由所述第二电平B’下拉至第一电平A’。在时段t5’之后，伴随时钟信号CK8的脉冲，移位暂存器4会接收前述的反馈信号FB，对增压节点BP进行放电，将电压信号Q4’从第一电平A’下拉至预设低电平。
值得注意的是，所述耦合上拉模块42除了以图3d中所显示的信号控制方式外，还能透过不同的信号控制方式，来产生所需的第一上拉信号Pu1与第二上拉信号Pu2。
例如，在图3d中，开关T25的控制端T25a电性耦接前一级移位暂存器的时钟信号CK(n-1)，第一端T25b则是电性耦接前二级移位暂存器的时钟信号CK(n-2)。但是，在一实施例中，开关T25的控制端T25a亦可电性耦接前二级移位暂存器的时钟信号CK(n-2)，至于第一端T25b则可电性耦接前一级移位暂存器的时钟信号CK(n-1)。其中，开关T25回应于所述前二级移位暂存器的时钟信号CK(n-2)而开启，导通所述开关T25的第一端T25b与第二端T25c，将所述前一级移位暂存器的时钟信号CK(n-1)传送至开关T25的第二端T25c。
此外，图3d中，开关T27的控制端T27a电性耦接后一级移位暂存器的时钟信号CK(n+1)，第一端T27b则电性耦接后二级移位暂存器的时钟信号CK(n+2)。但是，在一实施例中，开关T27的控制端T27a亦可电性耦接后二级移位暂存器的时钟信号CK(n+2)，至于第一端T27b则可电性耦接后一级移位暂存器的时钟信号CK(n+1)。如此，开关T27回应于所述后二级移位暂存器的时钟信号CK(n+2)而开启，导通所述开关T27的所述第一端T27b与第二端T27c，将所述后一级移位暂存器的时钟信号CK(n+1)传送至所述开关T27的第二端T27c。
在一实施例中，所述开关T26的一控制端T26a，亦可电性耦接前二级移位暂存器的电压信号Q(n-2)，并回应于前二级移位暂存器的电压信号Q(n-2)而开启，输出所述第一上拉信号Pu1(n)。
在另一实施例中，所述第八开关T28的一控制端T28a，亦可电性耦接后二级移位暂存器的电压信号Q(n+2)，并回应于所述后二级移位暂存器的电压信号Q(n+2)而开启，输出所述第二上拉信号Pu2(n)。
图5为本申请一实施例的显示装置示意图。请参照图5，所述显示装置12，包括一主动开关阵列基板121、一对向基板120与所述主动开关阵列基板121对向设置、以及一阵列基板栅极驱动电路122,其中阵列基板栅极驱动电路122以微影制程直接制作在主动开关阵列基板121的表面上。所述的阵列基板栅极驱动电路122包括了图3c与图3d中所显示的移位暂存电路。亦即，在所述阵列基板栅极驱动电路110中会具有多级的移位暂存器3或移位暂存器4。
本申请由于使用了一耦合上拉模块，输出第一上拉信号Pu1，透过电性耦合，间接作用于增压节点，而使增压节点的电压信号上拉至更高的电平。因此，当时钟信号与输出模块电性耦和时，能确保开关迅速的打开，使移位暂存器能准确且顺利的输出栅极扫描信号。其次，由于本申请的耦合上拉模块，在栅极扫描信号的脉冲结束时，还会输出第二上拉信号Pu2，透过电性耦合，间接作用于增压节点，来维持增压节点的电压信号于一高电平，因此可加速下拉栅极扫描信号，进而改善栅极扫描信号的拖尾现象，从而提升显示画面的品质。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请,任何熟悉本专业的技术人员,在不脱离本申请技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种移位暂存电路，包括多级移位暂存器，其中任一级移位暂存器包括：
    输入模块，输入前级移位暂存器的级传信号至增压节点；
    耦合上拉模块，耦接于所述增压节点，用于产生第一上拉信号与第二上拉信号，其中所述第一上拉信号，透过电性耦合，将所述电压信号由第一电平耦合拉高至第二电平；
    输出模块，接收时钟信号，并根据所述时钟信号将所述电压信号从所述第二电平耦合拉高至第三电平，所述输出模块受到所述第三电平的所述电压信号控制，经由输出端输出栅极扫描信号，其中当所述时钟信号的脉冲结束时，所述耦合上拉模块产生所述第二上拉信号，并透过电性耦合，将所述电压信号维持于所述第二电平；以及
    反馈模块，接收反馈信号，将所述增压节点的所述电压信号以及所述栅极扫描信号，拉低至预设低电平。
  2. 如权利要求1所述的移位暂存电路，其中所述任一级移位暂存器还包括子下拉模块，用于维持所述电压信号于所述预设低电平；以及子下拉控制模块，用于控制所述子下拉模块的操作。
  3. 如权利要求1所述的移位暂存电路，其中所述子下拉模块电性耦接于所述增压节点、所述栅极扫描信号及所述预设低电位。
  4. 如权利要求1所述的移位暂存电路，其中所述输出模块包括第一开关，所述第一开关的一控制端电性耦接所述增压节点，所述第一开关的一第一端用于接收所述时钟信号，所述第一开关的一第二端电性耦接所述输出端，用于输出所述栅极扫描信号，其中当所述增压节点的电压信号耦合提高至所述第三电平时，所述第一开关开启并输出所述栅极扫描信号。
  5. 如权利要求1所述的移位暂存电路，其中所述输入模块包括第二开关，所述第二开关的一控制端电性耦接所述所述第二开关的第一端，所述第二开关的第二端用于输出所述级传信号。
  6. 如权利要求1所述的移位暂存电路，其中所述反馈模块包括第三开关，所述第三开关的一控制端电性耦接于所述反馈信号，所述第第三开关的一第一端电性耦接于所述输出端，所述第三开关的一第二端电性耦接于所述预设低电平，其中所述第三开关回应于所述反馈信号而开启，导通所述第三开关的所述第一端与所述第二端，将所述栅极扫描信号拉低至所述预设低电平。
  7. 如权利要求1所述的移位暂存电路，其中所述反馈模块包括第四开关，所述第四开关的一控制端电性耦接于所述反馈信号，所述第四开关的一第一端电性耦接于所述增压节点，所述第四开关的一第二端电性耦接于所述预设低电平，其中所述第四开关回应于所述反馈信号而开启，导通所述第四开关的所述第一端与所述第二端，将所述电压信号拉低至所述预设低电平。
  8. 如权利要求1所述的移位暂存电路，其中所述耦合上拉模块包括:
    第五开关，所述第五开关的一控制端电性耦接前一级移位暂存器的时钟信号，所述第五开关的一第一端电性耦接前二级移位暂存器的时钟信号，其中所述第五开关回应于所述前一级移位暂存器的时钟信号而开启，导通所述第五开关的所述第一端与一第二端，将所述前二级移位暂存器的时钟信号传送至所述第五开关的所述第二端；
    第六开关，所述第六开关的一控制端电性耦接前一级移位暂存器的电压信号，所述第六开关的一第一端电性耦接所述第五开关的所述第二端，所述第六开关的一第二端电性耦接所述增压节点，其中所述第六开关回应于所述前一级移位暂存器的电压信号而开启，导通所述第六开 关的所述第一端与所述第二端，并输出所述第一上拉信号；
    第七开关，所述第七开关的一控制端电性耦接后一级移位暂存器的时钟信号，所述第七开关的一第一端电性耦接后二级移位暂存器的时钟信号，其中所述第七开关回应于所述后一级移位暂存器的时钟信号而开启，导通所述第七开关的所述第一端与一第二端，将所述后二级移位暂存器的时钟信号传送至所述第七开关的所述第二端；以及
    第八开关，所述第八开关的一控制端电性耦接后一级移位暂存器的电压信号，所述第八开关的一第一端电性耦接所述第七开关的所述第二端，所述第八开关的一第二端电性耦接所述增压节点，其中所述第八开关回应于所述后一级移位暂存器的电压信号而开启，导通所述第八开关的所述第一端与所述第二端，并输出所述第二上拉信号。
  9. 如权利要求8所述的移位暂存电路，其中所述第六开关的所述第二端电性耦接所述第八开关的所述第二端。
  10. 如权利要求8所述的移位暂存电路，其中所述耦合上拉模块还包括第九开关，所述第九开关的一控制端电性耦接所述增压节点，所述第九开关的一第一端电性耦接所述第六开关的所述第二端以及所述第八开关的所述第二端，所述第九开关的一第二端电性耦接于所述预设低电平，其中所述第九开关回应于所述电压信号而开启，导通所述第九开关的所述第一端与所述第二端。
  11. 如权利要求1所述的移位暂存电路，其中所述耦合上拉模块还包括第九开关，所述第九开关的一控制端电性耦接所述增压节点，所述第九开关的一第一端用于接收所述第一上拉信号与所述第二上拉信号，所述第九开关的一第二端电性耦接于所述预设低电平，其中所述第九开关回应于所述电压信号而开启，导通所述第九开关的所述第一端与所述第二端。
  12. 如权利要求1所述的移位暂存电路，其中所述耦合上拉模块是受到前一级移位暂存器的电压信号控制而产生所述第一上拉信号，将所述电压信号由所述第一电平耦合拉高至所述第二电平，并且是受到后一级移位暂存器的电压信号控制而产生所述第二上拉信号，电性耦合至所述增压节点，使所述电压信号维持于所述第二电平。
  13. 如权利要求1所述的移位暂存电路，其中所述耦合上拉模块是根据前一级移位暂存器的时钟信号产生所述第一上拉信号，将所述电压信号由所述第一电平耦合拉高至所述第二电平，并且根据后二级移位暂存器的时钟信号产生所述第二上拉信号，电性耦合至所述增压节点，使所述电压信号维持于所述第二电平。
  14. 一种显示装置，包括：
    一主动开关阵列基板；以及
    一对向基板，与所述主动开关阵列基板对向设置；
    其中，所述主动开关阵列基板上制作了阵列基板栅极驱动电路，且所述阵列基板栅极驱动电路包括移位暂存电路，所述移位暂存电路包括多级移位暂存器，其中任一级移位暂存器包括：
    输入模块，输入前级移位暂存器的级传信号至增压节点；
    耦合上拉模块，耦接于所述增压节点，用于产生第一上拉信号与第二上拉信号，其中所述第一上拉信号，透过电性耦合，将所述电压信号由第一电平耦合拉高至第二电平；
    输出模块，接收时钟信号，并根据所述时钟信号将所述电压信号从所述第二电平耦合拉高至第三电平，所述输出模块受到所述第三电平的所述电压信号控制，经由输出端输出栅极扫描信号，其中当所述时钟信号的脉冲结束时，所述耦合上拉模块产生所述第二上拉信号，并透过 电性耦合，将所述电压信号维持于所述第二电平；以及
    反馈模块，接收反馈信号，将所述增压节点的所述电压信号以及所述栅极扫描信号，拉低至预设低电平。
  15. 如权利要求14所述的显示装置，其中所述输出模块包括第一开关，所述第一开关的一控制端电性耦接所述增压节点，所述第一开关的一第一端用于接收所述时钟信号，所述第一开关的一第二端电性耦接所述输出端，用于输出所述栅极扫描信号，其中当所述增压节点的电压信号耦合提高至所述第三电平时，所述第一开关开启并输出所述栅极扫描信号。
  16. 如权利要求14所述的显示装置，其中所述输入模块包括第二开关，所述第二开关的一控制端电性耦接所述所述第二开关的第一端，所述第二开关的第二端用于输出所述级传信号。
  17. 如权利要求14所述的显示装置，其中所述反馈模块包括：
    第三开关，所述第三开关的一控制端电性耦接于所述反馈信号，所述第第三开关的一第一端电性耦接于所述输出端，所述第三开关的一第二端电性耦接于所述预设低电平，其中所述第三开关回应于所述反馈信号而开启，导通所述第三开关的所述第一端与所述第二端，将所述栅极扫描信号拉低至所述预设低电平；以及
    第四开关，所述第四开关的一控制端电性耦接于所述反馈信号，所述第四开关的一第一端电性耦接于所述增压节点，所述第四开关的一第二端电性耦接于所述预设低电平，其中所述第四开关回应于所述反馈信号而开启，导通所述第四开关的所述第一端与所述第二端，将所述电压信号拉低至所述预设低电平。
  18. 如权利要求14所述的显示装置，其中所述耦合上拉模块包括:
    第五开关，所述第五开关的一控制端电性耦接前一级移位暂存器的时钟信号，所述第五开关的一第一端电性耦接前二级移位暂存器的时钟信号，其中所述第五开关回应于所述前一级移位暂存器的时钟信号而开启，导通所述第五开关的所述第一端与一第二端，将所述前二级移位暂存器的时钟信号传送至所述第五开关的所述第二端；
    第六开关，所述第六开关的一控制端电性耦接前一级移位暂存器的电压信号，所述第六开关的一第一端电性耦接所述第五开关的所述第二端，所述第六开关的一第二端电性耦接所述增压节点，其中所述第六开关回应于所述前一级移位暂存器的电压信号而开启，导通所述第六开关的所述第一端与所述第二端，并输出所述第一上拉信号；
    第七开关，所述第七开关的一控制端电性耦接后一级移位暂存器的时钟信号，所述第七开关的一第一端电性耦接后二级移位暂存器的时钟信号，其中所述第七开关回应于所述后一级移位暂存器的时钟信号而开启，导通所述第七开关的所述第一端与一第二端，将所述后二级移位暂存器的时钟信号传送至所述第七开关的所述第二端；以及
    第八开关，所述第八开关的一控制端电性耦接后一级移位暂存器的电压信号，所述第八开关的一第一端电性耦接所述第七开关的所述第二端，所述第八开关的一第二端电性耦接所述增压节点，其中所述第八开关回应于所述后一级移位暂存器的电压信号而开启，导通所述第八开关的所述第一端与所述第二端，并输出所述第二上拉信号。
  19. 如权利要求14所述的显示装置，其中所述耦合上拉模块还包括第九开关，所述第九开关的一控制端电性耦接所述增压节点，所述第九开关的一第一端用于接收所述第一上拉信号与所述第二上拉信号，所述第九开关的一第二端电性耦接于所述预设低电平，其中所述第九开关回应于所述电压信号而开启，导通所述第九开关的所述第一端与所述第二端。
  20. 一种移位暂存电路，包括多级移位暂存器，其中任一级移位暂存器包括：
    输入模块，输入前级移位暂存器的级传信号至增压节点；
    耦合上拉模块，耦接于所述增压节点，用于产生第一上拉信号与第二上拉信号，其中所述第一上拉信号，透过电性耦合，将所述电压信号由第一电平耦合拉高至第二电平；
    输出模块，接收时钟信号，并根据所述时钟信号将所述电压信号从所述第二电平耦合拉高至第三电平，所述输出模块受到所述第三电平的所述电压信号控制，经由输出端输出栅极扫描信号，其中当所述时钟信号的脉冲结束时，所述耦合上拉模块产生所述第二上拉信号，并透过电性耦合，将所述电压信号维持于所述第二电平；以及
    反馈模块，接收反馈信号，将所述增压节点的所述电压信号以及所述栅极扫描信号，拉低至预设低电平；
    其中所述耦合上拉模块包括:
    第五开关，所述第五开关的一控制端电性耦接前一级移位暂存器的时钟信号，所述第五开关的一第一端电性耦接前二级移位暂存器的时钟信号，其中所述第五开关回应于所述前一级移位暂存器的时钟信号而开启，导通所述第五开关的所述第一端与一第二端，将所述前二级移位暂存器的时钟信号传送至所述第五开关的所述第二端；
    第六开关，所述第六开关的一控制端电性耦接前一级移位暂存器的电压信号，所述第六开关的一第一端电性耦接所述第五开关的所述第二端，所述第六开关的一第二端电性耦接所述增压节点，其中所述第六开关回应于所述前一级移位暂存器的电压信号而开启，导通所述第六开关的所述第一端与所述第二端，并输出所述第一上拉信号；
    第七开关，所述第七开关的一控制端电性耦接后一级移位暂存器的时钟信号，所述第七开关的一第一端电性耦接后二级移位暂存器的时钟信号，其中所述第七开关回应于所述后一级移位暂存器的时钟信号而开启，导通所述第七开关的所述第一端与一第二端，将所述后二级移位暂存器的时钟信号传送至所述第七开关的所述第二端；
    第八开关，所述第八开关的一控制端电性耦接后一级移位暂存器的电压信号，所述第八开关的一第一端电性耦接所述第七开关的所述第二端，所述第八开关的一第二端电性耦接所述增压节点，其中所述第八开关回应于所述后一级移位暂存器的电压信号而开启，导通所述第八开关的所述第一端与所述第二端，并输出所述第二上拉信号，其中所述第六开关的所述第二端电性耦接所述第八开关的所述第二端；以及
    第九开关，所述第九开关的一控制端电性耦接所述增压节点，所述第九开关的一第一端电性耦接所述第六开关的所述第二端以及所述第八开关的所述第二端，所述第一端用于接收所述第一上拉信号与所述第二上拉信号，所述第九开关的一第二端电性耦接于所述预设低电平，其中所述第九开关回应于所述电压信号而开启，导通所述第九开关的所述第一端与所述第二端。
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