WO2020015337A1 - 像素驱动电路感测方法及像素驱动电路 - Google Patents

像素驱动电路感测方法及像素驱动电路 Download PDF

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Publication number
WO2020015337A1
WO2020015337A1 PCT/CN2019/070042 CN2019070042W WO2020015337A1 WO 2020015337 A1 WO2020015337 A1 WO 2020015337A1 CN 2019070042 W CN2019070042 W CN 2019070042W WO 2020015337 A1 WO2020015337 A1 WO 2020015337A1
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Prior art keywords
potential
sensing
line
node
film transistor
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English (en)
French (fr)
Inventor
金羽锋
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2020015337A1 publication Critical patent/WO2020015337A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the gate of the first thin film transistor (T1) is electrically connected to the scan line (WR), the source is electrically connected to the data line (Data), and the drain is electrically connected to the first node (G); the second thin film transistor The gate of (T2) is electrically connected to the first node (G), the drain is electrically connected to the positive voltage (VDD), and the source is electrically connected to the second node (S); the gate of the third thin film transistor (T3)
  • the electrode is electrically connected to the sensing control line (RD), the source is electrically connected to the second node (S), and the drain is electrically connected to the sense line (10); the first end and the second end of the capacitor (C1)
  • the first node (G) and the second node (S) are electrically connected respectively; the anode of the organic light emitting diode (D1) is electrically connected to the second node (S), and the cathode is connected to a negative voltage (VSS);
  • the switch (K1) is a single-pole double-th
  • the scanning line (WR) transmits the scanning signal to control the first thin film transistor (T1) to be turned on
  • the sensing control line (RD) transmits the sensing signal to control the third thin film transistor (T3) to be turned on
  • the switch (K1) turns its moving contact (1)
  • Conducting with the first static contact (2) the data line (Data) writes the reference potential to the first node (G), and the common voltage (Vcm) is a first potential writing to the sensing line (10)
  • the second node (S) the reference potential is greater than the first potential;
  • Step S4 Enter the sensing phase (t3)
  • step S2 step S3, and step S5
  • the scanning line (WR) transmits a high-potential scanning signal
  • the sensing control line (RD) transmits a high-potential sensing signal
  • step S4 the scanning line (WR) A low-potential scanning signal is transmitted, and a low-potential sensing signal is transmitted by the sensing control line (RD); and in the steps S3 and S4, the common voltage (Vcm) is a first potential.
  • step S5 the specific method for switching the common voltage (Vcm) from the second potential to the first potential is: the common voltage (Vcm) is first switched from the second potential to a plurality of intermediate potentials in sequence, and then from the last One intermediate potential is switched to the first potential; among the multiple intermediate potentials, the odd-numbered intermediate potential is greater than the first potential, the even-numbered intermediate potential is smaller than the first potential, and the absolute values of the differences between the multiple intermediate potentials and the first potential are sequentially decreased. And the difference between the first intermediate potential and the first potential is smaller than the difference between the first potential and the second potential.
  • the pixel driving circuit further includes a circuit board (40), and the voltage modulation module (30) is disposed on the circuit board (40).
  • the present invention further provides a pixel driving circuit sensing method, including the following steps:
  • the scan line transmits the scanning signal to control the first thin film transistor to be turned on
  • the sensing control line transmits the sensing signal to control the third thin film transistor to be turned on
  • the switch turns its moving contact to the first static contact
  • the data line writes the reference potential Into the first node, the common voltage is a first potential write sensing line and the second node; the reference potential is greater than the first potential;
  • Step S3 Enter the charging phase
  • the scanning line transmits a scanning signal to control the first thin film transistor to be turned on
  • the sensing control line transmits a sensing signal to control the third thin film transistor to be turned on
  • the switch disconnects its moving contact from the first static contact and the second static contact
  • the data line writes the reference potential to the first node, and the positive voltage of the power source charges the second node and the sensing line, so that the voltage on the second node and the sensing line continues to rise until the voltage of the second node and the sensing line is equal to A difference between a reference potential and a threshold voltage of the second thin film transistor;
  • Step S5 Enter the rewrite phase
  • the scanning line transmits the scanning signal to control the first thin film transistor to be turned on
  • the sensing control line transmits the sensing signal to control the third thin film transistor to be turned on
  • the switch connects its moving contact with the first static contact
  • the data line will write the display potential
  • the common voltage is first a second potential and then switched to the first potential and written to the sensing line and the second node, and the potentials of the sensing line and the second node are pulled down to the first potential; the second The potential is less than the first potential.
  • step S5 the specific method of switching the common voltage from the second potential to the first potential is: the common voltage is first switched from the second potential to a plurality of intermediate potentials in order, and then the last intermediate potential is switched to the first potential.
  • the pixel driving circuit further includes a voltage modulation module electrically connected to the first static contact of the switch; the common voltage is provided by the voltage modulation module.
  • the pixel driving circuit further includes a circuit board, and the voltage modulation module is disposed on the circuit board.
  • step S4 after the analog-to-digital converter senses the voltage on the sensing line, it also performs analog-to-digital conversion processing on the voltage on the sensing line to generate corresponding data and latch it.
  • step S3 and step S4 the common voltage is the first potential.
  • the invention also provides a pixel driving circuit, which includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a capacitor, an organic light emitting diode, a switch, a sensing line, a sensing module, a data line, a scanning line, and a sensing device.
  • a pixel driving circuit which includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a capacitor, an organic light emitting diode, a switch, a sensing line, a sensing module, a data line, a scanning line, and a sensing device.
  • Control line and voltage modulation module which includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a capacitor, an organic light emitting diode, a switch, a sensing line, a sensing module, a data line, a scanning line, and a sensing device.
  • the gate of the first thin film transistor is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to the first node; the gate of the second thin film transistor is electrically connected to the first node and the drain Connect the positive voltage of the power source, the source is electrically connected to the second node; the gate of the third thin film transistor is electrically connected to the sensing control line, the source is electrically connected to the second node, and the drain is electrically connected to the sensing line;
  • the first end and the second end of the capacitor are electrically connected to the first node and the second node, respectively; the anode of the organic light emitting diode is electrically connected to the second node, and the cathode is connected to the negative voltage of the power source;
  • the switch is single-pole double Throw switch, whose moving contact is electrically connected to the sensing line, the first static contact is electrically connected to the voltage modulation module, and the second static contact is electrically connected to the sensing module;
  • the voltage modulation module is used to output a common voltage to the first static contact.
  • the voltage modulation module makes the common voltage first a second potential and switches from the second potential to a plurality of intermediate potentials in sequence.
  • the last intermediate potential is switched to the first potential; the second potential is smaller than the first potential, the odd-numbered intermediate potentials of the plurality of intermediate potentials are larger than the first potential, the even-numbered intermediate potentials are smaller than the first potential, and the plurality of intermediate potentials are The absolute value of the difference between the first potential decreases sequentially, and the difference between the first intermediate potential and the first potential is smaller than the difference between the first potential and the second potential.
  • the common voltage in the rewriting phase, is first set to a second potential lower than the first potential, and then switched to the first potential and written to the second potential. Node, when the common voltage is at the second potential, the voltage on the sensing line will be quickly pulled down to close to the first potential due to overdrive charging, and then the common voltage is switched to the first potential to write the correct potential to the sensing line ,
  • Can effectively reduce the length of the rewrite phase is beneficial to increase the length of the charging phase, and improve the accuracy of sensing the pixel driving circuit.
  • the pixel driving circuit of the present invention can effectively reduce the duration of the rewrite phase, is beneficial to increase the duration of the charging phase, and improves the accuracy of sensing the pixel driving circuit.
  • FIG. 1 is a circuit diagram of a conventional pixel driving circuit
  • FIG. 2 is a timing diagram of the pixel driving circuit shown in FIG. 1 during a frame blanking stage
  • FIG. 6 is a circuit diagram of a pixel driving circuit according to a second embodiment of the pixel driving circuit sensing method of the present invention and a circuit diagram of a pixel driving circuit of the present invention
  • FIG. 7 is a timing diagram of a pixel driving circuit sensing method according to a second embodiment of the present invention.
  • the sensing module 20 is an analog-to-digital converter ADC.
  • Step S2 enter the initial stage t1.
  • the first potential is 4V.
  • the low potentials of the scanning signal and the sensing signal are both -5V.
  • step S4 after the analog-to-digital converter ADC senses the voltage on the sensing line 10, it also performs analog-to-digital conversion processing on the voltage on the sensing line 10 to generate corresponding data and latch it.
  • the scanning line WR transmits a scanning signal to control the first thin film transistor T1 to be turned on
  • the sensing control line RD transmits a sensing signal to control the third thin film transistor T3 to be turned on
  • the switch K1 turns on its moving contact 1 and the first static contact 2
  • the data line Data writes the display potential to the first node G via the turned-on first thin-film transistor T1, and the common voltage Vcm is firstly a second potential, and then switched to the first potential and written to the sensing line 10, and is turned on
  • the third thin film transistor T3 is written into the second node S. In this process, the common voltage Vcm discharges the voltage on the sensing line 10, and the potentials of the sensing line 10 and the second node S are pulled down to the first potential.
  • the second potential is smaller than the first potential.
  • the second potential is 1V.
  • the common voltage Vcm is first set to a second potential smaller than the first potential.
  • the voltage on the sensing line 10 may be overdriven ( Over Drive) is charged and is quickly pulled down to near the first potential, and then the common voltage Vcm is directly switched from the second potential to the first potential, and the correct potential writing is performed on the sensing line 10 and the second node S, compared with the current
  • the time taken for the sensing line 10 to discharge to the first potential is greatly shortened, which can effectively reduce the duration of the rewriting phase t4.
  • the durations of the plurality of intermediate potentials are sequentially reduced, and the duration of the first intermediate potential is less than the duration of the second potential.
  • the time for the sensing line 10 to discharge to the first potential is greatly shortened, which can effectively reduce the length of the rewrite phase t4.
  • the initial phase t1 and the charging phase t2 On the premise that the total duration of the sensing phase t3 and the rewriting phase t4 is limited, it is beneficial to increase the duration of the charging phase t2 and improve the accuracy of the pixel driving circuit sensing.
  • the present invention further provides a pixel driving circuit, which includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a capacitor C1, an organic light emitting diode D1, a switch K1,
  • the sensing line 10 the sensing module 20, the data line Data, the scanning line WR, the sensing control line RD, and the voltage modulation module 30.
  • the anode of the organic light emitting diode D1 is electrically connected to the second node S, and the cathode is connected to the negative voltage VSS of the power source.
  • the switch K1 is a single-pole double-throw switch.
  • the moving contact 1 is electrically connected to the sensing line 10
  • the first static contact 2 is electrically connected to the voltage modulation module 30, and the second static contact 3 is electrically connected to the sensing module 20. .
  • the voltage modulation module 30 is configured to output a common voltage Vcm to the first stationary contact 2.
  • the voltage modulation module 30 causes the common voltage Vcm to be a second potential, and then switches from the second potential to a plurality of intermediate potentials in sequence, and then switches from the last intermediate potential to the first potential.
  • the second potential is less than the first potential
  • the odd-numbered intermediate potentials of the plurality of intermediate potentials are greater than the first potential
  • the even-numbered intermediate potentials are less than the first potential
  • the absolute values of the differences between the plurality of intermediate potentials and the first potential are in order Decreases
  • the difference between the first intermediate potential and the first potential is smaller than the difference between the first potential and the second potential.
  • the scanning line WR transmits a scanning signal to control the first thin film transistor T1 to be turned on
  • the sensing control line RD transmits a sensing signal to control the third thin film transistor T3 to be turned on
  • the switch K1 turns on its moving contact 1 and the first static contact 2
  • the data line Data writes the reference potential to the first node G via the first thin film transistor T1 that is turned on
  • the common voltage Vcm is written to the sensing line 10 as a first potential and is written to the third node through the third thin film transistor T3 that is turned on.
  • Two nodes S complete the initialization of the potentials of the first node G and the second node S.
  • the reference potential is greater than the first potential.
  • the three thin film transistors T3 charge the sensing line 10, so that the voltage on the second node S and the sensing line 10 continues to increase until the voltage of the second node S and the sensing line 10 is equal to the reference potential and the threshold voltage of the second thin film transistor T2. The difference is complete and charging is completed.
  • the scanning line WR transmits a scanning signal to control the first thin film transistor T1 to be turned off, and the sensing control line RD transmits a sensing signal to control the third thin film transistor T3 to be turned off.
  • the switch K1 turns on its moving contact 1 and the second static contact 3, and the sensing The detecting module 20 senses the voltage on the sensing line 10.
  • the scanning line WR transmits a scanning signal to control the first thin film transistor T1 to be turned on
  • the sensing control line RD transmits a sensing signal to control the third thin film transistor T3 to be turned on
  • the switch K1 turns on its moving contact 1 and the first static contact 2
  • the data line Data writes the display potential to the first node G via the turned-on first thin-film transistor T1, and the common voltage Vcm is firstly a second potential, and then switched to the first potential and written to the sensing line 10, and is turned on
  • the third thin film transistor T3 is written into the second node S.
  • the common voltage Vcm discharges the voltage on the sensing line 10, and the potentials of the sensing line 10 and the second node S are pulled down to the first potential.
  • the second potential is smaller than the first potential.
  • the pixel driving circuit of the present invention uses a voltage modulation module 30 capable of nanosecond level potential switching during operation to provide a common voltage Vcm to the first static contact 2 of the switch K1, and in the rewriting phase t4,
  • the common voltage Vcm is first a second potential smaller than the first potential, and then the common voltage Vcm is switched from the second potential to a plurality of intermediate potentials in order, and then the last intermediate potential is switched to the first potential.
  • the two nodes S perform correct potential writing.
  • the potential of the common voltage Vcm is lower than the first potential each time, the voltage on the sensing line 10 will be rapidly pulled down due to overdriving and charging. The voltage is quickly pulled down to the first potential.
  • the time for the sensing line 10 to discharge to the first potential is greatly shortened, which can effectively reduce the length of the rewrite phase t4.
  • the initial phase t1 and the charging phase t2 On the premise that the total duration of the sensing phase t3 and the rewriting phase t4 is limited, it is beneficial to increase the duration of the charging phase t2 and improve the accuracy of the pixel driving circuit sensing.
  • the common voltage in the rewriting phase, is first set to a second potential lower than the first potential, and then switched to the first potential and written to the second node.
  • the voltage on the sensing line will be quickly pulled down to close to the first potential due to overdrive charging, and then the common voltage is switched to the first potential to write the correct potential to the sensing line, which can effectively reduce
  • the length of the rewrite phase is beneficial to increase the length of the charging phase and improve the accuracy of sensing the pixel driving circuit.
  • the pixel driving circuit of the present invention can effectively reduce the duration of the rewrite phase, is beneficial to increase the duration of the charging phase, and improves the accuracy of sensing the pixel driving circuit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种像素驱动电路感测方法及像素驱动电路。该像素驱动电路感测方法在重新写入阶段（t4）中使公共电压（Vcm）先为一低于第一电位的第二电位而后切换为第一电位并写入第二节点（S），在公共电压（Vcm）为第二电位时感测线（10）上的电压会由于过驱动充电而被迅速拉低至接近第一电位，而后公共电压（Vcm）切换至第一电位对感测线（10）进行正确的电位写入，能够有效降低重新写入阶段（t4）时长，有利于增加充电阶段（t2）的时长，提升对像素驱动电路感测的准确性。

Description

像素驱动电路感测方法及像素驱动电路 技术领域
本发明涉及显示技术领域，尤其涉及一种像素驱动电路感测方法及像素驱动电路。
 背景技术
有机发光二极管（Organic Light Emitting Display，OLED）显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽、可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最具有发展潜力的显示装置。
OLED显示装置按照驱动方式可以分为无源矩阵型OLED（Passive Matrix OLED，PMOLED）和有源矩阵型OLED（Active Matrix OLED，AMOLED）两大类，即直接寻址和薄膜晶体管（Thin Film Transistor，TFT）矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光能效高，通常用作高清晰度的大尺寸显示装置。
AMOLED是电流驱动器件，当有电流流过有机发光二极管时，有机发光二极管发光，且发光亮度由流过有机发光二极管自身的电流决定。大部分已有的集成电路（IC）都只传输电压信号，故AMOLED的像素驱动电路需要完成将电压信号转变为电流信号的任务。同时，由于OLED显示装置的工艺和材料特性，显示时会出现显示不良（Mura），需要通过电学的方式实时对其感测以便于进行补偿。
请参阅图1，为现有的一种像素驱动电路的电路图，该像素驱动电路包括第一薄膜晶体管T10、第二薄膜晶体管T20、第三薄膜晶体管T30、电容C10、有机发光二极管D10、开关K10、感测线100、模数转换器ADC、扫描线WR、数据线DATA及感测控制线RD。所述第一薄膜晶体管T10的栅极电性连接扫描线WR，以接收扫描信号，源极电性连接数据线DATA，以接收数据信号，漏极电性连接第二薄膜晶体管T20的栅极。所述第二薄膜晶体管T20的漏极接入电源正电压VDD，源极电性连接有机发光二极管D10的阳极。所述第三薄膜晶体管T30的栅极电性连接感测控制线RD，以接收感测信号，源极电性连接有机发光二极管D10的阳极，漏极电性连接感测线100。所述电容C10的第一端电性连接第二薄膜晶体管T20的栅极，第二端电性连接第二薄膜晶体管T20的源极。有机发光二极管D10的阴极接入电源负电压VSS。开关K10为单刀双掷开关，其动触点4电性连接感测线100，第一静触点5接入公共电压VCM，第二静触点6电性连接模数转换器ADC。该像素驱动电路的工作过程包括显示阶段及帧消隐（Blank）阶段，在显示阶段，扫描线WR传输具有高电平脉冲的扫描信号，控制第一薄膜晶体管T10导通后截止，数据线DATA将显示电位写入第二薄膜晶体管T20的栅极，驱动有机发光二极管D10发光。请参阅图2，消隐阶段包括初始阶段t10、充电阶段t20、感测阶段t30及重新写入阶段t40。在初始阶段t10，扫描线WR传输高电位的扫描信号控制第一薄膜晶体管T10导通，感测控制线RD传输高电位的感测信号控制第三薄膜晶体管T30导通，开关K10将其动触点4与第一静触点5导通，数据线DATA将参考电位写入第二薄膜晶体管T20的栅极，公共电压VCM写入第二薄膜晶体管T20的源极，该参考电位大于公共电压VCM。在充电阶段t20，扫描线WR传输高电位的扫描信号控制第一薄膜晶体管T10导通，感测控制线RD传输高电位的感测信号控制第三薄膜晶体管T30导通，开关K1将其动触点4与第一静触点5及第二静触点6均断开，此时第二薄膜晶体管T20的源极电压也即感测线100上的电压不断上升直至第二薄膜晶体管T20的源极电压以及感测线100上的电压等于参考电位与第二薄膜晶体管T20阈值电压的差值。在感测阶段t30，扫描线WR传输低电位的扫描信号控制第一薄膜晶体管T10截止，感测控制线RD传输低电位的感测信号控制第三薄膜晶体管T30截止，开关K1将其动触点4与第二静触点6导通，模数转换器ADC对感测线100上的电压进行感测并产生对应的数据后锁存。在重新写入阶段t40，扫描线WR传输高电位的扫描信号控制第一薄膜晶体管T10导通，感测控制线RD传输高电位的感测信号控制第三薄膜晶体管T30导通，开关K1将其动触点4与第一静触点5导通，数据线DATA将显示电位写入第二薄膜晶体管T20的栅极，公共电压VCM写入感测线100，而此时由于感测线100上的电位相对于公共电压VCM已经抬升，公共电压VCM写入感测线100会需要较长时间将感测线100放电，使得重新写入阶段t40的时长较长，现有的OLED显示装置中帧消隐阶段的总时长很短（对于4K显示装置而言，帧消隐阶段的总时长为0.68ms），初始阶段t10的时长由于已经很短无法进行压缩，而感测阶段t30的时长受限于模数转换器ADC的特性也无法改变，重新写入阶段t40的时长增加使得充电阶段t20的时长被严重压缩，导致感测线100充电不充分，感测结果不准确。
 技术问题
本发明的目的在于提供一种像素驱动电路感测方法，能够有效降低重新写入阶段的时长，有利于增加充电阶段的时长，提升对像素驱动电路感测的准确性。
本发明的目的还在于提供一种像素驱动电路，能够有效降低重新写入阶段的时长，有利于增加充电阶段的时长，提升对像素驱动电路感测的准确性。
 技术解决方案
为实现上述目的，本发明提供一种像素驱动电路感测方法，包括如下步骤：
步骤S1、提供一像素驱动电路；所述像素驱动电路包括第一薄膜晶体管（T1）、第二薄膜晶体管（T2）、第三薄膜晶体管（T3）、电容（C1）、有机发光二极管（D1）、开关（K1）、感测线（10）、感测模块（20）、数据线（Data）、扫描线（WR）及感测控制线（RD）；
所述第一薄膜晶体管（T1）的栅极电性连接扫描线（WR），源极电性连接数据线（Data），漏极电性连接第一节点（G）；所述第二薄膜晶体管（T2）的栅极电性连接第一节点（G），漏极接入电源正电压（VDD），源极电性连接第二节点（S）；所述第三薄膜晶体管（T3）的栅极电性连接感测控制线（RD），源极电性连接第二节点（S），漏极电性连接感测线（10）；所述电容（C1）的第一端及第二端分别电性连接第一节点（G）及第二节点（S）；所述有机发光二极管（D1）的阳极电性连接第二节点（S），阴极接入电源负电压（VSS）；所述开关（K1）为单刀双掷开关，其动触点（1）电性连接感测线（10），第一静触点（2）接入公共电压（Vcm），第二静触点（3）电性连接感测模块（20）；
步骤S2、进入初始阶段（t1）；
扫描线（WR）传输扫描信号控制第一薄膜晶体管（T1）导通，感测控制线（RD）传输感测信号控制第三薄膜晶体管（T3）导通，开关（K1）将其动触点（1）与第一静触点（2）导通，数据线（Data）将参考电位写入第一节点（G），公共电压（Vcm）为一第一电位写入感测线（10）及第二节点（S）；所述参考电位大于第一电位；
步骤S3、进入充电阶段（t2）；
扫描线（WR）传输扫描信号控制第一薄膜晶体管（T1）导通，感测控制线（RD）传输感测信号控制第三薄膜晶体管（T3）导通，开关（K1）将其动触点（1）与第一静触点（2）及第二静触点（3）均断开，数据线（Data）将参考电位写入第一节点（G），电源正电压（VDD）为第二节点（S）及感测线（10）进行充电，使第二节点（S）及感测线（10）上的电压不断上升直至第二节点（S）及感测线（10）的电压等于参考电位与第二薄膜晶体管（T2）阈值电压的差值；
步骤S4、进入感测阶段（t3）；
扫描线（WR）传输扫描信号控制第一薄膜晶体管（T1）截止，感测控制线（RD）传输感测信号控制第三薄膜晶体管（T3）截止，开关（K1）将其动触点（1）与第二静触点（3）导通，感测模块（20）对感测线（10）上的电压进行感测；
步骤S5、进入重新写入阶段（t4）；
扫描线（WR）传输扫描信号控制第一薄膜晶体管（T1）导通，感测控制线（RD）传输感测信号控制第三薄膜晶体管（T3）导通，开关（K1）将其动触点（1）与第一静触点（2）导通，数据线（Data）将显示电位写入第一节点（G），公共电压（Vcm）先为一第二电位而后切换为第一电位并写入感测线（10）及第二节点（S），将感测线（10）及第二节点（S）的电位下拉至第一电位；所述第二电位小于第一电位；
所述步骤S2、步骤S3及步骤S5中，扫描线（WR）传输高电位的扫描信号，感测控制线（RD）传输高电位的感测信号；所述步骤S4中，扫描线（WR）传输低电位的扫描信号，感测控制线（RD）传输低电位的感测信号；及所述步骤S3及步骤S4中，所述公共电压（Vcm）均为第一电位。
所述步骤S5中，所述公共电压（Vcm）由第二电位切换为第一电位的具体方式为：所述公共电压（Vcm）先由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位；多个中间电位中奇数位的中间电位大于第一电位，偶数位的中间电位小于第一电位，多个中间电位与第一电位的差值的绝对值依次减小，且第一个中间电位与第一电位的差值小于第一电位与第二电位的差值。
所述像素驱动电路还包括与开关（K1）的第一静触点（2）电性连接的电压调制模块（30）；所述公共电压（Vcm）由所述电压调制模块（30）提供。
所述电压调制模块（30）改变公共电压（Vcm）的电位时，任意两个相邻的公共电压（Vcm）电位变化时刻之间的时间间隔为纳秒级别。
所述像素驱动电路还包括电路板（40），所述电压调制模块（30）设于所述电路板（40）上。
所述第一电位为4伏特(V)，第二电位为1伏特(V)。
所述感测模块（20）为模数转换器（ADC）；
所述步骤S4中，模数转换器（ADC）对感测线（10）上的电压进行感测后还对感测线（10）上的电压进行模数转换处理产生对应的数据并进行锁存。
为实现上述目的，本发明还提供一种像素驱动电路感测方法，包括如下步骤：
步骤S1、提供一像素驱动电路；所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、电容、有机发光二极管、开关、感测线、感测模块、数据线、扫描线及感测控制线；
所述第一薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接第一节点；所述第二薄膜晶体管的栅极电性连接第一节点，漏极接入电源正电压，源极电性连接第二节点；所述第三薄膜晶体管的栅极电性连接感测控制线，源极电性连接第二节点，漏极电性连接感测线；所述电容的第一端及第二端分别电性连接第一节点及第二节点；所述有机发光二极管的阳极电性连接第二节点，阴极接入电源负电压；所述开关为单刀双掷开关，其动触点电性连接感测线，第一静触点接入公共电压，第二静触点电性连接感测模块；
步骤S2、进入初始阶段；
扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点导通，数据线将参考电位写入第一节点，公共电压为一第一电位写入感测线及第二节点；所述参考电位大于第一电位；
步骤S3、进入充电阶段；
扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点及第二静触点均断开，数据线将参考电位写入第一节点，电源正电压为第二节点及感测线进行充电，使第二节点及感测线上的电压不断上升直至第二节点及感测线的电压等于参考电位与第二薄膜晶体管阈值电压的差值；
步骤S4、进入感测阶段；
扫描线传输扫描信号控制第一薄膜晶体管截止，感测控制线传输感测信号控制第三薄膜晶体管截止，开关将其动触点与第二静触点导通，感测模块对感测线上的电压进行感测；
步骤S5、进入重新写入阶段；
扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点导通，数据线将显示电位写入第一节点，公共电压先为一第二电位而后切换为第一电位并写入感测线及第二节点，将感测线及第二节点的电位下拉至第一电位；所述第二电位小于第一电位。
所述步骤S5中，所述公共电压由第二电位切换为第一电位的具体方式为：所述公共电压先由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位；多个中间电位中奇数位的中间电位大于第一电位，偶数位的中间电位小于第一电位，多个中间电位与第一电位的差值的绝对值依次减小，且第一个中间电位与第一电位的差值小于第一电位与第二电位的差值。
所述像素驱动电路还包括与开关的第一静触点电性连接的电压调制模块；所述公共电压由所述电压调制模块提供。
所述电压调制模块改变公共电压的电位时，任意两个相邻的公共电压电位变化时刻之间的时间间隔为纳秒级别。
所述像素驱动电路还包括电路板，所述电压调制模块设于所述电路板上。
所述步骤S2、步骤S3及步骤S5中，扫描线传输高电位的扫描信号，感测控制线传输高电位的感测信号；
所述步骤S4中，扫描线传输低电位的扫描信号，感测控制线传输低电位的感测信号。
所述第一电位为4V，第二电位为1V。
所述感测模块为模数转换器；
所述步骤S4中，模数转换器对感测线上的电压进行感测后还对感测线上的电压进行模数转换处理产生对应的数据并进行锁存。
所述步骤S3及步骤S4中，所述公共电压均为第一电位。
本发明还提供一种像素驱动电路，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、电容、有机发光二极管、开关、感测线、感测模块、数据线、扫描线、感测控制线及电压调制模块；
所述第一薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接第一节点；所述第二薄膜晶体管的栅极电性连接第一节点，漏极接入电源正电压，源极电性连接第二节点；所述第三薄膜晶体管的栅极电性连接感测控制线，源极电性连接第二节点，漏极电性连接感测线；所述电容的第一端及第二端分别电性连接第一节点及第二节点；所述有机发光二极管的阳极电性连接第二节点，阴极接入电源负电压；所述开关为单刀双掷开关，其动触点电性连接感测线，第一静触点电性连接电压调制模块，第二静触点电性连接感测模块；
所述电压调制模块用于向第一静触点输出公共电压；在重新写入阶段，电压调制模块使公共电压先为一第二电位并由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位；所述第二电位小于第一电位，多个中间电位中奇数位的中间电位大于第一电位，偶数位的中间电位小于第一电位，多个中间电位与第一电位的差值的绝对值依次减小，且第一个中间电位与第一电位的差值小于第一电位与第二电位的差值。
 有益效果
本发明的有益效果：本发明提供的一种像素驱动电路感测方法在重新写入阶段中使公共电压先为一低于第一电位的第二电位而后切换为第一电位并写入第二节点，在公共电压为第二电位时感测线上的电压会由于过驱动充电而被迅速拉低至接近第一电位，而后公共电压切换至第一电位对感测线进行正确的电位写入，能够有效降低重新写入阶段的时长，有利于增加充电阶段的时长，提升对像素驱动电路感测的准确性。本发明的像素驱动电路能够有效降低重新写入阶段的时长，有利于增加充电阶段的时长，提升对像素驱动电路感测的准确性。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种像素驱动电路的电路图；
图2为图1所示的像素驱动的电路在帧消隐阶段的时序图；
图3为本发明的像素驱动电路感测方法的流程图；
图4为本发明的像素驱动电路感测方法的第一实施例的像素驱动电路的电路图；
图5为本发明的像素驱动电路感测方法的第一实施例的时序图；
图6为本发明的像素驱动电路感测方法的第二实施例的像素驱动电路的电路图暨本发明的像素驱动电路的电路图；
图7为本发明的像素驱动电路感测方法的第二实施例的时序图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3至图5，本发明的像素驱动电路感测方法的第一实施例包括如下步骤：
步骤S1、请参阅图4，提供一像素驱动电路。所述像素驱动电路包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、电容C1、有机发光二极管D1、开关K1、感测线10、感测模块20、数据线Data、扫描线WR及感测控制线RD。所述第一薄膜晶体管T1的栅极电性连接扫描线WR，源极电性连接数据线Data，漏极电性连接第一节点G。所述第二薄膜晶体管T2的栅极电性连接第一节点G，漏极接入电源正电压VDD，源极电性连接第二节点S。所述第三薄膜晶体管T3的栅极电性连接感测控制线RD，源极电性连接第二节点S，漏极电性连接感测线10。所述电容C1的第一端及第二端分别电性连接第一节点G及第二节点S。所述有机发光二极管D1的阳极电性连接第二节点S，阴极接入电源负电压VSS。所述开关K1为单刀双掷开关，其动触点1电性连接感测线10，第一静触点2接入公共电压Vcm，第二静触点3电性连接感测模块20。
具体地，请参阅图4，所述感测模块20为模数转换器ADC。
步骤S2、进入初始阶段t1。
扫描线WR传输扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输感测信号控制第三薄膜晶体管T3导通，开关K1将其动触点1与第一静触点2导通，数据线Data经导通的第一薄膜晶体管T1将参考电位写入第一节点G，公共电压Vcm为一第一电位写入感测线10并经导通的第三薄膜晶体管T3写入第二节点S，完成第一节点G及第二节点S电位的初始化。所述参考电位大于第一电位。
具体地，请参阅图5，所述步骤S2中，扫描线WR传输高电位的扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输高电位的感测信号控制第三薄膜晶体管T3导通。
优选地，所述第一电位为4V。
优选地，扫描信号及感测信号的高电位均为25V。
步骤S3、进入充电阶段t2。
扫描线WR传输扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输感测信号控制第三薄膜晶体管T3导通，开关K1将其动触点1与第一静触点2及第二静触点3均断开，数据线Data将参考电位写入第一节点G，此时第二薄膜晶体管T2导通，电源正电压VDD为第二节点S进行充电，并经导通的第三薄膜晶体管T3为感测线10进行充电，使第二节点S及感测线10上的电压不断上升直至第二节点S及感测线10的电压等于参考电位与第二薄膜晶体管T2阈值电压的差值，完成充电。
具体地，请参阅图5，所述步骤S3中，扫描线WR传输高电位的扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输高电位的感测信号控制第二薄膜晶体管T2导通。
具体地，请参阅图5，所述步骤S3中，所述公共电压Vcm保持第一电位。
步骤S4、进入感测阶段t3。
扫描线WR传输扫描信号控制第一薄膜晶体管T1截止，感测控制线RD传输感测信号控制第三薄膜晶体管T3截止，开关K1将其动触点1与第二静触点3导通，感测模块20对感测线10上的电压进行感测。
具体地，请参阅图5，所述步骤S4中，扫描线WR传输低电位的扫描信号控制第一薄膜晶体管T1截止，感测控制线RD传输低电位的感测信号控制第三薄膜晶体管T3截止。
优选地，扫描信号及感测信号的低电位均为-5V。
具体地，请参阅图5，所述步骤S4中，所述公共电压Vcm保持第一电位。
具体地，所述步骤S4中，模数转换器ADC对感测线10上的电压进行感测后还对感测线10上的电压进行模数转换处理产生对应的数据并进行锁存。
步骤S5、进入重新写入阶段t4。
扫描线WR传输扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输感测信号控制第三薄膜晶体管T3导通，开关K1将其动触点1与第一静触点2导通，数据线Data将显示电位经导通的第一薄膜晶体管T1写入第一节点G，公共电压Vcm先为一第二电位而后切换为第一电位并写入感测线10，并经导通的第三薄膜晶体管T3写入第二节点S，此过程公共电压Vcm对感测线10上的电压进行放电，将感测线10及第二节点S的电位下拉至第一电位。所述第二电位小于第一电位。
具体地，请参阅图5，步骤S5中，扫描线WR传输高电位的扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输高电位的感测信号控制第二薄膜晶体管T2导通。
具体地，请参阅图5，在本发明的第一实施例中，所述步骤S5中，公共电压Vcm先为第二电位而后直接切换为第一电位。
优选地，所述第二电位为1V。
需要说明的是，本发明的第一实施例中，在重新写入阶段t4，使公共电压Vcm先为小于第一电位的第二电位，此时感测线10上的电压会由于过驱动（Over Drive）充电而被迅速拉低至接近第一电位，而后公共电压Vcm由第二电位直接切换至第一电位，对感测线10及第二节点S进行正确的电位写入，相较于现有技术，感测线10放电至第一电位的时间大大缩短，能够有效降低重新写入阶段t4的时长，在初始阶段t1、充电阶段t2、感测阶段t3、重新写入阶段t4的总时长有限的前提下，有利于增加充电阶段t2的时长，提升对像素驱动电路感测的准确性。
请参阅图3、图6及图7，本发明的像素驱动电路感测方法的第二实施例与上述第一实施例的区别在于：请参阅图7，所述步骤S5中，所述公共电压Vcm由第二电位切换为第一电位的具体方式为：所述公共电压Vcm先由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位。多个中间电位中奇数位的中间电位大于第一电位，偶数位的中间电位小于第一电位，多个中间电位与第一电位的差值的绝对值依次减小，且第一个中间电位与第一电位的差值小于第一电位与第二电位的差值。
具体地，请参阅图6，在本发明的第二实施例中，所述像素驱动电路还包括与开关K1的第一静触点2电性连接的电压调制模块30以及电路板（PCB）40。所述公共电压Vcm由所述电压调制模块30提供。该电压调制模块30设置在电路板40上。
进一步地，所述电压调制模块30改变公共电压Vcm的电位时，任意两个相邻的公共电压Vcm电位变化时刻之间的时间间隔为纳秒级别，也即所述电压调整模块30能够对公共电压Vcm进行纳秒级别的电位切换，进而在本发明的第二实施例中，所述第二电位及每一中间电位的时长均为纳秒级别。
优选地，请参阅图7，多个中间电位的时长依次减小，且第一个中间电位的时长小于第二电位的时长。
需要说明的是，本发明的第二实施例中，利用能够进行纳秒级别电位切换的电压调制模块30向开关K1的第一静触点2提供公共电压Vcm，在重新写入阶段t4，使公共电压Vcm先为小于第一电位的第二电位，而后公共电压Vcm先由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位，对感测线10及第二节点S进行正确的电位写入，在每一次公共电压Vcm的电位小于第一电位时，感测线10上的电压均会由于过驱动充电而被迅速拉低，使得感测线10上的电压被迅速拉低至第一电位，相较于现有技术，感测线10放电至第一电位的时间大大缩短，能够有效降低重新写入阶段t4的时长，在初始阶段t1、充电阶段t2、感测阶段t3、重新写入阶段t4的总时长有限的前提下，有利于增加充电阶段t2的时长，提升对像素驱动电路感测的准确性。
请参阅图6，基于同一发明构思，本发明还提供一种像素驱动电路，包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、电容C1、有机发光二极管D1、开关K1、感测线10、感测模块20、数据线Data、扫描线WR、感测控制线RD及电压调制模块30。
所述第一薄膜晶体管T1的栅极电性连接扫描线WR，源极电性连接数据线Data，漏极电性连接第一节点G。所述第二薄膜晶体管T2的栅极电性连接第一节点G，漏极接入电源正电压VDD，源极电性连接第二节点S。所述第三薄膜晶体管T3的栅极电性连接感测控制线RD，源极电性连接第二节点S，漏极电性连接感测线10。所述电容C1的第一端及第二端分别电性连接第一节点G及第二节点S。所述有机发光二极管D1的阳极电性连接第二节点S，阴极接入电源负电压VSS。所述开关K1为单刀双掷开关，其动触点1电性连接感测线10，第一静触点2电性连接电压调制模块30，第二静触点3电性连接感测模块20。
所述电压调制模块30用于向第一静触点2输出公共电压Vcm。在重新写入阶段，电压调制模块30使公共电压Vcm先为一第二电位并由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位。所述第二电位小于第一电位，多个中间电位中奇数位的中间电位大于第一电位，偶数位的中间电位小于第一电位，多个中间电位与第一电位的差值的绝对值依次减小，且第一个中间电位与第一电位的差值小于第一电位与第二电位的差值。
具体地，请参阅图6，所述像素驱动电路还包括电路板40。所述电压调制模块30设置在电路板40上。
具体地，所述电压调制模块30改变公共电压Vcm的电位时，任意两个相邻的公共电压Vcm电位变化时刻之间的时间间隔为纳秒级别，也即所述电压调整模块30能够对公共电压Vcm进行纳秒级别的电位切换，进而在重新写入阶段，所述第二电位及每一中间电位的时长均为纳秒级别。
具体地，请结合图6及图7，本发明的像素驱动电路的工作过程如下：
首先，进入初始阶段t1。扫描线WR传输扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输感测信号控制第三薄膜晶体管T3导通，开关K1将其动触点1与第一静触点2导通，数据线Data经导通的第一薄膜晶体管T1将参考电位写入第一节点G，公共电压Vcm为一第一电位写入感测线10并经导通的第三薄膜晶体管T3写入第二节点S，完成第一节点G及第二节点S电位的初始化。所述参考电位大于第一电位。
接着，进入充电阶段t2。扫描线WR传输扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输感测信号控制第三薄膜晶体管T3导通，开关K1将其动触点1与第一静触点2及第二静触点3均断开，数据线Data将参考电位写入第一节点G，此时第二薄膜晶体管T2导通，电源正电压VDD为第二节点S进行充电，并经导通的第三薄膜晶体管T3为感测线10进行充电，使第二节点S及感测线10上的电压不断上升直至第二节点S及感测线10的电压等于参考电位与第二薄膜晶体管T2阈值电压的差值，完成充电。
之后，进入感测阶段t3。扫描线WR传输扫描信号控制第一薄膜晶体管T1截止，感测控制线RD传输感测信号控制第三薄膜晶体管T3截止，开关K1将其动触点1与第二静触点3导通，感测模块20对感测线10上的电压进行感测。
而后，进入重新写入阶段t4。扫描线WR传输扫描信号控制第一薄膜晶体管T1导通，感测控制线RD传输感测信号控制第三薄膜晶体管T3导通，开关K1将其动触点1与第一静触点2导通，数据线Data将显示电位经导通的第一薄膜晶体管T1写入第一节点G，公共电压Vcm先为一第二电位而后切换为第一电位并写入感测线10，并经导通的第三薄膜晶体管T3写入第二节点S，此过程公共电压Vcm对感测线10上的电压进行放电，将感测线10及第二节点S的电位下拉至第一电位。所述第二电位小于第一电位。
需要说明的是，本发明的像素驱动电路在工作时利用能够进行纳秒级别电位切换的电压调制模块30向开关K1的第一静触点2提供公共电压Vcm，在重新写入阶段t4，使公共电压Vcm先为小于第一电位的第二电位，而后公共电压Vcm先由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位，对感测线10及第二节点S进行正确的电位写入，在每一次公共电压Vcm的电位小于第一电位时，感测线10上的电压均会由于过驱动充电而被迅速拉低，使得感测线10上的电压被迅速拉低至第一电位，相较于现有技术，感测线10放电至第一电位的时间大大缩短，能够有效降低重新写入阶段t4的时长，在初始阶段t1、充电阶段t2、感测阶段t3、重新写入阶段t4的总时长有限的前提下，有利于增加充电阶段t2的时长，提升对像素驱动电路感测的准确性。
综上所述，本发明的像素驱动电路感测方法在重新写入阶段中使公共电压先为一低于第一电位的第二电位而后切换为第一电位并写入第二节点，在公共电压为第二电位时感测线上的电压会由于过驱动充电而被迅速拉低至接近第一电位，而后公共电压切换至第一电位对感测线进行正确的电位写入，能够有效降低重新写入阶段的时长，有利于增加充电阶段的时长，提升对像素驱动电路感测的准确性。本发明的像素驱动电路能够有效降低重新写入阶段的时长，有利于增加充电阶段的时长，提升对像素驱动电路感测的准确性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (17)

  1. 一种像素驱动电路感测方法，其包括如下步骤：
    步骤S1、提供一像素驱动电路；所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、电容、有机发光二极管、开关、感测线、感测模块、数据线、扫描线及感测控制线；
    所述第一薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接第一节点；所述第二薄膜晶体管的栅极电性连接第一节点，漏极接入电源正电压，源极电性连接第二节点；所述第三薄膜晶体管的栅极电性连接感测控制线，源极电性连接第二节点，漏极电性连接感测线；所述电容的第一端及第二端分别电性连接第一节点及第二节点；所述有机发光二极管的阳极电性连接第二节点，阴极接入电源负电压；所述开关为单刀双掷开关，其动触点电性连接感测线，第一静触点接入公共电压，第二静触点电性连接感测模块；
    步骤S2、进入初始阶段；
    扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点导通，数据线将参考电位写入第一节点，公共电压为一第一电位写入感测线及第二节点；所述参考电位大于第一电位；
    步骤S3、进入充电阶段；
    扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点及第二静触点均断开，数据线将参考电位写入第一节点，电源正电压为第二节点及感测线进行充电，使第二节点及感测线上的电压不断上升直至第二节点及感测线的电压等于参考电位与第二薄膜晶体管阈值电压的差值；
    步骤S4、进入感测阶段；
    扫描线传输扫描信号控制第一薄膜晶体管截止，感测控制线传输感测信号控制第三薄膜晶体管截止，开关将其动触点与第二静触点导通，感测模块对感测线上的电压进行感测；
    步骤S5、进入重新写入阶段；
    扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点导通，数据线将显示电位写入第一节点，公共电压先为一第二电位而后切换为第一电位并写入感测线（10）及第二节点，将感测线及第二节点的电位下拉至第一电位；所述第二电位小于第一电位；
    所述步骤S2、步骤S3及步骤S5中，扫描线传输高电位的扫描信号，感测控制线传输高电位的感测信号；所述步骤S4中，扫描线传输低电位的扫描信号，感测控制线传输低电位的感测信号；及所述步骤S3及步骤S4中，所述公共电压均为第一电位。
  2. 如权利要求1所述的像素驱动电路感测方法，其中，所述步骤S5中，所述公共电压由第二电位切换为第一电位的具体方式为：所述公共电压先由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位；多个中间电位中奇数位的中间电位大于第一电位，偶数位的中间电位小于第一电位，多个中间电位与第一电位的差值的绝对值依次减小，且第一个中间电位与第一电位的差值小于第一电位与第二电位的差值。
  3. 如权利要求2所述的像素驱动电路感测方法，其中，所述像素驱动电路还包括与开关的第一静触点电性连接的电压调制模块；所述公共电压由所述电压调制模块提供。
  4. 如权利要求3所述的像素驱动电路感测方法，其中，所述电压调制模块改变公共电压的电位时，任意两个相邻的公共电压电位变化时刻之间的时间间隔为纳秒级别。
  5. 如权利要求3所述的像素驱动电路感测方法，其中，所述像素驱动电路还包括电路板，所述电压调制模块设于所述电路板上。
  6. 如权利要求1所述的像素驱动电路感测方法，其中，所述第一电位为4伏特，第二电位为1伏特。
  7. 如权利要求1所述的像素驱动电路感测方法，其中，所述感测模块为模数转换器；
    所述步骤S4中，模数转换器对感测线上的电压进行感测后还对感测线上的电压进行模数转换处理产生对应的数据并进行锁存。
  8. 一种像素驱动电路感测方法，其包括如下步骤：
    步骤S1、提供一像素驱动电路；所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、电容、有机发光二极管、开关、感测线、感测模块、数据线、扫描线及感测控制线；
    所述第一薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接第一节点；所述第二薄膜晶体管的栅极电性连接第一节点，漏极接入电源正电压，源极电性连接第二节点；所述第三薄膜晶体管的栅极电性连接感测控制线，源极电性连接第二节点，漏极电性连接感测线；所述电容的第一端及第二端分别电性连接第一节点及第二节点；所述有机发光二极管的阳极电性连接第二节点，阴极接入电源负电压；所述开关为单刀双掷开关，其动触点电性连接感测线，第一静触点接入公共电压，第二静触点电性连接感测模块；
    步骤S2、进入初始阶段；
    扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点导通，数据线将参考电位写入第一节点，公共电压为一第一电位写入感测线及第二节点；所述参考电位大于第一电位；
    步骤S3、进入充电阶段；
    扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点及第二静触点均断开，数据线将参考电位写入第一节点，电源正电压为第二节点及感测线进行充电，使第二节点及感测线上的电压不断上升直至第二节点及感测线的电压等于参考电位与第二薄膜晶体管阈值电压的差值；
    步骤S4、进入感测阶段；
    扫描线传输扫描信号控制第一薄膜晶体管截止，感测控制线传输感测信号控制第三薄膜晶体管截止，开关将其动触点与第二静触点导通，感测模块对感测线上的电压进行感测；
    步骤S5、进入重新写入阶段；
    扫描线传输扫描信号控制第一薄膜晶体管导通，感测控制线传输感测信号控制第三薄膜晶体管导通，开关将其动触点与第一静触点导通，数据线将显示电位写入第一节点，公共电压先为一第二电位而后切换为第一电位并写入感测线及第二节点，将感测线及第二节点的电位下拉至第一电位；所述第二电位小于第一电位。
  9. 如权利要求8所述的像素驱动电路感测方法，其中，所述步骤S5中，所述公共电压由第二电位切换为第一电位的具体方式为：所述公共电压先由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位；多个中间电位中奇数位的中间电位大于第一电位，偶数位的中间电位小于第一电位，多个中间电位与第一电位的差值的绝对值依次减小，且第一个中间电位与第一电位的差值小于第一电位与第二电位的差值。
  10. 如权利要求9所述的像素驱动电路感测方法，其中，所述像素驱动电路还包括与开关的第一静触点电性连接的电压调制模块；所述公共电压由所述电压调制模块提供。
  11. 如权利要求10所述的像素驱动电路感测方法，其中，所述电压调制模块改变公共电压的电位时，任意两个相邻的公共电压电位变化时刻之间的时间间隔为纳秒级别。
  12. 如权利要求10所述的像素驱动电路感测方法，其中，所述像素驱动电路还包括电路板，所述电压调制模块设于所述电路板上。
  13. 如权利要求8所述的像素驱动电路感测方法，其中，所述步骤S2、步骤S3及步骤S5中，扫描线传输高电位的扫描信号，感测控制线传输高电位的感测信号；
    所述步骤S4中，扫描线传输低电位的扫描信号，感测控制线传输低电位的感测信号。
  14. 如权利要求8所述的像素驱动电路感测方法，其中，所述第一电位为4伏特，第二电位为1伏特。
  15. 如权利要求8所述的像素驱动电路感测方法，其中，所述感测模块为模数转换器；
    所述步骤S4中，模数转换器对感测线上的电压进行感测后还对感测线上的电压进行模数转换处理产生对应的数据并进行锁存。
  16. 如权利要求8所述的像素驱动电路感测方法，其中，所述步骤S3及步骤S4中，所述公共电压均为第一电位。
  17. 一种像素驱动电路，其包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、电容、有机发光二极管、开关、感测线、感测模块、数据线、扫描线、感测控制线及电压调制模块；
    所述第一薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接第一节点；所述第二薄膜晶体管的栅极电性连接第一节点，漏极接入电源正电压，源极电性连接第二节点；所述第三薄膜晶体管的栅极电性连接感测控制线，源极电性连接第二节点，漏极电性连接感测线；所述电容的第一端及第二端分别电性连接第一节点及第二节点；所述有机发光二极管的阳极电性连接第二节点，阴极接入电源负电压；所述开关为单刀双掷开关，其动触点电性连接感测线，第一静触点电性连接电压调制模块，第二静触点电性连接感测模块；
    所述电压调制模块用于向第一静触点输出公共电压；在重新写入阶段，电压调制模块使公共电压先为一第二电位并由第二电位依次切换为多个中间电位，而后由最后一个中间电位切换为第一电位；所述第二电位小于第一电位，多个中间电位中奇数位的中间电位大于第一电位，偶数位的中间电位小于第一电位，多个中间电位与第一电位的差值的绝对值依次减小，且第一个中间电位与第一电位的差值小于第一电位与第二电位的差值。
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