WO2020015129A1 - 一种随机内存使用纠错码校验免去冗余储存单元的方法 - Google Patents

一种随机内存使用纠错码校验免去冗余储存单元的方法 Download PDF

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WO2020015129A1
WO2020015129A1 PCT/CN2018/105886 CN2018105886W WO2020015129A1 WO 2020015129 A1 WO2020015129 A1 WO 2020015129A1 CN 2018105886 W CN2018105886 W CN 2018105886W WO 2020015129 A1 WO2020015129 A1 WO 2020015129A1
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memory
unit
check
memory storage
data
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PCT/CN2018/105886
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English (en)
French (fr)
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陈育鸣
李庭育
洪振洲
魏智汎
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江苏华存电子科技有限公司
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Publication of WO2020015129A1 publication Critical patent/WO2020015129A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/102—Error in check bits

Definitions

  • the present invention relates to the field of memory technology, and in particular to a method for using random error memory to eliminate redundant storage units by using error correction code checking.
  • Memory is one of the important components in a computer, and it is the bridge that communicates with the CPU. All programs in the computer run in memory, so the performance of memory has a great impact on the computer. Memory is also called internal memory, which is used to temporarily store the operational data in the CPU and data exchanged with external memories such as hard disks. As long as the computer is running, the CPU will transfer the data to be calculated into the memory for operation. When the operation is completed, the CPU will transfer the results. The operation of the memory also determines the stable operation of the computer. Memory is made up of memory chips, circuit boards, and gold fingers.
  • the current memory control system mostly uses Hamming code for random data protection, and the ratio of the data bit width to the parity bit width is roughly 2: 1/4: 1/8: 1/16: 1/32: 1.
  • This traditional school The protection mode requires redundant storage units to store error correction check codes.
  • the purpose of the present invention is to provide a method for using random error memory to check error-correcting codes to eliminate redundant storage units, so as to solve the problems mentioned in the background art.
  • a method for random memory using error correction code verification to eliminate redundant storage units including a main control chip, wherein the main control chip is provided with a memory storage control module and a memory Control the physical layer, the memory storage control module is provided with a writing unit and a reading unit, the writing unit and the reading unit are respectively connected to the memory control physical layer, and the memory control physical layer is connected to a plurality of memory storage components;
  • the multiple memory storage components include a first memory storage component, a second memory storage component, a third memory storage component, and an Nth memory storage component, where N is an integer greater than 3.
  • it further comprises a check bit generating unit and a check checking unit.
  • the check bit generating unit and the check checking unit are both provided in a memory storage control module, and the check bit generating unit is connected to a writing unit; the check The inspection unit is connected to the reading unit.
  • a method for using random error memory to eliminate redundant storage units by using error correction code verification includes the following steps:
  • the present invention has the beneficial effect that the present invention uses a check digit embedded manner to store the check digit and data into an external random memory space at the same time to improve the traditional use of a Hamming code requiring additional storage space.
  • FIG. 1 is a schematic diagram of a random memory control unit inside a main control of the present invention
  • FIG. 2 is a schematic diagram of a memory component configured with additional parity bit storage in the present invention
  • FIG. 3 is a schematic diagram of a memory component for storage according to the present invention without an additional parity bit
  • FIG. 4 is a schematic diagram of generating and writing a parity bit controlled by a random memory control unit of the present invention
  • FIG. 5 is a schematic diagram of reading data and verifying data from a random memory controlled by a random memory control unit according to the present invention
  • FIG. 6 is a schematic diagram of an unconfigured dedicated check bit storage component according to the present invention.
  • FIG. 7 is another schematic diagram of an unconfigured dedicated check bit storage component according to the present invention.
  • the present invention provides a technical solution: a method for random memory using error correction code verification to eliminate redundant storage units, including a main control chip 1, which is provided with a memory therein A storage control module 2 and a memory control physical layer 3, the memory storage control module 2 is provided with a writing unit 4 and a reading unit 5, and the writing unit 4 and the reading unit 5 are respectively connected to the memory control physical layer 3,
  • the memory control physical layer 3 is connected to multiple memory storage components; the multiple memory storage components include a first memory storage component 6, a second memory storage component 7, a third memory storage component 8, and an Nth memory storage component, where N is greater than An integer of 3; further comprising a check bit generating unit 9 and a check checking unit 10, the check bit generating unit 9 and the check checking unit 10 are both provided in a memory storage control module 2, and the check bit generating unit 9 is connected to write Input unit 4; the check unit 10 is connected to the reading unit 5.
  • a method for using random error memory to check an error correction code to eliminate redundant storage units includes the following steps:
  • the present invention uses a check digit embedding method to store the check digit and data into an external random memory space at the same time to improve the traditional use of Hamming codes, which requires additional storage space.
  • User data and parity bit data are used to verify user data in the verification module.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

一种随机内存使用纠错码校验免去冗余储存单元的方法，包括主控芯片(1)，主控芯片(1)内设有内存储存控制模块(2)和内存控制物理层(3)，内存储存控制模块(2)内设有写入单元(4)和读取单元(5)，写入单元(4)和读取单元(5)分别连接内存控制物理层(3)，内存控制物理层(3)连接多个内存储存组件，该方法使用以校验位内嵌的方式将校验位与数据同时存进外部随机内存空间以改善传统使用汉明码需要额外储存空间，读取时,同时或依序读出用户数据与校验位数据,于校验模块内进行用户数据校验运算。

Description

一种随机内存使用纠错码校验免去冗余储存单元的方法 技术领域
本发明涉及内存技术领域，具体为一种随机内存使用纠错码校验免去冗余储存单元的方法。
背景技术
内存是计算机中重要的部件之一，它是与CPU进行沟通的桥梁。计算机中所有程序的运行都是在内存中进行的，因此内存的性能对计算机的影响非常大。内存也被称为内存储器，其作用是用于暂时存放CPU中的运算数据，以及与硬盘等外部存储器交换的数据。只要计算机在运行中，CPU就会把需要运算的数据调到内存中进行运算，当运算完成后CPU再将结果传送出来，内存的运行也决定了计算机的稳定运行。内存是由内存芯片、电路板、金手指等部分组成的。
现行内存控制系统多以汉明码方式做随机数据保护,其数据位宽与校验位宽的比例大致为2:1/4:1/8:1/16:1/32:1.此传统校验保护方式需配置冗余储存单元用以储存纠错校验码。
发明内容
本发明的目的在于提供一种随机内存使用纠错码校验免去冗余储存单元的方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种随机内存使用纠错码校验免去冗余储存单元的方法，包括主控芯片，所述主控芯片内设有内存储存控制模块和内存控制物理层，所述内存储存控制模块内设有写入单元和读取单元，所述写入单元和读取单元分别连接内存控制物理层，所述内存控制物理层连接多个内存储存组件；多个内存储存组件包括第一内存储存组件、第二内存储存组件、第三内存储存组件、第N内存储存组件，N为大于3的整数。
优选的，还包括检验位产生单元和校验检查单元，所述检验位产生单元和校验检查单元均设置在内存储存控制模块中，所述检验位产生单元连接写入单元；所述校验检查单元连接读取单元。
优选的，一种随机内存使用纠错码校验免去冗余储存单元的方法，包括以下步骤：
A、首先对数据数据做运算产生校验用的校验位,以跟随或配置到另一区块的方式将校验位与数据同时存进外部随机内存空间；
B、读取时,同时读出用户数据与校验位数据,于校验模块内进行用户数据校验运算。
与现有技术相比，本发明的有益效果是：本发明使用以校验位内嵌的方式将校验位与数据同时存进外部随机内存空间以改善传统使用汉明码需要额外储存空间，读取时,同时或依序读出用户数据与校验位数据,于校验模块内进行用户数据校验运算。
附图说明
图1为本发明一个主控内部的随机内存控制单元示意图；
图2为本发明中配置额外的校验位储存用内存组件示意图；
图3为本发明不配置额外的校验位储存用内存组件示意图；
图4为本发明随机内存控制单元所控制的校验位产生与写入随机内存的示意图；
图5为本发明随机内存控制单元所控制从随机内存读出资料与校验示意图；
图6为本发明无配置专用校验位储存组件示意图；
图7为本发明无配置专用校验位储存组件另一示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1-7，本发明提供一种技术方案：一种随机内存使用纠错码校验免去冗余储存单元的方法，包括主控芯片1，所述主控芯片1内设有内存储存控制模块2和内存控制物理层3，所述内存储存控制模块2内设有写入单元4和读取单元5，所述写入单元4和读取单元5分别连接内存控制物理层3，所述内存控制物理层3连接多个内存储存组件；多个内存储存组件包括第一内存储存组件6、第二内存储存组件7、第三内存储存组件8、第N内存储存组件，N为大于3的整数；还包括检验位产生单元9和校验检查单元10，所述检验位产生单元9和校验检查单元10均设置在内存储存控制模块2中，所述检验位产生单元9连接写入单元4；所述校验检查单元10连接读取单元5。
本发明中，一种随机内存使用纠错码校验免去冗余储存单元的方法包括以下步骤：
A、首先对数据数据做运算产生校验用的校验位,以跟随或配置到另一区块的方式将校验位与数据同时存进外部随机内存空间；
B、读取时,同时读出用户数据与校验位数据,于校验模块内进行用户数据校验运算。
综上所述，本发明使用以校验位内嵌的方式将校验位与数据同时存进外部随机内存空间以改善传统使用汉明码需要额外储存空间，读取时,同时或依序读出用户数据与校验位数据,于校验模块内进行用户数据校验运算。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (3)

  1. 一种随机内存使用纠错码校验免去冗余储存单元的方法，包括主控芯片(1)，其特征在于：所述主控芯片(1)内设有内存储存控制模块(2)和内存控制物理层(3)，所述内存储存控制模块(2)内设有写入单元(4)和读取单元(5)，所述写入单元(4)和读取单元(5)分别连接内存控制物理层(3)，所述内存控制物理层(3)连接多个内存储存组件；多个内存储存组件包括第一内存储存组件(6)、第二内存储存组件(7)、第三内存储存组件(8)、第N内存储存组件，N为大于3的整数。
  2. 根据权利要求1所述的一种随机内存使用纠错码校验免去冗余储存单元的方法，其特征在于：还包括检验位产生单元(9)和校验检查单元(10)，所述检验位产生单元(9)和校验检查单元(10)均设置在内存储存控制模块(2)中，所述检验位产生单元(9)连接写入单元(4)；所述校验检查单元(10)连接读取单元(5)。
  3. 根据权利要求1所述的一种随机内存使用纠错码校验免去冗余储存单元的方法，其特征在于：包括以下步骤：
    A、首先对数据数据做运算产生校验用的校验位,以跟随或配置到另一区块的方式将校验位与数据同时存进外部随机内存空间；
    B、读取时,同时读出用户数据与校验位数据,于校验模块内进行用户数据校验运算。
PCT/CN2018/105886 2018-07-20 2018-09-15 一种随机内存使用纠错码校验免去冗余储存单元的方法 WO2020015129A1 (zh)

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