WO2020010648A1 - 显示面板的驱动系统及应用其的显示装置 - Google Patents

显示面板的驱动系统及应用其的显示装置 Download PDF

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Publication number
WO2020010648A1
WO2020010648A1 PCT/CN2018/096547 CN2018096547W WO2020010648A1 WO 2020010648 A1 WO2020010648 A1 WO 2020010648A1 CN 2018096547 W CN2018096547 W CN 2018096547W WO 2020010648 A1 WO2020010648 A1 WO 2020010648A1
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Prior art keywords
bit data
ramp voltage
data
display panel
driving system
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PCT/CN2018/096547
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English (en)
French (fr)
Inventor
刘炳麟
张皓东
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上海视欧光电科技有限公司
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Priority to US16/728,002 priority Critical patent/US10923034B2/en
Publication of WO2020010648A1 publication Critical patent/WO2020010648A1/zh

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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2320/00—Control of display operating conditions
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    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the present invention relates to the field of display technology, and particularly to a driving system for a display panel and a display device using the same.
  • ramp (slope) source gamma for 10bits of image data, low 4bits of data is used as the interpolation control of the source op amp; a group of 10bits of digital signals B ⁇ 9: 0> is used for continuous generation.
  • the ramp voltage control signal generates two sets of ramp voltage curves, and compares this set of 10-bit digital signals B ⁇ 9: 0> with the higher 10 bits of image data A ⁇ 9: 0>.
  • the 10-bit numbers at this time A set of ramp step voltage values corresponding to the signal B ⁇ 9: 0> is sent to the source op amp, so only one voltage routing channel is required in the source op amp; if you want to use this method to achieve the independent gamma curve of RGB , You need to have 3 voltage routing channels in the source op amp; but at this time, the generation time for each grayscale voltage is only 1 line of sub-pixel display time / 1024, which is the amount of time when the resolution is high The level reaches nanoseconds, which is very difficult to achieve.
  • the 10-bit image data is extended to 12-bits to implement the dithing (dither) function, but this requires a digital circuit to perform higher-speed signal processing, which will cause the function of the digital circuit Consumption shows an exponential increase.
  • the technical problem to be solved by the present invention is to provide a driving system of a display panel and a display device using the same, which can solve the traditional analog source gamma implementation method with a large occupied area, the traditional ramp source gamma implementation method, which requires high time and traditional Digital gamma implementation has a very high power consumption problem.
  • a driving system for a display panel includes a pixel circuit.
  • the pixel circuit includes a plurality of columns of data signal inputs.
  • the driving system includes:
  • a ramp voltage curve generating circuit is configured to generate 2 m +1 ramp voltage curves by using the 2 m + k +1 initial grayscale voltages according to the k-bit data in the received pixel data.
  • Each ramp voltage curve includes 2 k step voltages;
  • An output control circuit is configured to select a gray-scale voltage in the ramp voltage curve to be sent to a data signal input terminal of the pixel circuit according to the received pixel data.
  • the driving system of the display panel further includes:
  • the source driver circuit particularly for the m-bit pixel data according to the received selection of any two adjacent 2 m +1 from the ramp voltage curve buffered buffered ramp voltage curve, according to the received pixel
  • the n-bit data in the data is used to interpolate and divide the selected two buffer ramp voltage curves to generate an additional 2 n ramp voltage curves;
  • An output control circuit is configured to select a gray-scale voltage in the ramp voltage curve to be sent to a data signal input terminal of the pixel circuit according to the received pixel data.
  • the ramp voltage curve generating circuit is specifically configured to use the first, 1 + 2 k , ..., 1 + 2 k * (2 m -1) initial grayscale voltages to form a first ramp voltage curve; use by the first 2, 2 + 2 k th second, ..., 2 + 2 k * (2 m -1) constitute a second initial grayscale voltage ramp voltage curve; ...; m by the second +1, 2 m + 1 + 2 k , ..., 2 m + 1 + 2 k * (2 m -1) gray scale voltages form the 2 m +1 ramp voltage curve.
  • the source driving circuit includes:
  • a multiplexer is configured to select the (x + 1) th and (x + 2) th buffer ramp voltage curves when the decimal number corresponding to the m-bit data is x.
  • the source driving circuit further includes:
  • An interpolation voltage dividing circuit is configured to generate a grayscale voltage when the decimal number corresponding to the n-bit data is y: (y * OUT_H + (2 n -y) * OUT_L) / 2 n , where OUT_H is the xth +2 buffer ramp voltage curves, OUT_L is x + 1 buffer ramp voltage curves.
  • the output control circuit includes:
  • a comparator configured to compare the k-bit data in the pixel data at the input end of one of the columns of data signal with the value of the digital register that is transitioned;
  • a controller configured to send a grayscale voltage corresponding to m + n-bit data in the pixel data to the data signal input terminal when the k-bit data is the same as the value of the digital register.
  • the pixel data includes (k + m + n) bit data.
  • the k-bit data is first k-bit data
  • the m-bit data is middle m-bit data
  • the n-bit data is last n-bit data.
  • the k bits are intermediate k-bit data
  • the m-bit data is first m-bit data
  • the n-bit data is last n-bit data.
  • An embodiment of the present invention further provides a display device including a display panel and a driving system of the display panel as described above.
  • the display panel is an OLED display panel or a liquid crystal display panel.
  • RGB gamma voltage curves of the display device are independent of each other.
  • the pixel data is divided into three parts of k + m + n, k bits data is used to generate 2 k step voltages, m bits data is used to select any two adjacent buffer ramp voltage curves, and n bits data It is used to do interpolation control signals, and to interpolate and divide the selected two buffer ramp voltage curves to generate an additional 2 n ramp voltage curves.
  • the RGB independent gamma can be realized by the driving system of the present invention, so that no additional digits are needed to achieve pseudo RGB independent gamma, which reduces digital information processing, reduces the power consumption of the digital and the overall chip, and solves the traditional digital
  • the gamma implementation method has a very high power consumption problem.
  • FIG. 1 is a schematic diagram of an existing analog source gamma circuit
  • FIG. 2 is a schematic diagram of a conventional ramp source circuit
  • FIG. 3 is a schematic structural diagram of a driving system of a display panel according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a source driving circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an output control circuit according to an embodiment of the present invention.
  • 6, 6A, 6B, and 6C are schematic circuit diagrams of a driving system of a display panel according to a specific embodiment of the present invention.
  • 7, 7A, 7B, and 7C are schematic circuit diagrams of a driving system of a display panel according to another embodiment of the present invention.
  • the independent gamma curve requires three voltage routing channels in the source op amp; however, the generation time for each grayscale voltage at this time is only one line of subpixel display time / 1024, which is higher when the resolution is higher. The magnitude of time reaches nanoseconds, which is very difficult to achieve.
  • the embodiments of the present invention are directed to the problems that the traditional analog source gamma area is very large, the traditional ramp source gamma implementation method requires very short time, and the traditional digital gamma implementation of independent RGB gamma curves has a very high power consumption, and provides a display panel driver.
  • the system and the display device using the system can solve the problems that the traditional analog source gamma implementation method occupies a large area, the traditional ramp source gamma implementation method has high time requirements, and the traditional digital gamma implementation method has very high power consumption.
  • An embodiment of the present invention provides a driving system for a display panel.
  • the display panel includes a pixel circuit.
  • the pixel circuit includes multiple columns of data signal input terminals.
  • the driving system includes:
  • a ramp voltage curve generating circuit 12 is configured to generate 2 m +1 ramp voltage curves by using the 2 m + k +1 initial grayscale voltages according to the k-bit data in the received pixel data, and each ramp voltage curve Includes 2 k step voltages;
  • a source driving circuit 14 configured to generate an additional 2 n ramp voltage curves by using any two adjacent ramp voltage curves of the 2 m + 1 ramp voltage curves according to the m-bit data in the received pixel data;
  • An output control circuit 15 is configured to select a gray-scale voltage in the ramp voltage curve to be sent to a data signal input terminal of the pixel circuit according to the received pixel data.
  • the pixel data is divided into three parts of k + m + n, k bits data is used to generate 2 k step voltages, m bits data is used to select any two adjacent buffer ramp voltage curves, n bits The data is used to interpolate the control signals. Interpolating the selected two buffered ramp voltage curves to generate additional 2 n ramp voltage curves.
  • the RGB independent gamma can be realized by the driving system of the present invention, so that no additional digits are needed to achieve pseudo RGB independent gamma, which reduces digital information processing, reduces the power consumption of the digital and the overall chip, and solves the traditional digital
  • the gamma implementation method has a very high power consumption problem.
  • the driving system further includes:
  • the source driving circuit 14 is specifically configured to select any two adjacent buffer ramp voltage curves from the 2 m + 1 buffer ramp voltage curves according to the m-bit data in the received pixel data, and according to the received pixel data
  • the n-bit data in the interpolation divides the selected two buffer ramp voltage curves to generate an additional 2 n ramp voltage curves;
  • the ramp voltage curve generating circuit 12 is specifically configured to use the first, 1 + 2 k , ..., 1 + 2 k * (2 m -1) initial grayscale voltages to form a first ramp Voltage curve; using the second, 2 + 2 k , ..., 2 + 2 k * (2 m -1) initial gray scale voltage to form the second ramp voltage curve; ...; using the 2 m +1, 2 m + 1 + 2 k , ..., 2 m + 1 + 2 k * (2 m -1) gray scale voltages form the 2 m +1 ramp voltage curve.
  • the source driving circuit 14 includes:
  • the multiplexer 141 is configured to select the x + 1th and x + 2th buffer ramp voltage curves when the decimal number corresponding to the m-bit data is x.
  • the source driving circuit 14 further includes:
  • the interpolation voltage dividing circuit 142 is configured to generate a grayscale voltage when the decimal number corresponding to the n-bit data is y: (y * OUT_H + (2 n -y) * OUT_L) / 2 n , where OUT_H is the first x + 2 buffer ramp voltage curves, OUT_L is x + 1 buffer ramp voltage curves.
  • the output control circuit 15 includes:
  • the comparator 151 is configured to compare the k-bit data in the pixel data of the input end of one column of the data signal with the value of the digital register to which the transition occurs;
  • the controller 152 is configured to send a grayscale voltage corresponding to m + n-bit data in the pixel data to the data signal input terminal when the k-bit data is the same as the value of the digital register.
  • the pixel data includes (k + m + n) bit data, that is, the pixel data has no extra data except for the necessary (k + m + n) bit data, which can reduce the number of bits of the pixel data.
  • the pixel data includes (k + m + n) bit data, that is, the pixel data has no extra data except for the necessary (k + m + n) bit data, which can reduce the number of bits of the pixel data.
  • the transmission amount of pixel data includes (k + m + n) bit data, that is, the pixel data has no extra data except for the necessary (k + m + n) bit data, which can reduce the number of bits of the pixel data.
  • the positions of the k-bit data, the m-bit data, and the n-bit data in the pixel data are not limited, and the k-bit data, the m-bit data, and the n-bit can be designed according to requirements.
  • the position of the data in the pixel data is not limited, and the k-bit data, the m-bit data, and the n-bit can be designed according to requirements.
  • the k-bit data may be the first k-bit data in the pixel data
  • the m-bit data may be the middle m-bit data of the pixel data
  • the n-bit data May be the last n bits of pixel data
  • the k bits may be intermediate k bits of pixel data
  • the m bits of data may be the first m bits of pixel data
  • the The n-bit data may be the last n-bit data in the pixel data.
  • the positions of the k-bit data, the m-bit data, and the n-bit data in the pixel data are not limited to the positions in the above two embodiments.
  • the k-bits may also be pixel data
  • the last k-bit data, the m-bit data may be the middle m-bit data in the pixel data, the n-bit data may be the first n-bit data in the pixel data, and so on.
  • k can take the value of 3
  • m can take the value of 3
  • n can take the value of 4, of course, the values of k, m, and n are not limited to this. Other values are required.
  • a hybrid (hybrid) source gamma architecture is provided.
  • the pixel data is a 10-bits (k + m + n) data signal, and the first 3 (k) -bit data are used to generate 2 k step voltages.
  • the middle 3 (m) bit data is used to select any two adjacent buffer ramp voltage curves from the 2 m + 1 buffer ramp voltage curve, and the last 4 (n) bit data is used to select the two buffered ramp voltages. Interpolating the curve to divide the voltage results in an additional 2 n ramp voltage curves. This has 2 m +1 trace in the channel in the source op amp, each time the step voltage occupied row 1/2 k.
  • the lower half of the figure is a gamma voltage generating circuit
  • an enlarged schematic diagram of the gamma voltage generating circuit is shown in FIG. 6B
  • the lower left part is a voltage generating circuit (Voltage generator).
  • V1-V65 initial grayscale voltages
  • 65 2k + m + 1.
  • SL counter clock and multiplexer
  • the specific implementation method for generating the ramp voltage curve is: at the initial stage, the value of digital register B ⁇ 9: 7> is set to 000, and at the rising edge of the counter clock CounterClock, the value of digital register B ⁇ 9: 7> Becomes 001, at the next rising edge of CounterClock, the value of digital register B ⁇ 9: 7> becomes 010, and so on, until the value of digital register B ⁇ 9: 7> becomes 111, at CounterClock At the next rising edge of the chip, the value of digital register B ⁇ 9: 7> is reset to 000, which is used as a cycle; the specific voltage selected by VGAMMA ⁇ 9: 1> is shown in Table 1:
  • each ramp voltage curve includes 2 k initial grayscale voltages, such as VGAMMA ⁇ 1> includes V ⁇ 1>, V ⁇ 9>, V ⁇ 17>, V ⁇ 25>, V ⁇ 33>, V ⁇ 41>, V ⁇ 49>, and V ⁇ 57>;
  • VGAMMA ⁇ 2> includes V ⁇ 2>, V ⁇ 10>, V ⁇ 18>, V ⁇ 26>, V ⁇ 34>, V ⁇ 42>, V ⁇ 50> and V ⁇ 58>;...
  • VGAMMA ⁇ 9> includes V ⁇ 9>, V ⁇ 17>, V ⁇ 25>, V ⁇ 33>, V ⁇ 41>, V ⁇ 49>, V ⁇ 57> and V ⁇ 65>.
  • the upper part of FIG. 6 is the source driving part.
  • the enlarged schematic diagram of the source driving part is shown in FIG. 6C, which mainly includes a multiplexer, an interpolation driving op amp and a digital comparator.
  • the last 7 bits of pixel data determines the only set of step voltages, and then the comparison result of A1 ⁇ 9: 7> and B ⁇ 9: 7>
  • the level conversion circuit controls whether the switch connected to the output of the source operational amplifier and the data signal input terminal of the first column of pixel circuits is turned off.
  • A1 ⁇ 9: 7> is the first 3 bits of pixel data corresponding to the data signal input end of the pixel circuit of the first column, that is, the 7th to 9th data in A1, and B ⁇ 9: 7> is constantly changing.
  • the value of a digital register is the first 3 bits of pixel data corresponding to the data signal input end of the pixel circuit of the first column, that is, the 7th to 9th data in A1, and B ⁇ 9: 7> is constantly changing.
  • the value of a digital register is the first 3 bits of pixel data corresponding to the data signal input end of the pixel circuit of the first column, that is, the 7th to 9th data in A1, and B ⁇
  • the source op amp starts to work and generates the grayscale voltage corresponding to A1 ⁇ 9: O> at this time, which is sent to the data signal input terminal of the pixel circuit in the first column; when B ⁇ 9: 7> transitions again, A1 ⁇ 9: 7> and B ⁇ 9: 7> are different.
  • the comparison result is low and the switch is turned off. At this time, the gray-scale voltage is maintained by the capacitor in the pixel circuit for display.
  • the active display area (Active Area) of the display panel is provided with N columns of pixel circuits, and the data signal input terminal of each column of pixel circuits is correspondingly connected to the output terminal of the source op amp.
  • the process of sending the step voltage to the pixel circuits of the first column is similar.
  • the source op amp generates the gray scale voltage corresponding to the pixel circuits from the first column to the N column, and sends the gray scale voltage to the data of the corresponding pixel circuit at the corresponding time. Signal input.
  • each ramp has a total of 2 10-n step voltages, and the time occupied by each step voltage is 1 line of sub-pixel display time / 2 10-n , so the higher the resolution The shorter the time occupied, the severely limited the application of ramp source gamma.
  • each ramp has a total of 2 k step voltages, and the time occupied by each step voltage is 1 line of sub-pixel display time / 2 k ; when k is 3, The time occupied by each step voltage is 1 line of sub-pixel display time / 8, which is much larger than the traditional ramp source gamma structure.
  • the time limit is much looser and can be applied to high Resolution display product.
  • the image data of 10bits is expanded to 12bits to implement the dithing function, but this requires digital circuits to perform higher-speed signal processing, which will cause the power consumption of digital circuits to appear exponential Level increase.
  • the hybrid source source gamma architecture of this embodiment is used to implement the RGB independent gamma curve, three sets of gamma generating circuits are needed, which are sent to the RGB pixel-driven op amp circuits. In this way, a 27-channel routing channel is required in the source op amp. , Much smaller than the traditional source gamma architecture.
  • the hybrid source and gamma architecture of this embodiment can be used to implement RGB independent gamma. This eliminates the need for digital data processing to achieve pseudo RGB independent gamma, reduces digital information processing, and reduces the power of digital and overall chips. Consuming.
  • a hybrid source gamma architecture in which the pixel data is a 10-bits (m + k + n) data signal, and the first 3 (m) -bit data are used to buffer the slope voltage curve from 2 * 2 m Select any two adjacent buffer ramp voltage curves.
  • the middle 3 (k) bit data is used to generate 2 k step voltages, and the last 4 (n) bit data is used to inner the selected two buffer ramp voltage curves. Interpolating the divided voltages results in an additional 2 n ramp voltage curves. In this way, there are 2 * 2 m trace channels in the source op amp, and the time taken by each step voltage is 1 line / 2 k .
  • the lower half of the figure is a gamma voltage generating circuit, and an enlarged schematic diagram of the gamma voltage generating circuit is shown in FIG. 7B.
  • the lower left part is a voltage generating circuit (Voltage generator), an enlarged schematic diagram of the voltage generating circuit.
  • V1-V65 initial grayscale voltages
  • 65 2k + m + 1.
  • SL counter clock and multiplexer
  • the specific implementation method for generating the ramp voltage curve is: at the initial stage, the value of digital register B ⁇ 6: 4> is set to 000, and at the rising edge of the counter clock CounterClock, the value of digital register B ⁇ 6: 4> Becomes 001, at the next rising edge of CounterClock, the value of digital register B ⁇ 6: 4> becomes 010, and so on, until the value of digital register B ⁇ 6: 4> becomes 111, at CounterClock At the next rising edge of , the value of digital register B ⁇ 6: 4> is reset to 000, which is used as a cycle; the specific VGAMMA_H ⁇ 8: 1> and VGAMMA_L ⁇ 8: 1> selected voltage are shown in Table 4 :
  • each ramp voltage curve includes 2 k initial grayscale voltages.
  • FIG. 7 The upper part of FIG. 7 is a source driving part.
  • An enlarged schematic diagram of the source driving part is shown in FIG. 7C, which mainly includes a multiplexer, an interpolation driving op amp, and a digital comparator.
  • the source drive circuit of the first column Take the source drive circuit of the first column as an example: the first 3 bits of pixel data corresponding to the data signal input end of the pixel circuit of the first column are used as the 7th to 9th data in A1 A1 ⁇ 9: 7> as the control signal Select two adjacent VGAMMA_H_BUF and VGAMMA_L_BUF voltages.
  • the 7bits data in the pixel data determine the only set of step voltages, and then the comparison results of A1 ⁇ 6: 4> and B ⁇ 6: 4> are passed through
  • the flat conversion circuit controls whether the switch connected to the output of the source operational amplifier and the data signal input terminal of the first column of pixel circuits is turned off.
  • A1 ⁇ 6: 4> is the middle 3 bits data of the pixel data corresponding to the data signal input terminal of the first column of pixel circuits, that is, the fourth to sixth data in A1, and B ⁇ 6: 4> is constantly changing.
  • the value of a digital register is the middle 3 bits data of the pixel data corresponding to the data signal input terminal of the first column of pixel circuits, that is, the fourth to sixth data in A1, and B ⁇ 6: 4> is constantly changing.
  • the value of a digital register is the middle 3 bits data of the pixel data corresponding to the data signal input terminal of the first column of pixel circuits, that is, the fourth to sixth data in A1,
  • the source op amp starts to work and generates the grayscale voltage corresponding to A1 ⁇ 9: 0> at this time, which is sent to the data signal input terminal of the first column of pixel circuits; when B ⁇ 6: 4> transitions again, A1 ⁇ 6: 4> and B ⁇ 6: 4> are not the same.
  • the comparison result is low and the switch is turned off. At this time, the gray level voltage is maintained by the capacitor in the pixel circuit for display.
  • the effective display area of the display panel is provided with N columns of pixel circuits, and the data signal input terminal of each column of pixel circuits is correspondingly connected to the output terminal of the source op amp, and the source op amp sends the grayscale voltage to the source op amp.
  • the process of the pixel circuit in the first column is similar.
  • the source op amp generates the grayscale voltage corresponding to the pixel circuit from the first column to the Nth column, and sends the grayscale voltage to the data signal input terminal of the corresponding pixel circuit at the corresponding time.
  • An embodiment of the present invention further provides a display device including a display panel and a driving system of the display panel as described above.
  • the display panel may be an OLED display panel or a liquid crystal display panel.
  • the driving system adopts a hybrid source gamma architecture.
  • the pixel data is k + m + n bits
  • k-bit data is used to generate 2 k step voltages
  • m-bit data is used to select any two adjacent buffer ramp voltage curves
  • n-bit data is used to perform interpolation
  • only 2 m + 1 voltage routing channels are required in the source op amp
  • the time occupied by each step voltage is 1 line of sub-pixel display time / 2 k
  • the area occupied by the traditional source gamma architecture is much smaller, and the area of the digital-to-analog converter and data latch is omitted; and the time occupied by each step voltage is much larger than that of the traditional ramp source gamma structure.
  • the time limit is much looser and can be applied to high-resolution display products.
  • the hybrid source gamma architecture of this embodiment is used to implement the RGB independent gamma curve, three sets of gamma generating circuits are required, which are respectively sent to the RGB pixel driving op amp circuits. In this way, 3 * (2 m +1) cable routing channels are much smaller than the traditional source gamma architecture. Therefore, the hybrid source gamma architecture of this embodiment can be used to implement RGB independent gamma. This eliminates the need for digital data processing to achieve pseudo RGB independent gamma, reduces digital information processing, and reduces the power of digital and overall chips. Consuming.

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Abstract

一种显示面板的驱动系统及显示装置，驱动系统包括：电压产生电路，产生2 m+k+1个初始灰阶电压；斜坡电压曲线产生电路，根据k比特数据，利用2 m+k+1个初始灰阶电压产生2 m+1个斜坡电压曲线；缓冲器，缓冲2 m+1个斜坡电压曲线，输出2 m+1个缓冲斜坡电压曲线；源驱动电路，根据接收到的像素数据中的m比特数据利用所述2 m+1个斜坡电压曲线中的任意两个相邻的斜坡电压曲线产生额外的2 n个斜坡电压曲线；输出控制电路，根据接收到的像素数据选择所述斜坡电压曲线中的一灰阶电压输送给所述像素电路的数据信号输入端。本驱动系统占用面积小，对时间要求低且功耗较低，可实现独立的RGB伽马电压曲线。

Description

显示面板的驱动系统及应用其的显示装置 技术领域
本发明涉及显示技术领域，特别是指一种显示面板的驱动系统及应用其的显示装置。
背景技术
随着手机和电视等显示产品的分辨率越来越高，需要能实现更高分辨率的驱动芯片来驱动像素电路；需要显示的灰阶越来越精细，这样就导致送给源驱动运放的走线变得越来越多；并且现在为了更好的显示效果，会将原始的图像数据由8bits变为10bits，会增加传统source(源)架构的实现难度；另外，RGB三色的灰阶电压范围不同，为了达到更好的显示效果，需要对每一种颜色的亚像素产生独立的gamma(伽马)曲线。
传统的模拟source gamma的实现方法中：对于10bits的图像数据，利用其中的低4bits做source运放的内插控制；高6bits做为数字模拟转换电路的选择控制信号，从65个灰阶电压中选择出相邻的两个电压送给source运放做内插分压产生16个电压，这样就可以产生64*16＝1024个灰阶；因此需要在source运放里有65个电压走线通道；如果要采用此方法实现RGB的独立gamma曲线，就需要在source运放里有65*3＝195个电压走线通道，要占用非常大的面积，并且需要在source运放前做6bits的数字模拟转换器来选择65个电压中的相邻两个，6bits的数字模拟转换器需要的面积也很大。
传统ramp(斜坡)source gamma的实现方法中：对于10bits的图像数据，采用低4bits数据做source运放的内插控制；用一组10bits连续跳变的数字信号B<9：0>做为产生ramp电压的控制信号，产生两组ramp电压曲线，并用这组10bits数字信号B<9：0>和图像数据的高10bits A<9：0>作比较，当它们相同时，将此时10bits数字信号B<9：0>所对应的一组ramp阶跃电压值送给source运放，这样只需要在source运放里有1个电压走线通道；如果要采用此方法实现RGB的独立 gamma曲线，需要在source运放里有3个电压走线通道；但是此时留给每个灰阶电压的产生时间只有1行亚像素的显示时间/1024，在分辨率较高的时候这个时间的量级达到纳秒，实现难度非常之大。
传统数字gamma的实现方法中，为了实现RGB的独立gamma曲线，将10bits的图像数据扩展为12bits来实现dithing(抖动)功能，但这样需要数字电路进行更高速的信号处理，会导致数字电路的功耗呈现指数级别的增加。
发明内容
本发明要解决的技术问题是提供一种显示面板的驱动系统及应用其的显示装置，能够解决传统的模拟source gamma实现方法占用面积大、传统的ramp source gamma实现方法对时间要求高、传统的数字gamma实现方法功耗非常高的问题。
为解决上述技术问题，本发明的实施例提供技术方案如下：
一方面，提供一种显示面板的驱动系统，所述显示面板包括像素电路，所述像素电路包括多列数据信号输入端，所述驱动系统包括：
电压产生电路，用于产生2 m+k+1个初始灰阶电压；
斜坡电压曲线产生电路，用于根据接收到的像素数据中的k比特数据，利用所述2 m+k+1个初始灰阶电压产生2 m+1个斜坡电压曲线，每一斜坡电压曲线包括2 k个阶跃电压；
源驱动电路，用于根据接收到的像素数据中的m比特数据利用所述2 m+1个斜坡电压曲线中的任意两个相邻的斜坡电压曲线产生额外的2 n个斜坡电压曲线；
输出控制电路，用于根据接收到的像素数据选择所述斜坡电压曲线中的一灰阶电压输送给所述像素电路的数据信号输入端。
进一步地，显示面板的驱动系统还包括：
缓冲器，用于缓冲所述2 m+1个斜坡电压曲线，输出2 m+1个缓冲斜坡电压曲线；
所述源驱动电路，具体用于根据接收到的像素数据中的m比特数据从所述2 m+1个缓冲斜坡电压曲线选择任意两个相邻的缓冲斜坡电压曲线，并根据接收 到的像素数据中的n比特数据对所选择的两个缓冲斜坡电压曲线做内插分压产生额外的2 n个斜坡电压曲线；
输出控制电路，用于根据接收到的像素数据选择所述斜坡电压曲线中的一灰阶电压输送给所述像素电路的数据信号输入端。
进一步地，所述斜坡电压曲线产生电路具体用于利用第1个、第1+2 k个、...、1+2 k*(2 m-1)个初始灰阶电压组成第一斜坡电压曲线；利用利用第2个、第2+2 k个、...、2+2 k*(2 m-1)个初始灰阶电压组成第二斜坡电压曲线；...；利用第2 m+1个、第2 m+1+2 k个、...、2 m+1+2 k*(2 m-1)个灰阶电压组成第2 m+1斜坡电压曲线。
进一步地，所述源驱动电路包括：
多路选择器，用于在所述m比特数据对应的十进制数为x时，选择第x+1和第x+2个缓冲斜坡电压曲线。
进一步地，所述源驱动电路还包括：
内插分压电路，用于在所述n比特数据对应的十进制数为y时，生成灰阶电压：(y*OUT_H+(2 n-y)*OUT_L)/2 n，其中，OUT_H为第x+2个缓冲斜坡电压曲线，OUT_L为x+1个缓冲斜坡电压曲线。
进一步地，所述输出控制电路包括：
比较器，用于将其中一列数据信号输入端的像素数据中的k比特数据与跳变的数字寄存器的值进行比较；
控制器，用于在所述k比特数据与所述数字寄存器的值相同时，将所述像素数据中的m+n位数据对应的灰阶电压输送给所述数据信号输入端。
进一步地，所述像素数据包括(k+m+n)比特数据。
进一步地，所述k比特数据为前k位数据，所述m比特数据为中间m位数据，所述n比特数据为后n位数据。
进一步地，所述k比特为中间k位数据，所述m比特数据为前m位数据，所述n比特数据为后n位数据。
进一步地，k＝3，m＝3，n＝4。
本发明实施例还提供了一种显示装置，包括显示面板和如上所述的显示面板的驱动系统。
进一步地，所述显示面板为OLED显示面板或液晶显示面板。
进一步地，所述显示装置的RGB伽马电压曲线为相互独立的。
本发明的实施例具有以下有益效果：
上述方案中，将像素数据分为k+m+n三部分，k bits数据用来产生2 k个阶跃电压，m bits数据用来选择任意两个相邻的缓冲斜坡电压曲线，n bits数据用来做内插控制信号，对所选择的两个缓冲斜坡电压曲线做内插分压产生额外的2 n个斜坡电压曲线。这样在source运放里有2 m+1根走线通道，比传统的source gamma架构要小很多，解决了传统的模拟source gamma实现方法占用面积大的问题；并且每个阶跃电压所占的时间为1行亚像素显示时间/2 k，要远大于传统的ramp source gamma结构中每个阶跃电压所占的时间，解决了传统的ramp source gamma实现方法对时间要求高的问题；另外，通过本发明的驱动系统可以实现RGB独立gamma，这样就不需要增加额外的位数来实现伪RGB独立gamma，减少了数字的信息处理，减少了数字和整体芯片的功耗，解决了传统的数字gamma实现方法功耗非常高的问题。
附图说明
图1为现有模拟source gamma电路的示意图；
图2为现有ramp source gamma电路的示意图；
图3为本发明实施例显示面板的驱动系统的结构示意图；
图4为本发明实施例源驱动电路的结构示意图；
图5为本发明实施例输出控制电路的结构示意图；
图6、图6A、图6B和图6C为本发明具体实施例显示面板的驱动系统的电路示意图；
图7、图7A、图7B和图7C为本发明另一具体实施例显示面板的驱动系统的电路示意图。
具体实施方式
为使本发明的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
如图1所示，传统的模拟source gamma的实现方法中：对于10bits的图像数据，利用其中的低4bits做source运放的内插控制；高6bits做为数字模拟转换电路的选择控制信号，从65个灰阶电压(V1-V65)中选择出相邻的两个电压送给source运放做内插分压产生16个电压，这样就可以产生64*16＝1024个灰阶；因此需要在source运放里有65个电压走线通道；如果要采用此方法实现RGB的独立gamma曲线，就需要在source运放里有65*3＝195个电压走线通道，要占用非常大的面积，并且需要在source运放前做6bits的数字模拟转换器来选择65个电压中的相邻两个，6bits的数字模拟转换器需要的面积也很大。
如图2所示，传统ramp source gamma的实现方法中：对于10bits的图像数据，采用低4bits数据做source运放的内插控制；用一组10bits连续跳变的数字信号B<9：0>做为产生ramp电压的控制信号，产生两组ramp电压曲线，并用这组10bits数字信号B<9：0>和图像数据的高10bits A<9：0>作比较，当它们相同时，将此时10bits数字信号B<9：0>所对应的一组ramp阶跃电压值送给source运放，这样只需要在source运放里有1个电压走线通道；如果要采用此方法实现RGB的独立gamma曲线，需要在source运放里有3个电压走线通道；但是此时留给每个灰阶电压的产生时间只有1行亚像素的显示时间/1024，在分辨率较高的时候这个时间的量级达到纳秒，实现难度非常之大。
传统数字gamma的实现方法中，为了实现RGB的独立gamma曲线，将10bits的图像数据扩展为12bits来实现dithing功能，但这样需要数字电路进行更高速的信号处理，会导致数字电路的功耗呈现指数级别的增加。
本发明的实施例针对传统的模拟source gamma面积非常大、传统的ramp source gamma实现方法时间要求非常短、传统数字gamma实现独立RGB gamma曲线的功耗非常高的问题，提供一种显示面板的驱动系统及应用其的显示装置，能够解决传统的模拟source gamma实现方法占用面积大、传统的ramp source gamma实现方法对时间要求高、传统的数字gamma实现方法功耗非常高的问题。
本发明实施例提供了一种显示面板的驱动系统，所述显示面板包括像素电路，所述像素电路包括多列数据信号输入端，如图3所示，所述驱动系统包括：
电压产生电路11，用于产生2 m+k+1个初始灰阶电压；
斜坡电压曲线产生电路12，用于根据接收到的像素数据中的k比特数据， 利用所述2 m+k+1个初始灰阶电压产生2 m+1个斜坡电压曲线，每一斜坡电压曲线包括2 k个阶跃电压；
源驱动电路14，用于根据接收到的像素数据中的m比特数据利用所述2 m+1个斜坡电压曲线中的任意两个相邻的斜坡电压曲线产生额外的2 n个斜坡电压曲线；输出控制电路15，用于根据接收到的像素数据选择所述斜坡电压曲线中的一灰阶电压输送给所述像素电路的数据信号输入端。本实施例中，将像素数据分为k+m+n三部分，k bits数据用来产生2 k个阶跃电压，m bits数据用来选择任意两个相邻的缓冲斜坡电压曲线，n bits数据用来做内插控制信号，对所选择的两个缓冲斜坡电压曲线做内插分压产生额外的2 n个斜坡电压曲线。这样在source运放里有2 m+1根走线通道，比传统的source gamma架构要小很多，解决了传统的模拟source gamma实现方法占用面积大的问题；并且每个阶跃电压所占的时间为1行亚像素显示时间/2 k，要远大于传统的ramp source gamma结构中每个阶跃电压所占的时间，解决了传统的ramp source gamma实现方法对时间要求高的问题；另外，通过本发明的驱动系统可以实现RGB独立gamma，这样就不需要增加额外的位数来实现伪RGB独立gamma，减少了数字的信息处理，减少了数字和整体芯片的功耗，解决了传统的数字gamma实现方法功耗非常高的问题。
进一步地，如图3所示，所述驱动系统还包括：
缓冲器13，用于缓冲所述2 m+1个斜坡电压曲线，输出2 m+1个缓冲斜坡电压曲线；
源驱动电路14，具体用于根据接收到的像素数据中的m比特数据从所述2 m+1个缓冲斜坡电压曲线选择任意两个相邻的缓冲斜坡电压曲线，并根据接收到的像素数据中的n比特数据对所选择的两个缓冲斜坡电压曲线做内插分压产生额外的2 n个斜坡电压曲线；
进一步地，所述斜坡电压曲线产生电路12具体用于利用第1个、第1+2 k个、...、1+2 k*(2 m-1)个初始灰阶电压组成第一斜坡电压曲线；利用第2个、第2+2 k个、...、2+2 k*(2 m-1)个初始灰阶电压组成第二斜坡电压曲线；...；利用第2 m+1个、第2 m+1+2 k个、...、2 m+1+2 k*(2 m-1)个灰阶电压组成第2 m+1斜坡电压曲线。
进一步地，如图4所示，所述源驱动电路14包括：
多路选择器141，用于在所述m比特数据对应的十进制数为x时，选择第x+1和第x+2个缓冲斜坡电压曲线。
进一步地，如图4所示，所述源驱动电路14还包括：
内插分压电路142，用于在所述n比特数据对应的十进制数为y时，生成灰阶电压：(y*OUT_H+(2 n-y)*OUT_L)/2 n，其中，OUT_H为第x+2个缓冲斜坡电压曲线，OUT_L为x+1个缓冲斜坡电压曲线。
进一步地，如图5所示，所述输出控制电路15包括：
比较器151，用于将其中一列数据信号输入端的像素数据中的k比特数据与跳变的数字寄存器的值进行比较；
控制器152，用于在所述k比特数据与所述数字寄存器的值相同时，将所述像素数据中的m+n位数据对应的灰阶电压输送给所述数据信号输入端。
优选地，所述像素数据包括(k+m+n)比特数据，即像素数据中除必要的(k+m+n)比特数据之外，没有多余的数据，这样可以减少像素数据的位数，降低像素数据的传输量。
其中，对所述k比特数据、所述m比特数据和所述n比特数据在像素数据中的位置不做限定，可以根据需要设计所述k比特数据、所述m比特数据和所述n比特数据在像素数据中的位置，一具体实施例中，所述k比特数据可以为像素数据中的前k位数据，所述m比特数据可以为像素数据的中间m位数据，所述n比特数据可以为像素数据中的后n位数据；另一具体实施例中，所述k比特可以为像素数据的中间k位数据，所述m比特数据可以为像素数据中的前m位数据，所述n比特数据可以为像素数据中的后n位数据。
当然，所述k比特数据、所述m比特数据和所述n比特数据在像素数据中的位置并不局限于上述两个实施例中的位置，比如，所述k比特还可以为像素数据的后k位数据，所述m比特数据可以为像素数据中的中间m位数据，所述n比特数据可以为像素数据中的前n位数据等等。
在像素数据包括10比特数据时，k可以取值为3，m可以取值为3，n可以取值为4，当然，k、m和n的取值并不局限于此，还可以根据实际需要采用其他取值。
下面结合附图以及具体的实施例对本发明的显示面板的驱动系统做进一步 地介绍：
实施例一
本实施例中，提供了一种hybrid(混合)source gamma的架构，其中，像素数据为10bits(k+m+n)数据信号，前3(k)比特数据用来产生2 k个阶跃电压，中间3(m)比特数据用来从2 m+1个缓冲斜坡电压曲线选择任意两个相邻的缓冲斜坡电压曲线，后4(n)比特数据用来对所选择的两个缓冲斜坡电压曲线做内插分压产生额外的2 n个斜坡电压曲线。这样在source运放里有2 m+1根走线通道，每个阶跃电压所占的时间为1行/2 k。
如图6所示，图中的下半部分为伽马电压产生电路，伽马电压产生电路的放大示意图如图6B所示，左下部分为电压产生电路(Voltage generator)，电压产生电路的放大示意图如图6A所示，用来产生65个初始灰阶电压(V1-V65)，其中，65＝2 k+m+1。然后通过计数器(Counter Clock)和多路选择器(SL)利用65个初始灰阶电压产生23+1个斜坡电压曲线，从VGAMMA<1>-VGAMMA<9>。
产生斜坡电压曲线的具体实现方法为：在最初始时，数字寄存器B<9：7>的值设定为000，在计数器时钟Counter Clock的上升沿时，数字寄存器B<9：7>的值变为001，在Counter Clock的下个上升沿时，数字寄存器B<9：7>的值变为010，以此类推，直到数字寄存器B<9：7>的值变为111，在Counter Clock的下个上升沿时，数字寄存器B<9：7>的值重置为000，以此作为循环；具体的VGAMMA<9：1>选取的电压如表1所示：
表1
Figure PCTCN2018096547-appb-000001
Figure PCTCN2018096547-appb-000002
可以看出，每一斜坡电压曲线包括2 k个初始灰阶电压，如VGAMMA<1>包括V<1>、V<9>、V<17>、V<25>、V<33>、V<41>、V<49>和V<57>；VGAMMA<2>包括V<2>、V<10>、V<18>、V<26>、V<34>、V<42>、V<50>和V<58>；...；VGAMMA<9>包括V<9>、V<17>、V<25>、V<33>、V<41>、V<49>、V<57>和V<65>。
然后将上述产生的9个斜坡电压曲线经过缓冲器后产生9个缓冲斜坡电压曲线，VGAMMA_BUF<1>-VGAMMA_BUF<9>，送给source运放，也即图6的上半部分。
图6的上半部分为source驱动部分，source驱动部分的放大示意图如图6C所示，主要包含多路选择器，内插驱动运放和数字的比较器。以第一列的source驱动电路为例：利用对应第一列像素电路的数据信号输入端的像素数据中间的3bits数据即A1中的第4位-第6位数据A1<6：4>作为控制信号选择相邻的两个VGAMMA_BUF电压作为OUT_H和OUT_L；选取的VGAMMA_BUF电压如表2所示：
表2
A1<6：4> 000 001 010 011
OUT_H VGAMMA_BUF<2> VGAMMA_BUF<3> VGAMMA_BUF<4> VGAMMA_BUF<5>
OUT_L VGAMMA_BUF<1> VGAMMA_BUF<2> VGAMMA_BUF<3> VGAMMA_BUF<4>
A1<6：4> 100 101 110 111
OUT_H VGAMMA_BUF<6> VGAMMA_BUF<7> VGAMMA_BUF<8> VGAMMA_BUF<9>
OUT_L VGAMMA_BUF<5> VGAMMA_BUF<6> VGAMMA_BUF<7> VGAMMA_BUF<8>
利用第一列数据信号输入端输入的像素数据的后4bits数据即A1中的第0位-第3位数据A1<3：0>来做为内插驱动运放的控制信号产生OUT_H和OUT_L两个电压中间的16个灰阶电压，产生的灰阶电压如表3所示。
表3
A1<3：0> 0000 0001
OP_OUT OUT_L (OUT_H+15*OUT_L)/16
A1<3：0> 0010 0011
OP_OUT (2*OUT_H+14*OUT__L)/16 (3*OUT_H+13*OUT_L)/16
A1<3：0> 0100 0101
OP_OUT (4*OUT_H+12*OUT_L)/16 (5*OUT_H+11*OUT_L)/16
A1<3：0> 0110 0111
OP_OUT (6*OUT_H+10*OUT_L)/16 (7*OUT_H+9*OUT_L)/16
A1<3：0> 1000 1001
OP_OUT (8*OUT_H+8*OUT_L)/16 (9*OUT_H+7*OUT_L)/16
A1<3：0> 1010 1011
OP_OUT (10*OUT_H+6*OUT_L)/16 (11*OUT_H+5*OUT_L)/16
A1<3：0> 1100 1101
OP_OUT (12*OUT_H+4*OUT_L)/16 (13*OUT_H+3*OUT_L)/16
A1<3：0> 1110 1111
OP_OUT (14*OUT_H+2*OUT_L)/16 (15*OUT_H+1*OUT_L)/16
这样利用像素数据中的后7bits数据也即低7位比特数据A1<6：O>决定了唯一的一组阶跃电压，然后由A1<9：7>和B<9：7>的比较结果经过电平转换电路控制source运放的输出和第一列像素电路的数据信号输入端相连的开关是否关断。其中，A1<9：7>为对应第一列像素电路的数据信号输入端的像素数据的前3bits数据即A1中的第7位-第9位数据，B<9：7>为不断跳变的数字寄存器的值。
假设A1<9：7>和B<9：7>不相同时，比较结果为低，开关处于关断状态，source运放的使能信号为低，source运放处于无效状态，此时B<9：7>由000向111跳变，在这个过程中B<9：7>变化到和A1<9：7>相同时，比较结果变为高，开关闭合，source运放的使能信号变为高，source运放开始工作产生此时A1<9：O>所对应的灰阶电压，送给第一列像素电路的数据信号输入端；当B<9：7>再次跳变时，A1<9：7>和B<9：7>不相同，比较结果为低，开关关断，此时依靠像素电路里的 电容保持住灰阶电压用于显示。
如图6所示，显示面板的有效显示区域(Active Area)设置有N列像素电路，每列像素电路的数据信号输入端与source运放的输出端一一对应连接，与source运放将灰阶电压送给第一列像素电路的过程类似，source运放产生从第1列到第N列的像素电路对应的灰阶电压，并在相应的时刻将灰阶电压送给对应像素电路的数据信号输入端。
传统的source gamma结构中：2 10-n+1个电压走线占用source运放的走线通道，增大source运放的面积，还需要有10-n bits的数字模拟转换器和数据锁存器，严重增加source驱动芯片的面积；并且几乎不可能实现RGB独立gamma。而本实施例的hybrid source gamma的架构只需要在source运放里有2 10-k-n+1个电压走线通道，在k取值为3，n取值为4时，仅需要9个电压走线通道，比传统的source gamma架构要小很多，而且省去了数字模拟转换器以及数据锁存器的面积。
传统的ramp source gamma结构中，每个ramp共有2 10-n个阶跃电压，每个阶跃电压所占的时间为1行亚像素显示时间/2 10-n，这样分辨率越高阶跃电压所占的时间越短，严重限制了ramp source gamma的应用。而本实施例的hybrid source gamma结构中，每个ramp共有2 k个阶跃电压，每个阶跃电压所占的时间为1行亚像素显示时间/2 k；在k取值为3时，每个阶跃电压所占的时间为1行亚像素显示时间/8，要远大于传统的ramp source gamma结构，和传统的ramp source gamma结构相比，时间的限制要宽松很多，可以适用于高分辨率显示产品。
传统数字gamma的实现方法中，为了实现RGB的独立gamma曲线，将10bits的图像数据扩展为12bits来实现dithing功能，但这样需要数字电路进行更高速的信号处理，会导致数字电路的功耗呈现指数级别的增加。如果采用本实施例的hybrid source gamma架构实现RGB独立gamma曲线，需要三组的gamma产生电路，分别送给RGB的像素驱动运放电路，这样在source运放里需要有27根线的走线通道，远远小于传统的source gamma架构。因此可以采用本实施例的hybrid source gamma架构来实现RGB独立gamma，这样就不需要数字做额外的数据处理来实现伪RGB独立gamma，减少了数字的信息处理，就减少了数字 和整体芯片的功耗。
实施例二
本实施例中，提供了一种hybrid source gamma的架构，其中，像素数据为10bits(m+k+n)数据信号，前3(m)比特数据用来从2*2 m个缓冲斜坡电压曲线选择任意两个相邻的缓冲斜坡电压曲线，中间3(k)比特数据用来产生2 k个阶跃电压，后4(n)比特数据用来对所选择的两个缓冲斜坡电压曲线做内插分压产生额外的2 n个斜坡电压曲线。这样在source运放里有2*2 m根走线通道，每个阶跃电压所占的时间为1行/2 k。
如图7所示，图中的下半部分为伽马电压产生电路，伽马电压产生电路的放大示意图如图7B所示，左下部分为电压产生电路(Voltage generator)，电压产生电路的放大示意图如图7A所示，用来产生65个初始灰阶电压(V1-V65)，其中，65＝2 k+m+1。然后通过计数器(Counter Clock)和多路选择器(SL)利用65个初始灰阶电压产生2*2 m个斜坡电压曲线，从VGAMMA_H<1>-VGAMMA_H<8>，VGAMMA_L<1>-VGAMMA_L<8>。
产生斜坡电压曲线的具体实现方法为：在最初始时，数字寄存器B<6：4>的值设定为000，在计数器时钟Counter Clock的上升沿时，数字寄存器B<6：4>的值变为001，在Counter Clock的下个上升沿时，数字寄存器B<6：4>的值变为010，以此类推，直到数字寄存器B<6：4>的值变为111，在Counter Clock的下个上升沿时，数字寄存器B<6：4>的值重置为000，以此作为循环；具体的VGAMMA_H<8：1>和VGAMMA_L<8：1>选取的电压如表4所示：
表4
Figure PCTCN2018096547-appb-000003
Figure PCTCN2018096547-appb-000004
可以看出，每一斜坡电压曲线包括2 k个初始灰阶电压。
然后将上述产生的2*2 m个斜坡电压曲线经过缓冲器后产生2*2 m个缓冲斜坡电压曲线，VGAMMA_H_BUF<1>-VGAMMA_H_BUF<8>，VGAMMA_L_BUF<1>-VGAMMA_L_BUF<8>送给source运放，也即图7的上半部分。
图7的上半部分为source驱动部分，source驱动部分的放大示意图如图7C所示，主要包含多路选择器，内插驱动运放和数字的比较器。以第一列的source驱动电路为例：利用对应第一列像素电路的数据信号输入端的像素数据的前3bits数据即A1中的第7位-第9位数据A1<9：7>作为控制信号选择相邻的两个VGAMMA_H_BUF和VGAMMA_L_BUF电压。
利用第一列数据信号输入端输入的像素数据的后4bits数据即A1中的第0位-第3位数据A1<3：0>来做为内插驱动运放的控制信号产生VGAMMA_H_BUF和VGAMMA_L_BUF电压中间的16个灰阶电压。
这样利用像素数据中的7bits数据，也即前3比特数据和后4比特数据决定了唯一的一组阶跃电压，然后由A1<6：4>和B<6：4>的比较结果经过电平转换电路控制source运放的输出和第一列像素电路的数据信号输入端相连的开关是否关断。其中，A1<6：4>为对应第一列像素电路的数据信号输入端的像素数据的中 间3bits数据即A1中的第4位-第6位数据，B<6：4>为不断跳变的数字寄存器的值。
假设A1<6：4>和B<6：4>不相同时，比较结果为低，开关处于关断状态，source运放的使能信号为低，source运放处于无效状态，此时B<6：4>由000向111跳变，在这个过程中B<6：4>变化到和A1<6：4>相同时，比较结果变为高，开关闭合，source运放的使能信号变为高，source运放开始工作产生此时A1<9：0>所对应的灰阶电压，送给第一列像素电路的数据信号输入端；当B<6：4>再次跳变时，A1<6：4>和B<6：4>不相同，比较结果为低，开关关断，此时依靠像素电路里的电容保持住灰阶电压用于显示。
如图7所示，显示面板的有效显示区域设置有N列像素电路，每列像素电路的数据信号输入端与source运放的输出端一一对应连接，与source运放将灰阶电压送给第一列像素电路的过程类似，source运放产生从第1列到第N列的像素电路对应的灰阶电压，并在相应的时刻将灰阶电压送给对应像素电路的数据信号输入端。
本发明实施例还提供了一种显示装置，包括显示面板和如上所述的显示面板的驱动系统。
具体地，所述显示面板可以为OLED显示面板或者为液晶显示面板。
本实施例的显示装置中，驱动系统采用hybrid source gamma的架构。在像素数据为k+m+n比特，k比特数据用来产生2 k个阶跃电压，m比特数据用来选择任意两个相邻的缓冲斜坡电压曲线，n比特数据用来做内插分压产生额外的2 n个斜坡电压曲线时，只需要在source运放里有2 m+1个电压走线通道，每个阶跃电压所占的时间为1行亚像素显示时间/2 k，比传统的source gamma架构所占的面积要小很多，而且省去了数字模拟转换器以及数据锁存器的面积；并且每个阶跃电压所占的时间要远大于传统的ramp source gamma结构，时间的限制要宽松很多，可以适用于高分辨率显示产品。进一步地，如果采用本实施例的hybrid source gamma架构实现RGB独立gamma曲线，需要三组的gamma产生电路，分别送给RGB的像素驱动运放电路，这样在source运放里需要有3*(2 m+1)根线的走线通道，远远小于传统的source gamma架构。因此可以采用本实施例的hybrid source gamma架构来实现RGB独立gamma，这样就不需要数字做额外 的数据处理来实现伪RGB独立gamma，减少了数字的信息处理，就减少了数字和整体芯片的功耗。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (13)

  1. 一种显示面板的驱动系统，其特征在于，所述显示面板包括像素电路，所述像素电路包括多列数据信号输入端，所述驱动系统包括：
    电压产生电路，用于产生2 m+k+1个初始灰阶电压；
    斜坡电压曲线产生电路，用于根据接收到的像素数据中的k比特数据，利用所述2 m+k+1个初始灰阶电压产生2 m+1个斜坡电压曲线，每一斜坡电压曲线包括2 k个阶跃电压；
    源驱动电路，用于根据接收到的像素数据中的m比特数据利用所述2 m+1个斜坡电压曲线中的任意两个相邻的斜坡电压曲线产生额外的2 n个斜坡电压曲线；
    输出控制电路，用于根据接收到的像素数据选择所述斜坡电压曲线中的一灰阶电压输送给所述像素电路的数据信号输入端。
  2. 根据权利要求1所述的显示面板的驱动系统，其特征在于，还包括：缓冲器，用于缓冲所述2 m+1个斜坡电压曲线，输出2 m+1个缓冲斜坡电压曲线；
    所述源驱动电路，具体用于根据接收到的像素数据中的m比特数据从所述2 m+1个缓冲斜坡电压曲线选择任意两个相邻的缓冲斜坡电压曲线，并根据接收到的像素数据中的n比特数据对所选择的两个缓冲斜坡电压曲线做内插分压产生额外的2 n个斜坡电压曲线。
  3. 根据权利要求1所述的显示面板的驱动系统，其特征在于，
    所述斜坡电压曲线产生电路具体用于利用第1个、第1+2 k个、...、1+2 k*(2 m-1)个初始灰阶电压组成第一斜坡电压曲线；利用利用第2个、第2+2 k个、...、2+2 k*(2 m-1)个初始灰阶电压组成第二斜坡电压曲线；...；利用第2 m+1个、第2 m+1+2 k个、...、2 m+1+2 k*(2 m-1)个灰阶电压组成第2 m+1斜坡电压曲线。
  4. 根据权利要求2所述的显示面板的驱动系统，其特征在于，所述源驱动电路包括：
    多路选择器，用于在所述m比特数据对应的十进制数为x时，选择第x+1和第x+2个缓冲斜坡电压曲线。
  5. 根据权利要求4所述的显示面板的驱动系统，其特征在于，所述源驱动 电路还包括：
    内插分压电路，用于在所述n比特数据对应的十进制数为y时，生成灰阶电压：(y*OUT_H+(2 n-y)*OUT_L)/2 n，其中，OUT_H为第x+2个缓冲斜坡电压曲线，OUT_L为x+1个缓冲斜坡电压曲线。
  6. 根据权利要求1所述的显示面板的驱动系统，其特征在于，所述输出控制电路包括：
    比较器，用于将其中一列数据信号输入端的像素数据中的k比特数据与跳变的数字寄存器的值进行比较；
    控制器，用于在所述k比特数据与所述数字寄存器的值相同时，将所述像素数据中的m+n位数据对应的灰阶电压输送给所述数据信号输入端。
  7. 根据权利要求1-6中任一项所述的显示面板的驱动系统，其特征在于，所述像素数据包括(k+m+n)比特数据。
  8. 根据权利要求7所述的显示面板的驱动系统，其特征在于，所述k比特数据为前k位数据，所述m比特数据为中间m位数据，所述n比特数据为后n位数据。
  9. 根据权利要求7所述的显示面板的驱动系统，其特征在于，所述k比特为中间k位数据，所述m比特数据为前m位数据，所述n比特数据为后n位数据。
  10. 根据权利要求7所述的显示面板的驱动系统，其特征在于，k＝3，m＝3，n＝4。
  11. 一种显示装置，其特征在于，包括显示面板和如权利要求1-10中任一项所述的显示面板的驱动系统。
  12. 根据权利要求11所述的显示装置，其特征在于，所述显示面板为OLED显示面板或液晶显示面板。
  13. 根据权利要求11所述的显示装置，其特征在于，所述显示装置的RGB伽马电压曲线为相互独立的。
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