Classifications

• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
  • A61B8/44—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
  • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
  • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
  • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
  • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
  • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
  • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
  • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
  • B06B1/0644—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using a single piezoelectric element
  • B06B1/0655—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using a single piezoelectric element of cylindrical shape
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
  • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
  • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
  • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
  • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
  • B06B1/0688—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction with foil-type piezoelectric elements, e.g. PVDF
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
  • B81B7/0032—Packages or encapsulation
  • B81B7/007—Interconnections between the MEMS and external electrical signals
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
  • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
  • G01N29/22—Details, e.g. general constructional or apparatus details
  • G01N29/24—Probes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
  • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
  • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/63—Vias, e.g. via plugs
  • H10W70/635—Through-vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/69—Insulating materials thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
  • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
  • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
  • A61B8/44—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device
  • A61B8/4483—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device characterised by features of the ultrasound transducer
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B2201/00—Specific applications of microelectromechanical systems
  • B81B2201/02—Sensors
  • B81B2201/0271—Resonators; ultrasonic resonators
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B2207/00—Microstructural systems or auxiliary parts thereof
  • B81B2207/09—Packages
  • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
  • B81B2207/098—Arrangements not provided for in groups B81B2207/092 - B81B2207/097
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
  • G01N2291/00—Indexing codes associated with group G01N29/00
  • G01N2291/02—Indexing codes associated with the analysed material
  • G01N2291/024—Mixtures
  • G01N2291/02475—Tissue characterisation
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
  • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
  • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
  • G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
  • G01S7/52079—Constructional features
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7436—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support a device or a wafer when forming electrical connections thereto
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07331—Connecting techniques
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/877—Bump connectors and die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• the aspects of the technology described herein relate to ultrasound devices. Some aspects relate to packaging an ultrasound-on-a-chip.
• Ultrasound devices may be used to perform diagnostic imaging and/or treatment, using sound waves with frequencies that are higher with respect to those audible to humans.
• Ultrasound imaging may be used to see internal soft tissue body structures, for example to find a source of disease or to exclude any pathology.
• pulses of ultrasound are transmitted into tissue (e.g., by using an ultrasound imaging device)
• sound waves are reflected off the tissue, with different tissues reflecting varying degrees of sound.
• These reflected sound waves may then be recorded and displayed as an ultrasound image to the operator.
• the strength (amplitude) of the sound signal and the time it takes for the wave to travel through the body provide information used to produce the ultrasound image.
• Many different types of images can be formed using ultrasound devices, including real-time images. For example, images can be generated that show two-dimensional cross-sections of tissue, blood flow, motion of tissue over time, the location of blood, the presence of specific molecules, the stiffness of tissue, or the anatomy of a three-dimensional region.
• an apparatus comprises: an ultrasound-on-a-chip comprising a top surface and a bottom surface; an interposer layer comprising a top surface and a bottom surface; and a redistribution layer; wherein: the top surface of the ultrasound-on-a-chip device is coupled to the redistribution layer; and the bottom surface of the ultrasound-on-a chip device is coupled to the top surface of the interposer layer.
• a method comprises:
• a method comprises:
• FIGs. 1-37 illustrate cross-sections of various structures during packaging of an ultrasound-on-a-chip device using one process, in accordance with certain embodiments described herein;
• FIGs. 38-42 illustrate cross-sections of a various structures during packaging of an ultrasound-on-a-chip device using another process, in accordance with certain embodiments described herein;
• FIG. 43 illustrates an example process for packaging an ultrasound-on-a-chip, in accordance with certain embodiments described herein.
• FIG. 44 illustrates an example process for packaging an ultrasound-on-a-chip, in accordance with certain embodiments described herein.
• Such imaging devices may include ultrasonic transducers monolithically integrated onto a single semiconductor die to form a monolithic ultrasound device. Aspects of such ultrasound-on-a chip devices are described in U.S. Patent Application No. 15/415,434 titled“UNIVERSAL ULTRASOUND DEVICE AND RELATED APPARATUS AND METHODS,” filed on January 25, 2017 (and assigned to the assignee of the instant application), which is incorporated by reference herein in its entirety.
• the inventors have recognized features that may be helpful for packaging such ultrasound-on-a-chip devices compared with other packaging methods such as wirebonding.
• the inventors have recognized that integrated fan-out (InFO) packaging and interposer layers augmented with metal pillars may provide benefits for packaging ultrasound-on-a-chip devices.
• Example benefits include lower parasitic inductance and resistance, higher efficiency, less heating, higher packaging throughput, and improved packaging reliability.
• such packaging may enable devices to have smaller sensor heads, which may be helpful for ultrasound imaging applications such as cardiac applications where it may be desirable for the sensor head to fit between ribs.
• such packaging may enable devices to have thinner lenses, which may increase signal intensity.
• FIGs. 1-37 illustrate cross-sections of various structures during packaging of an ultrasound-on-a-chip device using one process, in accordance with certain embodiments described herein.
• FIG. 1 illustrates a release layer 104 coupled to a carrier substrate 106, and an insulating layer 102 coupled to the release layer 104.
• the carrier substrate 106 may include, for example, glass.
• the release layer 104 may include, for example, light-to-heat- conversion (LTHC) coating material.
• the insulating material 102 may include, for example, a polymer that can be patterned with light exposure and developed, such as polyimide, polybenzoxazole (PBO), or benzocyclobutene (BCB).
• a metal layer 108 is formed on the insulating layer 102.
• the metal layer 108 may be formed, for example, using physical vapor deposition (PVD) or sputtering.
• the metal layer 108 may include, for example, copper, or in some embodiments, the metal layer 108 may include two layers, such as a titanium layer coupled to the insulating layer 102 and a copper layer coupled to the titanium layer.
• a resist layer 110 is formed on the metal layer 108.
• the resist layer 110 may include photoresist.
• openings are formed in the resist layer 110.
• light exposure through a lithography mask followed by development may create openings in portions of the resist layer 110 that were exposed to light through the mask.
• metal pillars 112 are formed in the openings in the resist layer 110 using electroplating.
• the metal layer 108 may serve as a seed layer for the electroplating.
• the metal pillars 112 may include the same material as the metal layer 108, such as copper. It should be appreciated that while four metal pillars 112 are shown, there may be more metal pillars 112 (e.g., tens or hundreds) arranged two-dimensionally.
• the resist layer 110 is removed.
• a resist stripper may be used to remove the resist layer 110.
• Portions of the metal layer 108 that were previously under unexposed portions of the resist layer 110 are also removed.
• an anisotropic etch may be used to remove the metal layer 108, in which the metal layer 108 is etched faster than the metal pillars 112.
• FIG. 7 illustrates an ultrasound-on-a-chip 114 coupled to an insulating layer 116.
• openings are created in the insulating layer 116 (e.g., using
• a resist layer 118 is formed on the insulating layer 116.
• openings are created in the resist layer 118 (e.g., using photolithography), where the openings created in the resist layer 118 extend into the openings created in the insulating layer 116.
• metal contacts 120 are formed within the openings in the resist layer 118 and the insulating layer 116.
• the metal contacts 120 may be formed by electroplating, and may include copper or a copper alloy.
• an under bump metallurgy layer (not shown in FIG. 11) may be formed between the metal contacts 120 and the ultrasound-on-a-chip 114.
• the resist layer 118 is removed (e.g., using a resist stripper).
• a die-attach film (DAF) 122 is coupled to the insulating layer 102.
• the ultrasound-on-a-chip 114 is coupled to the die-attached film 122.
• encapsulation 124 is formed to encapsulate the ultrasound-on-a-chip 114, the insulating layer 116, the die-attach film 122, and the metal pillars 112.
• the encapsulation 124 may include a molding compound, a molding underfill, an epoxy, or a resin.
• the top surface of the encapsulation 124 extends above the top surfaces of the insulating layer 116 and the metal pillars 112.
• the top surfaces of the encapsulating 124 and the insulating layer 116 are planarized until the top surfaces of the top surfaces of the metal pillars 112 and the metal contacts 116 are exposed.
• CMP chemical mechanical planarization
• additional insulating material is added to the insulating layer 116, such that the insulating layer 116 covers the top surfaces of the metal contacts 120 and the metal pillars 112.
• openings are created in the insulating layer 116 above the metal contacts 120 and the metal pillars 112.
• photolithography may be used to create the openings.
• redistribution lines (RDL) 126 are formed in the openings in the insulating layer 116 and on the insulating layer 116. As shown, the RDL 126 may electrically connect certain of the metal contacts 120 to certain of the metal pillars 122.
• the RDL 126 may include metal traces and vias, may be formed using electroplating (including formation of a seed layer not shown), and may include metal such as aluminum, copper, tungsten, and/or alloys of these metals.
• the RDL 126 may include multiple layers of metal traces and vias.
• additional insulating material is added to the insulating layer 116 to cover the top surface of the RDL 126.
• the carrier substrate 106 and the release layer 104 are detached from the insulating layer 102.
• projecting light e.g., ultraviolet or laser
• the surface of the insulating layer 102 may also be cleaned to remove any residue.
• the structure of FIG. 21 is flipped over to arrive at the orientation of FIG. 22.
• openings are created in the insulating layer 102.
• solder balls 128 are placed in the openings in the insulating layer 102.
• the solder balls 128 may be formed by electroplating.
• other forms of electrical connectors e.g., metal pillars
• an under-bump metallurgy layer (not shown in FIG. 24) may be formed between the solder balls 128 and the metal pillars 112.
• FIG. 25 illustrates a release layer 134 coupled to a carrier substrate 136, an insulating layer 132 coupled to the release layer 134, and an interposer layer 130 coupled to the insulating layer 132.
• the interposer layer 130 may include, for example, aluminum nitride.
• openings are formed in the interposer layer 130.
• laser drilling may be used to form the openings.
• a metal layer 138 is formed on the interposer layer 130.
• the metal layer 138 may be formed, for example, using sputtering.
• the metal layer 138 may include, for example, copper, or in some embodiments, the metal layer 138 may include two layers, such as a titanium layer coupled to the interposer layer 130 and a copper layer coupled to the titanium layer.
• metal pillars 142 are formed in the openings in the resist layer 130 using electroplating.
• the metal layer 138 may serve as a seed layer for the electroplating.
• the metal pillars 142 may include the same material as the metal layer 138, such as copper. It should be appreciated that in addition to serving as electrical routing, the metal pillars 142 may also help to strengthen the interposer layer 130, which may be brittle.
• a resist layer 140 is formed on the metal layer 138 and the metal pillars 142.
• the resist layer 140 is patterned (e.g., using photolithography) to block the top surfaces of the metal pillars 142.
• non-blocked portions of the metal layer 108 are etched to electrically isolate the metal pillars 142.
• a timed etch or an anisotropic etch may be used instead of or in addition to using photolithography to block the metal pillars 142.
• the resist layer 140 is removed (e.g., using resist stripper).
• openings are created in the insulating later 132.
• solder balls 144 are placed in the openings in the insulating layer 132.
• a thermal adhesive layer 150 is coupled to the interposer layer 142.
• the thermal adhesive layer 150 may include a silver-containing epoxy.
• the solder balls 144 are coupled to a printer circuit board (PCB) 148.
• PCB printer circuit board
• SMT surface-mount technology
• flip-chip soldering may be used to couple the solder balls 144 to the PCB 148.
• An underfill (e.g., epoxy) layer 146 is formed between the insulating layer 132 and the PCB 148.
• the solder balls 128 are coupled to the metal pillars 142.
• the metal pillars 112 are aligned with the metal pillars 142.
• surface-mount technology (SMT) or flip-chip soldering may be used to couple the solder balls 128 to the metal pillars 142.
• the interposer may provide electrical routing between the ultrasound-on-a-chip 114 and the PCB 148, as well as a heatsink for the ultrasound-on-a-chip 114.
• FIGs. 38-42 illustrate cross-sections of various structures during packaging of an ultrasound-on-a-chip device using another process, in accordance with certain embodiments described herein.
• FIG. 38 illustrates the structure of FIG. 32.
• the metal pillars 142 are extended upwards using electroplating. As can be seen, the metal pillars 142 extend beyond the top surface of the interposer layer 130.
• the ultrasound-on-a-chip 114 is coupled to the interposer layer 130 through the die- attach film 122.
• FIG. 41 further insulating material is added to the insulating layer 116.
• the encapsulation 124 is formed to encapsulate the ultrasound-on-a-chip 114, the insulating layer 116, the die-attach film 122, and the metal pillars 142, similar to in FIG. 16.
• the RDL 126 is formed, similar to in FIGs. 18-21.
• the carrier substrate 136 and the release layer 134 are detached from the insulating layer 132, the solder balls 144 are formed on the metal pillars 142, the solder balls 144 are coupled to the PCB 148, and an underfill layer 146 is formed between the insulating layer 132 and the PCB 148, similar to in FIGs. 33-36.
• the process of FIGs. 38-42 may enable the ultrasound-on-a-chip 114 to be bound to the interposer layer 130 in a semiconductor foundry, where process control, quality, and yield may be high. Additionally, while the process of FIGs. 1-37 may require simultaneous bonding of the solder balls 128 to the metal pillars 142 and bonding of the insulating layer 102 to the thermal adhesive 150, the process of FIGs. 38- 42 may eliminate the thermal adhesive layer 150.
• FIG. 43 illustrates an example process 4300 for packaging an ultrasound-on-a-chip, in accordance with certain embodiments described herein.
• an interposer layer containing metal pillars is coupled to a printed circuit board.
• Act 4302 may correspond to the step illustrated in FIG. 36.
• the interposer layer is coupled to a packaged ultrasound-on-a-chip containing metal pillars.
• Act 4304 may correspond to the step illustrated in FIG. 37.
• the interposer layer may be coupled to the packaged ultrasound-on-a- chip through a thermal adhesive layer.
• FIG. 44 illustrates an example process 4400 for packaging an ultrasound-on-a-chip, in accordance with certain embodiments described herein.
• metal pillars are formed in an interposer layer.
• Act 4402 may correspond to the steps illustrated in FIGs. 38-39.
• the interposer layer is coupled to an ultrasound-on-a-chip.
• Act 4404 may correspond to the step illustrated in FIG. 40.
• a redistribution layer is formed on the packaged ultrasound-on-a-chip.
• Act 4406 may correspond to the step illustrated in FIG. 41.
• a reference to“A and/or B”, when used in conjunction with open-ended language such as“comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
• the phrase“at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements.
• This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase“at least one” refers, whether related or unrelated to those elements specifically identified.
• “at least one of A and B” can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another
• the terms“approximately” and“about” may be used to mean within ⁇ 20% of a target value in some embodiments, within ⁇ 10% of a target value in some embodiments, within ⁇ 5% of a target value in some embodiments, and yet within ⁇ 2% of a target value in some embodiments.
• the terms“approximately” and“about” may include the target value.

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• 2019
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