WO2020007107A1 - 显示面板及其制造方法和显示终端 - Google Patents

显示面板及其制造方法和显示终端 Download PDF

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Publication number
WO2020007107A1
WO2020007107A1 PCT/CN2019/084859 CN2019084859W WO2020007107A1 WO 2020007107 A1 WO2020007107 A1 WO 2020007107A1 CN 2019084859 W CN2019084859 W CN 2019084859W WO 2020007107 A1 WO2020007107 A1 WO 2020007107A1
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Prior art keywords
layer
pixel
cathode
display panel
embedding portion
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PCT/CN2019/084859
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English (en)
French (fr)
Inventor
许�鹏
程芸
纪卢芳月
周同凯
杜伟
岑岗
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Yungu Guan Technology Co Ltd
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Yungu Guan Technology Co Ltd
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Priority to US16/701,167 priority Critical patent/US10944075B2/en
Publication of WO2020007107A1 publication Critical patent/WO2020007107A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering

Definitions

  • the present disclosure relates to the field of display devices, and in particular, to a display panel, a manufacturing method thereof, and a display terminal.
  • OLED Organic Light-Emitting Diode
  • smart terminal products such as mobile phones, tablet computers and even TVs.
  • OLED display devices have better flexibility, due to the material and Structural limitation, its impact resistance is weak.
  • the hit area is prone to display defects such as black spots, bright spots, and colorful spots, which seriously affects the service life and use stability of the OLED display device.
  • a display panel includes:
  • a pixel-defining layer, the interlayer insulating layer, the planarization layer, and the pixel-defining layer are sequentially stacked and arranged, and the pixel-defining layer is provided with an opening
  • a sub-pixel which is disposed in an opening of the pixel-defining layer
  • a cathode provided on the pixel defining layer and covering the sub-pixel
  • a thin film packaging structure provided on the cathode.
  • the thin film packaging structure or the cathode is provided with a first embedding portion, and the first embedding portion is embedded in the pixel defining layer and the planarization layer. And in contact with the interlayer insulating layer.
  • the first embedding portion is embedded in the pixel-defining layer and the planarization layer and is in contact with the interlayer insulating layer.
  • the embedded structure increases the bonding force between the film layers.
  • the interlayer insulating layer is generally made of an inorganic material.
  • the cathode is a metal material
  • the bottom layer of the thin film encapsulation structure is also an inorganic encapsulation layer. Therefore, the adhesion between the inorganic material and the inorganic material and the adhesion between the inorganic material and the metal material are compared with those of the traditional metal material.
  • the adhesion between the cathode and the pixel-defining layer which is often an organic material, is greatly improved.
  • the first embedding portion is disposed between two adjacent sub-pixels.
  • the first embedding portion is disposed around the sub-pixel.
  • an outer diameter dimension of the first embedding portion is gradually reduced from the pixel defining layer to the interlayer insulating layer.
  • the first embedding portion includes a bottom wall in contact with the interlayer insulating layer and a side wall in contact with the pixel defining layer and the planarization layer, and the bottom wall and the side wall are in contact with each other.
  • the included angle is 100 ° -150 °.
  • the first embedding portion is in surface-to-surface contact with the interlayer insulating layer.
  • the thin-film encapsulation structure includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are arranged in a stack, and the first inorganic encapsulation layer covers the cathode;
  • the first embedding portion is formed at least in part of the first inorganic encapsulation layer.
  • the cathode when the cathode is provided with a first embedding portion, the first embedding portion is a hollow structure, the thin film packaging structure is provided with a second embedding portion, and the second embedding portion is filled in the first embedding portion.
  • the pixel-defining layer is at least partially embedded in the hollow portion of the portion.
  • the second embedding portion embeds the pixel-defining layer and the planarization layer simultaneously.
  • a display terminal includes the above display panel.
  • a method for manufacturing a display panel including an interlayer insulating layer, a planarization layer, and a pixel-defining layer, which are sequentially stacked, and the manufacturing method includes the following steps:
  • the first through hole and the second through hole are formed with the thin film encapsulation structure Material or a first embedding portion made of a material of the cathode.
  • the method further includes a step of patterning the position of the cathode corresponding to the second through hole;
  • the step of forming the thin film encapsulation structure on the cathode is specifically: depositing the material of the thin film encapsulation structure on the patterned cathode and in the first through hole and the second through hole to form a device.
  • the thin film packaging structure having the first embedding portion.
  • the material of the cathode forms a hollow structure in the first through hole and the second through hole, and is embedded in the first embedding portion.
  • a second embedding portion made of the material of the thin film packaging structure is formed in the hollow portion of the portion.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment
  • FIG. 2 is a plan view of the display panel shown in FIG. 1 before a cathode is formed;
  • FIG. 3 is a top view of a display panel before a cathode is formed according to another embodiment
  • FIG. 4 is a schematic structural diagram of a display panel according to another embodiment
  • FIG. 5 is a schematic structural diagram of another embodiment of a first embedding portion of the display panel shown in FIG. 4.
  • the present disclosure provides a display panel according to an embodiment, and provides a method for manufacturing the display panel.
  • the display panel 100 includes an array substrate, a sub-pixel 50, a cathode 60, and a thin film packaging structure 70.
  • the array substrate may include a substrate 11, a buffer layer 12, a thin film transistor, and a sub-pixel electrode provided on the thin film transistor.
  • the manufacturing method of the display panel 100 is as follows.
  • the substrate 11 may be formed of a suitable material such as a glass material, a metal material, or a plastic material including polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide. .
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyimide polyimide
  • the substrate 11 includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region.
  • a set of the first subpixel region, the second subpixel region, and the third subpixel region may constitute a pixel region.
  • the substrate 11 may have a plurality of pixel regions.
  • the first sub-pixel region may be a sub-pixel region that emits red light
  • the second sub-pixel region may be a sub-pixel region that emits green light
  • the third sub-pixel region may be a sub-pixel region that emits blue light.
  • each pixel region may also include other sub-pixel regions, for example, may also include a fourth sub-pixel region that emits white light, which is not limited herein.
  • a thin-film transistor may be disposed on the substrate 11.
  • another layer such as the buffer layer 12 may be formed on the substrate 11.
  • the buffer layer 12 may be formed on the entire surface of the substrate 11, or may be formed by being patterned.
  • the buffer layer 12 may have a suitable material including materials such as PET, PEN, polyacrylate, and / or polyimide, and form a layered structure in the form of a single layer or a multilayer stack.
  • the buffer layer 12 may also be formed of silicon oxide or silicon nitride, or may include a composite layer of an organic material and / or an inorganic material.
  • the TFT can control the emission of each sub-pixel, or can control the amount of emission when each sub-pixel emits light.
  • the TFT may include a semiconductor layer 21, a gate electrode 22, a source electrode 23, and a drain electrode 24.
  • the semiconductor layer 21 may be formed of an amorphous silicon layer, a metal oxide, or a polysilicon layer, or may be formed of an organic semiconductor material. In one embodiment, the semiconductor layer 21 includes a channel region and a source region and a drain region doped with a dopant.
  • the semiconductor layer 21 may be covered with a gate insulating layer 25.
  • the gate electrode 22 may be disposed on the gate insulating layer 25.
  • the gate insulating layer 25 may cover the entire surface of the substrate 11.
  • the gate insulating layer 25 may be formed by patterning.
  • the gate insulating layer 25 may be formed of silicon oxide, silicon nitride, or other insulating organic or inorganic materials.
  • the gate electrode 22 may be directly covered by the interlayer insulating layer 27.
  • an insulating dielectric layer 26 of a capacitor may be formed on the gate electrode 22 first, and then the interlayer insulating layer 27 may be covered.
  • the interlayer insulating layer 27 is formed of silicon oxide, silicon nitride, and / or other suitable insulating inorganic materials. Specifically, hydrogen-containing ions generated during the preparation of the interlayer insulating layer 27 enter the gate insulating layer 25 and the trench. The channel area neutralizes the film defects, thereby acting as a passivation and insulation. Specifically, in one embodiment, the interlayer insulating layer 27 is a stack of silicon nitride and silicon oxide.
  • a part of the gate insulating layer 25 and the interlayer insulating layer 27 may be removed, and a contact hole may be formed after the removal to expose a predetermined region of the semiconductor layer 21.
  • the source electrode 23 and the drain electrode 24 may contact the semiconductor layer 21 via a contact hole.
  • the source electrode 23 and the drain electrode 24 may be composed of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), In neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) or other suitable alloys A single material layer or a composite material layer of at least one material is formed.
  • the TFT has a complicated layer structure, it is necessary to form a planarization layer 28 on the TFT in order to form a sufficiently flat top surface. After the planarization layer 28 is formed, an electrode through hole may be formed in the planarization layer 28 to expose the drain electrode 24 of the TFT.
  • the inventor discovered during the research process that in the falling ball reliability test of the soft screen, the steel ball hits the screen, and the hit area cannot be displayed in full color instantly, and black, bright, and colorful spots appear poorly in the display area. The problem. Then, through a large number of studies, it was found that mainly due to the moment when the heavy object hits, the stress concentration cannot be dispersed and the element is damaged, and the most important reason is that the poor adhesion of the film layer is easy to peel when the ball is concentrated on the panel, and the OLED layer It is easiest to peel from the cathode.
  • the present disclosure also provides a first through hole 101 in the planarization layer 28 to expose at least part of the interlayer insulating layer 27, thereby facilitating subsequent cathode materials used to form the cathode 60.
  • the thin film packaging material used to form the thin film packaging structure 70 is in contact with the interlayer insulating layer 27.
  • the interlayer insulating layer 27 may be provided with a gap at a position corresponding to the first through hole 101, that is, the cathode material or the thin film encapsulating material is also embedded in the interlayer insulating layer 27 at the same time.
  • the cathode material or the thin film encapsulating material directly contact the top surface of the interlayer insulating layer 27.
  • the arrangement of the first through hole 101 preferably avoids the source electrode 23 and the drain electrode 24, and avoids damaging and exposing the source electrode 23 and the drain electrode 24.
  • the first through holes 101 are distributed between two adjacent openings for setting the sub-pixels 50, so as to better protect the sub-pixels 50.
  • the first through hole 101 is a circular hole shape, and specifically may be a shape such as a perfect circle, an ellipse, and a square. It can be understood that the shape of the first through hole 101 is not limited thereto.
  • the first through hole 101 is disposed around the sub-pixel 50.
  • the plurality of first through holes 101 may be arranged around the sub-pixel 50 to form a surrounding shape, or the first through-holes 101 themselves are annular holes and are arranged around the sub-pixel 50 so as to better enhance the sub-pixel. Impact resistance at 50 places. It can be understood that, in the same embodiment, there are multiple sub-pixels 50, a part of the sub-pixels 50 may surround a plurality of first through holes 101, and a part of the sub-pixels 50 may be surrounded by a ring. ⁇ ⁇ ⁇ ⁇ ⁇ 101 ⁇ The first through hole 101.
  • the annular hole is not limited to a circular ring, but may be a square ring, as long as it forms a closed annular structure hole.
  • the first through hole 101 is an annular hole and there are multiple holes, one of the first through holes 101 may be located in the other first through hole 101.
  • the cathode material or the thin-film encapsulation material and the interlayer insulation layer 27 are in surface-to-surface contact, so as to increase the contact area of the cathode material or the thin-film encapsulation material and the interlayer insulation layer 27, thereby improving the cathode or the thin-film encapsulation material and
  • the adhesion between the interlayer insulating layers 27 further improves the problem that the poor adhesion between the OLED layer and the cathode 60 when a heavy object hits the display panel results in easy peeling between the film layers, thereby helping to improve the impact resistance of the OLED display device.
  • a first sub-pixel electrode 31, a second sub-pixel electrode 32, and a third sub-pixel electrode are formed on the planarization layer 28.
  • the first sub-pixel electrode 31 is formed in a first pixel region.
  • the second sub-pixel electrode 32 is formed in a second sub-pixel region.
  • the third sub-pixel electrode is formed in the third sub-pixel region.
  • the first sub-pixel electrode 31, the second sub-pixel electrode 32, and the third sub-pixel electrode may be formed simultaneously or synchronously.
  • Each of the first subpixel electrode 31, the second subpixel electrode 32, and the third subpixel electrode may be electrically connected to the TFT through an electrode through hole.
  • the first sub-pixel electrode 31, the second sub-pixel electrode 32, and the third sub-pixel electrode are generally referred to as anodes.
  • Each of the first subpixel electrode 31, the second subpixel electrode 32, and the third subpixel electrode may form a transparent electrode (transflective type) or a reflective electrode.
  • the first sub-pixel electrode 31, the second sub-pixel electrode 32, and the third sub-pixel electrode form a transparent electrode (transflective) electrode, it may be made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide ( ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • IGO indium gallium oxide
  • AZO zinc aluminum oxide
  • the structures and materials of the first subpixel electrode 31, the second subpixel electrode 32, and the third subpixel electrode are not limited thereto.
  • a pixel defining layer 41 may be formed.
  • the formed pixel defining layer 41 covers the first subpixel electrode 31, the second subpixel electrode 32, and the third subpixel electrode at the same time.
  • the pixel defining layer 41 can be used to define a sub-pixel by opening an opening corresponding to each sub-pixel.
  • the sub-pixel 50 is disposed in the opening of the pixel-defining layer 41.
  • the pixel defining layer 41 is generally formed of a single material layer or a composite material layer of a suitable organic material among materials such as polyacrylate and polyimide.
  • a second through hole communicating with the first through hole 101 is further provided on the pixel defining layer 41 so that the cathode material or the thin film encapsulating material is in contact with the interlayer insulating layer.
  • the first through hole 101 can be formed by patterning after the interlayer insulating layer 27 is formed, and the second through hole can also be formed by patterning after the pixel defining layer 41 is formed.
  • the first through hole 101 and the second through hole may be formed by one punching after the interlayer insulating layer 27 and the pixel defining layer 41 are formed.
  • the arrangement of the openings and the second through holes on the pixel defining layer 41 is also not limited in a specific order, and the arrangement of the sub-pixels 50 and the second through holes is also not limited in a specific order.
  • the outer diameter of the second and first vias 101 ranges from the pixel-defining layer 41 to the interlayer insulation
  • the layer 27 is gradually reduced.
  • the included angle between the side wall of the embedded hole formed by the second through hole and the first through hole 101 and the surface of the interlayer insulating layer 27 it is in contact with is 100 ° -150 °. In this angle range, it is convenient for interlayer insulation
  • a continuous material layer is formed on the surface of the layer 27 and on the sidewall of the embedded hole.
  • the pixel-defining layer 41 can be formed in such a manner that the planarization layer 28 on the entire substrate 11 is made of a material suitable for the pixel-defining layer 41 to form the pixel-defining layer 41 to cover the first sub-pixel electrode 31 and the second sub-pixel The pixel electrode 32 and the third sub-pixel electrode. Then, the pixel defining layer 41 is patterned to expose the central portions of the first, second, and third sub-pixel electrodes 31, 32, and 32.
  • the light emitting material may be vapor-deposited to form the sub-pixel 50.
  • the evaporation material covers a part of the first sub-pixel electrode 31 that is not covered by the pixel-defining layer 41, a portion of the second sub-pixel electrode 32 that is not covered by the pixel-defining layer 41, and a third sub-pixel electrode that is not covered by the pixel-defining layer 41 a part of.
  • a cathode 60 is formed on the pixel defining layer 41 to cover the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region.
  • the cathode 60 may be integrally formed with respect to a plurality of sub-pixels so as to cover the entire display area.
  • the cathode 60 is also commonly referred to as a counter electrode.
  • a thin film encapsulation structure 70 is formed on the cathode 60.
  • the thin-film encapsulation structure 70 includes a first inorganic encapsulation layer 71, an organic encapsulation layer 73, and a second inorganic encapsulation layer 75, which are disposed in a stack.
  • the first inorganic encapsulation layer 71 covers the cathode.
  • the structure of the thin film encapsulation structure 70 is not limited thereto, and it may further include a third inorganic encapsulation layer laminated on the second inorganic encapsulation layer 75 and a third inorganic encapsulation layer disposed between the second inorganic encapsulation layer and the third inorganic encapsulation layer. Another organic encapsulation layer.
  • the first inorganic encapsulation layer 71 and the second inorganic encapsulation layer 75 are silicon nitride films or silicon dioxide films.
  • the first inorganic encapsulation layer 71 and the second inorganic encapsulation layer 75 may be formed by a chemical vapor deposition method.
  • the organic encapsulation layer 73 may be formed by inkjet printing. Specifically, the organic encapsulation layer 73 may be an acrylate film.
  • the material of the organic encapsulation layer 73 is not limited thereto.
  • a first through hole 101 is opened in the planarization layer 28 and a second through hole communicating with the first through hole 101 is opened in the pixel defining layer 41, a thin film packaging structure is formed on the cathode 60
  • a first embedding portion 72 made of a material of the thin film packaging structure 70 is formed in the first through hole 101 and the second through hole (see FIG. 1).
  • the cathode 60 Since the cathode 60 is located between the pixel-defining layer 41 and the thin-film encapsulation structure 70, the thin-film encapsulation structure 70 is provided with a structure in which the first embedding portion 72 is embedded.
  • the cathode 60 is also protected, and the problem of easy peeling between the film layers caused by the poor adhesion between the OLED layer and the cathode 60 when a heavy object hits the display panel is improved, thereby improving the impact resistance of the OLED display device.
  • the method further includes a step of patterning the position of the cathode 60 corresponding to the second through hole to form a via hole.
  • the via holes are patterned to facilitate the deposition of the material of the thin film packaging structure 70 in the first through holes 101 and the second through holes through the cathode.
  • the step of forming the thin film encapsulation structure 70 on the cathode 60 is specifically: depositing the material of the thin film encapsulation structure 70 on the patterned cathode 60 and in the first through holes 101 and the second through holes to form a first embedding structure.
  • the thin film encapsulation structure 70 of the portion 72 is in direct contact with the interlayer insulating layer 27, and the adhesion between the thin-film encapsulation structure 70 whose outer layer is an inorganic encapsulation layer and the interlayer insulating layer 27 is strong, which greatly improves the bonding force between the film layers.
  • the first embedded portion 72 when the thin film packaging structure 70 is formed with the first embedded portion 72, the first embedded portion 72 is formed of a first inorganic packaging material deposited in the first through hole 101 and the second through hole.
  • the top surface of the first inorganic packaging layer 71 formed by the first inorganic packaging material is substantially flush.
  • the structure of the first embedding portion 72 is not limited to this.
  • the first embedding portion 72 in addition to the first inorganic packaging material, is also made of an organic packaging material deposited on the first inorganic packaging material. And / or a second inorganic packaging material. That is, the first embedding portion 72 is formed of at least the first inorganic encapsulation layer 71 deposited in the first through hole 101 and the second through hole.
  • the thin film packaging structure 70 when the diameter of the first through hole 101 and the second through hole is large or the overall thickness of the thin film packaging structure 70 is small, the thin film packaging structure 70 is located between the first through hole 101 and the second The upper surface of the first embedding portion 72 formed in the through hole is not flush with other positions, that is, the first embedding portion 72 has a hollow structure recessed toward the substrate 11.
  • the first through hole is opened in the planarization layer 28, and the pixel defining layer 41 is provided with a first through hole that communicates with the first through hole.
  • the second through hole therefore, in the process of forming the cathode 60 covering the sub-pixel 50, a first embedding portion 61 made of a material of the cathode 60 is formed in the first through hole and the second through hole.
  • the structure in which the cathode 60 is provided with the first embedding portion 61 enhances the bonding force between the cathode 60 and the pixel-defining layer 41, thereby improving the poor adhesion between the OLED layer and the cathode 60 when a heavy object hits the display panel, resulting in easy interlayer adhesion.
  • the problem of peeling improves the impact resistance of the OLED display device.
  • the first embedding portion 61 is made of the material of the cathode 60 and fills the entire first through hole and the second through hole.
  • FIG. 5 a structure of another embodiment of the first embedding portion 61 when the first embedding portion 61 is made of the material of the cathode 60 is provided.
  • a first embedded portion 61 having a hollow structure is formed in the first through hole and the second through hole, and a second embedded portion 74 made of a material of the thin film encapsulation structure 70 is formed in the hollow of the first embedded portion 61. That is, the first embedding portion 61 is a hollow structure, which at least does not completely fill the second through hole, and the second embedding portion 74 is filled in the hollow of the first embedding portion 61 and is at least partially embedded in the pixel defining layer 41.
  • the first embedding portion 61 is in direct contact with the interlayer insulating layer 27, and the second embedding portion 74 is not in direct contact with the interlayer insulating layer 27.
  • the first embedding portion 61 made of the material of the cathode 60 is provided on the one hand, which improves the bonding force between the cathode 60 and the interlayer insulating layer 27, and further improves the adhesion between the cathode 60 and the OLED layer.
  • the bonding force between the thin film encapsulation structure 70 and the cathode 60 is improved, thereby jointly improving the impact resistance of the OLED display device.
  • the first embedding portion 61 does not completely fill the first through hole, that is, the hollow portion of the first embedding portion 61 penetrates the first through hole and the second through hole, and the second embedding portion 74 is formed at the first An embedded portion 61 is filled in the hollow to fill the first through hole and the second through hole together with the first embedded portion 61. That is, the first embedding portion 61 simultaneously embeds the pixel defining layer 41 and the planarization layer 28 and is in direct contact with the pixel defining layer 41 and the planarizing layer 28, and the second embedding portion 74 simultaneously embeds the pixel defining layer 41 and the planarization layer. Layer 28, but is not in direct contact with the pixel defining layer 41 and the planarization layer 28.
  • the second embedding portion 74 in this embodiment may be formed of the same material as the first embedding portion 61, and details are not described herein again.
  • the other structures of the display panel 200 are basically similar to those of the display panel 100, and are not repeated here.
  • the first embedding portions 72/61 of the display panel 100/200 are embedded in the pixel defining layer 41 and the planarization layer 28 and are in contact with the interlayer insulating layer 27.
  • the embedded structure increases the
  • the interlayer insulating layer 27 is generally made of an inorganic material
  • the cathode 60 is a metal material
  • the bottom layer of the thin film encapsulation structure 70 is also an inorganic encapsulation layer, so the adhesion between the inorganic material and the inorganic material
  • the adhesion between the inorganic material and the metal material is greatly improved compared with the adhesion between the cathode 60 of the conventional metal material and the pixel-defining layer 41, which is often an organic material.
  • the adhesion between the film layers is greatly enhanced, which further improves the poor adhesion between the OLED layer and the cathode 60 when a heavy object hits the display panel, causing the film layer to interlayer
  • the problem of easy peeling improves the impact resistance of the OLED display device.
  • the first embedded portion 72/61 includes a bottom wall in contact with the interlayer insulating layer 27 and a side wall in contact with the pixel defining layer 41 and the planarization layer 28.
  • a display panel 100/200 may be manufactured by the above manufacturing method, and includes an interlayer insulation layer 27, a planarization layer 28, and Pixel-defined layer 41.
  • the pixel defining layer 41 is provided with an opening for setting the sub-pixel 50.
  • the display panel 100/200 further includes a sub-pixel 50, a cathode 60, and a thin film packaging structure 70.
  • the sub-pixel 50 is disposed in the opening of the pixel-defining layer 41.
  • the cathode 60 is disposed on the pixel defining layer 41 and covers the sub-pixels 50.
  • the thin film packaging structure 70 is disposed on the cathode 60.
  • the thin film encapsulation structure 70 or the cathode 60 is provided with a first embedding portion 72/61.
  • the first embedding portion 72/61 is embedded in the pixel defining layer 41 and the planarization layer 28 and is in contact with the interlayer insulating layer 27.
  • the positions of the first embedding portions 72/61 correspond to the positions of the first through holes 101 and the second through holes, that is, the first embedding portions 72/61 are distributed between two adjacent sub-pixels 50.
  • the first embedding portion 72/61 is disposed around the sub-pixel 50.
  • a plurality of first embedding portions 72/61 may be arranged around the sub-pixel 50 to form a surrounding shape, or a first embedding portion 72/61 may be annular to surround the sub-pixel 50 It is set to better enhance the impact strength at the sub-pixel 40.
  • the sub-pixels 50 there are multiple sub-pixels 50, and a portion of the sub-pixels 50 may surround a plurality of first embedding portions 72/61, and a portion of the sub-pixels 50 may be surrounded by The first insertion part 72/61 is an annular hole.
  • the outer diameter dimension of the first embedding portion 72/61 is gradually reduced from the pixel defining layer 41 to the interlayer insulating layer 27. It is worth noting that when the first inserting portion 72/61 is ring-shaped, the outer diameter dimension refers to the ring width, that is, the difference between the outer ring radius and the inner ring radius of the ring. Further, the first embedding portion 72/61 includes a bottom wall that is in contact with the interlayer insulating layer 27 and a side wall that is in contact with the pixel defining layer 41 and the planarization layer 28. The angle between the bottom wall and the side wall is 100 ° -150 °.
  • the thin film encapsulation structure 70 includes a first inorganic encapsulation layer 71, an organic encapsulation layer 73, and a second inorganic encapsulation layer 75 which are disposed in a stacked manner.
  • the first inorganic encapsulation layer 71 covers the cathode;
  • the first embedding portion 71 is formed at least part of the first inorganic encapsulation layer 71.
  • part of the first inorganic encapsulation layer 71 refers to the first inorganic encapsulation layer 71 deposited in the first through hole and the second through hole. It can be understood that the structure of the first embedding portion 71 is not limited to this.
  • the first embedding portion 71 is further formed of an organic packaging material and / or a second inorganic packaging material deposited on the first inorganic packaging material. .
  • the cathode material or the thin film encapsulating material and the interlayer insulating layer 27 are in surface-to-surface contact, so as to increase the contact area between the cathode material or the thin film encapsulating material and the interlayer insulating layer; correspondingly, the first embedding portion 71 / 61 is in surface-to-surface contact with the interlayer insulation layer.
  • the first embedding portion 71/61 cooperates with the notch, that is, the first embedding portion 71/61 is embedded in the interlayer insulation layer 27.
  • the display panel 100/200 can be manufactured by the above manufacturing method, and other structural features are not described in detail one by one.
  • the display panel 100/200 has improved the structure and cleverly made use of the characteristics of the materials, which greatly enhanced the adhesion between the film layers, thereby improving the adhesion between the OLED layer and the cathode 60 when a heavy object hits the display panel.
  • an embodiment of the present disclosure further provides a display terminal including the above display panel 100/200.
  • the display terminal may be a television, a tablet computer, a mobile phone, or the like.
  • the display terminal includes the display panel 100/200 and a control unit, and the control unit is configured to transmit a display signal to the display panel.
  • the display terminal adopts the above display panel 100/200, which improves the problem of easy peeling between the film layers caused by the poor adhesion between the OLED layer and the cathode when a heavy object hits the display panel, thereby improving the impact resistance of the OLED display device.

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Abstract

本公开涉及一种显示面板及其制造方法和显示终端，该显示面板包括依次层叠设置的层间绝缘层、平坦化层及像素限定层，显示面板还包括子像素、阴极和薄膜封装结构；像素限定层设有开口；子像素设置于像素限定层的开口内；阴极设于像素限定层上且覆盖子像素，薄膜封装结构设于阴极上，薄膜封装结构或阴极设有第一嵌入部，第一嵌入部嵌入像素限定层和平坦化层并与层间绝缘层接触。如此通过结构的改进，并巧妙地利用了材料之间的特性，大大增强了膜层之间的附着力，进而改善了重物击中显示面板时OLED层与阴极附着力差导致膜层间易剥离的问题，从而提高了OLED显示器件的抗冲击能力。

Description

显示面板及其制造方法和显示终端
援引加入
本申请要求于2018年7月5日提交中国专利局、申请号为201810730611.X、发明名称为“显示面板及其制造方法和显示终端”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示装置领域，特别是涉及一种显示面板及其制造方法和显示终端。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管显示装置)被越来越广泛地应用于手机、平板电脑甚至电视等智能终端产品中，然而OLED显示器件在具有较好柔韧性的同时，由于材料及结构限制，其抗冲击性能较弱。当有重物击中OLED显示器件时，被击中的区域容易出现黑斑、亮斑、彩斑等显示不良的情况，从而严重影响了OLED显示器件的使用寿命与使用稳定性。
发明内容
基于此，有必要针对OLED显示器件的抗冲击能力较弱的问题，提供一种改善上述问题的显示面板及其制造方法和显示终端。
一种显示面板，包括：
层间绝缘层；
平坦化层；
像素限定层，所述层间绝缘层、平坦化层及像素限定层依次层叠设置，所述像素限定层设有开口，
子像素，所述子像素设置于所述像素限定层的开口内；
阴极，所述阴极设于所述像素限定层上且覆盖所述子像素；和
薄膜封装结构，所述薄膜封装结构设于所述阴极上，所述薄膜封装结构或所述阴极设有第一嵌入部，所述第一嵌入部嵌入所述像素限定层和所述平坦化层并与所述层间绝缘层接触。
如此第一嵌入部嵌入像素限定层及平坦化层并与层间绝缘层接触，一方面嵌入式的结构增加了膜层之间的结合力，另一方面由于层间绝缘层一般由无机材料制备而成，而阴极为金属材料，薄膜封装结构的底层也为无机封装层，因此无机材料与无机材料之间的附着力、无机材料与金属材料之间的附着力，相比于传统金属材料的阴极与常为有机材料的像素限定层之间的附着力大大提升。如此通过结构的改进，并巧妙地利用了材料之间的特性，大大增强了膜层之间的附着力，进而改善了重物击中显示面板时OLED层与阴极附着力差导致膜层间易剥离的问题，从而提高了OLED显示器件的抗冲击能力，进而提高了其使用寿命与使用稳定性。
可选地，所述第一嵌入部分布于相邻两个所述子像素之间。
可选地，所述第一嵌入部环绕所述子像素设置。
可选地，所述第一嵌入部的外径尺寸自所述像素限定层至所述层间绝缘层逐渐缩小。
可选地，所述第一嵌入部包括与所述层间绝缘层接触的底壁及与所述像素限定层和所述平坦化层接触的侧壁，所述底壁与所述侧壁之间的夹角为100°-150°。
可选地，所述第一嵌入部与所述层间绝缘层为面与面接触。
可选地，所述薄膜封装结构包括层叠设置的第一无机封装层、有机封装层以及第二无机封装层，所述第一无机封装层覆盖所述阴极；
所述薄膜封装结构设有第一嵌入部时，所述第一嵌入部至少由部分所述第一无机封装层形成。
可选地，所述阴极设有第一嵌入部时，所述第一嵌入部为空心结构，所述薄膜封装结构设有第二嵌入部，所述第二嵌入部填充于所述第一嵌入部的空心 内且至少部分嵌入所述像素限定层。
可选地，所述第二嵌入部同时嵌入所述像素限定层和所述平坦化层。
一种显示终端，包括上述显示面板。
一种显示面板的制造方法，所述显示面板包括依次层叠设置的层间绝缘层、平坦化层及像素限定层，所述制造方法包括以下步骤：
在所述平坦化层上开设第一通孔，以暴露出至少部分所述层间绝缘层；
在所述像素限定层开设用于设置子像素的开口及与所述第一通孔连通的第二通孔；
在所述像素限定层的开口内设置子像素；
在所述像素限定层上形成覆盖所述子像素的阴极，在所述阴极上形成薄膜封装结构；
在所述阴极上形成所述薄膜封装结构的过程中或在形成覆盖所述子像素的阴极的过程中，所述第一通孔及所述第二通孔内形成有由所述薄膜封装结构的材料或由所述阴极的材料制得的第一嵌入部。
可选地，所述第一嵌入部由所述薄膜封装结构的材料制得时，在形成所述阴极之后，还包括将所述阴极对应所述第二通孔的位置图案化的步骤；
在所述阴极上形成所述薄膜封装结构的步骤具体为：在图案化的所述阴极上及所述第一通孔和所述第二通孔内沉积所述薄膜封装结构的材料，形成设有所述第一嵌入部的所述薄膜封装结构。
可选地，所述第一嵌入部由所述阴极的材料制得时，所述阴极的材料在所述第一通孔及所述第二通孔内形成空心结构，在所述第一嵌入部的空心内形成有所述薄膜封装结构的材料制得的第二嵌入部。
附图说明
图1为一实施例的显示面板的结构示意图；
图2为图1所示显示面板在形成阴极之前的俯视图；
图3为另一实施例的显示面板在形成阴极之前的俯视图；
图4为另一实施例的显示面板的结构示意图；
图5为图4所示显示面板的第一嵌入部又一实施方式的结构示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的较佳实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容的理解更加透彻全面。
本公开提供了一实施例的显示面板，并提供了该显示面板的制造方法。
请参照图1及图2，显示面板100包括阵列基板、子像素50、阴极60和薄膜封装结构70。阵列基板可以包括基板11、缓冲层12、薄膜晶体管及设于薄膜晶体管上的子像素电极。
显示面板100的制造方法如下。
提供基板11。基板11可以由诸如玻璃材料、金属材料或包括聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)或聚酰亚胺等的塑胶材料中合适的材料形成。
其中，基板11具有第一子像素区域、第二子像素区域和第三子像素区域。一组第一子像素区域、第二子像素区域和第三子像素区域可以构成一个像素区域。在一个实施例中，基板11可以具有多个像素区域，每个像素区域中第一子像素区域可以是发射红光的子像素区域，第二子像素区域可以是发射绿光的子像素区域，第三子像素区域可以是发射蓝光的子像素区域。可以理解地，在其它一些实施例中，每个像素区域亦可包括其他子像素区域，例如，还可包括发射白光的第四子像素区域，在此不作限定。
薄膜晶体管(Thin-film transistor，TFT)可以设置在基板11上。在一个实施例中，在形成TFT之前，可以在基板11上形成诸如缓冲层12的另外的层。缓冲层12可以形成在基板11的整个表面上，也可以通过被图案化来形成。
缓冲层12可以具有包括PET、PEN、聚丙烯酸酯和/或聚酰亚胺等材料中合 适的材料，以单层或多层堆叠的形式形成层状结构。缓冲层12还可以由氧化硅或氮化硅形成，或者可以包括有机材料和/或无机材料的复合层。
TFT可以控制每个子像素的发射，或者可以控制每个子像素发射光时发射的量。TFT可以包括半导体层21、栅电极22、源电极23和漏电极24。
半导体层21可以由非晶硅层、金属氧化物或多晶硅层形成，或者可以由有机半导体材料形成。在一个实施例中，半导体层21包括沟道区和掺杂有掺杂剂的源区与漏区。
可以利用栅极绝缘层25覆盖半导体层21。栅电极22可以设置在栅极绝缘层25上。大体上，栅极绝缘层25可以覆盖基板11的整个表面。在一个实施例中，可以通过图案化来形成栅极绝缘层25。考虑到与相邻层的粘合、堆叠目标层的可成形性和表面平整性，栅极绝缘层25可以由氧化硅、氮化硅或其他绝缘有机或无机材料形成。栅电极22可以被由层间绝缘层27直接覆盖。在一些实施例中，也可在栅电极22上先形成电容的绝缘介质层26，再覆盖层间绝缘层27。
一般地，层间绝缘层27由氧化硅、氮化硅和/或其他合适的绝缘无机材料形成，具体地，层间绝缘层27制备过程中生成的含氢离子进入栅极绝缘层25和沟道区域中和膜层缺陷，从而起到钝化和绝缘作用。具体在一实施例中，层间绝缘层27为氮化硅和氧化硅叠层。
可以去除栅极绝缘层25和层间绝缘层27的一部分，在去除之后形成接触孔以暴露半导体层21的预定区域。源电极23和漏电极24可以经由接触孔接触半导体层21。考虑到导电性，源电极23和漏电极24可以由包括铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)、钼(Mo)、钛(Ti)、钨(W)和铜(Cu)或其他合适的合金中的至少一种材料的单一材料层或复合材料层形成。
由于TFT具有复杂的层结构，因此有必要在TFT上形成平坦化层28，以便形成足够平坦的顶表面。在形成平坦化层28后，可以在平坦化层28中形成电极通孔，以暴露TFT的漏电极24。
本发明人在研究过程中发现，在软屏的落球可靠性测试中，钢球击中屏幕，被击中的区域瞬间不能全彩显示、显示区域出现黑斑、亮斑、彩斑等显示不良的问题。继而通过大量研究发现，主要是因为重物击中瞬间，应力集中无法分散导致元件受损，而其中很重要的原因是落球集中面板时粘附性差的膜层间易发生剥离，而其中OLED层与阴极最易剥离。
如图1及图2所示，基于此，本公开在平坦化层28中还开设第一通孔101，以暴露出至少部分层间绝缘层27，从而便于后续用于形成阴极60的阴极材料或用于形成薄膜封装结构70的薄膜封装材料与层间绝缘层27接触。可理解的是，层间绝缘层27可在对应第一通孔101的位置设置缺口，也就是说阴极材料或薄膜封装材料同时也嵌入层间绝缘层27。可理解的是，考虑制造工艺的复杂性及对层间绝缘层27设置缺口可能导致的缺陷，优选阴极材料或薄膜封装材料直接与层间绝缘层27的顶表面接触。
进一步地，第一通孔101的设置优选避开源电极23和漏电极24，避免破坏和暴露出源电极23和漏电极24。此外，第一通孔101分布于相邻两个用于设置子像素50的开口之间，以便于更好地保护子像素50。具体在本实施例中，第一通孔101为圆形孔状，具体可为正圆形或椭圆形、方形等形状。可理解第一通孔101的形状不限于此。
请参阅图3，在其他实施例中，第一通孔101环绕子像素50设置。进一步地，可以是多个第一通孔101环绕子像素50的周围设置形成环绕状，也可是第一通孔101本身为环状孔，并环绕子像素50设置，以便更好地增强子像素50处的抗冲击强度。可理解的是，在同一实施例中，子像素50的数量有多个，其中一部分的子像素50的周围可环绕多个第一通孔101，一部分的子像素50的周围可环绕有为环状孔的第一通孔101。
可理解，此处环状孔不限于圆形环状，也可以为方形环状，只要其形成闭合的环状结构孔即可。第一通孔101为环状孔且为多个时，可以是其中一个第一通孔101位于另一个第一通孔101内。
进一步优选地，阴极材料或薄膜封装材料与层间绝缘层27为面与面接触， 如此以便于增加阴极材料或薄膜封装材料与层间绝缘层27的接触面积，从而提高阴极或薄膜封装材料与层间绝缘层27之间的附着力，进而改善重物击中显示面板时OLED层与阴极60附着力差导致膜层间易剥离的问题，从而有利于提高OLED显示器件的抗冲击能力。
然后，在平坦化层28上形成第一子像素电极31、第二子像素电极32和第三子像素电极(图未示)。第一子像素电极31形成在第一像素区域。第二子像素电极32形成在第二子像素区域。第三子像素电极形成在第三子像素区域。这里，第一子像素电极31、第二子像素电极32和第三子像素电极可以同时地或同步地形成。第一子像素电极31、第二子像素电极32和第三子像素电极中的每一个可以经过电极通孔电连接到TFT。这里的第一子像素电极31、第二子像素电极32、第三子像素电极通常被称为阳极。
第一子像素电极31、第二子像素电极32和第三子像素电极中的每个可以形成透明电极(透反射式)或反射电极。当第一子像素电极31、第二子像素电极32和第三子像素电极形成透明电极(透反射式)电极时，可以由氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓(IGO)或氧化铝锌(AZO)形成。这里，第一子像素电极31、第二子像素电极32和第三子像素电极的结构和材料不限于此。
在形成第一子像素电极31、第二子像素电极32和第三子像素电极之后，如图1所示，可以形成像素限定层41(PDL)。形成的像素限定层41同时覆盖第一子像素电极31、第二子像素电极32和第三子像素电极。像素限定层41可以通过开设对应每个子像素的开口以用于限定子像素。子像素50设置于像素限定层41的开口内。像素限定层41通常由诸如聚丙烯酸酯和聚酰亚胺等材料中合适的有机材料的单一材料层或复合材料层形成。
请继续参阅图1及图2，本公开在像素限定层41上还开设与第一通孔101连通的第二通孔，以便于阴极材料或薄膜封装材料与层间绝缘层接触。可理解是，第一通孔101可在形成层间绝缘层27后通过图案化形成，第二通孔也可在形成像素限定层41后通过图案化形成。当然在其他方式中，也可在形成层间绝 缘层27及像素限定层41后通过一次打孔形成第一通孔101和第二通孔。可理解的是，像素限定层41上开口和第二通孔的设置也无特定的顺序限定，子像素50和第二通孔的设置也无特定的顺序限定。
考虑到设置通孔的工艺难度或沉积在第一通孔101和第二通孔内材料的连续性，第二通孔和第一通孔101的外径尺寸自像素限定层41至层间绝缘层27逐渐缩小。第二通孔和第一通孔101形成的嵌入孔的侧壁与其所接触的层间绝缘层27的表面之间的夹角为100°-150°，在该角度范围，便于在层间绝缘层27的表面及嵌入孔的侧壁上沉积形成连续的材料层。
像素限定层41可以以下面的方式形成，即在整个基板11的平坦化层28的利用适于像素限定层41的材料，形成像素限定层41，以覆盖第一子像素电极31、第二子像素电极32和第三子像素电极。然后，将像素限定层41图案化，以暴露第一子像素电极31、第二子像素电极32和第三子像素电极的中心部分。
可以蒸镀发光材料形成子像素50。蒸镀材料覆盖第一子像素电极31没有被像素限定层41覆盖的一部分，覆盖第二子像素电极32没有被像素限定层41覆盖的一部分，覆盖第三子像素电极没有被像素限定层41覆盖的一部分。
然后，在像素限定层41上蒸镀形成覆盖第一子像素区域、第二子像素区域和第三子像素区域的阴极60。阴极60可以相对多个子像素一体形成，从而覆盖整个显示区域。阴极60也通常被称为对电极。
在阴极60上形成薄膜封装结构70。薄膜封装结构70包括层叠设置的第一无机封装层71、有机封装层73以及第二无机封装层75，第一无机封装层71覆盖阴极。可理解，薄膜封装结构70的结构不限定于此，其还可包括层叠于第二无机封装层75上的第三无机封装层及设置在第二无机封装层和第三无机封装层之间的另一有机封装层。
具体地，第一无机封装层71和第二无机封装层75为氮化硅薄膜或二氧化硅薄膜。第一无机封装层71和第二无机封装层75可通过化学气相沉积方法形成。有机封装层73可采用喷墨打印形成。具体地，有机封装层73可为丙烯酸酯薄膜，当然有机封装层73的材料不限于此。
请继续参照图1，本公开由于在平坦化层28开设第一通孔101，在像素限定层41开设有与第一通孔101连通的第二通孔，因此在阴极60上形成薄膜封装结构70的过程中，在第一通孔101及第二通孔内形成有由薄膜封装结构70的材料制得的第一嵌入部72(参照图1)。
由于阴极60位于像素限定层41和薄膜封装结构70之间，因此薄膜封装结构70设有第一嵌入部72嵌入的结构在增强薄膜封装结构70与像素限定层41之间的结合力的同时，也保护了阴极60，改善了重物击中显示面板时OLED层与阴极60附着力差导致膜层间易剥离的问题，从而提高了OLED显示器件的抗冲击能力。
第一嵌入部72由薄膜封装结构70的材料制得时，在形成阴极60之后，还包括将阴极60对应第二通孔的位置图案化以形成过孔的步骤。图案化形成的过孔以便于穿过阴极在第一通孔101和第二通孔内沉积薄膜封装结构70的材料。
相应地，在阴极60上形成薄膜封装结构70的步骤具体为：在图案化的阴极60上及第一通孔101和第二通孔内沉积薄膜封装结构70的材料，形成设有第一嵌入部72的薄膜封装结构70。如此薄膜封装结构70与层间绝缘层27直接接触，外层为无机封装层的薄膜封装结构70与层间绝缘层27的附着力很强，大大提升了膜层之间的结合力。
具体在本实施例中，薄膜封装结构70形成有第一嵌入部72时，第一嵌入部72由沉积在第一通孔101及第二通孔内的第一无机封装材料形成。且第一无机封装材料形成的第一无机封装层71的顶表面基本齐平。可理解的是，第一嵌入部72的结构不限于此，在其他实施例中，除第一无机封装材料之外，第一嵌入部72还由沉积在第一无机封装材料上的有机封装材料和/或第二无机封装材料形成。也就是说，第一嵌入部72至少由沉积在第一通孔101及第二通孔内的第一无机封装层71形成。
可以理解的是，在一些实施例中，如第一通孔101及第二通孔的孔径较大或薄膜封装结构70的整体厚度较小时，薄膜封装结构70在第一通孔101及第二通孔内形成的第一嵌入部72的上表面与其他位置未齐平，即第一嵌入部72 呈向基板11凹陷的空心结构。
请参照图4，在另外一些实施例的显示面板200中，基于同样的发明构思，本公开由于在平坦化层28开设第一通孔，在像素限定层41开设有与第一通孔连通的第二通孔，因此在形成覆盖子像素50的阴极60的过程中，在第一通孔及第二通孔内形成有由阴极60的材料制得的第一嵌入部61。
阴极60设有第一嵌入部61的结构，增强了阴极60与像素限定层41之间的结合力，进而改善了重物击中显示面板时OLED层与阴极60附着力差导致膜层间易剥离的问题，从而提高了OLED显示器件的抗冲击能力。
具体在本实施方式中，第一嵌入部61由阴极60的材料制得，且填充整个第一通孔和第二通孔。
请参照图5，提供了第一嵌入部61由阴极60的材料制得时，第一嵌入部61另一实施方式的结构。
在第一通孔及第二通孔内形成为空心结构的第一嵌入部61，且在第一嵌入部61的空心内形成有薄膜封装结构70的材料制得的第二嵌入部74。也就是说，第一嵌入部61为空心结构，其至少没有将第二通孔完全填充，第二嵌入部74填充于第一嵌入部61的空心内且至少部分嵌入像素限定层41。其中，第一嵌入部61与层间绝缘层27直接接触，而第二嵌入部74没有与层间绝缘层27直接接触。
如此一方面设置由阴极60的材料制得的第一嵌入部61，提高了阴极60与层间绝缘层27的结合力，进而提高了阴极60与OLED层之间的附着力，另一方面也提高了薄膜封装结构70与阴极60之间的结合力，从而共同提高了OLED显示器件的抗冲击能力。
具体在本实施例中，第一嵌入部61也没有将第一通孔完全填充，即第一嵌入部61的空心部分贯穿第一通孔与第二通孔，第二嵌入部74形成于第一嵌入部61的空心内，以与第一嵌入部61共同填充第一通孔和第二通孔。也就是说，第一嵌入部61同时嵌入像素限定层41和平坦化层28，并与像素限定层41和平坦化层28直接接触，而第二嵌入部74同时嵌入像素限定层41和平坦化层28， 但并没有与像素限定层41和平坦化层28直接接触。
本实施方式的第二嵌入部74可与第一嵌入部61的形成材料相同，在此不再赘述。显示面板200的其他结构与显示面板100基本相似，在此不赘述。
综上所述，显示面板100/200的第一嵌入部72/61嵌入像素限定层41及平坦化层28并与层间绝缘层27接触，一方面嵌入式的结构增加了膜层之间的结合力，另一方面由于层间绝缘层27一般由无机材料制备而成，而阴极60为金属材料，薄膜封装结构70的底层也为无机封装层，因此无机材料与无机材料之间的附着力、无机材料与金属材料之间的附着力，相比于传统金属材料的阴极60与常为有机材料的像素限定层41之间的附着力大大提升。如此通过结构的改进，并巧妙地利用了材料之间的特性，大大增强了膜层之间的附着力，进而改善了重物击中显示面板时OLED层与阴极60附着力差导致膜层间易剥离的问题，从而提高了OLED显示器件的抗冲击能力。
第一嵌入部72/61包括与层间绝缘层27接触的底壁及与像素限定层41和平坦化层28接触的侧壁，第一嵌入部72/61的底壁与嵌入孔的底壁贴合，第一嵌入部72/61的侧壁与嵌入孔的侧壁贴合。
请继续参阅图1、图4或图5，本较佳实施例的一种显示面板100/200，可由上述制造方法制得，其包括依次层叠设置的层间绝缘层27、平坦化层28及像素限定层41。像素限定层41设有开口以用于设置子像素50。
该显示面板100/200还包括子像素50、阴极60和薄膜封装结构70。子像素50设置于像素限定层41的开口内。
阴极60设于像素限定层41上且覆盖子像素50。薄膜封装结构70设于阴极60上。薄膜封装结构70或阴极60设有第一嵌入部72/61，第一嵌入部72/61嵌入像素限定层41和平坦化层28并与层间绝缘层27接触。
请继续参照图2，第一嵌入部72/61的位置对应第一通孔101及第二通孔的位置分布，即第一嵌入部72/61分布于相邻两个子像素50之间。在其他实施例中，第一嵌入部72/61环绕子像素50设置。请继续参照图3，进一步地，可以是多个第一嵌入部72/61环绕子像素50的周围设置形成环绕状，也可是一个第 一嵌入部72/61为环状，从而环绕子像素50设置，以便更好地增强子像素40处的抗冲击强度。
可理解的是，在同一实施例中，子像素50的数量有多个，其中一部分的子像素50的周围可环绕多个第一嵌入部72/61，一部分的子像素50的周围可环绕有为环状孔的第一嵌入部72/61。
在一些实施例中，第一嵌入部72/61的外径尺寸自像素限定层41至层间绝缘层27逐渐缩小。值得说明的是，当第一嵌入部72/61为环状时，外径尺寸是指环宽，即环的外环半径与内环半径之差。进一步地，第一嵌入部72/61包括与层间绝缘层27接触的底壁及与像素限定层41和平坦化层28接触的侧壁，底壁与侧壁之间的夹角为100°-150°。
可选地，薄膜封装结构70包括层叠设置的第一无机封装层71、有机封装层73以及第二无机封装层75，第一无机封装层71覆盖阴极；薄膜封装结构70设有第一嵌入部71时，第一嵌入部71至少由部分第一无机封装层71形成。此处部分第一无机封装层71是指沉积在第一通孔和第二通孔内的第一无机封装层71。可理解的是，第一嵌入部71的结构不限于此，在其他实施例中，第一嵌入部71还由沉积在第一无机封装材料上的有机封装材料和/或第二无机封装材料形成。
在制造方法中，阴极材料或薄膜封装材料与层间绝缘层27为面与面接触，如此以便于增加阴极材料或薄膜封装材料与层间绝缘层的接触面积；相应地，第一嵌入部71/61与层间绝缘层为面与面接触。
值得说明的是，层间绝缘层27在对应第一通孔的位置设置缺口时，第一嵌入部71/61与该缺口配合，即第一嵌入部71/61嵌入层间绝缘层27。
该显示面板100/200可由上述制造方法制得，其他结构特征不再一一赘述。该显示面板100/200通过结构的改进，并巧妙地利用了材料之间的特性，大大增强了膜层之间的附着力，进而改善了重物击中显示面板时OLED层与阴极60附着力差导致膜层间易剥离的问题，从而提高了OLED显示器件的抗冲击能力。
基于同样的发明构思，本公开的实施例还提供了一种显示终端，包括上述 显示面板100/200。一些实施例中，该显示终端可为电视、平板电脑、手机等等。
在一些实施例中，该显示终端包括该显示面板100/200及控制单元，该控制单元用于向显示面板传输显示信号。
该显示终端，采用上述显示面板100/200，改善了重物击中显示面板时OLED层与阴极附着力差导致膜层间易剥离的问题，从而提高了OLED显示器件的抗冲击能力。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种显示面板，包括：
    层间绝缘层；
    平坦化层；
    像素限定层，所述层间绝缘层、平坦化层及像素限定层依次层叠设置，所述像素限定层设有开口，
    子像素，所述子像素设置于所述像素限定层的开口内；
    阴极，所述阴极设于所述像素限定层上且覆盖所述子像素；和
    薄膜封装结构，所述薄膜封装结构设于所述阴极上，所述薄膜封装结构或所述阴极设有第一嵌入部，所述第一嵌入部嵌入所述像素限定层和所述平坦化层并与所述层间绝缘层接触。
  2. 如权利要求1所述的显示面板，其中，所述第一嵌入部分布于相邻两个所述子像素之间。
  3. 如权利要求1所述的显示面板，其中，所述第一嵌入部环绕所述子像素设置。
  4. 如权利要求1所述的显示面板，其中，所述第一嵌入部的外径尺寸自所述像素限定层至所述层间绝缘层逐渐缩小。
  5. 如权利要求4所述的显示面板，其中，所述第一嵌入部包括与所述层间绝缘层接触的底壁及与所述像素限定层和所述平坦化层接触的侧壁。
  6. 如权利要求5所述的显示面板，其中，所述底壁与所述侧壁之间的夹角为100°-150°。
  7. 如权利要求1所述的显示面板，其中，所述第一嵌入部与所述层间绝缘层为面与面接触。
  8. 如权利要求1-7任一项所述的显示面板，其中，所述薄膜封装结构包括层叠设置的第一无机封装层、有机封装层以及第二无机封装层，所述第一无机封装层覆盖所述阴极；
    所述薄膜封装结构设有第一嵌入部时，所述第一嵌入部至少由部分所述第 一无机封装层形成。
  9. 如权利要求1-7任一项所述的显示面板，其中，所述阴极设有第一嵌入部时，所述第一嵌入部为空心结构，所述薄膜封装结构设有第二嵌入部，所述第二嵌入部填充于所述第一嵌入部的空心内且至少部分嵌入所述像素限定层。
  10. 如权利要求9所述的显示面板，其中，所述第二嵌入部同时嵌入所述像素限定层和所述平坦化层。
  11. 一种显示终端，其中，包括如权利要求1-10任意一项所述的显示面板。
  12. 一种显示面板的制造方法，其中，所述显示面板包括依次层叠设置的层间绝缘层、平坦化层及像素限定层，所述制造方法包括以下步骤：
    在所述平坦化层上开设第一通孔，以暴露出至少部分所述层间绝缘层；
    在所述像素限定层开设用于设置子像素的开口及与所述第一通孔连通的第二通孔；
    在所述像素限定层的开口内设置子像素；
    在所述像素限定层上形成覆盖所述子像素的阴极，在所述阴极上形成薄膜封装结构；
    在所述阴极上形成所述薄膜封装结构的过程中或在形成覆盖所述子像素的阴极的过程中，所述第一通孔及所述第二通孔内形成有由所述薄膜封装结构的材料或由所述阴极的材料制得的第一嵌入部。
  13. 如权利要求12所述的显示面板的制造方法，其中，所述第一嵌入部由所述薄膜封装结构的材料制得时，在形成所述阴极之后，还包括将所述阴极对应所述第二通孔的位置图案化的步骤；
    在所述阴极上形成所述薄膜封装结构的步骤具体为：在图案化的所述阴极上及所述第一通孔和所述第二通孔内沉积所述薄膜封装结构的材料，形成设有所述第一嵌入部的所述薄膜封装结构。
  14. 如权利要求13所述的显示面板的制造方法，其中，所述第一嵌入部由所述阴极的材料制得时，所述阴极的材料在所述第一通孔及所述第二通孔内形成空心结构，在所述第一嵌入部的空心内形成有所述薄膜封装结构的材料制得 的第二嵌入部。
  15. 如权利要求14所述的显示面板的制造方法，其中，所述第一通孔为正圆形或椭圆形或方形或环状孔。
  16. 根据权利要求15所述的显示面板的制造方法，其中，当第一通孔为环状孔且为多个时，其中一个第一通孔位于另一个第一通孔内。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102022129717B3 (de) 2022-11-10 2023-11-16 Schaeffler Technologies AG & Co. KG Lageranordnung

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735791A (zh) * 2018-07-05 2018-11-02 云谷（固安）科技有限公司 显示面板及其制造方法和显示终端
KR102646218B1 (ko) * 2018-11-02 2024-03-08 엘지디스플레이 주식회사 전계 발광 표시 장치
CN109346624B (zh) * 2018-11-27 2020-01-31 云谷（固安）科技有限公司 一种柔性显示面板以及柔性显示装置
CN109860415B (zh) * 2018-12-13 2020-05-22 武汉华星光电半导体显示技术有限公司 有机发光二极管显示装置
US10804491B2 (en) 2018-12-13 2020-10-13 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Organic light emitting diode display device
CN110828520B (zh) 2019-11-15 2022-09-09 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板和显示装置
CN111627951B (zh) * 2020-06-10 2024-06-11 京东方科技集团股份有限公司 一种显示面板、其制作方法及显示装置
KR102817673B1 (ko) 2020-09-04 2025-06-05 어플라이드 머티어리얼스, 인코포레이티드 무기 픽셀 봉입 배리어를 갖는 oled 패널을 제작하는 방법들
CN112951847B (zh) * 2021-01-28 2023-05-30 武汉华星光电技术有限公司 显示面板及显示装置
CN113013181B (zh) * 2021-02-23 2024-04-09 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN113013362B (zh) * 2021-02-26 2023-04-18 云谷（固安）科技有限公司 显示面板、显示面板的制备方法及显示装置
US12581825B2 (en) 2021-04-23 2026-03-17 Applied Materials, Inc. Conductive oxide overhang structures for OLED devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170084675A1 (en) * 2015-09-18 2017-03-23 Samsung Display Co., Ltd. Organic light-emitting display devices and methods of manufacturing organic light-emitting display devices
CN106783881A (zh) * 2016-12-26 2017-05-31 武汉华星光电技术有限公司 一种柔性显示面板及其制造方法
CN108039418A (zh) * 2016-10-31 2018-05-15 乐金显示有限公司 显示装置及其制造方法
CN108735791A (zh) * 2018-07-05 2018-11-02 云谷（固安）科技有限公司 显示面板及其制造方法和显示终端

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8766269B2 (en) * 2009-07-02 2014-07-01 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device, lighting device, and electronic device
US9876064B2 (en) * 2013-08-30 2018-01-23 Lg Display Co., Ltd. Flexible organic electroluminescent device and method for fabricating the same
KR102471111B1 (ko) * 2015-11-23 2022-11-28 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
KR102524535B1 (ko) * 2016-03-29 2023-04-24 삼성디스플레이 주식회사 디스플레이 장치
EP4380340A3 (en) * 2016-04-29 2024-08-07 LG Display Co., Ltd. Organic light-emitting display device and method of manufacturing the same
KR102066099B1 (ko) * 2016-07-29 2020-01-14 엘지디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR102711102B1 (ko) * 2016-11-15 2024-09-27 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
JP2019046175A (ja) * 2017-09-01 2019-03-22 株式会社ジャパンディスプレイ 表示装置
CN108039356B (zh) 2017-11-21 2021-03-16 上海天马微电子有限公司 显示面板、显示装置和显示面板的制造方法
KR102485295B1 (ko) * 2017-11-30 2023-01-04 엘지디스플레이 주식회사 표시장치
KR102579252B1 (ko) * 2018-06-27 2023-09-15 엘지디스플레이 주식회사 발광 표시 장치 및 이의 제조 방법
CN109411522A (zh) * 2018-11-06 2019-03-01 京东方科技集团股份有限公司 一种透明显示面板及其制备方法、显示装置
KR102772063B1 (ko) * 2018-12-18 2025-02-21 엘지디스플레이 주식회사 유기발광 표시장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170084675A1 (en) * 2015-09-18 2017-03-23 Samsung Display Co., Ltd. Organic light-emitting display devices and methods of manufacturing organic light-emitting display devices
CN108039418A (zh) * 2016-10-31 2018-05-15 乐金显示有限公司 显示装置及其制造方法
CN106783881A (zh) * 2016-12-26 2017-05-31 武汉华星光电技术有限公司 一种柔性显示面板及其制造方法
CN108735791A (zh) * 2018-07-05 2018-11-02 云谷（固安）科技有限公司 显示面板及其制造方法和显示终端

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102022129717B3 (de) 2022-11-10 2023-11-16 Schaeffler Technologies AG & Co. KG Lageranordnung

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