WO2020001479A1 - 开机启动电路及终端 - Google Patents

开机启动电路及终端 Download PDF

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WO2020001479A1
WO2020001479A1 PCT/CN2019/093021 CN2019093021W WO2020001479A1 WO 2020001479 A1 WO2020001479 A1 WO 2020001479A1 CN 2019093021 W CN2019093021 W CN 2019093021W WO 2020001479 A1 WO2020001479 A1 WO 2020001479A1
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pin
power
level
terminal
state
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PCT/CN2019/093021
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English (en)
French (fr)
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刘春辉
宋建峰
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南京中兴软件有限责任公司
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Publication of WO2020001479A1 publication Critical patent/WO2020001479A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

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  • the present disclosure relates to, but is not limited to, the technical field of booting.
  • the power-on sequence has such requirements: On the one hand, the terminal changes from the first state (for example, G3 state) to the power-on state (that is, the terminal is powered on and the user A state where normal operations can be performed).
  • the terminal When the user shuts down normally (that is, the user selects shutdown through the desktop menu of the terminal) and unplugs the power adapter, the terminal enters the first state.
  • the power-on sequence in this case is: first state- -> Plug in the power adapter-> Power on some terminal circuits-> Power supply unit (for example, nuclear power VNN, which is the nuclear power of the Apollo Lake platform CPU, this power supply unit has no power in the G3 state and S5 state, and is powered on There is power, which mainly supplies power to the key circuits inside the CPU.)
  • Power on-> the user presses the power button-> the power-on sequence control signal (for example, SLP_S3) output by the CPU is high-> the terminal is turned on; ,
  • the terminal changes from the second state (for example, the S5 state) to the power-on state.
  • the terminal enters the second state.
  • the power-on sequence in this case is: the second state ( in In this state, the terminal part of the circuit has power)-> the user presses the power-on button-> the power-on sequence control signal output by the CPU is high-> the power unit is powered on-> the terminal is turned on.
  • a boot-up startup circuit including: a D trigger configured to identify whether a terminal is in a first state or a second state in response to the terminal being in the first state Enabling the power supply unit to power on by itself, and in response to the terminal being in the second state, controlling the power supply unit to be powered on by a power-on timing control signal and a power-on control signal; and a MOS tube configured to be In the two states, the power supply unit is controlled to be powered on according to the power-on timing control signal, the power-on control signal, and the output level of the D flip-flop.
  • a terminal including a startup circuit described herein.
  • FIG. 1 is a circuit schematic diagram of a startup circuit according to some embodiments of the present disclosure.
  • FIG. 2 is another circuit schematic diagram of a startup circuit according to some embodiments of the present disclosure.
  • FIG. 1 is a circuit schematic diagram of a startup circuit according to some embodiments of the present disclosure.
  • the startup circuit includes a D flip-flop D1 and a MOS transistor VT1.
  • the D trigger D1 is used to identify whether the terminal is currently in a first state (for example, G3 state) or a second state (for example, S5 state), in response to the terminal being in the first state, causing the nuclear power VNN to power itself on, and in response to The terminal is in the second state, and the nuclear power VNN is controlled to be powered on by the power-on sequence control signal SLP_S3 and the MOS tube VT1.
  • the MOS tube VT1 is used to control the nuclear power VNN to be powered on according to the power-on timing control signal SLP_S3 and the output level of the Q pin of the D flip-flop D1.
  • the first state refers to the state where the terminal is completely depleted, that is, the external power adapter has not been plugged into the terminal, and the second state refers to that some circuits of the terminal are powered, but the nuclear power VNN has not been powered on.
  • the power-on sequence control signal SLP_S3 can be issued by the CPU, and is high level in the power-on state and low level in the second state.
  • the power-on timing control signal SLP_S3 changes from low to high.
  • the power-on timing control signal SLP_S3 changes from high Goes low.
  • the nuclear power VNN is the power supply unit for the CPU of the Apollo Lake platform. It has no power in the first state and the second state, and has power in the power-on state, which is used to supply power to the key circuits inside the CPU.
  • the D flip-flop D1 includes a CLK pin, a D pin, a PRE * pin, a CLR * pin, and a Q pin.
  • the D pin is a preset terminal
  • the Q pin is an output terminal
  • the default output level of the Q pin can be set by the input levels of the PRE * and CLR * pins.
  • the specific setting method is as follows: After the D flip-flop D1 is powered on, if the input level of the PRE * pin is Is low level, the input level of the CLR * pin is high level, the output of the Q pin is high level; if the input level of the PRE * pin is high level, the input level of the CLR * pin If it is low, the output of the Q pin is low; or if the input level of the PRE * pin is high and the input level of the CLR * pin is high, the output of the Q pin The level remains unchanged.
  • the D pin of the D flip-flop D1 is connected to a + 3.3V power supply through a pull-up resistor R3.
  • the PRE * pin of the D flip-flop D1 is connected to a + 3.3V power supply through a pull-up resistor R1 to set the input level of the PRE * pin.
  • CLR D flip-flop D1 * RC circuit pin implemented by the CLR pin * input level is provided, the RC circuit comprises a capacitor C1 and a resistor R2, a capacitor C1 is connected between the ground pin and the CLR *, resistor R2 Connect between CLR * pin and + 3.3V power supply.
  • D flip-flop D1 also includes a CLK pin, a Q * pin, a GND pin, and a VCC pin.
  • the CLK pin is connected to the power-on timing control signal SLP_S3, the Q * pin is left empty, and the VCC pin is connected to the + 3.3V power supply.
  • the MOS transistor VT1 is an N-channel MOS transistor, and the gate (G) pin of the N-channel MOS transistor is connected to the Q pin of the D flip-flop D1 and the N-channel MOS transistor.
  • the source (S) pin of the tube is connected to the power-up timing control signal SLP_S3, and the drain (D) pin of the N-channel MOS tube is connected to the VNN network unit 100.
  • the VNN network unit 100 includes an access terminal VNN_ON for providing a power-on control signal of the nuclear power VNN.
  • the access terminal VNN_ON is connected to the drain (D) pin of the N-channel MOS tube.
  • R4 is connected to a + 3.3V power supply, and the access terminal VNN_ON is connected to the ground line through a capacitor C3.
  • the MOS tube VT1 is an N-channel MOS tube.
  • the gate (G) pin of the MOS tube VT1 is low and the source (S) pin is also low. Therefore, the MOS tube VT1 is turned off.
  • the access terminal VNN_ON is pulled up to the power supply + V3.3 by the resistor R4, which is a high level, so the nuclear power VNN is powered on.
  • the CPU pulls up the power-on sequence control signal SLP_S3, and then the terminal powers on.
  • the power-on timing control signal SLP_S3 is connected to the CLK pin of the D flip-flop D1, so during the power-on process, the level of the CLK pin of the D flip-flop D1 will change from low to high (that is, a rising edge ), Then the state of the D flip-flop D1 is reversed, and the level of the Q pin is equal to the level of the D pin, that is, the Q pin outputs a high level.
  • the second state is achieved by the user's normal shutdown operation.
  • Normal shutdown refers to the user's shutdown operation through the desktop menu of the terminal.
  • the CPU will pull down the power-on sequence control signal SLP_S3. Since the CLK pin of D flip-flop D1 is a valid rising edge, the Q pin of D flip-flop D1 remains high during the shutdown process. .
  • the gate (G) pin of the MOS transistor VT1 is high, the source (S) pin is low, and the voltage at the gate (G) pin It is higher than the voltage of the source (S) pin and the voltage difference between the two is greater than 1V. Therefore, the MOS tube VT1 is turned on, then the access terminal VNN_ON is pulled down to a low level, and the nuclear power VNN is powered off.
  • the power-on sequence control signal SLP_S3 is low, the Q pin of the D flip-flop D1 outputs a high level, the power source + V3.3 is powered on, the MOS tube VT1 is turned on, Nuclear power VNN is dead.
  • the CPU will pull up the power-on timing control signal SLP_S3, and the level of the CLK pin of the D flip-flop D1 will change from low to high (ie, rising edge). The pin remains high, so the Q pin remains high.
  • the gate (G) pin of the MOS tube VT1 is high and the source (S) pin is also high. Therefore, the MOS tube VT1 is turned off, and the access terminal VNN_ON is changed by the pull-up resistor R4. When it is high, the nuclear power VNN is powered on and the terminal is turned on.
  • the embodiment of the present disclosure uses the D flip-flop D1 and the N-channel MOS tube to realize the two different power-up sequence requirements of the Apollo Lake platform, which has low cost and simple circuit.
  • FIG. 2 is another circuit schematic diagram of a startup circuit according to some embodiments of the present disclosure.
  • the MOS tube VT2 is a P-channel MOS tube.
  • the gate (G) pin of the P-channel MOS tube is connected to the Q pin of the D flip-flop D1 and the drain of the P-channel MOS tube.
  • the (D) pin is connected to the power-on timing control signal SLP_S3, and the source (S) pin of the P-channel MOS tube is connected to the access terminal VNN_ON of the VNN network unit 100.
  • the D pin of the D flip-flop D1 is grounded, and the CLR * pin of the D flip-flop D1 is connected to a + 3.3V power supply through a pull-up resistor R1 to achieve the input level of the CLR * pin.
  • D flip-flop D1 PRE * input pin of a level set by the PRE * pin RC circuit the RC circuit comprises a capacitor C1 and a resistor R2, a capacitor C1 is connected between the ground pin and PRE *, And the resistor R2 is connected between the PRE * pin and the + 3.3V power supply.
  • the input level of the CLR * pin is set high by the pull-up resistor R1, and the input level of the PRE * pin is initially at the input level of the PRE * pin due to the external RC circuit. Low, as capacitor C1 is fully charged, the input level of the PRE * pin goes high and then remains high. Therefore, after power-on is complete, the input level of the PRE * pin is low and the input level of the CLR * pin is high, so the Q pin outputs a high level.
  • the MOS tube VT2 is a P-channel MOS tube.
  • the gate (G) pin of the MOS tube VT2 is high and the source (S) pin is also high. Therefore, the MOS tube VT2 is turned off.
  • the access terminal VNN_ON is pulled up to the power supply + V3.3 by the resistor R4, which is a high level, so the nuclear power VNN is powered on.
  • the CPU pulls up the power-on sequence control signal SLP_S3, and then the terminal powers on.
  • the power-on timing control signal SLP_S3 is connected to the CLK pin of the D flip-flop D1, so during the power-on process, the level of the CLK pin of the D flip-flop D1 will change from low to high (that is, a rising edge ), Then the state of the D flip-flop D1 is reversed, and the level of the Q pin is equal to the level of the D pin, that is, the Q pin outputs a low level.
  • the second state is achieved by the user's normal shutdown operation.
  • the CPU will pull down the power-on sequence control signal SLP_S3. Since the CLK pin of D flip-flop D1 is a valid rising edge, the Q pin of D flip-flop D1 remains low during the shutdown process. .
  • the power-on timing control signal SLP_S3 is pulled low by the CPU, the gate (G) pin of the MOS tube VT2 is low, the source (S) pin is high, and the voltage at the gate (G) pin It is lower than the voltage of the source (S) pin and the voltage difference between the two is greater than 1V. Therefore, the MOS tube VT2 is turned on, and then the access terminal VNN_ON is pulled down to a low level, and the nuclear power VNN is powered off.
  • the power-on sequence control signal SLP_S3 is low, the Q pin of the D flip-flop D1 outputs a low level, the power source + V3.3 is powered, the MOS tube VT2 is turned on, Nuclear power VNN is dead.
  • the CPU will pull up the power-on timing control signal SLP_S3, and the level of the CLK pin of the D flip-flop D1 will change from low to high (ie, rising edge). The pin remains low, so the Q pin remains low.
  • the gate (G) pin of the MOS tube VT2 is at a low level and the source (S) pin is at a high level. Therefore, the MOS tube VT2 is turned on and the power-on timing control signal SLP_S3 has been pulled high.
  • the access terminal VNN_ON becomes high level, the nuclear power VNN is powered on, and the terminal is turned on.
  • the present disclosure provides a terminal, which may be a thin client based on the Intel Apollo Lake platform, or another terminal based on the Intel Apollo Lake platform and having the same power-on sequence requirements.
  • the terminal includes a startup circuit as shown in FIG. 1 or FIG. 2. In order to reduce redundancy, a detailed description of the above startup circuit is omitted here.
  • start-up startup circuit of the embodiment of the present disclosure and the terminal including the start-up startup circuit, two different power-up sequence requirements for the terminals of the Apollo Lake platform are achieved through D flip-flops and MOS tubes, and the cost is low and the circuit is simple.

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Abstract

本公开提供了一种开机启动电路及终端。开机启动电路包括：D触发器，其构造为识别终端是处于第一状态还是第二状态，以响应于终端处于第一状态使电源单元自行上电，并且响应于终端处于第二状态通过上电时序控制信号和上电控制信号来控制电源单元上电；以及MOS管，其构造为在终端处于第二状态时，根据上电时序控制信号、上电控制信号和D触发器的输出电平来控制电源单元上电。

Description

开机启动电路及终端 技术领域
本公开涉及(但不限于)开机启动技术领域。
背景技术
目前，对基于Intel Apollo Lake平台进行设计的瘦终端来说，上电顺序有这样的需求：一方面，终端从第一状态(例如，G3状态)变成开机状态(即，终端开机完成，用户可以进行正常操作的状态)，当用户正常关机(即，用户通过终端桌面菜单选择关机)并拔掉电源适配器，终端就会进入第一状态，该种情形的上电顺序是：第一状态-->电源适配器插入-->终端部分电路上电-->电源单元(例如，核电VNN，其为Apollo Lake平台CPU的核电，该电源单元在G3状态和S5状态下没电，在开机状态下有电，主要给CPU内部的关键电路供电)上电-->用户按下开机铵钮-->CPU输出的上电时序控制信号(例如，SLP_S3)为高-->终端开机；另一方面，终端从第二状态(例如，S5状态)变成开机状态，当用户进行正常关机但没有拔掉电源适配器，终端就会进行第二状态，该种情形的上电顺序是：第二状态(在该状态下，终端部分电路有电)-->用户按下开机按钮-->CPU输出的上电时序控制信号为高-->电源单元上电-->终端开机。
对于以上两种上电顺序的要求，通用做法有两种：使用专门的电源管理芯片，且该电源芯片只能与Apollo Lake平台配套使用，换言之，如果换成另外一个平台，则需要重新选择另外一个电源管理芯片，这种方案成本太高且通用性差；或者使用复杂可编程逻辑器件(CPLD)，设计专用逻辑程序，用以满足Apollo Lake平台的特殊上电顺序要求。
发明内容
根据本公开的一个方面，提供一种开机启动电路，所述开机启动电路包括：D触发器，其构造为识别终端是处于第一状态还是第二 状态，以响应于所述终端处于第一状态，使电源单元自行上电，并且响应于所述终端处于第二状态，通过上电时序控制信号和上电控制信号来控制电源单元上电；以及MOS管，其构造为在所述终端处于第二状态时，根据上电时序控制信号、上电控制信号和D触发器的输出电平来控制电源单元上电。
根据本公开的另一方面，提供一种终端，包括本文所述的开机启动电路。
附图说明
图1为根据本公开的一些实施例的开机启动电路的电路原理图。
图2为根据本公开的一些实施例的开机启动电路的另一电路原理图。
具体实施方式
为了使本公开所要解决的技术问题、技术方案及有益效果更加清楚、明白，以下结合附图和实施例，对本公开进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本公开，并不用于限定本公开。
在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或“单元”的后缀仅为了有利于本公开的说明，其本身没有特定的意义。因此，“模块”、“部件”或“单元”可以混合地使用。
图1为根据本公开的一些实施例的开机启动电路的电路原理图。
如图1所示，根据本公开实施例的开机启动电路包括D触发器D1和MOS管VT1。D触发器D1用于识别终端当前是处于第一状态(例如，G3状态)还是第二状态(例如，S5状态)，以响应于终端处于第一状态，使核电VNN自行上电，并且响应于终端处于第二状态，通过上电时序控制信号SLP_S3及MOS管VT1来控制核电VNN上电。MOS管VT1用于根据上电时序控制信号SLP_S3及D触发器D1的Q引脚的输出电平来控制核电VNN上电。第一状态指的是终端完全没电的状态，即，外置的电源适配器尚未插入终端，并且第二状态指的是终端的部 分电路有电，但核电VNN尚未上电。
上电时序控制信号SLP_S3可以由CPU发出，并且在开机状态下为高电平、在第二状态下为低电平。当终端从第二状态切换到开机状态时，上电时序控制信号SLP_S3由低电平变为高电平，当终端从开机状态切换到第二状态时，上电时序控制信号SLP_S3由高电平变为低电平。核电VNN是Apollo Lake平台的CPU的电源单元，在第一状态和第二状态下没电，并且在开机状态下有电，用于给CPU内部的关键电路供电。
在一些实施例中，如图1所示，D触发器D1包括CLK引脚、D引脚、PRE *引脚、CLR *引脚以及Q引脚。D引脚为预置端，Q引脚为输出端，CLK引脚为控制端(即，触发沿)。若CLK引脚的电平由低变高(即，上升沿)，则D引脚的电平会输出到Q引脚(即Q＝D)；若CLK引脚的电平没有变化或由高变低(即，下降沿)，则Q引脚的电平保持不变。可以通过PRE *引脚与CLR *引脚的输入电平来设置Q引脚的默认输出电平，具体设置方法如下：当D触发器D1上电完成后，若PRE *引脚的输入电平为低电平，CLR *引脚的输入电平为高电平，则Q引脚的输出高电平；若PRE *引脚的输入电平为高电平，CLR *引脚的输入电平为低电平，则Q引脚的输出低电平；或者，若PRE *引脚的输入电平为高电平，CLR *引脚的输入电平为高电平，则Q引脚的输出电平保持不变。
如图1所示，D触发器D1的D引脚通过上拉电阻R3与+3.3V电源连接。D触发器D1的PRE *引脚通过上拉电阻R1与+3.3V电源连接，以实现PRE *引脚的输入电平的设置。D触发器D1的CLR *引脚通过RC电路来实现CLR *引脚的输入电平的设置，RC电路包括电容C1和电阻R2，电容C1连接在CLR *引脚与地线之间，电阻R2连接在CLR *引脚与+3.3V电源之间。当D触发器D1上电完成后，PRE *引脚的输入电平通过上拉电阻R1设置为高，而CLR *引脚由于外接RC电路的作用，导致CLR *引脚的输入电平一开始为低，随着电容C1充电的完成，CLR *引脚的输入电平变高，随后保持高电平不变。因此，在上电完成后，CLR *引脚的输入电平为低、PRE *引脚的输入电平为高，从而Q引脚输出低 电平。
如图1所示，D触发器D1还包括CLK引脚、Q *引脚、GND引脚以及VCC引脚。CLK引脚连接上电时序控制信号SLP_S3，Q *引脚空置，并且VCC引脚连接+3.3V电源。在图1所示的实施例中，MOS管VT1为N沟道的MOS管，N沟道的MOS管的栅极(G)引脚连接D触发器D1的Q引脚，N沟道的MOS管的源极(S)引脚连接该上电时序控制信号SLP_S3，并且N沟道的MOS管的漏极(D)引脚连接VNN网络单元100。VNN网络单元100包括接入端VNN_ON用于提供核电VNN的上电控制信号，接入端VNN_ON与N沟道的MOS管的漏极(D)引脚连接，接入端VNN_ON还通过上拉电阻R4与+3.3V电源连接，并且接入端VNN_ON通过电容C3与地线连接。当上电控制信号为高电平时，核电VNN上电，并且当上电控制信号为低电平时，核电VNN掉电。
工作时，如图1所示，响应于终端的状态为第一状态(例如，G3状态)，在电源适配器插入以后，电源+V3.3上电，D触发器D1的Q引脚输出低电平，MOS管VT1为N沟道MOS管，此时，MOS管VT1的栅极(G)引脚为低电平，源极(S)引脚也为低电平，因此，MOS管VT1关断。接入端VNN_ON由电阻R4上拉至电源+V3.3，为高电平，因此核电VNN上电。用户按下开机键以后，CPU拉高上电时序控制信号SLP_S3，然后终端开机。需要说明的是，上电时序控制信号SLP_S3与D触发器D1的CLK引脚相连，因此在上电过程中，D触发器D1的CLK引脚的电平会由低变高(即，上升沿)，接着D触发器D1的状态会翻转，Q引脚的电平等于D引脚的电平，即，Q引脚输出高电平。
响应于终端的状态为第二状态(例如，S5状态)，如上所述，第二状态是通过用户正常关机操作实现，正常关机指的是用户通过终端的桌面菜单进行关机操作。在正常关机的过程中，CPU会拉低上电时序控制信号SLP_S3，由于D触发器D1的CLK引脚是上升沿有效，因此关机过程中，D触发器D1的Q引脚仍然保持高电平。当上电时序控制信号SLP_S3被CPU拉低以后，MOS管VT1的栅极(G)引脚为高电平，源极(S)引脚为低电平，栅极(G)引脚的电压比源极(S)引脚的电压高且二者的电压差大于1V。因此，MOS管VT1导通，接着 接入端VNN_ON被拉低至低电平，核电VNN掉电。
在第二状态下并且在用户按下开机键之前，上电时序控制信号SLP_S3为低、D触发器D1的Q引脚输出高电平、电源+V3.3有电、MOS管VT1导通、核电VNN没电。在第二状态下并且在用户按下开机键以后，CPU会拉高上电时序控制信号SLP_S3，D触发器D1的CLK引脚的电平会由低变高(即，上升沿)，由于D引脚持续保持高电平，因此Q引脚保持高电平不变。此时，MOS管VT1的栅极(G)引脚为高电平，源极(S)引脚也为高电平，因此，MOS管VT1断开，接入端VNN_ON通过上拉电阻R4变成高电平，核电VNN上电，终端开机。
如上所述，本公开实施例采用D触发器D1和N沟道的MOS管实现了Apollo Lake平台两种不同的上电顺序要求，成本低且电路简单。
图2为根据本公开的一些实施例的开机启动电路的另一电路原理图。如图2所示，MOS管VT2为P沟道的MOS管，P沟道的MOS管的栅极(G)引脚连接D触发器D1的Q引脚，P沟道的MOS管的漏极(D)引脚连接上电时序控制信号SLP_S3，并且P沟道的MOS管的源极(S)引脚连接VNN网络单元100的接入端VNN_ON。
此外，如图2所示，D触发器D1的D引脚接地，D触发器D1的CLR *引脚通过上拉电阻R1与+3.3V电源连接，以实现CLR *引脚的输入电平的设置，D触发器D1的PRE *引脚通过RC电路来实现PRE *引脚的输入电平的设置，RC电路包括电容C1和电阻R2，电容C1连接在PRE *引脚与地线之间，并且电阻R2连接在PRE *引脚与+3.3V电源之间。当D触发器D1上电完成后，CLR *引脚的输入电平由上拉电阻R1设置为高，而PRE *引脚由于外接RC电路的作用，导致PRE *引脚的输入电平一开始为低，随着电容C1充电的完成，PRE *引脚的输入电平变高，随后保持高电平不变。因此，在上电完成后，PRE *引脚的输入电平为低、CLR *引脚的输入电平为高，从而Q引脚输出高电平。
工作时，如图2所示，响应于终端的状态为第一状态(例如，G3状态)，在电源适配器插入以后，电源+V3.3上电，D触发器D1的Q引脚输出高电平，MOS管VT2为P沟道MOS管，此时，MOS管VT2的栅极(G)引脚为高电平，源极(S)引脚也高电平，因此，MOS管 VT2关断。接入端VNN_ON由电阻R4上拉至电源+V3.3，为高电平，因此核电VNN上电。用户按下开机键以后，CPU拉高上电时序控制信号SLP_S3，然后终端开机。需要说明的是，上电时序控制信号SLP_S3与D触发器D1的CLK引脚相连，因此在上电过程中，D触发器D1的CLK引脚的电平会由低变高(即，上升沿)，接着D触发器D1的状态会翻转，Q引脚的电平等于D引脚的电平，即，Q引脚输出低电平。
响应于终端的状态为第二状态(例如，S5状态)，如上所述，第二状态是通过用户正常关机操作实现。在正常关机的过程中，CPU会拉低上电时序控制信号SLP_S3，由于D触发器D1的CLK引脚是上升沿有效，因此关机过程中，D触发器D1的Q引脚仍然保持低电平。当上电时序控制信号SLP_S3被CPU拉低以后，MOS管VT2的栅极(G)引脚为低电平，源极(S)引脚为高电平，栅极(G)引脚的电压比源极(S)引脚的电压低且二者的电压差大于1V。因此，MOS管VT2导通，接着接入端VNN_ON被拉低至低电平，核电VNN掉电。
在第二状态下并且在用户按下开机键之前，上电时序控制信号SLP_S3为低、D触发器D1的Q引脚输出低电平、电源+V3.3有电、MOS管VT2导通、核电VNN没电。在第二状态下并且在用户按下开机键以后，CPU会拉高上电时序控制信号SLP_S3，D触发器D1的CLK引脚的电平会由低变高(即，上升沿)，由于D引脚持续保持低电平，因此Q引脚保持低电平不变。此时，MOS管VT2的栅极(G)引脚为低电平，源极(S)引脚为高电平，因此，MOS管VT2导通，上电时序控制信号SLP_S3已经被拉高，接入端VNN_ON变成高电平，核电VNN上电，终端开机。
另一方面，本公开提供了一种终端，该终端可以是基于Intel Apollo Lake平台的瘦客户端，也可以是基于Intel Apollo Lake平台的具有同样上电顺序需求的其他终端。终端包括如图1或图2所示的开机启动电路，为了减少冗余，在此省略对上述开机启动电路的详细描述。
根据本公开实施例的开机启动电路以及包括该开机启动电路的终端,通过D触发器和MOS管实现了Apollo Lake平台的终端两种不 同的上电顺序要求，成本低且电路简单。
应当理解的是，当在本文中使用术语“包括”、“包括……的”、“包含”和“包含……的”时，其指示了存在所述特征、整体、步骤、操作、元件和/或部件，但并不排除还存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或它们的组。
已经描述了本公开的各示例实施例，应当清楚的是，可以按照多种方式来对这些示例实施例进行修改。这些修改不应被看作背离本公开的示例实施例的预期精神和范围，并且对于本领域技术人员而言显而易见的所有这些修改都应包括在所附权利要求的范围之中。

Claims (11)

  1. 一种开机启动电路，包括：
    D触发器，其构造为识别终端是处于第一状态还是第二状态，以响应于所述终端处于所述第一状态，使电源单元自行上电，并且响应于所述终端处于所述第二状态，通过上电时序控制信号和上电控制信号来控制所述电源单元上电；以及
    MOS管，其构造为在所述终端处于所述第二状态时，根据所述上电时序控制信号、所述上电控制信号和所述D触发器的输出电平来控制所述电源单元上电。
  2. 如权利要求1所述的开机启动电路，其中，所述D触发器包括CLK引脚、D引脚、PRE *引脚、CLR *引脚以及Q引脚，所述D引脚为预置端，所述Q引脚为输出端，所述CLK引脚为控制端，
    其中，在所述CLK引脚的电平由低电平变为高电平时，所述D引脚的电平被输出到所述Q引脚，并且
    在所述CLK引脚的电平没有变化或者由高电平变为低电平时，通过所述PRE *引脚的输入电平与所述CLR *引脚的输入电平来设置所述Q引脚的输出电平。
  3. 如权利要求2所述的开机启动电路，其中，在所述D触发器上电完成时，
    响应于所述PRE *引脚的输入电平为低电平并且所述CLR *引脚的输入电平为高电平，所述Q引脚输出高电平，
    响应于所述PRE *引脚的输入电平为高电平并且所述CLR *引脚的输入电平为低电平，所述Q引脚输出低电平，并且
    响应于所述PRE *引脚的输入电平为高电平并且所述CLR *引脚的输入电平为高电平，所述Q引脚输出的电平保持不变。
  4. 如权利要求2所述的开机启动电路，其中，所述MOS管为N 沟道的MOS管，所述N沟道的MOS管的栅极连接所述Q引脚，所述N沟道的MOS管的源极连接所述上电时序控制信号，并且所述N沟道的MOS管的漏极连接VNN网络单元。
  5. 如权利要求4所述的开机启动电路，其中，所述PRE *引脚通过第一电阻与电源连接来实现所述PRE *引脚的输入电平的设置，并且所述CLR *引脚通过RC电路来实现所述CLR *引脚的输入电平的设置，并且所述RC电路包括第一电容和第二电阻。
  6. 如权利要求2所述的开机启动电路，其中，所述MOS管为P沟道的MOS管，所述P沟道的MOS管的栅极连接所述Q引脚，所述P沟道的MOS管的漏极连接所述上电时序控制信号，并且所述P沟道的MOS管的源极连接VNN网络单元。
  7. 如权利要求6所述的开机启动电路，其中，所述CLR *引脚通过第一电阻与电源连接来实现所述CLR *引脚的输入电平的设置，并且所述PRE *引脚通过RC电路来实现所述PRE *引脚的输入电平的设置，并且所述RC电路包括第一电容和第二电阻。
  8. 如权利要求2所述的开机启动电路，其中，所述D触发器还包括CLK引脚、Q *引脚、GND引脚以及VCC引脚，
    其中，所述CLK引脚连接所述上电时序控制信号，所述Q *引脚空置，所述VCC引脚连接电源。
  9. 如权利要求4所述的开机启动电路，其中，所述VNN网络单元包括接入端，所述接入端与所述N沟道的MOS管的漏极连接，所述接入端通过第三电阻与所述电源连接，并且所述接入端通过第三电容与地线连接。
  10. 如权利要求6所述的开机启动电路，其中，所述VNN网络 单元包括接入端，所述接入端与所述P沟道的MOS管的源极连接，所述接入端通过第三电阻与所述电源连接，并且所述接入端通过第三电容与地线连接。
  11. 一种终端，包括如权利要求1至10中任一项所述的开机启动电路。
PCT/CN2019/093021 2018-06-28 2019-06-26 开机启动电路及终端 WO2020001479A1 (zh)

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