WO2020000586A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2020000586A1
WO2020000586A1 PCT/CN2018/099240 CN2018099240W WO2020000586A1 WO 2020000586 A1 WO2020000586 A1 WO 2020000586A1 CN 2018099240 W CN2018099240 W CN 2018099240W WO 2020000586 A1 WO2020000586 A1 WO 2020000586A1
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WO
WIPO (PCT)
Prior art keywords
layer
anode
display panel
pixel definition
flat
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PCT/CN2018/099240
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English (en)
French (fr)
Inventor
陈彩琴
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/092,004 priority Critical patent/US10651250B2/en
Publication of WO2020000586A1 publication Critical patent/WO2020000586A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the invention relates to the field of display, in particular to a display panel and a manufacturing method thereof.
  • OLED Organic Light-Emitting Diode
  • LCD liquid crystal display
  • OLED has the advantages of more power saving, thinner, and wide viewing angle, which is incomparable with LCD.
  • people are increasingly demanding the fineness of display, that is, the resolution, but producing high-quality, high-resolution OLED displays still faces many challenges.
  • OLED display devices can be divided into passive matrix OLED (PMOLED) and active matrix (Active Matrix) OLED, AMOLED) two categories, namely direct addressing and thin film transistors (Thin Film Transistor (TFT) matrix addresses two types.
  • PMOLED passive matrix OLED
  • AMOLED Active Matrix OLED
  • TFT Thin Film Transistor
  • AMOLED has pixels arranged in an array, belongs to an active display type, and has high light emitting efficiency, and is generally used as a high-resolution large-sized display device.
  • AMOLED display panels mostly use a top-emitting structure.
  • the light-emitting layer starts to emit light.
  • the output from the cathode is increased by the effect of the resonant cavity Light intensity, but at the same time, a part of light is scattered to adjacent pixels, resulting in mixed colors.
  • the invention provides a display panel and a manufacturing method thereof, so as to solve the technical problem of color mixing in an AMOLED display panel.
  • the present invention provides a method for manufacturing a display panel, wherein the method for manufacturing a display panel includes steps:
  • a flat layer and a pixel definition layer, or the flat layer, the pixel definition layer, and the spacer are sequentially formed on the thin film transistor layer, and a multi-level transmission mask pair is used. Performing exposure and development on the flat layer and the pixel definition layer, or the flat layer, the pixel definition layer, and the spacer;
  • the anode layer covers part of the flat layer and part of the pixel definition layer, and the anode layer is connected to the source and drain electrodes through vias.
  • the anode layer includes at least two anodes, and the anodes correspond to the pixel units of the display panel one to one;
  • the anode includes a first portion in contact with the flat layer and a second portion in contact with the pixel defining layer.
  • an included angle between the first portion and the second portion is ⁇ , and 0 ° ⁇ ⁇ 90 °.
  • the anode is located between two adjacent spacers.
  • the flat layer, the pixel defining layer, and the spacer are made of a photoresist material.
  • the invention provides a display panel, which includes:
  • the light emitting device layer is formed between two adjacent pixel definition layers, and includes:
  • the anode layer includes at least two anodes, and the anodes are in one-to-one correspondence with the pixel units of the display panel; the anode includes a first portion in contact with the flat layer, and a pixel definition layer The second part of the contact.
  • an included angle between the first portion and the second portion is ⁇ , and 0 ° ⁇ ⁇ 90 °.
  • the display panel further includes a spacer formed on the pixel definition layer;
  • the anode is located between two adjacent spacers.
  • the light emitting device layer further includes a light emitting layer formed on the anode layer and a cathode layer formed on the light emitting layer;
  • the light-emitting layer includes a plurality of light-emitting units, and each of the light-emitting units is located in the anode.
  • the invention also provides a display panel, which includes:
  • the light emitting device layer is formed between two adjacent pixel definition layers, and includes:
  • An anode layer is formed on the pixel definition layer, the anode layer covers part of the flat layer and part of the pixel definition layer, and the anode layer is connected to a source and a drain through a via.
  • the display panel further includes a spacer formed on the pixel definition layer;
  • the anode is located between two adjacent spacers.
  • the light emitting device layer further includes a light emitting layer formed on the anode layer and a cathode layer formed on the light emitting layer;
  • the light-emitting layer includes a plurality of light-emitting units, and each of the light-emitting units is located in the anode.
  • the present invention completes the preparation of a flat layer and a pixel definition layer, or a flat layer, a pixel definition layer, and a spacer through a photomask.
  • the light emitting unit is set in the anode, so that the light emitted by the light emitting unit is reflected by the anode. Condensing reduces the risk of color mixing on the display panel and enhances the light intensity on the light exit side.
  • FIG. 1 is a step diagram of a display panel manufacturing method according to an embodiment of the present invention.
  • 2A-2J are process flow charts of a display panel according to an embodiment of the present invention.
  • FIG. 3 is a film structure diagram of a display panel according to a second embodiment of the present invention.
  • FIG. 1 is a step diagram of a method for manufacturing a display panel according to the present invention, wherein the method for manufacturing a display panel includes steps:
  • a substrate 101 is provided, and a raw material of the substrate 101 may be one of a glass substrate, a quartz substrate, and a resin substrate.
  • This step mainly includes sequentially forming a buffer layer 102, an active layer 103, a first insulating layer 104, a first gate 105, a second insulating layer 106, a second gate 107, and a third insulating layer 108 on the substrate 101 in this order.
  • an active layer film is first formed on the buffer layer 102, and the active layer film is made of polysilicon.
  • a first photomask is used for the active layer film.
  • a first photoresist layer (not shown) is formed on the active layer film, a mask (not shown) is used for exposure, and the active layer is processed after development and patterning processes of the first etching. Forming a thin layer of the active layer 103 as shown in FIG. 2B, and peeling off the first photoresist layer;
  • the first insulating layer 104 is formed on the active layer 103.
  • the first insulating layer 104 is an inter-insulating layer, and the inter-insulating layer
  • the source layer 103 is covered, and the inter-insulating layer is mainly used to isolate the active layer 103 from other metal layers;
  • a first metal layer is formed on the first insulating layer 104.
  • the metal material of the first metal layer may generally be molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. Metal, a combination of the above-mentioned metal materials can also be used;
  • a second photomask process is used for the first metal layer, a second photoresist layer is formed on the first metal layer, a mask (not shown) is used for exposure, and development and a second etching patterning process are performed. After that, the first metal layer is formed into the first gate 105 shown in FIG. 2B, and the second photoresist layer is peeled off;
  • ion implantation is performed on the active layer 103 to form a doped region; in this embodiment, a method of forming the doped region is not limited to the method of the embodiment;
  • the second insulating layer 106 is a first gate insulating layer, the second gate insulating layer covers the active layer 103, and the first gate insulating layer is mainly used for A gate 105 is isolated from the second gate 107; preferably, the thickness of the second insulating layer 106 is 50-200 nm; preferably, the material of the first gate insulating layer is usually silicon nitride, and it can also be used. Silicon oxide and silicon oxynitride;
  • the metal material of the second gate 107 is the same as the metal material of the first gate 105.
  • metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper can be used.
  • a combination of the foregoing metal materials may also be used; in this embodiment, the metal material of the second gate 107 is preferably molybdenum, and the thickness of the second gate 107 is 150-250 nm;
  • a third photomask process is used for the metal layer forming the second gate 107, a third photoresist layer is formed on the metal layer, and a mask (not shown) is used for exposure, development, and third etching patterning.
  • the metal layer is used to form a second gate 107 of the array substrate. As shown in FIG. 2D, a third insulating layer 108 is formed on the second gate 107;
  • a first via 109 is formed on the third insulating layer
  • the source and drain electrodes 110 are formed on the third insulating layer 108; a metal material of the source and drain electrodes 110, and a material of the first gate 105 and the second gate 107 It can be the same.
  • metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper can be used, or a combination of the above-mentioned metal materials can be used.
  • the metal of the source and drain 110 The material is preferably titanium aluminum titanium, and the thickness of the source and drain electrodes 110 is 400 to 600 nm;
  • a fourth photomask process is used for the metal layer forming the source and drain electrodes 110, a fourth photoresist layer is formed on the metal layer, and a mask (not shown) is used for exposure, development, and fourth etching patterning processes. After processing, the source layer and the drain layer 110 are formed by the metal layer;
  • the source and drain electrodes 110 are connected to the doped region through a first via hole 109.
  • a flat layer and a pixel definition layer, or the flat layer, the pixel definition layer, and the spacer are sequentially formed on the thin film transistor layer, and a multi-level transmission mask pair is used. Performing exposure and development on the flat layer and the pixel definition layer, or the flat layer, the pixel definition layer, and the spacer;
  • a flat layer 111 and a pixel definition layer 112, or the flat layer 111, the pixel definition layer 112, and the spacer 113 are sequentially formed on the source and drain electrodes 110, and a plurality of segments are used.
  • the mask of the type transmittance exposes and develops the flat layer 111 and the pixel defining layer 112, or the flat layer 111, the pixel defining layer 112, and the spacer 113 to form a layer such as The shape shown in Figure 2H;
  • the flat layer 111, the pixel defining layer 112, and the spacer 113 are all photoresist materials. Therefore, a photomask is used to form the shape using the characteristics of the photoresist; A second via hole 114 is also formed on the flat layer 111.
  • an anode layer is first formed on the pixel definition layer 112 and the flat layer 111, and the anode layer covers part of the flat layer 111 and part of the pixel definition layer 112, and the anode layer passes through the first
  • the two vias 114 are connected to the source and drain 110;
  • the anode layer includes at least two anodes, and the anodes correspond to the pixel units of the display panel in a one-to-one manner, wherein the anodes are located between two adjacent spacers 113;
  • the anode includes a first portion 114 that is in contact with the flat layer, and a second portion 115 that is in contact with the pixel defining layer.
  • the angle between the first portion 114 and the second portion 115 It is ⁇ , and 0 ° ⁇ ⁇ 90 °.
  • the second portion 115 includes a second parallel portion and a second inclined portion, the second parallel portion is parallel to the substrate 101, the second inclined portion is parallel to the second parallel portion, and The included angle of the first portion 114 is ⁇ ;
  • a light emitting layer 117 and a cathode layer 118 formed on the light emitting layer 117 are further formed on the anode layer; wherein the light emitting layer 117 includes at least two light emitting units, each of which emits light. Units are located in the anode, that is, each of the light-emitting units is wrapped by the anode and the cathode layer 118.
  • FIG. 3 is a structural diagram of a film layer of a display panel according to the present invention, wherein the display panel includes a substrate 301, a thin film transistor layer, a flat layer 311, a pixel definition layer 312, and a light emitting device layer;
  • the raw material of the substrate 301 may be one of a glass substrate, a quartz substrate, a resin substrate, and the like.
  • the thin film transistor layer includes a buffer layer 302, an active layer 303, a first insulating layer 304, a first gate 305, a second insulating layer 306, a second gate 307, a third insulating layer 308, and a source and drain 310;
  • the buffer layer 302 is formed on the substrate 301, and is mainly used for buffering the pressure between the layer structure of the membrane, and can also have a function of blocking water and oxygen to a certain extent;
  • the active layer 303 is formed on the buffer layer, and the active layer 303 includes a doped region doped with ions;
  • the first insulating layer 304 is formed on the active layer 303.
  • the first insulating layer 304 is an inter-insulating layer, and the inter-insulating layer covers the active layer 303.
  • An inter-insulating layer is used to isolate the active layer 303 from other metal layers;
  • the first gate electrode 305 is formed on the first insulating layer 304.
  • the metal material of the first gate electrode 305306 can generally be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. A combination of the above-mentioned metal materials can also be used;
  • a second insulating layer 306 is formed on the first gate 305.
  • the second insulating layer 306 is a first gate insulating layer, and the second gate insulating layer connects the active layer 303.
  • the first gate insulating layer is mainly used to isolate the first gate 305 and the second gate 307; preferably, the thickness of the second insulating layer 306 is 50-200 nm, and the first gate
  • the material of the insulating layer is usually silicon nitride, and silicon oxide and silicon oxynitride can also be used;
  • the second gate 307 is formed on the second insulating layer 306.
  • the material of the second gate 307 is the same as that of the first gate 305.
  • the first gate The metal material of the gate 305 and the second gate 307 is molybdenum;
  • the metal layer forming the second gate electrode 307 is subjected to a patterning process to form the second gate electrode 307 having an area larger than that of the first gate electrode 305, that is, the first gate electrode 305 is formed in the second gate electrode 305.
  • the orthographic projection on the grid 307 is within the second grid 307;
  • a third insulating layer 308 is formed on the second insulating layer 306.
  • the third insulating layer 308 is a second gate insulating layer, and the third gate insulating layer connects the second gate 307 cover, the second gate insulating layer is mainly used to isolate the second gate 307 from the source and drain 310; preferably, the thickness of the second insulating layer 306 is 50-200 nm;
  • the material of the second gate insulating layer is the same as that of the first gate insulating layer;
  • the source / drain 310 is formed on the third insulating layer 308.
  • the metal material of the source / drain 310 can generally be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum tungsten alloy, chromium, copper, or titanium aluminum alloy. A combination of the above-mentioned metal materials may also be used; preferably, in this embodiment, the metal material of the source / drain 310 is a titanium aluminum alloy; the source / drain 310 communicates with all of the sources through the first via hole 309. Said doped region connection.
  • the flat layer 311, the pixel defining layer 312, and the spacer 313 are formed on the source and drain electrodes 310.
  • the flat layer 311, the pixel defining layer 312, and the spacer 313 are light. Resist material, therefore, a photomask can be used to form the shape using the characteristics of photoresist.
  • the light emitting device layer is formed on the flat layer 311 and is formed between two adjacent pixel definition layers 312.
  • the light emitting device layer includes:
  • anode layer is formed on the pixel definition layer 312 and the flat layer 311, and the anode layer is connected to the source and drain electrodes 310 through a second via hole 314.
  • the anode layer includes At least two anodes, the anodes being in one-to-one correspondence with the pixel units of the display panel, wherein the anodes are located between two adjacent spacers 313;
  • the anode includes a first portion 314 that is in contact with the flat layer, and a second portion 315 that is in contact with the pixel defining layer.
  • the angle between the first portion 314 and the second portion 315 Is ⁇ , 0 ° ⁇ ⁇ 90 °;
  • the second portion 315 includes a second parallel portion and a second inclined portion, the second parallel portion is parallel to the substrate 301, the second inclined portion and the second parallel portion, and The included angle of the first portion 314 is ⁇ ;
  • a light emitting layer 317 is formed on the anode layer, and the light emitting layer 317 includes at least two light emitting units, and each of the light emitting units is located in the anode;
  • the cathode layer 318 is formed on the light-emitting layer 317.
  • the invention provides a display panel and a manufacturing method thereof.
  • the invention completes the preparation of a flat layer and a pixel definition layer, or a flat layer, a pixel definition layer, and a spacer through a photomask.
  • the light emitted by the light-emitting unit is reflected and concentrated by the anode, which reduces the risk of color mixing in the display panel and enhances the light intensity on the light emitting side.

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Abstract

提出了一种显示面板及其制作方法，通过一道光罩完成平坦层（111）以及像素定义层（112），或平坦层（111）、像素定义层（112）以及隔垫物（113）的制备，将发光单元设置于阳极内，使得发光单元发出的光被阳极反射而聚光，降低了显示面板发生混色的风险，增强了出光侧的光强。

Description

显示面板及其制作方法 技术领域
本发明涉及显示领域，特别涉及一种显示面板及其制作方法。
 背景技术
在平板显示技术中，有机发光二极管（Organic Light-Emitting Diode，OLED）显示器具有轻薄、主动发光、响应速度快、可视角大、色域宽、亮度高和功耗低等众多优点，逐渐成为继液晶显示器后的第三代显示技术。相对于LCD(Liquid crystal displays，液晶显示器)，OLED具有更省电，更薄，且视角宽的优势，这是LCD无法比拟的。目前人们对显示的细腻程度即分辨率要求越来越高，但生产高质量、高分辨率的OLED显示屏仍然面临着许多挑战。
OLED显示装置按照驱动方式可以分为无源矩阵型(Passive Matrix OLED，PMOLED)和有源矩阵型(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管(Thin Film Transistor，TFT)矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
现有的AMOLED显示面板多采用顶发光结构，当阳极和阴极之间加入一定电压时，发光层开始发光，光源发出的光经过阳极后反射后，通过谐振腔的作用，增加了阴极端的出射光强，但同时由于一部分光散射到相邻像素，形成混色。
 技术问题
本发明提供一种显示面板及其制作方法，以解决在AMOLED显示面板出现混色的技术问题。
 技术解决方案
本发明提供一种显示面板的制作方法，其中，所述显示面板的制作方法包括步骤：
S10、提供一基板；
S20、在所述基板上形成薄膜晶体管层；
S30、在所述薄膜晶体管层上依次形成平坦层以及像素定义层、或所述平坦层、所述像素定义层以及所述隔垫物，并采用一多段式穿透率的掩膜版对所述平坦层以及所述像素定义层、或所述平坦层、所述像素定义层以及所述隔垫物进行曝光以及显影；
S40、在所述平坦层以及所述像素定义层上形成阳极层、发光层以及阴极层，
其中，所述阳极层覆盖部分所述平坦层以及部分所述像素定义层，所述阳极层通过过孔与源漏极连接。
在本发明的显示面板中，所述所述阳极层包括至少两个阳极，所述阳极与所述显示面板的像素单元一一对应；
其中，所述阳极包括与所述平坦层接触的第一部分、以及与所述像素定义层接触的第二部分。
在本发明的显示面板中，所述第一部分与所述第二部分的夹角为θ，0°＜θ＜90°。
在本发明的显示面板中，所述阳极位于与相邻俩所述隔垫物之间。
在本发明的显示面板中，所述平坦层、所述像素定义层以及所述隔垫物由光阻材料制成。
本发明提出了一种显示面板，其包括：
基板；
薄膜晶体管层，形成于所述基板上；
平坦层，形成于所述薄膜晶体管层上；
像素定义层，形成于所述平坦层上；
发光器件层，形成于相邻俩所述像素定义层之间，包括：
阳极层，形成于所述像素定义层上，所述阳极层覆盖部分所述平坦层以及部分所述像素定义层，所述阳极层通过过孔与源漏极连接；
其中，所述所述阳极层包括至少两个阳极，所述阳极与所述显示面板的像素单元一一对应；所述阳极包括与所述平坦层接触的第一部分、以及与所述像素定义层接触的第二部分。
在本发明的显示面板中，所述第一部分与所述第二部分的夹角为θ，0°＜θ＜90°。
在本发明的显示面板中，所述显示面板还包括隔垫物，形成于所述像素定义层上；
其中，所述阳极位于相邻俩所述隔垫物之间。
在本发明的显示面板中，所述发光器件层还包括形成于所述阳极层上的发光层、以及形成于所述发光层上的阴极层；
其中，所述发光层包括多个发光单元，每一所述发光单元位于所述阳极内。
本发明还提出了一种显示面板，其包括：
基板；
薄膜晶体管层，形成于所述基板上；
平坦层，形成于所述薄膜晶体管层上；
像素定义层，形成于所述平坦层上；
发光器件层，形成于相邻俩所述像素定义层之间，包括：
阳极层，形成于所述像素定义层上，所述阳极层覆盖部分所述平坦层以及部分所述像素定义层，所述阳极层通过过孔与源漏极连接。
在本发明的显示面板中，所述显示面板还包括隔垫物，形成于所述像素定义层上；
其中，所述阳极位于相邻俩所述隔垫物之间。
在本发明的显示面板中，所述发光器件层还包括形成于所述阳极层上的发光层、以及形成于所述发光层上的阴极层；
其中，所述发光层包括多个发光单元，每一所述发光单元位于所述阳极内。
 有益效果
本发明通过一道光罩完成平坦层以及像素定义层，或平坦层、像素定义层以及隔垫物的制备，将发光单元设置于阳极内，使得所述发光单元发出的光被所述阳极反射而聚光，降低了显示面板发生混色的风险，增强了出光侧的光强。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例一一种显示面板制作方法的步骤图；
图2A~2J为本发明实施例一一种显示面板的工艺流程图；
图3为本发明实施例二一种显示面板的膜层结构图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
图1所示为本发明一种显示面板制作方法的步骤图，其中，所述显示面板的制作方法包括步骤：
S10、提供一基板；
提供一基板101，所述基板101的原材料可以为玻璃基板、石英基板、树脂基板等中的一种。
S20、在所述基板上形成薄膜晶体管层；
本步骤主要包括在所述基板101上依次形成缓冲层102、有源层103、第一绝缘层104、第一栅极105、第二绝缘层106、第二栅极107、第三绝缘层108以及源漏极110；
如图2A所示，本实施例中，首先在所述缓冲层102上形成一有源层薄膜，所述有源层薄膜由多晶硅构成；首先，对所述有源层薄膜使用第一光罩制程工艺，在所述有源层薄膜上形成第一光阻层（未画出），采用掩模板（未画出）曝光，经显影以及第一蚀刻的构图工艺处理后，使所述有源层薄膜形成如图2B所示的有源层103，并剥离所述第一光阻层；
如图2B所示，所述第一绝缘层104，形成于所述有源层103上；本实施例中，所述第一绝缘层104为间绝缘层，所述间绝缘层将所述有源层103覆盖，所述间绝缘层主要用于将所述有源层103与其他金属层隔离；
如图2B所示，在所述第一绝缘层104上形成第一金属层，所述第一金属层的金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物；
对所述第一金属层使用第二光罩制程工艺，在所述第一金属层上形成第二光阻层，采用掩模板（未画出）曝光，经显影以及第二蚀刻的构图工艺处理后，使所述第一金属层形成如图2B所示的所述第一栅极105，并剥离所述第二光阻层；
如图2B所示，对所述有源层103进行离子注入，形成掺杂区；本实施例中，形成所述掺杂区的方法不限于实施例的所述方法；
如图2C所示，所述第二绝缘层106为第一栅绝缘层，所述第二栅绝缘层将所述有源层103覆盖，所述第一栅绝缘层主要用于将所述第一栅极105和第二栅极107隔离；优选的，所述第二绝缘层106的厚度为50~200nm；优选的，所述第一栅绝缘层的材料通常为氮化硅，也可以使用氧化硅和氮氧化硅等；
如图2C所示，所述第二栅极107的金属材料和所述第一栅极105的金属材料相同，通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物；本实施例中，所述第二栅极107的金属材料优选为钼，所述第二栅极107的厚度为150~250nm；
此步骤对形成第二栅极107的金属层采用第三光罩制程工艺，在该金属层上形成第三光阻层，采用掩模板（未画出）曝光，经显影以及第三蚀刻的构图工艺处理后，使该金属层形成所述阵列基板的第二栅极107,如图2D所示，在所述第二栅极107上形成第三绝缘层108；
如图2E所示，在所述第三绝缘层上形成第一过孔109；
如图2F所示，在所述第三绝缘层108上形成所述源漏极110；所述源漏极110的金属材料和所述第一栅极105及所述第二栅极107的材料可以相同，通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物；本实施例中，所述源漏极110的金属材料优选为钛铝钛，所述源漏极110的厚度为400~600nm；
对形成所述源漏极110的金属层采用第四光罩制程工艺，在该金属层上形成第四光阻层，采用掩模板（未画出）曝光，经显影以及第四蚀刻的构图工艺处理后，使该金属层形成所述源漏极110；
另外，所述源漏极110通过第一过孔109与所述掺杂区连接。
S30、在所述薄膜晶体管层上依次形成平坦层以及像素定义层、或所述平坦层、所述像素定义层以及所述隔垫物，并采用一多段式穿透率的掩膜版对所述平坦层以及所述像素定义层、或所述平坦层、所述像素定义层以及所述隔垫物进行曝光以及显影；
本步骤中，首先在所述源漏极110上依次形成平坦层111以及像素定义层112、或所述平坦层111、所述像素定义层112以及所述隔垫物113，并采用一多段式穿透率的掩膜版对所述平坦层111以及所述像素定义层112、或所述平坦层111、所述像素定义层112以及所述隔垫物113进行曝光以及显影，以形成如图2H所示的形状；
本实施例中，所述平坦层111、所述像素定义层112以及所述隔垫物113均为光阻材料，因此，利用光阻的特性采用一道光罩形成该形状；其中，在所述平坦层111上还形成有第二过孔114。
S40、在所述平坦层以及所述像素定义层上形成阳极层、发光层以及阴极层；
本步骤中，首先在所述像素定义层112以及所述平坦层111上形成一阳极层，所述阳极层覆盖部分所述平坦层111以及部分所述像素定义层112，所述阳极层通过第二过孔114与源漏极110连接；
所述所述阳极层包括至少两个阳极，所述阳极与所述显示面板的像素单元一一对应，其中，所述阳极位于相邻俩所述隔垫物113之间；
在本实施例中，所述阳极包括与所述平坦层接触的第一部分114、以及与所述像素定义层接触的第二部分115，所述第一部分114与所述第二部分115的夹角为θ，0°＜θ＜90°。
如图2I所示，所述第二部分115包括第二平行部分与第二倾斜部分，所述第二平行部分与所述基板101平行，所述第二倾斜部分与所述第二平行部分以及所述第一部分114的夹角为θ；
如图2J所示，所述阳极层上还形成有发光层117以及形成于所述发光层117上的阴极层118；其中，所述发光层117包括至少两个发光单元，每一所述发光单元位于所述阳极内，即每一所述发光单元被所述阳极和所述阴极层118所包裹。
图3所示为本发明一种显示面板的膜层结构图，其中，所述显示面板包括基板301、薄膜晶体管层、平坦层311、像素定义层312以及发光器件层；
所述基板301的原材料可以为玻璃基板、石英基板、树脂基板等中的一种。
所述薄膜晶体管层包括缓冲层302、有源层303、第一绝缘层304、第一栅极305、第二绝缘层306、第二栅极307、第三绝缘层308、源漏极310；
所述缓冲层302形成于所述基板301上，主要用于缓冲膜层质结构之间的压力，并且还可以具有一定阻水氧的功能；
所述有源层303形成于所述缓冲层上，所述有源层303包括经离子掺杂的掺杂区；
所述第一绝缘层304形成于所述有源层303上；本实施例中，所述第一绝缘层304为间绝缘层，所述间绝缘层将所述有源层303覆盖，所述间绝缘层用于将所述有源层303与其他金属层隔离；
所述第一栅极305形成于所述第一绝缘层304上，所述第一栅极305306的金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物；
第二绝缘层306，形成于所述第一栅极305上；本实施例中，所述第二绝缘层306为第一栅绝缘层，所述第二栅绝缘层将所述有源层303覆盖，所述第一栅绝缘层主要用于将所述第一栅极305和第二栅极307隔离；优选的，所述第二绝缘层306的厚度为50~200nm，所述第一栅绝缘层的材料通常为氮化硅，也可以使用氧化硅和氮氧化硅等；
所述第二栅极307形成于所述第二绝缘层306上，所述第二栅极307的材料和所述第一栅极305的相同，优选的，本实施例中，所述第一栅极305和所述第二栅极307的金属材料为钼；
另外，形成所述第二栅极307的金属层经图案化处理，形成面积大于所述第一栅极305的所述第二栅极307，即所述第一栅极305在所述第二栅极307上的正投影在所述第二栅极307内；
第三绝缘层308，形成于所述第二绝缘层306上；本实施例中，所述第三绝缘层308为第二栅绝缘层，所述第三栅绝缘层将所述第二栅极307覆盖，所述第二栅绝缘层主要用于将所述第二栅极307和源漏极310隔离；优选的，所述第二绝缘层306的厚度为50~200nm；其中，所述第二栅绝缘层的材料和所述第一栅绝缘层的材料相同；
源漏极310，形成于所述第三绝缘层308上，所述源漏极310的金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金等金属，也可以使用上述几种金属材料的组合物；优选的，本实施例中，所述源漏极310的金属材料为钛铝合金；所述源漏极310通过所述第一过孔309与所述掺杂区连接。
所述平坦层311、所述像素定义层312以及所述隔垫物313形成于所述源漏极310上，所述平坦层311、所述像素定义层312以及所述隔垫物313为光阻材料，因此，利用光阻的特性可以采用一道光罩形成该形状。
所述发光器件层形成于所述平坦层311上，并且形成于相邻俩所述像素定义层312之间，所述发光器件层包括：
阳极层，形成于所述像素定义层312以及所述平坦层311上，所述阳极层通过第二过孔314与所述源漏极310连接；本实施例中，所述所述阳极层包括至少两个阳极，所述阳极与所述显示面板的像素单元一一对应，其中，所述阳极位于相邻俩所述隔垫物313之间；
在本实施例中，所述阳极包括与所述平坦层接触的第一部分314、以及与所述像素定义层接触的第二部分315，所述第一部分314与所述第二部分315的夹角为θ，0°＜θ＜90°；
如图2I所示，所述第二部分315包括第二平行部分与第二倾斜部分，所述第二平行部分与所述基板301平行，所述第二倾斜部分与所述第二平行部分以及所述第一部分314的夹角为θ；
发光层317，形成于所述阳极层上，所述发光层317包括至少两个发光单元，每一所述发光单元位于所述阳极内；
阴极层318，形成于所述发光层317上。
本发明提出了一种显示面板及其制作方法，本发明通过一道光罩完成平坦层以及像素定义层，或平坦层、像素定义层以及隔垫物的制备，将发光单元设置于阳极内，使得所述发光单元发出的光被所述阳极反射而聚光，降低了显示面板发生混色的风险，增强了出光侧的光强。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种显示面板的制作方法，其中，包括步骤：
    S10、提供一基板；
    S20、在所述基板上形成薄膜晶体管层；
    S30、在所述薄膜晶体管层上依次形成平坦层以及像素定义层、或所述平坦层、所述像素定义层以及所述隔垫物，并采用一多段式穿透率的掩膜版对所述平坦层以及所述像素定义层、或所述平坦层、所述像素定义层以及所述隔垫物进行曝光以及显影；
    S40、在所述平坦层以及所述像素定义层上形成阳极层、发光层以及阴极层，
    其中，所述阳极层覆盖部分所述平坦层以及部分所述像素定义层，所述阳极层通过过孔与源漏极连接。
  2. 根据权利要求1所述的制作方法，其中，所述所述阳极层包括至少两个阳极，所述阳极与所述显示面板的像素单元一一对应；
    其中，所述阳极包括与所述平坦层接触的第一部分、以及与所述像素定义层接触的第二部分。
  3. 根据权利要求2所述的制作方法，其中，所述第一部分与所述第二部分的夹角为θ，0°＜θ＜90°。
  4. 根据权利要求1所述的制作方法，其中，所述阳极位于与相邻俩所述隔垫物之间。
  5. 根据权利要求1所述的制作方法，其中，所述平坦层、所述像素定义层以及所述隔垫物由光阻材料制成。
  6. 一种显示面板，其包括：
    基板；
    薄膜晶体管层，形成于所述基板上；
    平坦层，形成于所述薄膜晶体管层上；
    像素定义层，形成于所述平坦层上；
    发光器件层，形成于相邻俩所述像素定义层之间，包括：
    阳极层，形成于所述像素定义层上，所述阳极层覆盖部分所述平坦层以及部分所述像素定义层，所述阳极层通过过孔与源漏极连接；
    其中，所述所述阳极层包括至少两个阳极，所述阳极与所述显示面板的像素单元一一对应，所述阳极包括与所述平坦层接触的第一部分、以及与所述像素定义层接触的第二部分。
  7. 根据权利要求6述的显示面板，其中，所述第一部分与所述第二部分的夹角为θ，0°＜θ＜90°。
  8. 根据权利要求6述的显示面板，其中，所述显示面板还包括隔垫物，形成于所述像素定义层上；
    其中，所述阳极位于相邻俩所述隔垫物之间。
  9. 根据权利要求6述的显示面板，其中，所述发光器件层还包括形成于所述阳极层上的发光层、以及形成于所述发光层上的阴极层；
    其中，所述发光层包括多个发光单元，每一所述发光单元位于所述阳极内。
  10. 一种显示面板，其包括：
    基板；
    薄膜晶体管层，形成于所述基板上；
    平坦层，形成于所述薄膜晶体管层上；
    像素定义层，形成于所述平坦层上；
    发光器件层，形成于相邻俩所述像素定义层之间，包括：
    阳极层，形成于所述像素定义层上，所述阳极层覆盖部分所述平坦层以及部分所述像素定义层，所述阳极层通过过孔与源漏极连接。
  11. 根据权利要求10述的显示面板，其中，所述显示面板还包括隔垫物，形成于所述像素定义层上；
    其中，所述阳极位于相邻俩所述隔垫物之间。
  12. 根据权利要求10述的显示面板，其中，所述发光器件层还包括形成于所述阳极层上的发光层、以及形成于所述发光层上的阴极层；
    其中，所述发光层包括多个发光单元，每一所述发光单元位于所述阳极内。
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