Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67242—Apparatus for monitoring, sorting or marking
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
  • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
  • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
  • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
  • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
  • G03F7/70441—Optical proximity correction [OPC]
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
  • G03F7/70605—Workpiece metrology
  • G03F7/70616—Monitoring the printed patterns
  • G03F7/7065—Defects, e.g. optical inspection of patterned layer for defects
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/10—Measuring as part of the manufacturing process
  • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
  • H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/0203—Particular design considerations for integrated circuits
  • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Definitions

• the processor cm be further configured to receive the printable layer layout and die non-printed layer layout for the wafer and to generate the hybrid design layout by incorporating at least a portion of the non-printable layer layout with die printable layer layout
• the non-printed layer can include optical proximity correction or sub-resolution assist features.
• the non-printed layer also can include an artificial layer that is generated by die processor.
• a non-transitory computer-readable storage medium is provided in a third embodiment.
• the non-transitory computer-readable storage medium comprises a hybrid design data structure.
• the hybrid design data structure inc ludes a printable layer and a non-printed layer.
• FIG. 3 is an exemplary diagram illustrating SRAF
• the non-printed layer can include OPC, SRAF, an artificial layer that is generated by the processor, a static random-access memory (SRAM) marker layer, an epitaxy marker layer, an implant layer that can support inspection, or an additional layer created to support inspection.
• one or more artificial layers can be Used fot alignment and binning purposes.
• the artificial layer can be generated or an existing non-printed layer can be modified.
• Implementation ibr each desist can be based on set up rules, which can be an algorithm.
• Polygons in the artificial layer can be generated independently or can be derived from existing polygons.
• an SRAM marker layer can be derived from existing polygons. When they repeat in a certain order that is set up as a different layer.
• the hybrid design layout may not include OPG features because die file size may be too large, but may include scattering bars that do not print on a wafer. Without OPC features, the file itself may not be production-worthy.
• use of the hybrid design layout can enable new grouping that was not possible using the traditional pre-OPC design approach because an algorithm like DBG can be used with the hybrid design layout to provide a new grouping scheme.
• use of a hybrid design layout can separate SRAF-related issues from other patterning defects.
• sensitive data from a semiconductor manufacturer is not needed. Thus, if a semiconductor manufacturer does not want to provide information or does not have the requested information, then the inspection can continue.
• processor 202 and electronic data storage unit 203 are illustrated, more than one processor 202 and/or more than one electronic data storage unit 203 can be included.
• Each processor 202 may be in electronic communication with one or more of the electronic data storage units 203.
• the one or more processors 202 are communicatively coupled.
• the one or more processors 202 may receive readings received at the beam source 201 and store the reading in the electronic data storage unit 203 of the processor 202.
• the processor 202 and/or electronic data storage unit 203 may be part of the wafer inspection tool 200 itself or may be separate from die wafer inspection tool 200 (e.g., a standalone control unit or in a centralized quality control unit).
• the processor 202 may be coupled to the components of the wafer inspection tool

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Geometry (AREA)
• Evolutionary Computation (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Analysing Materials By The Use Of Radiation (AREA)

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• 2018
  • 2018-11-26 US US16/200,060 patent/US10796065B2/en active Active
• 2019
  • 2019-06-12 KR KR1020217001725A patent/KR102471846B1/ko active IP Right Grant
  • 2019-06-12 CN CN201980037056.5A patent/CN112219271B/zh active Active
  • 2019-06-12 WO PCT/US2019/036640 patent/WO2019245806A1/en active Application Filing
  • 2019-06-21 TW TW108121628A patent/TWI769381B/zh active

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