WO2019242761A1 - 晶体硅太阳能电池及其制备方法、光伏组件 - Google Patents

晶体硅太阳能电池及其制备方法、光伏组件 Download PDF

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WO2019242761A1
WO2019242761A1 PCT/CN2019/092374 CN2019092374W WO2019242761A1 WO 2019242761 A1 WO2019242761 A1 WO 2019242761A1 CN 2019092374 W CN2019092374 W CN 2019092374W WO 2019242761 A1 WO2019242761 A1 WO 2019242761A1
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layer
solar cell
crystalline silicon
gallium oxide
type
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PCT/CN2019/092374
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English (en)
French (fr)
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陈孝业
薛文娟
蒋秀林
尹海鹏
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晶澳太阳能有限公司
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Priority claimed from CN201810649226.2A external-priority patent/CN109065639A/zh
Priority claimed from CN201810649228.1A external-priority patent/CN108767022A/zh
Priority claimed from CN201811223037.5A external-priority patent/CN109494261A/zh
Application filed by 晶澳太阳能有限公司 filed Critical 晶澳太阳能有限公司
Priority to AU2019290813A priority Critical patent/AU2019290813B2/en
Priority to EP19822415.6A priority patent/EP3783668B1/en
Priority to US17/055,370 priority patent/US11444212B2/en
Publication of WO2019242761A1 publication Critical patent/WO2019242761A1/zh

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    • H—ELECTRICITY
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    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H01L31/03682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic Table
    • H01L31/03685—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic Table including microcrystalline silicon, uc-Si
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H—ELECTRICITY
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/545—Microcrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the present disclosure relates to the technical field of solar cells, and in particular, to a crystalline silicon solar cell, a preparation method thereof, and a photovoltaic module.
  • Photovoltaic power generation which directly converts solar energy into electricity, is a clean, sustainable, and relatively cost-effective way to generate electricity.
  • the crystalline silicon solar cell is an important part of the photovoltaic power generation system.
  • the photoelectric conversion efficiency of the crystalline silicon solar cell has an important influence on the output power and cost of electricity of the photovoltaic power generation.
  • a crystalline silicon solar cell mainly includes a front electrode, a front passivation layer, an emitter, a crystalline silicon substrate, a back passivation layer, and a back electrode disposed in this order.
  • the crystalline silicon substrate may be a P-type crystalline silicon substrate or an N-type crystalline silicon substrate according to a conductivity type classification.
  • the material of the front passivation layer and the back passivation layer is usually silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, and the like.
  • An embodiment of the present disclosure provides a crystalline silicon solar cell capable of solving the above problem of high minority carrier recombination rate in a crystalline silicon solar cell and a preparation method thereof.
  • An embodiment of the present disclosure also provides a photovoltaic module based on the crystalline silicon solar cell , And the application of gallium oxide as a passivation or passivation structure in crystalline silicon solar cells.
  • an embodiment of the present disclosure provides a crystalline silicon solar cell including a gallium oxide layer in direct contact with a P-type silicon layer in the crystalline silicon solar cell.
  • the crystalline silicon solar cell includes: a crystalline silicon substrate having a conductivity type of N type, and an emitter layer provided on a surface of the crystalline silicon substrate and having a conductivity type of P type; the gallium oxide layer It is disposed on the emitter layer and is in direct contact with the emitter layer.
  • the crystalline silicon solar cell further includes: a first cover layer provided on the gallium oxide layer, a first electrode provided on the first cover layer and in contact with the emitter layer, A surface field layer disposed on a surface of the crystalline silicon substrate opposite to the emitter layer and having an N-type conductivity, a second cover layer disposed on the surface field layer, and A second electrode on the two cover layers and in contact with the surface field layer.
  • the crystalline silicon solar cell further includes: a first cover layer provided on the gallium oxide layer, a first electrode provided on the first cover layer and in contact with the emitter layer, A tunneling passivation layer disposed on a surface of the crystalline silicon substrate opposite to the emitter layer is provided on the tunneling passivation layer, and a doped silicon layer having an N-type conductivity is disposed on the The second cover layer on the doped silicon layer, and a second electrode disposed on the second cover layer and in contact with the doped silicon layer.
  • the doped silicon layer covers a partial region of the tunneling passivation layer, and the second capping layer is also provided on a region of the tunneling passivation layer where the doped silicon layer is not provided.
  • the thickness of the gallium oxide layer is 1 nm to 120 nm.
  • the thickness of the gallium oxide layer is 10 nm to 60 nm.
  • the thickness of the gallium oxide layer is 20 nm to 40 nm.
  • the crystalline silicon solar cell includes: a crystalline silicon substrate having a conductivity type of P type; the gallium oxide layer is disposed on one surface of the crystalline silicon substrate and is in direct contact with the crystalline silicon substrate.
  • the crystalline silicon solar cell further includes: a third cover layer provided on the gallium oxide layer, a third electrode provided on the third cover layer and in contact with the crystalline silicon substrate, An emitter layer disposed on a surface of the crystalline silicon substrate opposite to the gallium oxide layer and having an N-type conductivity; a fourth cover layer disposed on the emitter layer; and disposed on the first cover layer A fourth electrode on the four covering layers and in contact with the emitter layer.
  • the crystalline silicon solar cell further includes a third electrode provided on the gallium oxide layer and a third electrode provided on the third cover layer and in contact with the crystalline silicon substrate.
  • a tunneling passivation layer disposed on the emitter layer is disposed on the tunneling passivation layer.
  • a doped silicon layer with a conductivity type of N-type on a siliconized layer, a fourth cover layer disposed on the doped silicon layer, and a fourth cover layer disposed on the fourth cover layer and in contact with the doped silicon A fourth electrode in contact with the layer;
  • the doped silicon layer covers a partial region of the tunneling passivation layer, and the fourth capping layer is also provided on a region of the tunneling passivation layer where the doped silicon layer is not provided.
  • via holes are correspondingly provided on the gallium oxide layer and the third cover layer; a region corresponding to the via hole on the surface of the crystalline silicon substrate is formed with a P-type surface field layer.
  • the third electrode includes a first portion and a second portion, the first portion is linear, the second portion is disposed on a region of the third cover layer outside the first portion, and the The second part is in contact with the first part; the second part is in contact with the crystalline silicon substrate through the via hole, and forms the surface field layer on the surface of the crystalline silicon substrate corresponding to the via hole .
  • the thickness of the gallium oxide layer is 1 nm to 1000 nm.
  • the thickness of the gallium oxide layer is 2 nm to 150 nm.
  • the thickness of the gallium oxide layer is 5 nm to 60 nm.
  • the crystalline silicon solar cell includes a crystalline silicon substrate having a conductivity type of P type, a first tunneling passivation layer disposed on a surface of one side of the crystalline silicon substrate, and a first tunneling passivation layer.
  • a first doped silicon layer having a conductivity type of P type on a chemical layer a gallium oxide layer disposed on the first doped silicon layer, a fifth capping layer disposed on the gallium oxide layer, and, A fifth electrode disposed on the fifth cover layer and in contact with the first doped silicon layer.
  • the first doped silicon layer covers a local area of the first tunneling passivation layer, and the first tunneling passivation layer is also provided on a region where the first doped silicon layer is not provided.
  • the crystalline silicon solar cell further includes: an emitter layer disposed on a surface of the crystalline silicon substrate opposite to the first tunneling passivation layer and having an N-type conductivity, disposed on the surface A sixth covering layer on the emitter layer, and a sixth electrode disposed on the sixth covering layer and in contact with the emitter layer.
  • the crystalline silicon solar cell further includes: an emitter layer disposed on a surface of the crystalline silicon substrate opposite to the first tunneling passivation layer and having an N-type conductivity, disposed on the surface A second tunneling passivation layer on the emitter layer is provided on the second tunneling passivation layer, and a second doped silicon layer of conductivity type N is provided on the second doped silicon layer. A sixth covering layer thereon, and a sixth electrode disposed on the sixth covering layer and in contact with the second doped silicon layer.
  • the second doped silicon layer covers a local area of the second tunneling passivation layer, and the second tunneling passivation layer is also provided on an area where the second doped silicon layer is not provided. There is the sixth covering layer.
  • the thickness of the gallium oxide layer is 10 nm to 90 nm.
  • an embodiment of the present disclosure provides a photovoltaic module.
  • the photovoltaic module includes a cover plate, a first encapsulating film, a battery string, a second encapsulating film, and a back plate.
  • a solar cell which is the aforementioned crystalline silicon solar cell.
  • an embodiment of the present disclosure provides a method for preparing a crystalline silicon solar cell.
  • the method includes: forming a gallium oxide layer in direct contact with a P-type silicon layer in the crystalline silicon solar cell.
  • embodiments of the present disclosure provide an application of gallium oxide as a passivation structure or structure in a crystalline silicon solar cell.
  • the gallium oxide is in direct contact with a P-type silicon layer of the crystalline silicon solar cell.
  • the negative charge carried by the gallium oxide layer is used to chemically surface the P-type silicon layer.
  • Passivation and field passivation reduce the number of dangling bonds and minority carriers of the silicon atoms on the surface of the P-type silicon layer, thereby reducing the rate of minority carrier recombination at the surface of the P-type silicon layer, increasing the voltage and current of the solar cell Improve the photoelectric conversion efficiency of solar cells, thereby increasing the output power of photovoltaic modules, reducing the cost of electricity, and improving the cost-effectiveness of photovoltaic power generation.
  • the gallium oxide layer also has a wide band gap and a suitable optical refractive index, which is also conducive to improving the performance of crystalline silicon solar cells.
  • FIG. 1 is a schematic structural diagram of a crystalline silicon solar cell according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a crystalline silicon solar cell including a crystalline silicon substrate having a conductivity type of N type according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another crystalline silicon solar cell including a crystalline silicon substrate having a conductivity type of N type according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a crystalline silicon solar cell including a crystalline silicon substrate having a conductivity type of P type according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of another crystalline silicon solar cell including a crystalline silicon substrate having a conductivity type of P type according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of an all-aluminum back-field back electrode
  • FIG. 7 is a schematic structural diagram of a back electrode of a partial aluminum back field
  • FIG. 8 is a schematic structural diagram of still another crystalline silicon solar cell including a crystalline silicon substrate having a conductivity type of P type according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of still another crystalline silicon solar cell including a crystalline silicon substrate having a conductivity type of P type according to an embodiment of the present disclosure
  • FIG. 10 is a schematic structural diagram of still another crystalline silicon solar cell including a crystalline silicon substrate having a conductivity type of P type according to an embodiment of the present disclosure.
  • Improving the photoelectric conversion efficiency of crystalline silicon solar cells is an effective way to increase the output power of photovoltaic power generation and reduce the cost of electricity.
  • one of the important factors limiting the photoelectric conversion efficiency of single-crystal silicon solar cells is the composite annihilation of minority carriers in solar cells.
  • the composite annihilation of minority carriers will cause the loss of voltage and current of the solar cell, thereby reducing the photoelectric conversion efficiency of the cell.
  • There are a large number of unsaturated dangling bonds on the surface of crystalline silicon which is a serious recombination center. Setting a passivation layer on the surface of the silicon wafer to passivate the surface of the silicon wafer can reduce the recombination probability of minority carriers on the surface of the silicon wafer, which is beneficial to improving the photoelectric conversion efficiency of the solar cell.
  • embodiments of the present disclosure provide a crystalline silicon solar cell that uses gallium oxide (GaO x ) to passivate the surface of a P-type silicon layer and a method for preparing the same, and also provides a crystalline silicon solar cell based on the crystalline silicon solar cell.
  • GaO x gallium oxide
  • Photovoltaic modules and gallium oxide as passivation or passivation structure in crystalline silicon solar cells.
  • FIG. 1 illustrates a structure of a crystalline silicon solar cell provided by an embodiment of the present disclosure.
  • the crystalline silicon solar cell provided by an embodiment of the present disclosure includes a direct contact with a P-type silicon layer in the crystalline silicon solar cell.
  • Gallium oxide layer X is a direct contact with a P-type silicon layer in the crystalline silicon solar cell.
  • the gallium oxide layer X has a negative charge, which can chemically and field passivate the surface of the P-type silicon layer. Therefore, setting a gallium oxide layer X in direct contact with the P-type silicon layer on the surface of the P-type silicon layer can effectively reduce P
  • the number of dangling bonds and minority carriers of the silicon atoms on the surface of the silicon-type silicon layer reduces the recombination rate of minority carriers at the surface of the P-type silicon layer, increases the voltage and current of the solar cell, and improves the photoelectric conversion efficiency of the solar cell. Improve the output power of photovoltaic modules, reduce the cost of electricity, and improve the cost-effectiveness of photovoltaic power generation.
  • the gallium oxide layer X also has a wide band gap and a suitable optical refractive index, which is also conducive to improving the performance of the crystalline silicon solar cell.
  • the embodiment of the present disclosure also provides a method for preparing the above-mentioned crystalline silicon solar cell, and specifically includes a step of forming a gallium oxide layer X in direct contact with a P-type silicon layer in the crystalline silicon solar cell.
  • the positions of the gallium oxide layer X and the thickness of the gallium oxide layer X are also different.
  • the structure of the crystalline silicon solar cell provided by the embodiments of the present disclosure and the method for preparing the same will be further described in combination with a specific crystalline silicon solar cell structure.
  • FIG. 2 illustrates a structure of a crystalline silicon solar cell including an N-type crystalline silicon substrate.
  • the crystalline silicon solar cell provided in this embodiment includes:
  • N-type crystalline silicon substrate 1 N-type crystalline silicon substrate 1
  • An emitter layer 2 disposed on a surface of the crystalline silicon substrate 1 and having a conductivity type of P type,
  • a first electrode 51 provided on the first cover layer 41 and in contact with the emitter layer 2,
  • a surface field layer 3 disposed on the surface of the crystalline silicon substrate 1 opposite to the emitter layer 2 and having an N-type conductivity
  • a second electrode 52 is provided on the second cover layer 42 and is in contact with the surface field layer 3.
  • the P-type silicon layer is an emitter layer 2 having a conductivity type of P-type and disposed on the surface of the N-type crystalline silicon substrate 1 side. Therefore, in this embodiment, A gallium oxide layer X is provided on the emitter layer 2.
  • the N-type crystalline silicon substrate 1 may be single crystal silicon or polycrystalline silicon, and the resistivity may be 0.1 ⁇ ⁇ cm to 10 ⁇ ⁇ cm (for example, 0.1 ⁇ ⁇ cm, 0.2 ⁇ ⁇ cm, 0.3 ⁇ ⁇ cm, 0.4 ⁇ ⁇ cm, 0.5 ⁇ ⁇ cm, 0.6 ⁇ ⁇ cm, 0.7 ⁇ ⁇ cm, 0.8 ⁇ ⁇ cm, 0.9 ⁇ ⁇ cm, 1 ⁇ ⁇ cm, 2 ⁇ ⁇ cm, 3 ⁇ ⁇ cm, 4 ⁇ ⁇ cm, 5 ⁇ ⁇ cm, 6 ⁇ ⁇ cm, 7 ⁇ ⁇ cm, 8 ⁇ ⁇ cm, 9 ⁇ ⁇ cm, 10 ⁇ ⁇ cm, etc.).
  • the emitter layer 2 may be located on the front side (that is, the light receiving surface) of the crystalline silicon substrate 1 or on the back side (that is, the backlight surface) of the crystalline silicon substrate 1. Accordingly, the surface field layer 3 may be located on the back of the crystalline silicon substrate 1, or It may be on the front side of the crystalline silicon substrate 1.
  • the emitter layer 2 can be obtained by doping the N-type crystalline silicon substrate 1 with a P-type doping element (usually a Group III element, including but not limited to boron), and its block resistance value can be 40 ⁇ / ⁇ ⁇ 200 ⁇ / ⁇ (e.g.
  • the surface field layer 3 can be obtained by doping an N-type crystalline silicon substrate 1 with an N-type doping element (usually a Group V element, including but not limited to phosphorus), and its block resistance can be 20 ⁇ / ⁇ ⁇ 500 ⁇ / ⁇ , Such as 20 ⁇ / ⁇ , 30 ⁇ / ⁇ , 40 ⁇ / ⁇ , 50 ⁇ / ⁇ , 60 ⁇ / ⁇ , 70 ⁇ / ⁇ , 80 ⁇ / ⁇ , 90 ⁇ / ⁇ , 100 ⁇ / ⁇ , 150 ⁇ / ⁇ , 200 ⁇ / ⁇ , 250 ⁇ / ⁇ , 300 ⁇ / ⁇ , 350 ⁇ / ⁇ , 400 ⁇ / ⁇ , 450 ⁇ / ⁇ , 500 ⁇ / ⁇ and so on.
  • an N-type doping element usually a Group V element, including but not limited to phosphorus
  • the thickness of the gallium oxide layer X (that is, the size indicated by T1 in FIG. 2) may be 1 nm to 120 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 Nano, 7 nano, 8 nano, 9 nano, 10 nano, 15 nano, 20 nano, 25 nano, 30 nano, 35 nano, 40 nano, 45 nano, 50 nano, 55 nano, 60 nano, 65 nano, 70 nano, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, etc.
  • the thickness of the gallium oxide layer X may be 10 nm to 60 nm; more preferably, the thickness of the gallium oxide layer X may be 20 nm to 40 nm.
  • the first cover layer 41 may include at least one of a silicon nitride (SiN x ) layer, a silicon oxynitride (SiO x N y ) layer, a silicon oxide (SiO x ) layer, and a silicon carbide (SiC x ) layer. It is a single silicon nitride layer, a single silicon oxynitride layer, a single silicon oxide layer, or a single silicon carbide layer. It can also be two kinds of silicon nitride layer, silicon oxynitride layer, silicon oxide layer, and silicon carbide layer. Or two or more stacked settings.
  • the overall thickness of the first covering layer 41 (that is, the thickness indicated by T2 in FIG.
  • the thickness of each layer is not strictly required, and can be set as required, as long as the overall thickness meets the requirements.
  • the second cover layer 42 includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer. That is, the second cover layer 42 may be a separate silicon nitride layer or a separate silicon oxynitride layer.
  • the separate silicon oxide layer and the separate silicon carbide layer may also be two or more layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer.
  • the overall thickness of the second cover layer 42 (that is, the size indicated by T3 in FIG.
  • the second cover layer 42 may be 30 nm to 200 nm, such as 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 Nanometer, 70 nanometer, 75 nanometer, 80 nanometer, 85 nanometer, 90 nanometer, 95 nanometer, 100 nanometer, 105 nanometer, 110 nanometer, 115 nanometer, 120 nanometer, 125 nanometer, 130 nanometer, 135 nanometer.
  • the thickness of each layer is not strictly required, and can be set as required, as long as the overall thickness meets the requirements.
  • the first electrode 51 and the second electrode 52 may be metal electrodes (such as a silver electrode). Accordingly, the contact between the first electrode 51 and the emitter layer 2 is an ohmic contact, and the contact between the second electrode 52 and the surface field layer 3 is The contact is ohmic.
  • Both the first electrode 51 and the second electrode 52 can adopt electrodes of a gate line structure (including a main gate line and a sub-gate line), thereby achieving double-sided power generation.
  • the square resistance value of the region corresponding to the first electrode 51 of the emitter layer 2 may be greater than the square resistance value of other regions (ie, the selective emitter), and the square of the area corresponding to the second electrode 52 on the surface field layer 3
  • the resistance value can also be greater than the square resistance value (ie, selective surface field) in other regions, thereby improving the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • the method for preparing a crystalline silicon solar cell mainly includes cleaning and texturing the front surface of the crystalline silicon substrate 1, forming an emitter layer 2, flattening the back surface of the crystalline silicon substrate 1, forming a surface field layer 3, forming a gallium oxide layer X, forming The first cover layer 41 and the second cover layer 42, the steps of forming the first electrode 51 and the second electrode 52, and the like.
  • the crystalline silicon substrate 1 can be cleaned with a mixed aqueous solution of sodium hydroxide (NaOH) and hydrogen peroxide (H 2 O 2 ) to remove surface contaminants and damaged layers.
  • NaOH sodium hydroxide
  • H 2 O 2 hydrogen peroxide
  • the alkaline etching solution can be used for texturing, and the acidic etching solution can also be used for texturing.
  • the alkaline etching solution can be an aqueous sodium hydroxide solution.
  • the reflectance on the surface of the single crystal silicon wafer after texturing can be 10% to 18% (for example, 10%, 11%, 12%, 13%, 14%, 15%, 16 %, 17%, 18%, etc.), the reflectance of the surface of the polycrystalline silicon wafer may be 6% to 20% (for example, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14 %, 15%, 16%, 17%, 18%, 19%, 20%, etc.).
  • the emitter layer 2 may be formed by diffusion (such as furnace tube boron diffusion), deposition of a doped layer containing a doping source (such as borosilicate glass BSG) and annealing, or ion implantation (such as implantation of boron ions) and annealing.
  • a doping source such as borosilicate glass BSG
  • ion implantation such as implantation of boron ions
  • the back surface of the crystalline silicon substrate 1 can be leveled by a chemical solution to appropriately reduce the specific surface area of the back surface of the crystalline silicon substrate 1, and then the crystalline silicon substrate is washed with hydrofluoric acid (such as an aqueous solution of HF).
  • the chemical solution may be an alkali solution, including but not limited to a tetramethylammonium hydroxide (TMAH) solution, a sodium hydroxide (NaOH) solution, a potassium hydroxide (KOH), etc., and the concentration of the alkali solution may be adjusted as required; It can also be an acid solution, such as a mixed solution of nitric acid (HNO 3 ), hydrofluoric acid (HF) and sulfuric acid (H 2 SO 4 ). The concentration of each acid solution in the mixed solution and the ratio of each acid solution can also be determined according to Need to be adjusted.
  • TMAH tetramethylammonium hydroxide
  • NaOH sodium hydroxide
  • KOH potassium hydroxide
  • the surface field layer 3 can be formed by diffusion (such as furnace tube phosphorus diffusion), deposition of a doped layer containing a doping source (such as phosphosilicate glass PSG) and annealing, or ion implantation (such as phosphorus ion implantation) and annealing.
  • a doping source such as phosphosilicate glass PSG
  • ion implantation such as phosphorus ion implantation
  • the gallium oxide layer X can be formed by a single atomic layer deposition method (ALD), a plasma enhanced chemical vapor deposition method (PECVD), an atmospheric chemical vapor deposition method (APCVD) Or low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD). After the gallium oxide layer X is deposited, an annealing step may be performed.
  • ALD atomic layer deposition method
  • PECVD plasma enhanced chemical vapor deposition method
  • APCVD atmospheric chemical vapor deposition method
  • LPCVD low pressure chemical vapor deposition
  • the first cover layer 41 and the second cover layer 42 may also be formed by ALD, PECVD, APCVD, LPCVD, or the like. When the first cover layer 41 and the second cover layer 42 have the same composition, they can be formed simultaneously.
  • the first electrode 51 and the second electrode 52 can be formed by a method of screen-printing an electrode paste and quickly sintering at a high temperature.
  • the sintering temperature may be 600 ° C to 900 ° C (for example, 600 ° C, 650 ° C, 700 ° C, 750 ° C, 800 ° C, 850 ° C, 900 ° C, etc.), and the sintering time may be 10 seconds to 3 minutes, such as 10 seconds, 20 seconds, 30 seconds, 40 seconds, 60 seconds, 70 seconds, 80 seconds, 90 seconds, 100 seconds, 110 seconds, 120 seconds, 130 seconds, 140 seconds, 150 seconds, 160 seconds, 170 seconds, 180 seconds, etc.
  • FIG. 3 shows the structure of another crystalline silicon solar cell including an N-type crystalline silicon substrate.
  • the crystalline silicon solar cell provided in this embodiment is based on a tunnel oxidation passivated contact cell (TunnelOxidePassivatedContact TOP-Con) structure, including:
  • N-type crystalline silicon substrate 1 N-type crystalline silicon substrate 1
  • An emitter layer 2 disposed on a surface of the crystalline silicon substrate 1 and having a conductivity type of P type,
  • a first electrode 51 provided on the first cover layer 41 and in contact with the emitter layer 2,
  • a tunneling passivation layer 6 provided on a surface of the crystalline silicon substrate 1 opposite to the emitter layer 2,
  • a second cover layer 42 provided on the doped silicon layer 7, and,
  • a second electrode 52 is provided on the second cover layer 42 and is in contact with the doped silicon layer 7.
  • the P-type silicon layer is also an P-type emitter layer 2 provided on the surface of the N-type crystalline silicon substrate 1 side. Therefore, in this embodiment, Similarly, the gallium oxide layer X is disposed on the emitter layer 2.
  • the resistivity of the crystalline silicon substrate 1, the sheet resistance value of the emitter layer 2, the thickness of the gallium oxide layer X, the composition and thickness of the first cover layer 41, and the thickness of the first electrode 51 and the second electrode 52 are not described herein again.
  • the doped silicon layer 7 may be a doped polysilicon layer or a doped amorphous silicon layer, or a mixed layer of polysilicon and amorphous silicon.
  • the doping source of the doped silicon layer 7 may be a Group V element (including but not limited to phosphorus).
  • the square resistance of the doped silicon layer 7 can be 10 ⁇ / ⁇ ⁇ 1000 ⁇ / ⁇ , such as 10 ⁇ / ⁇ , 20 ⁇ / ⁇ , 30 ⁇ / ⁇ , 40 ⁇ / ⁇ , 50 ⁇ / ⁇ , 60 ⁇ / ⁇ , 70 ⁇ / ⁇ , 80 ⁇ / ⁇ , 90 ⁇ / ⁇ , 100 ⁇ / ⁇ , 150 ⁇ / ⁇ , 200 ⁇ / ⁇ , 250 ⁇ / ⁇ , 300 ⁇ / ⁇ , 350 ⁇ / ⁇ , 400 ⁇ / ⁇ , 450 ⁇ / ⁇ , 500 ⁇ / ⁇ , 550 ⁇ / ⁇ , 600 ⁇ / ⁇ , 650 ⁇ / ⁇ , 700 ⁇ / ⁇ , 750 ⁇ / ⁇ , 800 ⁇ / ⁇ , 850 ⁇ / ⁇ , 900 ⁇ / ⁇ , 950 ⁇ / ⁇ , 1000 ⁇ / ⁇ , etc.
  • the thickness of the doped silicon layer 7 may be 10 nm to 1000 nm, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 750nm, 800nm, 850nm, 900nm, 950nm , 1000 nm and so on.
  • the tunneling passivation layer 6 may be an electron tunneling passivation layer, which has a certain blocking effect on the diffusion of Group V elements at high temperatures, that is, the group V elements in the tunneling passivation layers at high temperatures.
  • the diffusion rate is much smaller than its diffusion rate in the doped silicon layer 7.
  • the tunneling passivation layer 6 may be an oxide, such as a silicon oxide (SiO x ) layer, a titanium oxide (TiO x ) layer, an aluminum oxide (AlO x ) layer, a tantalum oxide (TaO x ), or a silicon oxynitride (SiN x O At least one of y ) and the like, that is, the tunneling passivation layer 6 may be a single oxide layer, or a stacked structure of a plurality of oxide layers.
  • the thickness of the tunneling passivation layer 6 (that is, the size indicated by T4 in FIG.
  • 3) can be 0.5 nm to 6 nm, such as 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.5 nm, 2 Nano, 2.5 nano, 3 nano, 3.5 nano, 4 nano, 4.5 nano, 5 nano, 5.5 nano, 6 nano, etc.
  • the second cover layer 42 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer, that is, it may be a separate silicon nitride layer, a separate silicon oxynitride layer.
  • Layer, a single silicon oxide layer, or a single silicon carbide layer, or two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer may be stacked.
  • the thickness of the second cover layer 42 may be 60 nm to 120 nm (for example, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 Nanometers, 120 nanometers, etc.).
  • the thickness of each layer is not strictly limited, and can be set as required, as long as the overall thickness meets the requirements.
  • the emitter layer 2 may be disposed on the front surface of the crystalline silicon substrate 1 or on the back surface of the crystalline silicon substrate 1. Accordingly, the tunneling passivation layer 6 and the doped silicon layer 7 may be disposed on the crystalline silicon.
  • the back surface of the base body 1 may be provided on the front surface of the crystalline silicon base body 1.
  • the doped silicon layer 7 may cover only a partial region of the tunneling passivation layer 6, and at the same time, the second passivation layer 42 is also provided on the region of the tunneling passivation layer 6 where the doped silicon layer 7 is not provided.
  • the pattern of the doped silicon layer 7 may correspond to the pattern of the second electrode 52. Disposing the doped silicon layer 7 only in a partial region of the tunneling passivation layer 6 can reduce the absorption of light by the doped silicon layer 7, which is beneficial to the improvement of the photoelectric conversion efficiency of the crystalline silicon solar cell, and is particularly suitable for the tunneling passivation layer 6 and the case where the doped silicon layer 7 is provided on the front surface of the crystalline silicon substrate 1.
  • the method for preparing a crystalline silicon solar cell mainly includes cleaning and texturing the front surface of the crystalline silicon substrate 1, forming an emitter layer 2, flattening the back surface of the crystalline silicon substrate 1, forming a tunneling passivation layer 6, and forming a doped silicon layer. 7. Forming a gallium oxide layer X, forming a first covering layer 41 and a second covering layer 42, forming a first electrode 51 and a second electrode 52, and the like.
  • the front surface of the crystalline silicon substrate 1 is cleaned and textured, forming an emitter layer 2, the back surface of the crystalline silicon substrate 1 is flat, forming a first covering layer 41 and a second covering layer 42, forming a gallium oxide layer X, and forming a first electrode 51.
  • the steps such as the second electrode 52, reference may be made to the description in the foregoing first optional implementation manner, and details are not described herein again.
  • the preparation method can be selected according to the specific composition of the tunneling passivation layer 6.
  • a silicon oxide layer is used as the tunneling passivation layer 6, and a thermal oxidation process and a low temperature furnace can be used. Tube oxidation process, nitric acid oxidation process, ultraviolet / ozone oxidation process, hydrogen peroxide oxidation process, atomic layer deposition process, or chemical vapor deposition process.
  • an intrinsic silicon layer that is, an undoped silicon layer, which can be a polysilicon layer or an amorphous silicon layer
  • the intrinsic silicon layer can be formed on the tunneling passivation layer 6, and then the intrinsic silicon layer can be formed.
  • the silicon layer is doped to form a doped silicon layer 7.
  • the intrinsic silicon layer can be doped by diffusion, deposition of a doped layer containing a doping source (such as deposition of phosphosilicate glass PSG) and annealing, or ion implantation and annealing to dope the intrinsic silicon;
  • a doped source is passed in to obtain the doped silicon layer 7, that is, the doped silicon layer 7 is formed in an environment where the doped source is present.
  • a doped silicon layer 7 covering the entire tunneling passivation layer 6 may be formed on the tunneling passivation layer 6 first, and then doped on the silicon A protective layer is formed at a predetermined position of the layer 7, and then a part of the doped silicon layer 7 that is not covered by the protective layer is removed, thereby forming a doped silicon layer 7 in a local area of the tunneling passivation layer 6.
  • the preset position of the above-mentioned doped silicon layer 7 is a position corresponding to a local area on the tunneling passivation layer 6 where the doped silicon layer 7 needs to be set.
  • a predetermined position of the doped silicon layer 7 can be irradiated with a laser, a silicon oxide layer can be formed at the predetermined position of the doped silicon layer 7, and the silicon oxide layer can be used as a protective layer.
  • the portion of the doped silicon layer 7 not covered by the protective layer can be removed by an alkaline solution, such as a sodium hydroxide solution.
  • the protective layer if the protective layer has a small impact on the performance of the crystalline silicon solar cell, for example, in the case where the silicon oxide layer is used as the protective layer, the protective layer may or may not be removed.
  • the performance of the battery has a large impact, and eventually the protective layer needs to be removed.
  • FIG. 4 shows the structure of a crystalline silicon solar cell including a P-type crystalline silicon substrate
  • FIG. 5 shows the structure of another crystalline silicon solar cell including a P-type crystalline silicon substrate, as shown in FIGS. 4 and 5. It is shown that the crystalline silicon solar cell provided in this embodiment includes:
  • a gallium oxide layer X disposed on one surface of the crystalline silicon substrate 1 and in direct contact with the crystalline silicon substrate 1,
  • a third electrode 53 provided on the third cover layer 43 and in contact with the crystalline silicon substrate 1,
  • An emitter layer 2 provided on the surface of the crystalline silicon substrate 1 opposite to the gallium oxide layer X and having an N-type conductivity,
  • a fourth cover layer 44 provided on the emitter layer 2 and,
  • the fourth electrode 54 is provided on the fourth cover layer 44 and is in contact with the emitter layer 2.
  • the surface itself is a P-type surface. Therefore, in the crystalline silicon solar cell provided in this embodiment, the gallium oxide layer X is directly disposed on the P-type crystalline silicon substrate 1. surface.
  • the P-type crystalline silicon may be single crystal silicon or polycrystalline silicon
  • the resistivity may be 0.1 ⁇ ⁇ cm to 10 ⁇ ⁇ cm (for example, 0.1 ⁇ ⁇ cm, 0.2 ⁇ ⁇ cm, 0.3 ⁇ ⁇ cm, 0.4 ⁇ ⁇ cm, 0.5 ⁇ ⁇ cm, 0.6 ⁇ ⁇ cm, 0.7 ⁇ ⁇ cm, 0.8 ⁇ ⁇ cm, 0.9 ⁇ ⁇ cm, 1 ⁇ ⁇ cm, 2 ⁇ ⁇ cm, 3 ⁇ ⁇ cm, 4 ⁇ ⁇ cm, 5 ⁇ ⁇ cm, 6 ⁇ ⁇ cm, 7 ⁇ ⁇ cm, 8 ⁇ ⁇ cm, 9 ⁇ ⁇ cm, 10 ⁇ ⁇ cm, etc.).
  • the emitter layer 2 may be located on the front of the crystalline silicon substrate 1 or on the back of the crystalline silicon substrate 1. Accordingly, the gallium oxide layer X may be located on the back of the crystalline silicon substrate 1 or on the front of the crystalline silicon substrate 1.
  • the emitter layer 2 can be obtained by doping the P-type crystalline silicon substrate 1 with an N-type doping element (usually a Group V element, including but not limited to phosphorus), and its block resistance value can be 40 ⁇ / ⁇ ⁇ 200 ⁇ / ⁇ (e.g.
  • the thickness of the gallium oxide layer X may be 1 nanometer to 1000 nanometers, for example, 1 nanometer, 5 nanometers, 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm , 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc.
  • the thickness of the gallium oxide layer X may be 2 nm to 150 nm, and more preferably, the thickness of the gallium oxide layer X may be 5 nm to 60 n
  • the third covering layer 43 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide, that is, it may be a separate silicon nitride layer, a separate silicon oxynitride layer, or a separate silicon oxide.
  • the layer may be two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer.
  • the overall thickness of the third covering layer 43 may be less than 200 nanometers, such as 200 nanometers, 190 nanometers, 180 nanometers, 170 nanometers, 160 nanometers, 150 nanometers, 140 nanometers, 130 nanometers, 120 nanometers, 110 nanometers, 100 nanometers, and 90 nanometers. , 80nm, 70nm, 60nm, 50nm, 40nm, 30nm, 20nm, 10nm, 9nm, 8nm, 7nm, 6nm, 5nm, 4nm, 3nm, 2nm, 1 Nanometer, 0.5 nanometer, etc.
  • the thickness of each layer is not strictly required, and can be set as required, as long as the entire thickness of the third covering layer 43 meets the requirements.
  • the arrangement of the third covering layer 43 can further passivate (hydrogen diffusion) the crystalline silicon substrate 1. It should be noted that, in this embodiment, the third cover layer 43 may not be provided, and the third electrode 53 may be directly provided on the gallium oxide layer X.
  • the fourth covering layer 44 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer, that is, it may be a separate silicon nitride layer, a separate silicon oxynitride layer, a separate oxide layer.
  • the silicon layer or the separate silicon carbide layer may be two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer.
  • the thickness of the fourth covering layer 44 may be 60 nm to 120 nm (for example, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 Nanometers, 120 nanometers, etc.).
  • the thickness of each layer is not strictly required, and can be set as required, as long as the entire thickness of the fourth covering layer 44 meets the requirements.
  • the third electrode 53 and the fourth electrode 54 may be metal electrodes (for example, silver electrodes). Accordingly, the contact between the third electrode 53 and the crystalline silicon substrate 1 is an ohmic contact, and the fourth electrode 54 and the emitter layer 2 are in contact. The contact is ohmic.
  • the fourth electrode 54 may be an electrode having a gate line structure (including a main gate line and a sub gate line).
  • the block resistance value of the region corresponding to the fourth electrode 54 of the emitter layer 2 may be greater than the block resistance values (ie, selective emitters) of other regions, thereby improving the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • the crystalline silicon solar cell provided in this embodiment may be based on a Passivated Emitter and Rear Cell (PERC) structure.
  • PERC Passivated Emitter and Rear Cell
  • a via hole O is provided on the gallium oxide layer X and the third covering layer 43, and a surface field layer having a conductivity type of P type is formed on a region of the surface of the crystalline silicon substrate 1 corresponding to the via hole O.
  • the third electrode 53 includes a first portion 531 and a second portion 532.
  • the first portion 531 is linear.
  • the second portion 532 is disposed on the third cover layer 43 in a region other than the first portion 531.
  • the second portion 532 is in contact with the first portion 531. .
  • the second portion 532 is in contact with the crystalline silicon substrate 1 through the via hole O, and forms a surface field layer on a region of the surface of the crystalline silicon substrate 1 corresponding to the via hole O.
  • the first part 531 can also be referred to as a main electrode, which is used for conductive buses and string welding of solar cells during the preparation of photovoltaic modules.
  • the first part 531 can be provided with multiple pieces, for example, 2 to 4 pieces. The spaces may be parallel to each other, and the first portion 531 may be provided as a discontinuous linear electrode.
  • the first portion 531 may be formed of a silver paste or a silver-aluminum paste.
  • the second portion 532 may be formed of an aluminum paste. After the via hole O is provided on the gallium oxide layer X and the third covering layer 43, the aluminum paste used to form the second portion 532 is printed on the third covering layer 43.
  • the aluminum paste is at the same position as the via hole O during the high-temperature sintering process.
  • a diffusion reaction occurs on the surface of the exposed P-type crystalline silicon substrate 1 to form an aluminum-doped P + silicon layer and a silicon aluminum alloy.
  • the P + silicon layer that is, the P-type surface field layer
  • the aluminum paste which has not undergone a diffusion reaction, conducts electricity to form a second portion 532 of the third electrode 53.
  • the second portion 532 may cover the entire third covering layer 43, or as shown in FIG. 7, the second portion 532 may cover a portion of the third covering layer 43.
  • the second portion 532 may completely cover one via hole O, or may only cover a portion of one via hole O. It can be understood that the crystalline silicon solar cell covered by the second portion 532 and the third covering layer 43 can transmit light on both sides, and can generate electricity on both sides, and has higher photoelectric conversion efficiency.
  • the cross-sectional shape of the via hole O can be circular, linear (ie, long), square, triangular, polygon with 5 or more sides, or other shapes.
  • a circular via O its diameter can be 10 ⁇ m to 200 ⁇ m (for example, 10 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, 50 ⁇ m, 60 ⁇ m, 70 ⁇ m, 80 ⁇ m, 90 ⁇ m, 100 ⁇ m , 110 ⁇ m, 120 ⁇ m, 130 ⁇ m, 140 ⁇ m, 150 ⁇ m, 160 ⁇ m, 170 ⁇ m, 180 ⁇ m, 190 ⁇ m, 200 ⁇ m, etc.), and the hole pitch can be 100 ⁇ m to 1000 ⁇ m (for example, 100 ⁇ m, 200 ⁇ m, 300 microns, 400 microns, 500 microns, 600 microns, 700 microns, 800 microns, 900 microns, 1000 microns, etc.).
  • a linear via O its width can be 20 micrometers to 100 micrometers (for example, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, etc.).
  • the length may be slightly smaller than the side length of the crystalline silicon substrate 1 (the crystalline silicon substrate 1 is usually a square or a chamfered square).
  • the length direction of the linear via hole O may be perpendicular to the length direction of the first portion 531 of the third electrode 53.
  • a plurality of linear vias O may be provided, and the multiple linear vias O are parallel to each other.
  • the distance between two adjacent linear vias O may be 500 ⁇ m to 2000 ⁇ m (for example, 500 ⁇ m, 600 ⁇ m, 700 ⁇ m).
  • the linear via hole O may be provided in the form of a dotted line, that is, the linear via hole O is discontinuous in the length direction.
  • the method for preparing a crystalline silicon solar cell mainly includes cleaning and texturing the front surface of the crystalline silicon substrate 1, forming an emitter layer 2, flattening the back surface of the crystalline silicon substrate 1, forming a gallium oxide layer X, forming a third covering layer 43 and The fourth covering layer 44, the third electrode 53 and the fourth electrode 54 are formed.
  • cleaning and texturing the front surface of the crystalline silicon substrate 1 can reduce the reflectivity.
  • the crystalline silicon substrate 1 can be washed with a mixed aqueous solution of sodium hydroxide (NaOH) and hydrogen peroxide (H2O2) to remove surface contaminants and damaged layers.
  • NaOH sodium hydroxide
  • H2O2 hydrogen peroxide
  • the alkaline etching solution can be used for texturing, and the acidic etching solution can also be used for texturing.
  • the alkaline etching solution can be an aqueous sodium hydroxide solution.
  • the reflectance of the surface of the single crystal silicon wafer may be 10% to 18% (for example, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17 %, 18%, etc.), the reflectivity of the surface of the polycrystalline silicon wafer can be 6% to 20% (for example, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15 %, 16%, 17%, 18%, 19%, 20%, etc.).
  • the emitter layer 2 may be formed by methods such as diffusion (for example, furnace tube phosphorus diffusion), deposition of a doped layer containing a doping source (for example, phosphosilicate glass PSG) and annealing, or ion implantation (for example, implantation of phosphorus ions) and annealing.
  • diffusion for example, furnace tube phosphorus diffusion
  • deposition of a doped layer containing a doping source for example, phosphosilicate glass PSG
  • ion implantation for example, implantation of phosphorus ions
  • the back surface of the crystalline silicon substrate 1 can be flattened by a chemical solution to appropriately reduce the specific surface area of the back surface of the crystalline silicon substrate 1 and the silicon wafer can be washed with hydrofluoric acid.
  • the chemical solution may be an alkaline solution, including but not limited to a tetramethylammonium hydroxide solution, a sodium hydroxide solution, a potassium hydroxide, etc.
  • the concentration of the alkaline solution may be adjusted as required; it may also be an acid solution such as nitric acid,
  • the mixed solution of hydrofluoric acid and sulfuric acid, the concentration of each acid solution in the mixed solution, and the ratio of each acid solution can also be adjusted as required.
  • the gallium oxide layer X can be formed by a single atomic layer deposition method, a plasma enhanced chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or a low pressure chemical vapor deposition method. After the gallium oxide layer X is deposited, an annealing step is required.
  • the third covering layer 43 and the fourth covering layer 44 can also be formed by methods such as ALD, PECVD, APCVD, and LPCVD. When the third covering layer 43 and the fourth covering layer 44 have the same composition, they may be formed simultaneously.
  • the third electrode 53 and the fourth electrode 54 can be formed by a method of screen-printing an electrode paste and quickly sintering at a high temperature.
  • the sintering temperature may be 600 ° C to 900 ° C (for example, 600 ° C, 650 ° C, 700 ° C, 750 ° C, 800 ° C, 850 ° C, 900 ° C, etc.), and the sintering time may be 10 seconds to 3 minutes, such as 10 seconds, 20 seconds, 30 seconds, 40 seconds, 60 seconds, 70 seconds, 80 seconds, 90 seconds, 100 seconds, 110 seconds, 120 seconds, 130 seconds, 140 seconds, 150 seconds, 160 seconds, 170 seconds, 180 seconds, etc.
  • a step of forming a via hole O in the gallium oxide layer X and the third cover layer 43 is further performed.
  • the via hole O may be formed by a laser or chemical etching method.
  • the printing process of the third electrode 53 specifically includes first printing the paste for forming the first portion 531, and then printing the paste for forming the second portion 532.
  • FIG. 8 illustrates the structure of another crystalline silicon solar cell including a P-type crystalline silicon substrate.
  • the crystalline silicon solar cell includes:
  • a gallium oxide layer X disposed on one surface of the crystalline silicon substrate 1 and in direct contact with the crystalline silicon substrate 1,
  • a third electrode 53 provided on the third cover layer 43 and in contact with the crystalline silicon substrate 1,
  • An emitter layer 2 provided on the surface of the crystalline silicon substrate 1 opposite to the gallium oxide layer X and having an N-type conductivity,
  • a fourth capping layer 44 provided on the doped silicon layer 7, and,
  • a fourth electrode 54 is provided on the fourth cover layer 44 and is in contact with the doped silicon layer 7.
  • the gallium oxide layer X is also directly disposed on the surface of the P-type crystalline silicon substrate 1.
  • the crystalline silicon solar cell provided in this embodiment adopts a TOP-Con structure on the side of the emitter layer 2.
  • the resistivity of the crystalline silicon substrate 1, the square resistance value of the emitter layer 2, the composition and thickness of the third cover layer 43, and the specific form of the fourth electrode 54 may refer to the third optional implementation described above. The description in the mode is not repeated here.
  • the thickness of the gallium oxide layer X is preferably 10 nm to 90 nm, and more preferably 20 nm to 60 nm.
  • the doped silicon layer 7 may be a doped polysilicon layer, a doped amorphous silicon layer, or a doped polysilicon / silicon oxide mixed layer.
  • the polysilicon / silicon oxide mixed layer is that polysilicon particles are evenly distributed in the silicon oxide film or the surface of the polysilicon particles is coated with the silicon oxide film.
  • the thickness of the doped silicon layer 7 may be 20 nanometers to 1000 nanometers, such as 20 nanometers, 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers, 300 nanometers, 350 nanometers, 400 nanometers, 450 nanometers, 500 nanometers, 550 Nanometer, 600nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc.
  • the doped element in the doped silicon layer 7 may be a Group V element (including but not limited to phosphorus), and the doping concentration of the doped element may be 5 ⁇ 10 18 atoms / cm 3 to 9 ⁇ 10 20 atoms / cm 3 , such as 5 ⁇ 10 18 atoms / cm 3 , 6 ⁇ 10 18 atoms / cm 3 , 7 ⁇ 10 18 atoms / cm 3 , 8 ⁇ 10 18 atoms / cm 3 , 9 ⁇ 10 18 atoms / cm 3 , 1 ⁇ 10 19 atoms / cm 3 , 2 ⁇ 10 19 atoms / cm 3 , 3 ⁇ 10 19 atoms / cm 3 , 4 ⁇ 10 19 atoms / cm 3 , 5 ⁇ 10 19 atoms / cm 3 , 6 ⁇ 10 19 atoms / cm 3 , 7 ⁇ 10 19 atoms / cm 3 , 8 ⁇ 10 19 atoms / cm 3 , 9 ⁇
  • the tunneling passivation layer 6 provided on the emitter layer 2 may be an electron tunneling passivation layer, which has a certain blocking effect on the diffusion of Group V elements at high temperatures, that is, Group V elements at high temperatures
  • the diffusion rate in the tunneling passivation layer is much smaller than the diffusion rate in the doped silicon layer 7.
  • the tunneling passivation layer 6 may be at least one of a silicon oxide layer, a silicon oxynitride layer, and a hydrogenated amorphous silicon oxide layer.
  • the thickness of the front tunneling passivation layer 6 may be 1.2 nm to 2.5 nm, such as 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2.0 nm, 2.1 nm, 2.2 nm , 2.3 nm, 2.4 nm, 2.5 nm, etc.
  • the fourth covering layer 44 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer, that is, it may be a separate silicon nitride layer, a separate silicon oxynitride layer, a separate oxide layer.
  • the silicon layer or the separate silicon carbide layer may be two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer.
  • the thickness of the fourth cover layer 44 may be 68 nm to 100 nm (for example, 68 nm, 70 nm, 72 nm, 74 nm, 75 nm, 76 nm, 78 nm, 80 nm, 82 nm, 84 nm, 85 nm, 86 Nanometer, 88 nanometer, 90 nanometer, 92 nanometer, 94 nanometer, 95 nanometer, 96 nanometer, 98 nanometer, 100 nanometer, etc.).
  • the thickness of each layer is not strictly required, and can be set as required, as long as the entire thickness of the fourth covering layer 44 meets the requirements.
  • the doped silicon layer 7 may cover only a partial region of the tunneling passivation layer 6, and a fourth covering layer 44 is also provided on the region of the tunneling passivation layer 6 where the doped silicon layer 7 is not provided.
  • the pattern of the doped silicon layer 7 may correspond to the pattern of the fourth electrode 54. Disposing the doped silicon layer 7 only in a partial region of the tunneling passivation layer 6 can reduce the absorption of light by the doped silicon layer 7, which is beneficial to the improvement of the photoelectric conversion efficiency of the crystalline silicon solar cell, and is particularly suitable for the tunneling passivation layer. 6 and the case where the doped silicon layer 7 is provided on the front surface of the crystalline silicon substrate 1.
  • the gallium oxide layer X, the third covering layer 43 and the third electrode 53 may also be configured as a PERC structure.
  • PERC structure For specific structures, reference may be made to the description of the third optional embodiment described above, and details are not described herein again.
  • the method for preparing a crystalline silicon solar cell mainly includes cleaning and texturing the front surface of the crystalline silicon substrate 1, forming an emitter layer 2, flattening the back surface of the crystalline silicon substrate 1, forming a tunneling passivation layer 6, and forming a doped silicon layer. 7. Forming a gallium oxide layer X, forming a third covering layer 43 and a fourth covering layer 44, forming a third electrode 53 and a fourth electrode 54, and the like.
  • the front surface of the crystalline silicon substrate 1 is cleaned and textured, forming an emitter layer 2, the back surface of the crystalline silicon substrate 1 is flat, a gallium oxide layer X is formed, a third covering layer 43 and a fourth covering layer 44 are formed, and a third electrode 53 is formed.
  • the steps such as the fourth electrode 54 and the like, refer to the description in the third optional implementation manner described above, and details are not described herein again.
  • the steps of forming the tunneling passivation layer 6 and the doped silicon layer 7 can be referred to the description in the second alternative embodiment described above; for the doped silicon layer covering a partial region of the tunneling passivation layer 6
  • the preparation of 7 reference may also be made to the description in the foregoing second optional implementation manner, and details are not described herein again.
  • FIG. 9 shows a structure of another crystalline silicon solar cell including a P-type crystalline silicon substrate 1.
  • the crystalline silicon solar cell includes:
  • a first tunneling passivation layer 61 provided on a side surface of the crystalline silicon substrate 1,
  • a fifth electrode 55 disposed on the fifth cover layer 45 and in contact with the first doped silicon layer 71,
  • An emitter layer 2 disposed on a surface of the crystalline silicon substrate 1 opposite to the first tunneling passivation layer 61 and having an N-type conductivity
  • a sixth cover layer 46 provided on the emitter layer 2 and,
  • a sixth electrode 56 is provided on the sixth cover layer 46 and is in contact with the emitter layer 2.
  • a TOP-Con structure is adopted on the side of the P-type crystalline silicon substrate 1 opposite to the emitter layer 2 and the gallium oxide layer X is disposed on the P-type first doped silicon.
  • the gallium oxide layer X is in direct contact with the P-type first doped silicon layer 71.
  • the P-type crystalline silicon substrate 1 may be single crystal silicon or polycrystalline silicon, and the resistivity may be 0.1 ⁇ ⁇ cm to 10 ⁇ ⁇ cm (for example, 0.1 ⁇ ⁇ cm, 0.2 ⁇ ⁇ cm, 0.3 ⁇ ⁇ cm, 0.4 ⁇ ⁇ cm, 0.5 ⁇ ⁇ cm, 0.6 ⁇ ⁇ cm, 0.7 ⁇ ⁇ cm, 0.8 ⁇ ⁇ cm, 0.9 ⁇ ⁇ cm, 1 ⁇ ⁇ cm, 2 ⁇ ⁇ cm, 3 ⁇ ⁇ cm, 4 ⁇ ⁇ cm, 5 ⁇ ⁇ cm, 6 ⁇ ⁇ cm, 7 ⁇ ⁇ cm, 8 ⁇ ⁇ cm, 9 ⁇ ⁇ cm, 10 ⁇ ⁇ cm, etc.).
  • the emitter layer 2 may be located on the front surface of the crystalline silicon substrate 1 or on the back surface of the crystalline silicon substrate 1. Accordingly, the first tunneling passivation layer 61, the first doped silicon layer 71, and the gallium oxide layer X may be located on the crystalline silicon.
  • the back surface of the base body 1 may be located on the front surface of the crystalline silicon base body 1.
  • the emitter layer 2 can be formed by doping a P-type crystalline silicon substrate 1 with a Group V element (including but not limited to phosphorus), and its block resistance value can be 40 ⁇ / ⁇ ⁇ 200 ⁇ / ⁇ (for example, 40 ⁇ / ⁇ , 50 ⁇ / ⁇ , 60 ⁇ / ⁇ , 70 ⁇ / ⁇ , 80 ⁇ / ⁇ , 90 ⁇ / ⁇ , 100 ⁇ / ⁇ , 110 ⁇ / ⁇ , 120 ⁇ / ⁇ , 130 ⁇ / ⁇ , 140 ⁇ / ⁇ , 150 ⁇ / ⁇ , 160 ⁇ / ⁇ , 170 ⁇ / ⁇ , 180 ⁇ / ⁇ , 190 ⁇ / ⁇ , 200 ⁇ / ⁇ , etc.).
  • a Group V element including but not limited to phosphorus
  • the thickness of the gallium oxide layer X may be 10 nanometers to 90 nanometers, for example, 1 nanometer, 5 nanometers, 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, etc.
  • the thickness of the gallium oxide layer X may be 20 nm to 60 nm.
  • the first doped silicon layer 71 may be a doped polysilicon layer, a doped amorphous silicon layer, or a doped polysilicon / silicon oxide mixed layer.
  • the polysilicon / silicon oxide mixed layer is that polysilicon particles are evenly distributed in the silicon oxide film or the surface of the polysilicon particles is coated with the silicon oxide film.
  • the element doped in the first doped silicon layer 71 may be a group III element (including but not limited to boron), and the doping concentration of the doped element may be 1 ⁇ 10 18 atoms / cm 3 to 8 ⁇ 10 20 atoms.
  • the thickness of the first doped silicon layer 71 may be 20 nanometers to 1000 nanometers, such as 20 nanometers, 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers, 300 nanometers, 350 nanometers, 400 nanometers, 450 nanometers, and 500 nanometers. , 550nm, 600nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc.
  • the first tunneling passivation layer 61 may be a hole tunneling passivation layer, which has a certain blocking effect on the diffusion of group III elements at high temperatures, that is, the group III elements pass through the first tunnel at high temperatures.
  • the diffusion rate in the passivation layer 61 is much lower than the diffusion rate in the first doped silicon layer 71.
  • the first tunneling passivation layer 61 may be a silicon oxide layer, an aluminum oxide layer, a vanadium oxide layer, a tungsten oxide layer, For at least one of a nickel oxide layer, a molybdenum oxide layer, and a cuprous chloride layer, the thickness of the first tunneling passivation layer 61 may be 1.2 nm to 2.5 nm, such as 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2.0nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm.
  • the fifth covering layer 45 provided on the gallium oxide layer X may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide, which may be a separate silicon nitride layer and a separate nitrogen layer.
  • the silicon oxide layer, the single silicon oxide layer, or the single silicon carbide layer may also be two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer.
  • the overall thickness of the fifth covering layer 45 may be 20 nanometers to 200 nanometers, such as 20 nanometers, 30 nanometers, 40 nanometers, 50 nanometers, 60 nanometers, 70 nanometers, 80 nanometers, 90 nanometers, 100 nanometers, 110 nanometers, 120 nanometers, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, etc.
  • the fifth covering layer 45 has a laminated structure, the thickness of each layer is not strictly required, and can be set as required, as long as the entire thickness of the fifth covering layer 45 meets the requirements. It should be noted that, in the embodiment of the present disclosure, the fifth covering layer 45 may not be provided, and the fifth electrode 55 is directly disposed on the gallium oxide layer X.
  • the first doped silicon layer 71 may cover only a partial region of the first tunneling passivation layer 61, and at the same time, the first tunneling passivation layer 61 is also provided on a region where the first doped silicon layer 71 is not provided. There is a gallium oxide layer X.
  • the pattern of the first doped silicon layer 71 may correspond to the pattern of the fifth electrode 55.
  • the sixth covering layer 46 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer, that is, it may be a separate silicon nitride layer, a separate silicon oxynitride layer, a separate oxide
  • the silicon layer or the separate silicon carbide layer may be two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer.
  • the thickness of the sixth cover layer 46 may be 68 nm to 100 nm (for example, 68 nm, 70 nm, 72 nm, 74 nm, 75 nm, 76 nm, 78 nm, 80 nm, 82 nm, 84 nm, 85 nm, 86 Nanometer, 88 nanometer, 90 nanometer, 92 nanometer, 94 nanometer, 95 nanometer, 96 nanometer, 98 nanometer, 100 nanometer, etc.).
  • the thickness of each layer is not strictly required, and can be set as required, as long as the entire thickness of the sixth covering layer 46 meets the requirements.
  • Each of the fifth electrode 55 and the sixth electrode 56 is an electrode of a gate line structure including a main gate line and a sub gate line. Accordingly, the first doped silicon layer 71 has a grid-like structure. The width of the portion of the grid-shaped first doped silicon layer 71 corresponding to the main gate line of the fifth electrode 55 is slightly larger than the width of the main gate line, and the width of the portion corresponding to the sub-gate line is slightly larger than the width of the sub-gate line.
  • the block resistance value of the region corresponding to the sixth electrode 56 of the emitter layer 2 may be greater than the block resistance values (ie, selective emitters) of other regions, thereby improving the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • the method for preparing a crystalline silicon solar cell mainly includes cleaning and texturing the front surface of the crystalline silicon substrate 1, forming an emitter layer 2, flattening the back surface of the crystalline silicon substrate 1, forming a first tunneling passivation layer 61, and forming a first
  • the silicon layer 71 is doped, the gallium oxide layer X is formed, the fifth cover layer 45 and the sixth cover layer 46 are formed, the fifth electrode 55 and the sixth electrode 56 are formed, and the like.
  • the front surface of the crystalline silicon substrate 1 is cleaned and textured, forming an emitter layer 2, the back surface of the crystalline silicon substrate 1 is flat, a gallium oxide layer X is formed, a fifth cover layer 45 and a sixth cover layer 46 are formed, and a fifth electrode 55 and a first electrode are formed.
  • steps such as the six electrodes 56, reference may be made to the description in the third optional implementation manner described above, and details are not described herein again.
  • FIG. 10 shows a structure of another crystalline silicon solar cell including a P-type crystalline silicon substrate 1.
  • the crystalline silicon solar cell includes:
  • a first tunneling passivation layer 61 provided on a side surface of the crystalline silicon substrate 1,
  • a fifth electrode 55 disposed on the fifth cover layer 45 and in contact with the first doped silicon layer 71,
  • An emitter layer 2 disposed on a surface of the crystalline silicon substrate 1 opposite to the first tunneling passivation layer 61 and having an N-type conductivity
  • a sixth electrode 56 is disposed on the sixth cover layer 46 and is in contact with the second doped silicon layer 72.
  • a TOP-Con structure is used on both sides of the P-type crystalline silicon substrate 1, and a gallium oxide layer X is provided on the first doped silicon layer 71 of the P type, that is, the In the embodiment, the gallium oxide layer X is also in direct contact with the P-type first doped silicon layer 71.
  • the resistivity of the crystalline silicon substrate 1, the square resistance value of the emitter layer 2, the composition and thickness of the fifth covering layer 45, the composition and thickness of the sixth covering layer 46, and the first tunneling passivation layer 61 For the specific forms of the first doped silicon layer 71, the fifth electrode 55, and the sixth electrode 56, etc., reference may be made to the description in the third optional embodiment, and details are not described herein again.
  • the second doped silicon layer 72 may be a doped polysilicon layer, a doped amorphous silicon layer, or a doped polysilicon / silicon oxide mixed layer.
  • the polysilicon / silicon oxide mixed layer is that polysilicon particles are evenly distributed in the silicon oxide film or the surface of the polysilicon particles is coated with the silicon oxide film.
  • the thickness of the second doped silicon layer 72 may be 20 nanometers to 1000 nanometers, such as 20 nanometers, 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers, 300 nanometers, 350 nanometers, 400 nanometers, 450 nanometers, and 500 nanometers. , 550nm, 600nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc.
  • the element doped in the second doped silicon layer 72 may be a Group V element (including but not limited to phosphorus), and the doping concentration of the doped element may be 5 ⁇ 10 18 atoms / cm 3 to 9 ⁇ 10 20 atoms. / cm 3 , such as 5 ⁇ 10 18 atoms / cm 3 , 6 ⁇ 10 18 atoms / cm 3 , 7 ⁇ 10 18 atoms / cm 3 , 8 ⁇ 10 18 atoms / cm 3 , 9 ⁇ 10 18 atoms / cm 3 , 1 ⁇ 10 19 atoms / cm 3 , 2 ⁇ 10 19 atoms / cm 3 , 3 ⁇ 10 19 atoms / cm 3 , 4 ⁇ 10 19 atoms / cm 3 , 5 ⁇ 10 19 atoms / cm 3 , 6 ⁇ 10 19 atoms / cm 3 , 7 ⁇ 10 19 atoms / cm 3 , 8 ⁇ 10 19 atoms / cm 3 , 9
  • the second tunneling passivation layer 62 may be an electron tunneling passivation layer, which has a certain blocking effect on the diffusion of group V elements at high temperatures, that is, the group V elements pass through the passivation at the front side at high temperatures.
  • the diffusion rate in the layer is much smaller than the diffusion rate in the second doped silicon layer 72.
  • the second tunneling passivation layer 62 may be at least one of a silicon oxide layer, a silicon oxynitride layer, and a hydrogenated amorphous silicon oxide layer.
  • the thickness of the second tunneling passivation layer 62 may be 1.2 nm to 2.5 nm, for example, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2.0 nm, 2.1 nm, 2.2 Nanometer, 2.3 nanometer, 2.4 nanometer, 2.5 nanometer.
  • the second doped silicon layer 72 may cover only a partial region of the second tunneling passivation layer 62, and at the same time, the second tunneling passivation layer 62 is disposed on a region where the second doped silicon layer 72 is not provided.
  • the pattern of the second doped silicon layer 72 may correspond to the pattern of the sixth electrode 56.
  • the second doped silicon layer 72 may have a grid structure.
  • the width of the portion corresponding to the main gate line of the sixth electrode 56 is slightly larger than the width of the main gate line, and the width of the portion corresponding to the sub gate line is slightly larger than the width of the sub gate line.
  • the method for preparing a crystalline silicon solar cell mainly includes cleaning and texturing the front surface of the crystalline silicon substrate 1, forming an emitter layer 2, flattening the back surface of the crystalline silicon substrate 1, forming a first tunneling passivation layer 61, and forming a second Tunneling the passivation layer 62, forming a first doped silicon layer 71, forming a second doped silicon layer 72, forming a gallium oxide layer X, forming a fifth covering layer 45 and a sixth covering layer 46, forming a fifth electrode 55, and The sixth electrode 56 and the like.
  • the front surface of the crystalline silicon substrate 1 is cleaned and textured, forming an emitter layer 2, the back surface of the crystalline silicon substrate 1 is flat, a gallium oxide layer X is formed, a fifth cover layer 45 and a sixth cover layer 46 are formed, and a fifth electrode 55 and a first electrode are formed.
  • steps such as the six electrodes 56, reference may be made to the description in the third optional implementation manner described above, and details are not described herein again.
  • the steps of forming the first tunneling passivation layer 61, the second tunneling passivation layer 62, the first doped silicon layer 71, and the second doped silicon layer 72 may refer to the second optional The description in the embodiment; for the preparation of a first doped silicon layer 71 covering a local area of the first tunneling passivation layer 61 and a second doped silicon layer 72 covering a local area of the second tunneling passivation layer 62
  • an embodiment of the present disclosure provides a photovoltaic module.
  • the photovoltaic module includes a cover plate, a first encapsulating film, a battery string, a second encapsulating film, and a back plate.
  • Solar cells wherein the solar cell is a crystalline silicon solar cell provided by the embodiment of the present disclosure described above.
  • the crystalline silicon solar cell provided in the embodiment of the present disclosure is provided with a gallium oxide layer X that is in direct contact with the P-type silicon layer, the negative charge of the gallium oxide layer X is used to chemically passivate and field-blunt the surface of the P-type silicon.
  • the solar cell has improved the photoelectric conversion efficiency of the solar cell. Therefore, the photovoltaic module using the crystalline silicon solar cell has a higher output power, thereby reducing the cost of electricity and improving the cost-effectiveness of photovoltaic power generation.
  • the cover plate is usually a glass plate, and the material of the first encapsulating film and the second encapsulating film is EVA (ethylene-vinyl acetate copolymer).
  • the back plate may be a glass plate or TPT (PVF). / PET / PVF) board.
  • the photovoltaic module also includes a frame, and the frame is filled with silica gel.
  • the crystalline silicon solar cell may be a square or a square with rounded corners, or a sliced cell obtained by cutting the entire cell.
  • the photovoltaic module provided by the embodiment of the present disclosure may include multiple strings of battery strings, and the battery cells in each string of strings may be connected by a welding tape, or may be connected by conductive glue or other conductive materials.
  • a certain gap may be left between adjacent battery slices, or the edges of adjacent battery slices may be overlapped, that is, connected in a shingled manner.
  • the embodiments of the present disclosure also provide an application of gallium oxide as a passivation structure or a passivation structure in a crystalline silicon solar cell.
  • gallium oxide is in direct contact with the P-type silicon layer of the crystalline silicon solar cell.
  • the P-type silicon layer in the embodiment of the present disclosure may specifically be:
  • a P-type doped silicon layer disposed on one side of the P-type crystalline silicon substrate, and a gap between the doped silicon layer and the crystalline silicon substrate may be provided at a high temperature to diffuse the group III element.
  • the diffusion has a certain barrier effect on the tunneling passivation layer.
  • an electrode, a cover layer, a tunneling passivation layer, and a doped silicon layer provided on a front surface of a crystalline silicon solar cell are referred to as a front electrode, a front cover layer, a front tunnel passivation layer, Front doped silicon layer;
  • the electrodes, cover layer, tunneling passivation layer, and doped silicon layer provided on the back of the crystalline silicon solar cell are referred to as the back electrode, back cover layer, back tunnel passivation layer, and back doping, respectively Silicon layer.
  • the solar cell includes a front electrode, a front cover layer, a gallium oxide layer, and An electrode layer, an N-type crystalline silicon substrate, an N-type surface field layer, a back cover layer, and a back electrode.
  • the N-type crystalline silicon substrate is an N-type single crystal silicon wafer having a resistivity of 2.0 ⁇ ⁇ cm and a size of 156.75 mm ⁇ 156.75 mm.
  • the emitter layer is formed by the boron diffusion of the furnace tube, and the block resistance value after the doping is 80 ⁇ / ⁇ .
  • the gallium oxide layer is 20 nanometers thick.
  • the front cover layer is a silicon nitride layer with a thickness of 65 nanometers.
  • the N-type surface field layer on the back of the N-type crystalline silicon substrate is formed by a phosphorus ion implantation method, and the square resistance after the doping is 110 ⁇ / ⁇ .
  • the back cover layer on the N-type surface field layer is a silicon nitride layer with a thickness of 75 nanometers.
  • the front electrode and the back electrode are both grid lines. Among them, there are 4 main grid lines with a width of 1.1 mm, and 102 sub grid lines with a width of 40 ⁇ m. The distance between two adjacent sub grid lines is 1.5 mm. Both the electrode and the back electrode are formed of Heraeus SOL9360 type silver paste.
  • Step 101 using a mixed aqueous solution of NaOH and H 2 O 2 (NaOH, H 2 O 2 and H 2 O are mixed at a mass ratio of 0.5%: 1%: 98.5%) to clean the N-type single crystal silicon wafer (washing The time is 2 minutes), and then the front surface of the N-type single crystal silicon wafer is flocked with a 3% sodium hydroxide aqueous solution by mass concentration. After the texturing, the reflectance of the front surface of the N-type single crystal silicon wafer is 12%.
  • the emitter layer is formed by boron doping on the front surface of the N-type single crystal silicon wafer after the texturing by the boron diffusion method of the furnace tube to form a PN junction.
  • the tube boron diffusion using Tempress's TS-81255 type diffusion furnace diffusion conditions were as follows: BBr 3 as a boron source, at 940 °C diffusion into BBr the furnace quartz tube 3 (into time 20min), After that, the introduction of BBr 3 was stopped and the temperature was kept at 960 ° C for 20 minutes.
  • step 103 the diffused N-type single crystal silicon wafer is immersed in a TMAH solution at 70 ° C and a mass concentration of 20% for 5 minutes, the back surface of the N-type single crystal silicon wafer is flattened, and then a The silicon wafer was washed with an HF aqueous solution for 2 min.
  • Step 104 Use an iPV-2000 type ion implanter of Springfield (Shanghai Kaisto Semiconductor Co., Ltd.) to implant phosphorus ions into the back surface of the N-type single crystal silicon wafer, perform phosphorus doping to form an N-type surface field layer, and implant conditions.
  • the ion acceleration voltage is 10kV
  • the beam current after acceleration is 120mA
  • the vacuum degree of the ion implantation chamber is 2 ⁇ 10 -5 Torr.
  • a PEALD method is used to deposit a gallium oxide thin film on the emitter layer.
  • the equipment used is a TFS200 atomic layer deposition thin film system from Beneq of Finland.
  • the deposition conditions are: a temperature of 75 ° C and a pressure of 0.25 Torr.
  • the volume flow rate of methyl gallium (TMGa) was 70 sccm (standard state ml / min), and the volume flow rate of O 2 was 200 sccm.
  • a PECVD method is used to form a silicon nitride film on the emitter layer and the N-type surface field layer.
  • the equipment used is a SINA-type PECVD equipment from ROTH & RAU, and the deposition conditions are: temperature 400 ° C, pressure 0.25mBar, SiH
  • the volume flow rate of 4 is 100 sccm
  • the volume flow rate of NH 3 is 180 sccm.
  • step 107 the paste for forming the back electrode is screen-printed, and the screen printer used is a Baccini speedy thinking printer of Applied Materials (the same applies hereinafter).
  • step 108 a paste for forming a front electrode is screen-printed.
  • step 109 sintering is performed at a temperature of 820 ° C., and the sintering time is 10 seconds.
  • the front metal silver passes through the silicon nitride / gallium oxide film to form a local ohmic contact with the emitter layer, and the back silver paste corrodes the silicon nitride.
  • the thin film makes an ohmic contact with the N-type doped layer.
  • the IV test method (CetisPV-XF2-PB type IV tester from Halm, Germany) was used to test the performance of the solar cell provided by this embodiment (the test condition is 25 ° C and the spectral condition is AM1.5). The result is: open circuit voltage 0.668 V, short-circuit current 9.77A, photoelectric conversion efficiency 21.1%.
  • This embodiment provides a gallium oxide passivated N-type crystalline silicon double-sided solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 1 is that the gallium oxide in the solar cell provided in this embodiment
  • the thickness of the layer is 1 nanometer.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example was tested, and the results were: an open circuit voltage of 0.661V, a short-circuit current of 9.79A, and a photoelectric conversion efficiency of 20.92%.
  • This embodiment provides a gallium oxide passivated N-type crystalline silicon double-sided solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 1 is that the gallium oxide in the solar cell provided in this embodiment
  • the thickness of the layer is 40 nanometers.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.668V, a short-circuit current of 9.75A, and a photoelectric conversion efficiency of 21.06%.
  • This embodiment provides a gallium oxide passivated N-type crystalline silicon double-sided solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 1 is that the gallium oxide in the solar cell provided in this embodiment
  • the thickness of the layer is 80 nanometers.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open-circuit voltage of 0.668V, a short-circuit current of 9.73A, and a photoelectric conversion efficiency of 20.69%.
  • This embodiment provides a gallium oxide passivated N-type crystalline silicon double-sided solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 1 is that the gallium oxide in the solar cell provided in this embodiment
  • the thickness of the layer is 120 nm.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example was tested, and the results were: an open circuit voltage of 0.667V, a short-circuit current of 9.58A, and a photoelectric conversion efficiency of 19.87%.
  • This comparative example provides an N-type crystalline silicon double-sided solar cell without a gallium oxide layer.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 1 in that the solar cell provided in this comparative example is not Set the gallium oxide layer.
  • a silicon nitride film is formed directly on the emitter layer.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.656V, a short-circuit current of 9.8A, and a photoelectric conversion efficiency of 20.78%.
  • This comparative example provides a zirconia passivated N-type crystalline silicon double-sided solar cell.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 1 in that the solar cell provided in this comparative example uses oxidation.
  • a zirconium (ZrO x ) film replaces a gallium oxide film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.658V, a short-circuit current of 9.62A, and a photoelectric conversion efficiency of 20.47%.
  • This comparative example provides a tantalum oxide passivated N-type crystalline silicon double-sided solar cell.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 1 in that the solar cell provided in this comparative example uses oxidation.
  • a tantalum (TaO x ) film replaces a gallium oxide film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.66V, a short-circuit current of 9.68A, and a photoelectric conversion efficiency of 20.66%.
  • This comparative example provides an N-type crystalline silicon double-sided solar cell passivated with hafnium oxide.
  • the difference between the solar cell provided in this comparative example and the solar cell provided in Example 1 is that the solar cell provided in this comparative example uses oxidation.
  • a hafnium (HfO x ) film replaces a gallium oxide film.
  • the performance of the solar cell provided in this example was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.665V, a short-circuit current of 9.73A, and a photoelectric conversion efficiency of 20.92%.
  • Table 1 summarizes the performance test results of the solar cells of Examples 1 to 5 and Comparative Examples 1 to 4 above.
  • Example 1 Gallium oxide 20 nm 0.668V 9.77A 21.1%
  • Example 2 Gallium oxide 1 nanometer 0.661V 9.79A 20.92%
  • Example 3 Gallium oxide 40 nm 0.668V 9.75A 21.06%
  • Example 4 Gallium oxide 80 nm 0.668V 9.73A 20.69%
  • Example 5 Gallium oxide 120 nm 0.667V 9.58A 19.87% Comparative Example 1 —— ——— 0.656V 9.8A 20.78% Comparative Example 2 Zirconia 20 nm 0.658V 9.62A 20.47% Comparative Example 3 Tantalum oxide 20 nm 0.66V 9.68A 20.66% Comparative Example 4 Thorium oxide 20 nm 0.665V 9.73A 20.92%
  • the solar cell includes a front electrode, a front cover layer, a gallium oxide layer, an emitter layer, and an N-type electrode, which are arranged in order from the front to the back.
  • the N-type crystalline silicon substrate is an N-type single crystal silicon wafer having a resistivity of 2.0 ⁇ ⁇ cm and a size of 156.75 mm ⁇ 156.75 mm.
  • the emitter layer is formed by the boron diffusion of the furnace tube, and the block resistance value after the doping is 80 ⁇ / ⁇ .
  • the thickness of the gallium oxide layer is 20 nanometers.
  • the front cover layer is a silicon nitride layer with a thickness of 65 nanometers.
  • the thickness of the tunneling passivation layer is 1.8 nm
  • the thickness of the doped polysilicon layer is 100 nanometers, which is doped with phosphorus, and the square resistance after doping is 38 ⁇ / ⁇ .
  • the back passivation layer is a silicon nitride layer with a thickness of 70 nm.
  • the front electrode and the back electrode are both grid lines. Among them, there are 4 main grid lines with a width of 1.1 mm, and 102 sub grid lines with a width of 40 ⁇ m. The distance between two adjacent sub grid lines is 1.5 mm.
  • the electrode is formed of Heraeus SOL9360 type silver paste, and the back electrode is formed of Heraeus SOL9621 type silver paste.
  • step 601 a mixed aqueous solution of NaOH and H 2 O 2 (NaOH, H 2 O 2 and H 2 O are mixed at a mass ratio of 0.5%: 1%: 98.5%) is used to clean the N-type single crystal silicon wafer (washing The time is 2 minutes), and then the front surface of the N-type single crystal silicon wafer is flocked with a 3% sodium hydroxide aqueous solution by mass concentration. After the texturing, the reflectance of the front surface of the N-type single crystal silicon wafer is 12%.
  • the emitter layer is formed by boron doping on the front face of the N-type single crystal silicon wafer after the texturing by the boron diffusion method of the furnace tube to form a PN junction.
  • the tube boron diffusion using Tempress's TS-81255 type diffusion furnace diffusion conditions were as follows: BBr 3 as a boron source, at 940 °C diffusion into BBr the furnace quartz tube 3 (into time 20min), After that, the introduction of BBr 3 was stopped and the temperature was kept at 960 ° C for 20 minutes.
  • step 603 the diffused N-type single crystal silicon wafer is immersed in a TMAH solution at 40 ° C and a mass concentration of 20% for 30 seconds, the back surface of the N-type single crystal silicon wafer is flattened, and a The silicon wafer was washed with an HF aqueous solution for 2 min.
  • a tunneling passivation layer is grown on the back surface of the N-type single crystal silicon wafer by a thermal oxidation method.
  • the specific process parameters are: in an oxygen atmosphere, the heating temperature is 610 ° C and the heating time is 2 minutes.
  • an intrinsic polysilicon layer is grown on the tunneling passivation layer by the LPCVD method, and the intrinsic polycrystalline layer is doped with phosphorus by means of phosphorus ion implantation to form a doped polysilicon layer.
  • the equipment for growing the intrinsic polysilicon layer is a 997-AAK type LPCVD equipment from Temples Company.
  • the growth conditions are: the temperature is 600 ° C., the volume flow of SiH 4 is 600 sccm, and the pressure is 0.25 Torr.
  • Phosphorus ion implantation equipment is Springfield's iPV-2000 ion implanter.
  • the implantation conditions are: 10kV ion acceleration voltage, 120mA beam current after acceleration, and vacuum degree of ion implantation chamber 2 ⁇ 10 -5 Torr.
  • a PEALD method is used to deposit a gallium oxide thin film on the emitter.
  • the equipment used is a TFS200 atomic layer deposition thin film system from Beneq of Finland.
  • the deposition conditions are: a temperature of 75 ° C and a pressure of 0.25 Torr.
  • the volume flow rate of methyl gallium (TMGa) was 70 sccm (standard state ml / min), and the volume flow rate of O 2 was 200 sccm.
  • a PECVD method is used to form a silicon nitride film on the emitter layer and the doped polysilicon layer.
  • the equipment used is a SINA type PECVD equipment from ROTH & RAU Company, and the deposition conditions are: temperature 400 ° C, pressure 0.25mBar, SiH
  • the volume flow rate of 4 is 100 sccm
  • the volume flow rate of NH 3 is 180 sccm.
  • step 608 the paste for forming the back electrode is screen-printed, and the screen printer used is a Baccini speedy thinking printer of Applied Materials.
  • Step 609 screen printing a paste for forming a front electrode.
  • step 610 sintering is performed at a temperature of 820 ° C for 10 seconds. After sintering, the front metal silver passes through the silicon nitride / gallium oxide film to form local ohmic contact with the emitter, and the back silver paste corrodes the silicon nitride film and The doped polysilicon layer forms an ohmic contact.
  • the performance of the solar cell provided in this example was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.689V, a short-circuit current of 9.98A, and a photoelectric conversion efficiency of 22.23%.
  • This embodiment provides a gallium oxide passivated Topcon solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in embodiment 6 is that the thickness of the gallium oxide layer in the solar cell provided in this embodiment is 1 Nanometer.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example was tested, and the results were: an open-circuit voltage of 0.687V, a short-circuit current of 9.99A, and a photoelectric conversion efficiency of 22.19%.
  • This embodiment provides a gallium oxide passivated Topcon solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Example 6 is that the thickness of the gallium oxide layer in the solar cell provided in this embodiment is 40. Nanometer.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.688V, a short-circuit current of 9.896A, and a photoelectric conversion efficiency of 22.01%.
  • This embodiment provides a gallium oxide passivated Topcon solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Example 6 is that the thickness of the gallium oxide layer in the solar cell provided in this embodiment is 80 Nanometer.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: open circuit voltage 0.688V, short-circuit current 9.73A, and photoelectric conversion efficiency 21.64%.
  • This embodiment provides a gallium oxide passivated Topcon solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Example 6 is that the thickness of the gallium oxide layer in the solar cell provided in this embodiment is 120. Nanometer.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.688V, a short-circuit current of 9.48A, and a photoelectric conversion efficiency of 20.77%.
  • This comparative example provides a Topcon solar cell without a gallium oxide layer.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 6 in that the solar cell provided in this comparative example is not provided with a gallium oxide layer.
  • a silicon nitride film is formed directly on the emitter layer.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example is tested, and the results are: open circuit voltage 0.682V, short-circuit current 9.99A, and photoelectric conversion efficiency 22.03%.
  • This comparative example provides a zirconia passivated Topcon solar cell.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 6 in that the solar cell provided in this comparative example uses zirconia (ZrO x ).
  • the film replaces the gallium oxide film.
  • a zirconia film is formed on the emitter layer, and then a silicon nitride film is formed on the zirconia film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.680V, a short-circuit current of 9.86A, and a photoelectric conversion efficiency of 21.68%.
  • This comparative example provides a tantalum oxide passivated Topcon solar cell.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 6 in that the solar cell provided in this comparative example uses tantalum oxide (TaO x ).
  • the film replaces the gallium oxide film.
  • a tantalum oxide film is formed on the emitter layer, and then a silicon nitride film is formed on the tantalum oxide film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: open circuit voltage 0.682V, short circuit current 9.97A, and photoelectric conversion efficiency 21.99%.
  • This comparative example provides a thorium oxide passivated Topcon solar cell.
  • the difference between the solar cell provided in this comparative example and the solar cell provided in Example 6 is that hafnium oxide (HfO x ) is used in the solar cell provided in this comparative example.
  • the film replaces the gallium oxide film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open-circuit voltage of 0.684V, a short-circuit current of 9.95A, and a photoelectric conversion efficiency of 22.0%.
  • Table 2 summarizes the performance test results of the solar cells of Examples 6 to 10 and Comparative Examples 5 to 8 above.
  • the solar cell includes a front electrode, a front cover layer, an emitter layer, P-type crystalline silicon substrate, gallium oxide layer, back cover layer and back electrode.
  • the P-type crystalline silicon substrate is a P-type single crystal silicon wafer having a resistivity of 2.0 ⁇ ⁇ cm and a size of 156.75 mm ⁇ 156.75 mm.
  • the thickness of the gallium oxide layer is 40 nanometers.
  • the back cover layer is a silicon nitride layer with a thickness of 70 nanometers.
  • the gallium oxide layer and the back cover layer are respectively provided with 142 ⁇ 142 circular vias (that is, 142 per row, a total of 142 rows).
  • the via diameter is 50 ⁇ m, and the distance between two adjacent vias (the center of the circle) Distance) is 1100 microns.
  • the back electrode consists of a first part and a second part.
  • the first part is linear and is used for conductive buses and string welding of solar cells. It is formed by DuPont's PV56x silver paste. The number is 4 and the width is 1.6mm.
  • the second part is an aluminum electrode formed by Duupant's PV36x aluminum paste, which covers all areas except the first part on the back cover, and the second part passes through the via to contact the P-type crystalline silicon substrate. .
  • the front electrode is a gate line structure, which is formed by Heraeus SOL9621 type silver paste, in which there are 4 main gate lines with a width of 1.1 mm, and 102 sub-gate lines with a width of 40 ⁇ m and a pitch of 1.5 mm.
  • the front cover layer is a silicon nitride layer with a thickness of 80 nanometers.
  • the emitter layer is formed by phosphorus diffusion in the furnace tube, and the block resistance value after doping is 100 ⁇ / ⁇ .
  • Step 1101 using a mixed aqueous solution of NaOH and H 2 O 2 (NaOH, H 2 O 2 and H 2 O mixed at a mass ratio of 0.5%: 1%: 98.5%) to clean the P-type single crystal silicon wafer (washing The time is 2 minutes), and then the front surface of the P-type single crystal silicon wafer is made of wool with a 3% sodium hydroxide aqueous solution. After the texturing, the reflectance of the front surface of the P-type single crystal silicon wafer is 12%.
  • a phosphor is doped on the front surface of the P-type single crystal silicon wafer after the texturing to prepare an emitter by a method of phosphor diffusion of a furnace tube to form a PN junction.
  • a method of phosphor diffusion of a furnace tube to form a PN junction a phosphor is doped on the front surface of the P-type single crystal silicon wafer after the texturing to prepare an emitter by a method of phosphor diffusion of a furnace tube to form a PN junction.
  • dispersion conditions were as follows: POCl 3 as a phosphorus source, into POCl 3 (into time 20min) at 820 °C into the quartz tube, after stopping Pass in POCl 3 and incubate for 20 min at 840 ° C.
  • step 1103 the diffused P-type single crystal silicon wafer is immersed in a TMAH solution at 70 ° C and a mass concentration of 20% for 5 minutes, and the back surface of the N-type single crystal silicon wafer is flattened.
  • the silicon wafer was washed with an HF aqueous solution for 2 min.
  • Step 1104 the PEALD method is used to deposit a gallium oxide thin film on the back surface of the P-type single crystal silicon wafer.
  • the equipment used is a TFS 200 atomic layer deposition thin film system from Beneq, Finland.
  • the deposition conditions are: temperature is 75 ° C, pressure
  • the volume flow rate of trimethyl gallium (TMGa) was 0.25 Torr
  • the volume flow rate of O 2 was 200 sccm (standard state ml / min).
  • a PECVD method is used to form a silicon nitride film on the emitter layer on the front side of the P-type single crystal silicon wafer and on the gallium oxide film on the back side.
  • the equipment used is a SINA type PECVD equipment from ROTH & RAU.
  • the deposition conditions are: At 400 ° C, the pressure is 0.25 mBar, the volume flow rate of SiH 4 is 100 sccm, and the volume flow rate of NH 3 is 180 sccm.
  • step 1106 a laser is used to make holes in the gallium oxide / silicon nitride stacked structure on the back of the P-type single crystal silicon wafer.
  • step 1107 screen printing is used to form the paste of the first part of the back electrode.
  • the screen printing machine used is a Baccini speedy thinking printing machine of Applied Materials.
  • Step 1108 screen printing a paste for forming a second portion of the back electrode.
  • step 1109 a paste for forming a front electrode is screen-printed.
  • step 1110 sintering is performed at a temperature of 790 ° C for 10 seconds. After the sintering, the front part of the metallic silver is partially burned through the silicon nitride film to form an ohmic contact with the emitter, and the back aluminum particles and the silicon substrate corresponding to the via area Formation of aluminum-silicon alloy and aluminum back field.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.668V, a short-circuit current of 9.71A, and a photoelectric conversion efficiency of 20.73%.
  • This embodiment provides a gallium oxide passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the structure of the solar cell is different from that of the solar cell provided in Example 11 in that the back cover layer A part of the area is not covered by the second part of the back electrode formed of the aluminum paste.
  • the second part of the back electrode is linear, with a total of 102 pieces.
  • the width of each second part is 70 microns, and the distance between two adjacent second parts is 1.1 mm.
  • the first part of the weld is vertical.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.668V, a short-circuit current of 9.78A, and a photoelectric conversion efficiency of 20.83%.
  • This embodiment provides a gallium oxide passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Example 12 is that the solar cell provided in this embodiment is oxidized.
  • the thickness of the gallium layer is 1 nanometer.
  • the performance of the solar cell provided in this example was tested according to the test method and test conditions of Example 1. The results were: open circuit voltage 0.647V, short-circuit current 9.1A, and photoelectric conversion efficiency 19.04%.
  • This embodiment provides a gallium oxide passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Example 12 is that the solar cell provided in this embodiment is oxidized.
  • the thickness of the gallium layer is 80 nanometers.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open-circuit voltage of 0.667V, a short-circuit current of 9.7A, and a photoelectric conversion efficiency of 20.60%.
  • This embodiment provides a gallium oxide passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Example 12 is that the solar cell provided in this embodiment is oxidized.
  • the thickness of the gallium layer is 200 nm.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.666V, a short-circuit current of 9.68A, and a photoelectric conversion efficiency of 20.39%.
  • This embodiment provides a gallium oxide passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Example 12 is that the solar cell provided in this embodiment is oxidized.
  • the thickness of the gallium layer is 500 nanometers.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example was tested, and the results were: an open circuit voltage of 0.663V, a short-circuit current of 9.51A, and a photoelectric conversion efficiency of 19.48%.
  • This embodiment provides a gallium oxide passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Example 12 is that the solar cell provided in this embodiment is oxidized.
  • the thickness of the gallium layer is 1000 nanometers.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.660V, a short-circuit current of 9.52A, and a photoelectric conversion efficiency of 18.82%.
  • This comparative example provides a crystalline silicon PERC local aluminum back-field solar cell without a gallium oxide layer.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 12 in that the solar cell provided in this comparative example No gallium oxide layer is provided.
  • a silicon nitride film is formed directly on the back of a P-type single crystal silicon wafer.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example was tested, and the results were: an open circuit voltage of 0.642V, a short-circuit current of 8.50A, and a photoelectric conversion efficiency of 17.29%.
  • This comparative example provides a zirconia-passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the difference between the solar cell provided in this comparative example and the solar cell provided in Example 12 is that the solar cell provided in this comparative example is used in the solar cell provided in this comparative example.
  • a zirconia (ZrO x ) film replaces a gallium oxide film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: open circuit voltage 0.658V, short-circuit current 9.53A, and photoelectric conversion efficiency 20.04%.
  • This comparative example provides a tantalum oxide passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the difference between the solar cell provided in this comparative example and the solar cell provided in Example 12 is that the solar cell provided in this comparative example is used in the solar cell provided in this comparative example.
  • a tantalum oxide (TaO x ) film replaces a gallium oxide film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.660V, a short-circuit current of 9.63A, and a photoelectric conversion efficiency of 20.32%.
  • This comparative example provides a hafnium oxide-passivated crystalline silicon PERC local aluminum back-field solar cell.
  • the difference between the solar cell provided in this comparative example and the solar cell provided in Example 12 is that the solar cell provided in this comparative example is used in the solar cell provided in this comparative example.
  • a hafnium oxide (HfO x ) film replaces a gallium oxide film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.665V, a short-circuit current of 9.65A, and a photoelectric conversion efficiency of 20.51%.
  • Table 3 summarizes the performance test results of the solar cells of Examples 11 to 17 and Comparative Examples 9 to 12 above.
  • the solar cell includes a P-type crystalline silicon substrate, an emitter layer disposed on the front surface of the P-type crystalline silicon substrate, and an emitter layer A front cover layer on the electrode layer, a front electrode provided on the front cover layer, a backside tunneling passivation layer provided on the backside of the P-type crystalline silicon substrate, and a boron provided on the backside tunneling passivation layer in a region corresponding to the backside electrode
  • the P-type crystalline silicon substrate is a P-type single crystal silicon wafer having a resistivity of 2.0 ⁇ ⁇ cm and a size of 156.75 mm ⁇ 156.75 mm;
  • the square resistance of the emitter layer is 80 ⁇ / ⁇ ;
  • the front cover layer is a silicon nitride layer with a thickness of 80 nanometers
  • the front electrode is a gate line structure, which is formed by Heraeus SOL9621 type silver paste, in which there are 4 main gate lines with a width of 1.1 mm, 102 sub-gate lines with a width of 40 ⁇ m and a pitch of 1.5 mm;
  • the back-side tunneling passivation layer is a silicon oxide layer with a thickness of 1.9 nm;
  • the thickness of the back doped polysilicon layer is 200 nm
  • the thickness of the gallium oxide layer is 20 nanometers
  • the back cover layer is a silicon nitride layer with a thickness of 80 nanometers
  • the back electrode is also a gate line structure, which is formed by Heraeus SOL9360 type silver paste, in which there are 4 main gate lines with a width of 1.1 mm, 102 auxiliary gate lines with a width of 40 ⁇ m and a pitch of 1.5 mm;
  • Step 1801 using a mixed aqueous solution of NaOH and H 2 O 2 (NaOH, H 2 O 2 and H 2 O are mixed at a mass ratio of 0.5%: 1%: 98.5%) to clean the P-type single crystal silicon wafer (washing The time is 2 minutes), and then the front surface of the P-type single crystal silicon wafer is made of 3% sodium hydroxide aqueous solution, and the reflectance of the front surface of the P-type single crystal silicon wafer is 12%.
  • step 1802 phosphorescent doping is performed on the front face of the P-type single-crystal silicon wafer after the texturing by the furnace tube phosphorus diffusion method to form an PN junction.
  • the tube phosphorus diffusion using SevenStart's L4511II-40 / ZM-type diffusion apparatus diffusion conditions were as follows: POCl 3 as a phosphorus source, into POCl into the quartz tube at 820 °C 3 (passed through 20 minutes), then The introduction of POCl 3 was stopped and the temperature was maintained at 840 ° C for 20 minutes.
  • Step 1803 soaking the diffused P-type single-crystal silicon wafer in a TMAH solution at 70 ° C. and a mass concentration of 20% for 5 minutes, smoothing the back surface of the P-type single-crystal silicon wafer, and then using a mass concentration of 10%
  • the wafer was washed with an aqueous HF solution for 2 minutes.
  • Step 1804 using a furnace tube thermal oxidation method to grow a silicon oxide film on the back surface of the P-type single crystal silicon wafer as a back-channel tunneling passivation layer.
  • the process conditions are: in an oxygen atmosphere, the heating temperature is 610 ° C and the heating time is 2 minutes. .
  • step 1805 an intrinsic polysilicon thin film is grown on the backside tunneling passivation layer by the LPCVD method, and boron doping is performed on the intrinsic polycrystalline thin film by means of boron ion implantation to form a backside doped polysilicon layer.
  • the equipment for growing polysilicon thin film is 997-AAK type LPCVD equipment of Tempress Company.
  • the growth conditions are: the temperature is 600 ° C, the volume flow of SiH 4 is 600 sccm, and the pressure is 0.25 Torr.
  • the boron ion implantation equipment is Springfield's iPV-2000 ion implanter.
  • the implantation conditions are: 10kV ion acceleration voltage, 120mA beam current after acceleration, and 2 ⁇ 10 -5 Torr vacuum of ion implantation chamber.
  • step 1806 the area corresponding to the back doped polysilicon layer and the back electrode is irradiated with laser scanning, and a BSG protective layer is formed in the area corresponding to the back doped polysilicon layer and the back electrode.
  • the laser scanning pattern is the same as the back electrode pattern.
  • the laser used is a nanosecond laser with a laser energy of 20 watts.
  • Step 1807 using an alkaline solution to remove an area of the back doped polysilicon layer that is not covered by the BSG protective layer, to form a back doped polysilicon layer with the same back electrode pattern (where the alkali solution is a 7% mass concentration tetramethylammonium hydroxide solution). , Wash at 50 degrees Celsius for 5 minutes), and then use hydrofluoric acid to remove the BSG protective layer (wherein the hydrofluoric acid concentration is 5%, and wash at room temperature for 2 minutes).
  • the alkali solution is a 7% mass concentration tetramethylammonium hydroxide solution
  • a gallium oxide thin film is formed on the back-doped polysilicon layer obtained in step 1807 and the back-channel tunneling passivation layer without the doped poly-silicon layer by using an atomic layer deposition process.
  • the deposition conditions are: the temperature is 75 ° C, and the pressure is 0.25 Torr, the volume flow rate of trimethylgallium (TMGa) was 70 sccm (milliliter / minute in the standard state), and the volume flow rate of O 2 was 200 sccm.
  • a silicon nitride film is formed on the emitter layer and the gallium oxide layer.
  • the equipment used is a SINA type PECVD equipment from ROTH & RAU.
  • the deposition conditions are: temperature 400 ° C, pressure 0.25mBar, and volume flow rate of SiH 4 is 100 sccm.
  • the volume flow rate of NH 3 is 180 sccm.
  • a silver paste for forming a back electrode is screen-printed, and a screen printing machine used is a Baccini speedy thinking printing machine of Applied Materials (the same applies hereinafter).
  • Step 1811 screen printing a silver paste for forming a front electrode.
  • Step 1812 sintering at a temperature of 820 ° C for 10 seconds; during the sintering process, the front silver paste corrodes the front silicon nitride layer so that the front silver electrode passes through the front silicon nitride layer and forms an ohmic contact with the emitter layer
  • the back silver paste corrodes the silicon nitride cover layer 5 and the gallium oxide layer 4 so that the back metal electrode passes through the silicon nitride / gallium oxide stacked structure and forms an ohmic contact with the boron-doped polysilicon layer.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were as follows: the open-circuit voltage was 0.668V, the short-circuit current was 9.74A, and the photoelectric conversion efficiency was 20.76%.
  • This embodiment provides a crystalline silicon solar cell using gallium oxide passivation.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 18 is the thickness of the gallium oxide layer in the solar cell provided in this embodiment. 10 nm.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.660V, a short-circuit current of 9.72A, and a photoelectric conversion efficiency of 20.24%.
  • This embodiment provides a crystalline silicon solar cell using gallium oxide passivation.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 18 is the thickness of the gallium oxide layer in the solar cell provided in this embodiment. 40 nm.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example was tested, and the results were: an open circuit voltage of 0.669V, a short-circuit current of 9.81A, and a photoelectric conversion efficiency of 20.87%.
  • This embodiment provides a crystalline silicon solar cell using gallium oxide passivation.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 18 is the thickness of the gallium oxide layer in the solar cell provided in this embodiment. It is 60 nm.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.669V, a short-circuit current of 9.79A, and a photoelectric conversion efficiency of 20.68%.
  • This embodiment provides a crystalline silicon solar cell using gallium oxide passivation.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 18 is the thickness of the gallium oxide layer in the solar cell provided in this embodiment. It is 75 nm.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example was tested, and the results were: an open circuit voltage of 0.668V, a short-circuit current of 9.78A, and a photoelectric conversion efficiency of 20.58%.
  • This embodiment provides a crystalline silicon solar cell using gallium oxide passivation.
  • the difference between the solar cell provided in this embodiment and the solar cell provided in Embodiment 18 is the thickness of the gallium oxide layer in the solar cell provided in this embodiment. It is 90 nm.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.668V, a short-circuit current of 9.78A, and a photoelectric conversion efficiency of 20.49%.
  • This comparative example provides a crystalline silicon solar cell without a gallium oxide layer.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 18 in that the solar cell provided in this comparative example is not provided with a gallium oxide layer. .
  • a silicon nitride film is formed directly on the backside of the P-type crystalline silicon substrate on the backside doped polysilicon layer and on the backside tunneling passivation layer where the doped polysilicon layer is not provided as a backside cover layer.
  • Example 1 According to the test method and test conditions of Example 1, the performance of the solar cell provided in this example was tested, and the results were: an open circuit voltage of 0.642V, a short-circuit current of 8.5A, and a photoelectric conversion efficiency of 17.29%.
  • This comparative example provides a crystalline silicon solar cell using zirconium oxide (ZrO x ) passivation.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 18 in that the solar cell provided in this comparative example is used in Zirconia film replaces gallium oxide film.
  • a zirconia thin film is formed on the backside of the P-type crystalline silicon substrate with a doped polysilicon layer on the back and a region where the backside tunneling passivation layer is not provided with a doped polysilicon layer, and then nitrided on the zirconia film Silicon thin film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.660 V, a short-circuit current of 9.54 A, and a photoelectric conversion efficiency of 20.08%.
  • This comparative example provides a crystalline silicon solar cell using tantalum oxide (TaO x ) passivation.
  • the solar cell provided in this comparative example is different from the solar cell provided in Example 18 in that the solar cell provided in this comparative example is used in Tantalum oxide film replaces gallium oxide film.
  • a tantalum oxide film is first formed on the backside of the P-type crystalline silicon substrate with a doped polysilicon layer on the back and a region where the backside tunneling passivation layer is not provided with a doped polysilicon layer, and then nitrided on the zirconia film Silicon thin film.
  • the performance of the solar cell provided in this example was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.661V, a short-circuit current of 9.64A, and a photoelectric conversion efficiency of 20.39%.
  • This comparative example provides a crystalline silicon solar cell using hafnium oxide (HfO x ) passivation.
  • the difference between the solar cell provided in this comparative example and the solar cell provided in Example 18 is that the solar cell provided in this comparative example is used in the solar cell provided in this comparative example.
  • the hafnium oxide film replaces the gallium oxide film.
  • a hafnium oxide film is first formed on the backside of the P-type crystalline silicon substrate with a doped polysilicon layer on the backside and a region where the backside tunneling passivation layer is not provided with a doped polysilicon layer, and then a nitride is formed on the hafnium oxide film. Silicon thin film.
  • the performance of the solar cell provided in this embodiment was tested according to the test method and test conditions of Example 1. The results were: an open circuit voltage of 0.668V, a short-circuit current of 9.67A, and a photoelectric conversion efficiency of 20.62%.
  • Table 4 summarizes the performance test results of the solar cells of Examples 18 to 23 and Comparative Examples 13 to 16 above.
  • Comparative Example 13 —— ——— 0.642V 8.5A 17.29% Comparative Example 14 Zirconia 20 nm 0.660V 9.54A 20.08% Comparative Example 15 Tantalum oxide 20 nm 0.661V 9.64A 20.39% Comparative Example 16 Thorium oxide 20 nm 0.668V 9.67A 20.62%

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Abstract

本公开涉及一种晶体硅太阳能电池及制备方法、光伏组件，属于太阳能电池技术领域。该晶体硅太阳能电池包括与所述晶体硅太阳能电池中P型硅层直接接触的氧化镓层。本公开中，通过在晶体硅太阳能电池的P型硅层上设置与P型硅层直接接触的氧化镓层，利用氧化镓层所带有的负电荷对P型硅层的表面进行化学钝化和场钝化，降低P型硅层表面的硅原子的悬挂键和少数载流子数量，从而降低P型硅层表面处的少数载流子复合速率，提高太阳能电池的电压与电流，提升太阳能电池的光电转换效率，进而提高光伏组件的输出功率，降低度电成本，提高光伏发电的性价比。并且，氧化镓层还具有较宽的带隙与合适的光学折射系数，也有利于提高晶体硅太阳能电池的性能。

Description

晶体硅太阳能电池及其制备方法、光伏组件
本公开要求以下专利申请的优先权：
于2018年6月22日提交中国国家知识产权局，申请号为201810649226.2，发明名称为“N型晶体硅太阳能电池及制备方法、光伏组件”的中国专利申请；
于2018年6月22日提交中国国家知识产权局，申请号为201810649228.1，发明名称为“P型晶体硅太阳能电池及制备方法、光伏组件”的中国专利申请；
于2018年10月19日提交中国国家知识产权局，申请号为201811223037.5，发明名称为“硅基太阳能电池及制备方法、光伏组件”的中国专利申请；
其全部内容通过引用结合在本公开中。
技术领域
本公开涉及太阳能电池技术领域，具体涉及一种晶体硅太阳能电池及其制备方法、光伏组件。
背景技术
光伏发电，即直接将太阳能转化为电能，是一种清洁、可持续性和性价比相对较高的发电方式。晶体硅太阳能电池是光伏发电系统的重要组成部分，晶体硅太阳能电池的光电转换效率对光伏发电的输出功率及度电成本有重要影响。
一般来说，晶体硅太阳能电池主要包括依次设置的正面电极、正面钝化层、发射极、晶体硅基体、背面钝化层以及背面电极。其中，晶体硅基体按照导电类型分类可以是P型的晶体硅基体，也可以是N型的晶体硅基体。正面钝化层及背面钝化层的材料通常为氧化硅、碳化硅、氮化硅、氮氧化硅等。
现有的晶体硅太阳能电池中少数载流子复合速率较高，限制了太阳能电池光电转换效率。
公开内容
本公开实施例提供一种能够解决上述晶体硅太阳能电池中少数载流子复合速率较高的问题的晶体硅太阳能电池及制备方法，本公开实施例还提供了基于该晶体硅太阳能电池的光伏组件，以及氧化镓在晶体硅太阳能电池中作为钝化物或钝化结构的应用。
具体而言，包括以下的技术方案。
第一方面，本公开实施例提供了一种晶体硅太阳能电池，包括与所述晶体硅太阳能电池中P型硅层直接接触的氧化镓层。
可选地，所述晶体硅太阳能电池包括：导电类型为N型的晶体硅基体，及设置在所述晶体硅基体一侧表面、且导电类型为P型的发射极层；所述氧化镓层设置在所述发射极层上且与所述发射极层直接接触。
可选地，所述晶体硅太阳能电池还包括：设置在所述氧化镓层上的第一覆盖层，设置在所述第一覆盖层上、且与所述发射极层接触的第一电极，设置在所述晶体硅基体与所述发射极层相对一侧表面、且导电类型为N型的表面场层，设置在所述表面场层上的第二覆盖层，以及，设置在所述第二覆盖层上、且与所述表面场层接触的第二电极。
可选地，所述晶体硅太阳能电池还包括：设置在所述氧化镓层上的第一覆盖层，设置在所述第一覆盖层上、且与所述发射极层接触的第一电极，设置在所述晶体硅基体与所述发射极层相对一侧表面的隧穿钝化层，设置在所述隧穿钝化层上、且导电类型为N型的掺杂硅层，设置在所述掺杂硅层上的第二覆盖层，以及，设置在所述第二覆盖层上、且与所述掺杂硅层接触的第二电极。
可选地，所述掺杂硅层覆盖所述隧穿钝化层的局部区域，所述隧穿钝化层未设置所述掺杂硅层的区域上也设置有所述第二覆盖层。
可选地，所述氧化镓层的厚度为1纳米～120纳米。
可选地，所述氧化镓层的厚度为10纳米～60纳米。
可选地，所述氧化镓层的厚度为20纳米～40纳米。
可选地，所述晶体硅太阳能电池包括：导电类型为P型的晶体硅基体；所述氧化镓层设置在所述晶体硅基体一侧表面上且与所述晶体硅基体直接接触。
可选地，所述晶体硅太阳能电池还包括：设置在所述氧化镓层上的第三覆盖层，设置在所述第三覆盖层上、且与所述晶体硅基体接触的第三电极，设置在所述晶体硅基体与所述氧化镓层相对一侧表面、且导电类型为N型的发射极层，设置在所述发射极层上的第四覆盖层，以及，设置在所述第四覆盖层上、且与所述发射极层接触的第四电极。
可选地，所述晶体硅太阳能电池还包括：设置在所述氧化镓层上的第三覆盖层设置在所述第三覆盖层上、且与所述晶体硅基体接触的第三电极，设置在所述晶体硅基体与所述氧化镓层相对一侧表面、且导电类型为N型的发射极层，设置在所述发射极层上的隧穿钝化层，设置在所述隧穿钝化层上、且导电类型为N型的掺杂硅层，设置在所述掺杂硅层上的第四覆盖层，以及，设置在所述第四覆盖层上、且与所述掺杂硅层接触的第四电极；
可选地，所述掺杂硅层覆盖所述隧穿钝化层的局部区域，所述隧穿钝化层未设置所述掺杂硅层的区域上也设置有所述第四覆盖层。
可选地，所述氧化镓层和所述第三覆盖层上对应设置有过孔；所述晶体硅基体表面与所述过孔对应的区域形成有导电类型为P型的表面场层。
可选地，所述第三电极包括第一部分和第二部分，所述第一部分呈线形，所述第二部分设置在所述第三覆盖层上位于所述第一部分以外的区域，且所述第二部分与所述第一部分接触；所述第二部分通过所述过孔与所述晶体硅基体接触，并在所述晶体硅基体表面与所述过孔对应的区域形成所述表面场层。
可选地，所述氧化镓层的厚度为1纳米～1000纳米。
可选地，所述氧化镓层的厚度为2纳米～150纳米。
可选地，所述氧化镓层的厚度为5纳米～60纳米。
可选地，所述晶体硅太阳能电池包括：导电类型为P型的晶体硅基体，设置在所述晶体硅基体一侧表面的第一隧穿钝化层，设置在所述第一隧穿钝化层上、且导电类型为P型的第一掺杂硅层，设置在所述第一掺杂硅层上的氧化镓层，设置在所述氧化镓层上的第五覆盖层，以及，设置在所述第五覆盖层上、且与所述第一掺杂硅层接触的第五电极。
可选地，所述第一掺杂硅层覆盖所述第一隧穿钝化层的局部区域，所述第一隧穿钝化层未设置所述第一掺杂硅层的区域上也设置有所述氧化镓层。
可选地，所述晶体硅太阳能电池还包括：设置在所述晶体硅基体与所述第一隧穿钝化层相对一侧表面、且导电类型为N型的发射极层，设置在所述发射极层上的第六覆盖层，以及，设置在所述第六覆盖层上、且与所述发射极层接触的第六电极。
可选地，所述晶体硅太阳能电池还包括：设置在所述晶体硅基体与所述第一隧穿钝化层相对一侧表面、且导电类型为N型的发射极层，设置在所述发射极层上的第二隧穿钝化层，设置在所述第二隧穿钝化层上、且导电类型为N型的第二掺杂硅层，设置在所述第二掺杂硅层上的第六覆盖层，以及，设置在所述第六覆盖层上、且与所述第二掺杂硅层接触的第六电极。
可选地，所述第二掺杂硅层覆盖所述第二隧穿钝化层的局部区域，所述第二隧穿钝化层未设置所述第二掺杂硅层的区域上也设置有所述第六覆盖层。
可选地，所述氧化镓层的厚度为10纳米～90纳米。
第二方面，本公开实施例提供了一种光伏组件，该光伏组件包括依次设置的盖板、第一封装胶膜，电池串、第二封装胶膜和背板，所述电池串包括多个太阳能电池，所述太阳能电池为上述的晶体硅太阳能电池。
第三方面，本公开实施例提供了一种晶体硅太阳能电池的制备方法，该制备方法包括：形成与所述晶体硅太阳能电池中P型硅层直接接触的氧化镓层。
第四方面，本公开实施例提供了一种氧化镓在晶体硅太阳能电池中作为钝化物或钝化结构的应用。
可选地，所述氧化镓与所述晶体硅太阳能电池的P型硅层直接接触。
本公开实施例提供的技术方案的有益效果至少包括：
本公开实施例中，通过在晶体硅太阳能电池的P型硅层上设置与P型硅层直接接触的氧化镓层，利用氧化镓层所带有的负电荷对P型硅层的表面进行化学钝化和场钝化，降低P型硅层表面的硅原子的悬挂键和少数载流子数量，从而降低P型硅层表面处的少数载流子复合速率，提高太阳能电池的电压与电流，提升太阳能电池的光电转换效率，进而提高光伏组件的输出功率，降低度电成本，提高光伏发电的性价比。并且，氧化镓层还具有较宽的带隙与合适的光学折射系数，也有利于提高晶体硅太阳能电池的性能。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1为本公开实施例提供的一种晶体硅太阳能电池的结构示意图；
图2为本公开实施例提供的一种包括导电类型为N型的晶体硅基体的晶体硅太阳能电池的结构示意图；
图3为本公开实施例提供的另一种包括导电类型为N型的晶体硅基体的晶体硅太阳能电池的结构示意图；
图4为本公开实施例提供的一种包括导电类型为P型的晶体硅基体的晶体硅太阳能电池的结构示意图；
图5为本公开实施例提供的另一种包括导电类型为P型的晶体硅基体的晶体硅太阳能电池的结构示意图；
图6为全铝背场背面电极的结构示意图；
图7为局部铝背场背面电极的结构示意图；
图8为本公开实施例提供的又一种包括导电类型为P型的晶体硅基体的晶体硅太阳能电池的结构示意图；
图9为本公开实施例提供的再一种包括导电类型为P型的晶体硅基体的晶体硅太阳能电池的结构示意图；
图10为本公开实施例提供的再一种包括导电类型为P型的晶体硅基体的晶体硅太阳能电池的结构示意图。
图中的附图标记分别表示：
1   晶体硅基体
2   发射极层
3   表面场层
41  第一覆盖层
42  第二覆盖层
43  第三覆盖层
44  第四覆盖层
45  第五覆盖层
46  第六覆盖层
51  第一电极
52  第二电极
53  第三电极
531 第三电极的第一部分
532 第三电极的第二部分
54  第四电极
55  第五电极
56  第六电极
6   隧穿钝化层
61  第一隧穿钝化层
62  第二隧穿钝化层
7   掺杂硅层
71  第一掺杂硅层
72  第二掺杂硅层
X   氧化镓层
O   过孔
具体实施方式
为使本公开的技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
除非另有定义，本公开实施例所用的所有技术术语均具有与本领域技术人员通常理解的相同的含义。
提高晶体硅太阳能电池的光电转换效率是提高光伏发电输出功率、降低度电成本的有效途径。目前，限制单节晶体硅太阳能电池光电转化效率的重要因素之一是太阳能电池中少数载流子的复合湮灭。少数载流子的复合湮灭会造成太阳能电池电压和电流的流失，从而降低电池的光电转换效率。在晶体硅表面存在大量的不饱和悬挂键，是很严重的复合中心。在硅片表面设置钝化层以钝化硅片表面，能够降低硅片表面少数载流子的复合概率，有利于提高太阳能电池的光电转化效率。
基于以上所述，本公开实施例提供了一种利用氧化镓(Gallium oxide，GaO x)钝化P型硅层表面的晶体硅太阳能电池及其制备方法，同时还提供基于该晶体硅太阳能电池的光伏组件以及氧化镓在晶体硅太阳能电池中作为钝化物或钝化结构的应用。
图1示出了一种本公开实施例提供的晶体硅太阳能电池的结构，如图1所示，本公开实施例提供的晶体硅太阳能电池包括与晶体硅太阳能电池中P型硅层直接接触的氧化镓层X。
氧化镓层X带有负电荷，能够对P型硅层表面进行化学钝化和场钝化，因此在P型硅层表面设置与P型硅层直接接触的氧化镓层X，可有效降低P型硅层表面的硅原子的悬挂键和少数载流子数量，从而降低P型硅层表面处的少数载流子复合速率，提高太阳能电池的电压与电流，提升太阳能电池的光电转换效率，进而提高光伏组件的输出功率，降低度电成本，提高光伏发电的性价比。并且，氧化镓层X还具有较宽的带隙与合适的光学折射系数，也有利于提高晶体硅太阳能电池的性能。
本公开实施例还提供了上述晶体硅太阳能电池的制备方法，具体来说，包括形成与晶体硅太阳能电池中P型硅层直接接触的氧化镓层X的步骤。
对于不同结构的晶体硅太阳能电池来说，其氧化镓层X设置的位置、氧化镓层X的厚度也有所不同。下面，结合具体的晶体硅太阳能电池结构，对本公开实施例提供的晶体硅太阳能电池的结构及其制备方法作进一步说明。
以下描述中使用的“第一”、“第二”、“第三”、“第四”、“第五”、“第六”等类似的词语并不表示任何顺序、数量或者重要性，只是用来区分不同的组成部分，以便于描述。
第一种可选的实施方式
图2示出了一种包括N型晶体硅基体的晶体硅太阳能电池的结构，如图2所示，该实施方式中提供的晶体硅太阳能电池包括：
导电类型为N型的晶体硅基体1，
设置在晶体硅基体1一侧表面、且导电类型为P型的发射极层2，
设置在发射极层2上且与发射极层2直接接触的氧化镓层X，
设置在氧化镓层X上的第一覆盖层41，
设置在第一覆盖层41上、且与发射极层2接触的第一电极51，
设置在晶体硅基体1与发射极层2相对一侧表面、且导电类型为N型的表面场层3，
设置在表面场层3上的第二覆盖层42，
以及，设置在第二覆盖层42上、且与表面场层3接触的第二电极52。
对于该实施方式提供的晶体硅太阳能电池来说，其P型硅层为设置在N型的晶体硅基体1一侧表面的 导电类型为P型的发射极层2，因此，该实施方式中，将氧化镓层X设置在发射极层2上。
该实施方式中，N型的晶体硅基体1可以为单晶硅，也可以为多晶硅，电阻率可以为0.1Ω·cm～10Ω·cm(例如0.1Ω·cm、0.2Ω·cm、0.3Ω·cm、0.4Ω·cm、0.5Ω·cm、0.6Ω·cm、0.7Ω·cm、0.8Ω·cm、0.9Ω·cm、1Ω·cm、2Ω·cm、3Ω·cm、4Ω·cm、5Ω·cm、6Ω·cm、7Ω·cm、8Ω·cm、9Ω·cm、10Ω·cm等)。
发射极层2可以位于晶体硅基体1的正面(即受光面)，也可以位于晶体硅基体1的背面(即背光面)，相应地，表面场层3可以位于晶体硅基体1的背面，也可以位于晶体硅基体1的正面。
发射极层2可采用P型掺杂元素(通常为第III族元素，包括但不限于硼)对N型的晶体硅基体1进行掺杂得到，其方块电阻值可以为40Ω/□～200Ω/□(例如40Ω/□、50Ω/□、60Ω/□、70Ω/□、80Ω/□、90Ω/□、100Ω/□、110Ω/□、120Ω/□、130Ω/□、140Ω/□、150Ω/□、160Ω/□、170Ω/□、180Ω/□、190Ω/□、200Ω/□等)。
表面场层3可采用N型掺杂元素(通常为第V族元素，包括但不限于磷)对N型的晶体硅基体1进行掺杂得到，其方块电阻可以为20Ω/□～500Ω/□，例如20Ω/□、30Ω/□、40Ω/□、50Ω/□、60Ω/□、70Ω/□、80Ω/□、90Ω/□、100Ω/□、150Ω/□、200Ω/□、250Ω/□、300Ω/□、350Ω/□、400Ω/□、450Ω/□、500Ω/□等。
进一步地，该实施方式中，氧化镓层X的厚度(即图2中T1所指示的尺寸)可以为1纳米～120纳米，例如1纳米、2纳米、3纳米、4纳米、5纳米、6纳米、7纳米、8纳米、9纳米、10纳米、15纳米、20纳米、25纳米、30纳米、35纳米、40纳米、45纳米、50纳米、55纳米、60纳米、65纳米、70纳米、75纳米、80纳米、85纳米、90纳米、95纳米、100纳米、105纳米、110纳米、115纳米、120纳米等。优选地，氧化镓层X的厚度可以为10纳米～60纳米；更优选地，氧化镓层X的厚度可以为20纳米～40纳米。
第一覆盖层41可以包括氮化硅(SiN x)层、氮氧化硅(SiO xN y)层、氧化硅(SiO x)层及碳化硅(SiC x)层中的至少一种，即可以为单独的氮化硅层、单独的氮氧化硅层、单独的氧化硅层或者单独的碳化硅层，也可以为氮化硅层、氮氧化硅层、氧化硅层和碳化硅层中两种或两种以上层叠设置。第一覆盖层41整体的厚度(即图2中T2所指示的厚度)可以为10纳米～120纳米，例如10纳米、15纳米、20纳米、25纳米、30纳米、35纳米、40纳米、45纳米、50纳米、60纳米、65纳米、70纳米、75纳米、80纳米、85纳米、90纳米、95纳米、100纳米、105纳米、110纳米、115纳米、120纳米等。当第一覆盖层41采用叠层结构时，每一层的厚度没有严格要求，可以根据需要进行设置，只要整体厚度满足要求即可。
第二覆盖层42包括氮化硅层、氮氧化硅层、氧化硅层及碳化硅层中的至少一种，即第二覆盖层42可以为单独的氮化硅层、单独的氮氧化硅层、单独的氧化硅层以及单独的碳化硅层，也可以为氮化硅层、氮氧化硅层、氧化硅层和碳化硅层中的两种或者两种以上层叠设置。第二覆盖层42整体的厚度(即图2中T3所指示的尺寸)可以为30纳米～200纳米，例如30纳米、35纳米、40纳米、45纳米、50纳米、55纳米、60纳米、65纳米、70纳米、75纳米、80纳米、85纳米、90纳米、95纳米、100纳米、105纳米、110纳米、115纳米、120纳米、125纳米、130纳米、135纳米。当第二覆盖层42采用叠层结构时，每一层的厚度没有严格要求，可根据需要进行设置，只要整体厚度满足要求即可。
第一电极51和第二电极52可以为金属电极(例如银电极)，相应地，第一电极51与发射极层2之间的接触为欧姆接触，第二电极52与表面场层3之间的接触为欧姆接触。
第一电极51和第二电极52均可采用栅线结构(包括主栅线和副栅线)的电极，从而实现双面发电。并且，发射极层2与第一电极51相对应的区域的方块电阻值可以大于其他区域的方块电阻值(即选择性发射极)，表面场层3与第二电极52相对应的区域的方块电阻值也可以大于其他区域的方块电阻值(即选择性表面场)，从而提升晶体硅太阳能电池的光电转换效率。
该实施方式提供的晶体硅太阳能电池的制备方法主要包括晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成表面场层3、形成氧化镓层X、形成第一覆盖层41和第二覆盖层42、形成第一电极51和第二电极52等步骤。
其中，对晶体硅基体1的正面进行清洗并制绒可降低反射率。可以用氢氧化钠(NaOH)和过氧化氢(H 2O 2)的混合水溶液对晶体硅基体1进行清洗，以去除表面污染物及损伤层。可以利用碱性腐蚀液进行制绒，也可利用酸性腐蚀液进行制绒，碱性腐蚀液可以为氢氧化钠水溶液。
对于N型的晶体硅基体1来说，制绒后单晶硅片表面的反射率可以为10％～18％(例如10％、11％、12％、13％、14％、15％、16％、17％、18％等)，多晶硅片表面的反射率可以为6％～20％(例如6％、7％、8％、9％、10％、11％、12％、13％、14％、15％、16％、17％、18％、19％、20％等)。
可通过扩散(例如炉管硼扩散)、沉积含掺杂源的掺杂层(例如硼硅玻璃BSG)并退火、或者离子注入(例如注入硼离子)并退火等方法来形成发射极层2。
可通过化学溶液对晶体硅基体1的背表面进行平整，以适当降低晶体硅基体1背表面的比表面积，之后再用氢氟酸(例如HF的水溶液)清洗晶硅体基体。其中，化学溶液可以为碱溶液，包括但不限于四甲基氢氧化铵(TMAH)溶液、氢氧化钠(NaOH)溶液、氢氧化钾(KOH)等，碱溶液的浓度可根据需要进行调整；也可以为酸溶液，例如硝酸(HNO 3)、氢氟酸(HF)和硫酸(H 2SO 4)的混合溶液，混合溶液中各酸液的浓度以及各酸液间的配比也可根据需要进行调整。
可通过扩散(例如炉管磷扩散)、沉积含掺杂源的掺杂层(例如磷硅玻璃PSG)并退火、或者离子注入(例如注入磷离子)并退火等方法来形成表面场层3。
氧化镓层X可通过单原子层沉积法(Atomic Layer Deposition，ALD)、等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)、常压化学气相沉积法(Atmospheric Chemical Vapor Deposition，APCVD)或者低压化学气相沉积法(Low Pressure Chemical Vapor Deposition，LPCVD)形成。氧化镓层X沉积完成之后，还可以进行退火步骤。
第一覆盖层41和第二覆盖层42也可通过ALD、PECVD、APCVD、LPCVD等方法形成。当第一覆盖层41和第二覆盖层42组成相同时，二者可同时形成。
第一电极51和第二电极52可通过丝网印刷电极浆料并快速高温烧结的方法来形成。烧结的温度可以为600℃～900℃(例如600℃、650℃、700℃、750℃、800℃、850℃、900℃等)，烧结的时间可以为10秒～3分钟，例如10秒、20秒、30秒、40秒、60秒、70秒、80秒、90秒、100秒、110秒、120秒、130秒、140秒、150秒、160秒、170秒、180秒等。
第二种可选的实施方式
图3示出了另一种包括N型晶体硅基体的晶体硅太阳能电池的结构，如图3所示，该实施方式中提供的晶体硅太阳能电池基于隧道氧化钝化接触电池(Tunnel Oxide Passivated Contact，TOP-Con)结构，具体包括：
导电类型为N型的晶体硅基体1，
设置在晶体硅基体1一侧表面、且导电类型为P型的发射极层2，
设置在发射极层2上且与发射极层2直接接触的氧化镓层X，
设置在氧化镓层X上的第一覆盖层41，
设置在第一覆盖层41上、且与发射极层2接触的第一电极51，
设置在晶体硅基体1与发射极层2相对一侧表面的隧穿钝化层6，
设置在隧穿钝化层6上、且导电类型为N型的掺杂硅层7，
设置在掺杂硅层7上的第二覆盖层42，以及，
设置在第二覆盖层42上、且与掺杂硅层7接触的第二电极52。
对于该实施方式提供的晶体硅太阳能电池来说，其P型硅层也为设置在N型的晶体硅基体1一侧表面的导电类型为P型的发射极层2，因此，该实施方式中，同样将氧化镓层X设置在发射极层2上。
该实施方式中，晶体硅基体1的电阻率、发射极层2的方块电阻值、氧化镓层X的厚度、第一覆盖层41的组成及厚度、以及第一电极51和第二电极52的具体形式可参考上述第一种可选的实施方式中的描述，在此不再赘述。
该实施方式中，掺杂硅层7具体可为掺杂多晶硅层或掺杂非晶硅层，或多晶硅和非晶硅的混合层。掺杂硅层7的掺杂源可以为第V族元素(包括但不限于磷)。掺杂硅层7的方块电阻可以为10Ω/□～1000Ω/□，例如10Ω/□、20Ω/□、30Ω/□、40Ω/□、50Ω/□、60Ω/□、70Ω/□、80Ω/□、90Ω/□、100Ω/□、150Ω/□、200Ω/□、250Ω/□、300Ω/□、350Ω/□、400Ω/□、450Ω/□、500Ω/□、550Ω/□、600Ω/□、650Ω/□、700Ω/□、750Ω/□、800Ω/□、850Ω/□、900Ω/□、950Ω/□、1000Ω/□等。掺杂硅层7的厚度(即图3中T5所指示的尺寸)可以为10纳米～1000纳米例如10纳米、20纳米、30纳米、40纳米、50纳米、60 纳米、70纳米、80纳米、90纳米、100纳米、150纳米、200纳米、250纳米、300纳米、350纳米、400纳米、450纳米、500纳米、550纳米、600纳米、750纳米、800纳米、850纳米、900纳米、950纳米、1000纳米等。
相应地，隧穿钝化层6可以为电子遂穿钝化层，在高温下对第V族元素的扩散具有一定的阻挡作用，也即高温下第V族元素在遂穿钝化层中的扩散速率远小于其在掺杂硅层7中的扩散速率。隧穿钝化层6可以为氧化物，例如氧化硅(SiO x)层、氧化钛(TiO x)层、氧化铝(AlO x)层、氧化钽(TaO x)、氮氧化硅(SiN xO y)等中的至少一种，即隧穿钝化层6可以是单独某一种氧化层，也可以是多种氧化物层的叠层结构。隧穿钝化层6的厚度(即图3中T4所指示的尺寸)可以为0.5纳米～6纳米，例如0.5纳米、0.6纳米、0.7纳米、0.8纳米、0.9纳米、1纳米、1.5纳米、2纳米、2.5纳米、3纳米、3.5纳米、4纳米、4.5纳米、5纳米、5.5纳米、6纳米等。
该实施方式中，第二覆盖层42可以包括氮化硅层、氮氧化硅层、氧化硅层及碳化硅层中的至少一种，即可以为单独的氮化硅层、单独的氮氧化硅层、单独的氧化硅层或单独的碳化硅层，也可以为氮化硅层、氮氧化硅层、氧化硅层和碳化硅层中的两种或者两种以上层叠设置。第二覆盖层42的厚度可以为60纳米～120纳米(例如60纳米、65纳米、70纳米、75纳米、80纳米、85纳米、90纳米、95纳米、100纳米、105纳米、110纳米、115纳米、120纳米等)。当第二覆盖层42为叠层结构时，每一层的厚度没有严格限定，可以根据需要设置，只要整体厚度满足要求即可。
该实施方式中，发射极层2可以设置在晶体硅基体1的正面，也可以设置在晶体硅基体1的背面，相应地，隧穿钝化层6和掺杂硅层7可以设置在晶体硅基体1的背面，也可以设置在晶体硅基体1的正面。
该实施方式中，掺杂硅层7可以仅覆盖隧穿钝化层6的局部区域，同时隧穿钝化层6未设置掺杂硅层7的区域上也设置有第二覆盖层42。掺杂硅层7的图案可以与第二电极52的图案相对应。仅在隧穿钝化层6的局部区域设置掺杂硅层7，可以减少掺杂硅层7对光线的吸收，有利于晶体硅太阳能电池光电转换效率的提升，尤其适用于隧穿钝化层6和掺杂硅层7设置在晶体硅基体1正面的情况。
该实施方式提供的晶体硅太阳能电池的制备方法主要包括晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成隧穿钝化层6、形成掺杂硅层7、形成氧化镓层X、形成第一覆盖层41和第二覆盖层42、形成第一电极51和第二电极52等步骤。
其中，晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成第一覆盖层41和第二覆盖层42、形成氧化镓层X、以及形成第一电极51和第二电极52等步骤的具体实现方式可参考上述第一种可选的实施方式中的描述，在此不再赘述。
对于形成隧穿钝化层6的步骤，可以根据隧穿钝化层6具体的组成来选择制备方法，例如以氧化硅层作为隧穿隧穿钝化层6，可采用热氧化工艺、低温炉管氧化工艺、硝酸氧化工艺、紫外/臭氧氧化工艺、双氧水氧化工艺、原子层沉积工艺、或者化学气相沉积工艺等。
对于形成掺杂硅层7的步骤，可以先在隧穿钝化层6上形成本征硅层(即未掺杂的硅层，可以是多晶硅层，也可以是非晶硅层)，之后对本征硅层进行掺杂，形成掺杂硅层7。对本征硅层的掺杂方法可通过扩散、沉积含掺杂源的掺杂层(例如沉积磷硅玻璃PSG)并退火、或者离子注入并退火等方法来对本征硅进行掺杂；也可以在生长本征硅层的过程中通入掺杂源得到掺杂硅层7，即在存在掺杂源的环境中形成掺杂硅层7。
对于覆盖隧穿钝化层6局部区域的掺杂硅层7来说，可首先在隧穿钝化层6上形成覆盖全部隧穿钝化层6的掺杂硅层7，之后在掺杂硅层7的预设位置上形成保护层，之后去除掺杂硅层7未被保护层覆盖的部分，从而在隧穿钝化层6的局部区域形成掺杂硅层7。可以理解的是，上述掺杂硅层7的预设位置是与需要设置掺杂硅层7的隧穿钝化层6上的局部区域相对应的位置。
可以通过激光照射掺杂硅层7的预设位置，在掺杂硅层7的预设位置形成氧化硅层，以氧化硅层作为保护层。可通过碱性溶液，例如氢氧化钠溶液去除掺杂硅层7未被保护层覆盖的部分。
根据保护层成分的不同，如果保护层对于晶体硅太阳能电池的性能影响较小，例如上述以氧化硅层作为保护层的情况，保护层可以去除，也可以不去除；如果保护层对于晶体硅太阳能电池的性能影响较大，则最终需要将保护层去除。
第三种可选的实施方式
图4示出了一种包括P型晶体硅基体的晶体硅太阳能电池的结构，图5示出了另一种包括P型晶体硅基体的晶体硅太阳能电池的结构，如图4、图5所示，该实施方式提供中的晶体硅太阳能电池包括：
导电类型为P型的晶体硅基体1，
设置在晶体硅基体1一侧表面上且与晶体硅基体1直接接触的氧化镓层X，
设置在氧化镓层X上的第三覆盖层43，
设置在第三覆盖层43上、且与晶体硅基体1接触的第三电极53，
设置在晶体硅基体1与氧化镓层X相对一侧表面、且导电类型为N型的发射极层2，
设置在发射极层2上的第四覆盖层44，以及，
设置在第四覆盖层44上、且与发射极层2接触的第四电极54。
对于导电类型为P型的晶体硅基体1来说，其表面本身就是P型表面，因此，该实施方式提供的晶体硅太阳能电池中，将氧化镓层X直接设置在P型的晶体硅基体1表面。
该实施方式中，P型的晶体硅可以为单晶硅，也可以为多晶硅，电阻率可以为0.1Ω·cm～10Ω·cm(例如0.1Ω·cm、0.2Ω·cm、0.3Ω·cm、0.4Ω·cm、0.5Ω·cm、0.6Ω·cm、0.7Ω·cm、0.8Ω·cm、0.9Ω·cm、1Ω·cm、2Ω·cm、3Ω·cm、4Ω·cm、5Ω·cm、6Ω·cm、7Ω·cm、8Ω·cm、9Ω·cm、10Ω·cm等)。
发射极层2可以位于晶体硅基体1的正面，也可以位于晶体硅基体1的背面，相应地，氧化镓层X可以位于晶体硅基体1的背面，也可以位于晶体硅基体1的正面。
发射极层2可采用N型掺杂元素(通常为第V族元素，包括但不限于磷)对P型的晶体硅基体1进行掺杂得到，其方块电阻值可以为40Ω/□～200Ω/□(例如40Ω/□、50Ω/□、60Ω/□、70Ω/□、80Ω/□、90Ω/□、100Ω/□、110Ω/□、120Ω/□、130Ω/□、140Ω/□、150Ω/□、160Ω/□、170Ω/□、180Ω/□、190Ω/□、200Ω/□等)。
进一步地，该实施方式中，氧化镓层X的厚度可以为1纳米～1000纳米，例如1纳米、5纳米、10纳米、15纳米、20纳米、25纳米、30纳米、35纳米、40纳米、45纳米、50纳米、55纳米、60纳米、65纳米、70纳米、75纳米、80纳米、85纳米、90纳米、95纳米、100纳米、150纳米、200纳米、250纳米、300纳米、350纳米、400纳米、450纳米、500纳米、550纳米、600纳米、650纳米、700纳米、750纳米、800纳米、850纳米、900纳米、950纳米、1000纳米等。优选地，氧化镓层X的厚度可以为2纳米～150纳米，更优选地，氧化镓层X的厚度可以为5纳米～60纳米。
第三覆盖层43可以包括氮化硅层、氮氧化硅层、氧化硅层、碳化硅中的至少一种，即可以是单独的氮化硅层，单独的氮氧化硅层或者单独的氧化硅层，也可以是氮化硅层、氮氧化硅层、氧化硅层、碳化硅层中的两种或者两种以上层叠设置。第三覆盖层43整体的厚度可以为200纳米以下，例如200纳米、190纳米、180纳米、170纳米、160纳米、150纳米、140纳米、130纳米、120纳米、110纳米、100纳米、90纳米、80纳米、70纳米、60纳米、50纳米、40纳米、30纳米、20纳米、10纳米、9纳米、8纳米、7纳米、6纳米、5纳米、4纳米、3纳米、2纳米、1纳米、0.5纳米等。当第三覆盖层43为叠层结构时，每一层的厚度没有严格要求，可以根据需要进行设置，只要使第三覆盖层43整体的厚度满足要求即可。上述第三覆盖层43的设置可以进一步钝化(氢扩散)晶体硅基体1。需要说明的是，该实施方式中，也可不设置第三覆盖层43，第三电极53直接设置在氧化镓层X上。
第四覆盖层44可以包括氮化硅层、氮氧化硅层、氧化硅层、碳化硅层中的至少一种，即可以是单独的氮化硅层，单独的氮氧化硅层、单独的氧化硅层或者单独的碳化硅层，也可以是氮化硅层、氮氧化硅层、氧化硅层和碳化硅层中的两种或者两种以上层叠设置。第四覆盖层44的厚度可以为60纳米～120纳米(例如60纳米、65纳米、70纳米、75纳米、80纳米、85纳米、90纳米、95纳米、100纳米、105纳米、110纳米、115纳米、120纳米等)。当第四覆盖层44为叠层结构时，每一层的厚度没有严格要求，可以根据需要进行设置，只要使第四覆盖层44整体的厚度满足要求即可。
第三电极53和第四电极54可以为金属电极(例如银电极)，相应地，第三电极53与晶体硅基体1之间的接触为欧姆接触，第四电极54与发射极层2之间的接触为欧姆接触。
该实施方式中，第四电极54可采用栅线结构(包括主栅线和副栅线)的电极。并且，发射极层2与第四电极54相对应的区域的方块电阻值可以大于其他区域的方块电阻值(即选择性发射极)，从而提升晶体硅太阳能电池的光电转换效率。
如图4和图5所示，该实施方式提供的晶体硅太阳能电池可以基于钝化发射极背面接触电池(Passivated Emitter and Rear Cell，PERC)结构。具体而言，在氧化镓层X和第三覆盖层43上对应设置有过孔O，晶体硅基体1表面与过孔O对应的区域形成有导电类型为P型的表面场层。
上述P型的表面场层可通过以下方式形成：
第三电极53包括第一部分531和第二部分532，第一部分531呈线形，第二部分532设置在第三覆盖层43上位于第一部分531以外的区域，且第二部分532与第一部分531接触。第二部分532通过过孔O与晶体硅基体1接触，并在晶体硅基体1表面与过孔O对应的区域形成表面场层。
具体而言，第一部分531也可称为主电极，用于导电汇流以及光伏组件制备时的太阳能电池的串焊，第一部分531可以设置多条，例如2～4条，多条第一部分531之间可相互平行，第一部分531可以设置为非连续式线形电极。第一部分531可由银浆形成，也可由银铝浆形成。
第二部分532可以由铝浆形成。在氧化镓层X和第三覆盖层43上设置过孔O后，将用于形成第二部分532的铝浆印刷在第三覆盖层43上，铝浆在高温烧结过程中与过孔O处露出的P型的晶体硅基体1表面发生扩散反应形成铝掺杂的P+硅层以及硅铝合金，其中P+硅层(即P型的表面场层)可使能带发生弯曲排斥少子在表面的分布，提高少子寿命，起到场钝化的效果。未发生扩散反应的铝浆起到导通作用，形成第三电极53的第二部分532。
进一步地，如图6所示，第二部分532可覆盖全部第三覆盖层43，或者如图7所示，第二部分532覆盖部分第三覆盖层43。对于第二部分532覆盖部分第三覆盖层43的情况来说，第二部分532可以将一个过孔O全部覆盖，也可仅覆盖一个过孔O的部分。可以理解的是，第二部分532覆盖部分第三覆盖层43的晶体硅太阳能电池双面均可透光，双面均可发电，具有更高的光电转化效率。
过孔O的截面形状可以为圆形、线形(即长条形)、正方形、三角形、边数为5以上的多边形或者其他形状。
对于圆形的过孔O来说，其直径可以为10微米～200微米(例如10微米、20微米、30微米、40微米、50微米、60微米、70微米、80微米、90微米、100微米、110微米、120微米、130微米、140微米、150微米、160微米、170微米、180微米、190微米、200微米等)，孔间距可以为100微米～1000微米(例如100微米、200微米、300微米、400微米、500微米、600微米、700微米、800微米、900微米、1000微米等)。
对于线形的过孔O来说，其宽度可以为20微米～100微米(例如20微米、30微米、40微米、50微米、60微米、70微米、80微米、90微米、100微米等)，其长度可以略小于晶体硅基体1的边长(晶体硅基体1通常为正方形或者有倒角的正方形)。线形过孔O的长度方向可以与第三电极53的第一部分531的长度方向垂直。线形过孔O可以设置有多个，且多个线形过孔O之间相互平行，相邻两个线形过孔O之间的距离可以为500微米～2000微米(例如500微米、600微米、700微米、800微米、900微米、1000微米、1100微米、1200微米、1300微米、1400微米、1500微米、1600微米、1700微米、1800微米、1900微米、2000微米)。本公开实施例中，线形过孔O可以设置为虚线的形式，即线形过孔O在长度方向上是不连续的。
该实施方式提供的晶体硅太阳能电池的制备方法主要包括晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成氧化镓层X、形成第三覆盖层43和第四覆盖层44、形成第三电极53和第四电极54等步骤。
其中，对晶体硅基体1的正面进行清洗并制绒可降低反射率。可以用氢氧化钠(NaOH)和过氧化氢(H2O2)的混合水溶液对晶体硅基体1进行清洗，以去除表面污染物及损伤层。可以利用碱性腐蚀液进行制绒，也可利用酸性腐蚀液进行制绒，碱性腐蚀液可以为氢氧化钠水溶液。
对于P型的晶体硅基体1来说，单晶硅片表面的反射率可以在10％～18％(例如10％、11％、12％、13％、14％、15％、16％、17％、18％等)，多晶硅片表面的反射率可以在6％～20％(例如6％、7％、8％、9％、10％、11％、12％、13％、14％、15％、16％、17％、18％、19％、20％等)。
可通过扩散(例如炉管磷扩散)、沉积含掺杂源的掺杂层(例如磷硅玻璃PSG)并退火、或者离子注入(例如注入磷离子)并退火等方法来形成发射极层2。
可通过化学溶液对晶体硅基体1的背表面进行平整，以适当降低晶体硅基体1背表面的比表面积，并 用氢氟酸清洗硅片。其中，化学溶液可以为碱溶液，包括但不限于四甲基氢氧化铵溶液、氢氧化钠溶液、氢氧化钾等，碱溶液的浓度可根据需要进行调整；也可以为酸溶液，例如硝酸、氢氟酸和硫酸的混合溶液，混合溶液中各酸液的浓度以及各酸液间的配比也可根据需要进行调整。
氧化镓层X可通过单原子层沉积法、等离子体增强化学气相沉积法、常压化学气相沉积法或者低压化学气相沉积法形成。氧化镓层X沉积完成之后，还需进行退火步骤。
第三覆盖层43和第四覆盖层44也可通过ALD、PECVD、APCVD、LPCVD等方法形成。当第三覆盖层43和第四覆盖层44组成相同时，二者可同时形成。
第三电极53和第四电极54可通过丝网印刷电极浆料并快速高温烧结的方法来形成。烧结的温度可以为600℃～900℃(例如600℃、650℃、700℃、750℃、800℃、850℃、900℃等)，烧结的时间可以为10秒～3分钟，例如10秒、20秒、30秒、40秒、60秒、70秒、80秒、90秒、100秒、110秒、120秒、130秒、140秒、150秒、160秒、170秒、180秒等。
对于PERC电池来说，在形成第三覆盖层43之后，还需进行在氧化镓层X和第三覆盖层43上形成过孔O的步骤，可通过激光或者化学腐蚀的方法形成过孔O。第三电极53的印刷过程则具体包括先印刷用于形成第一部分531的浆料，再印刷用于形成第二部分532的浆料。
第四种可选的实施方式
图8示出了又一种包括P型晶体硅基体的晶体硅太阳能电池的结构，如图8所示，该晶体硅太阳能电池包括：
导电类型为P型的晶体硅基体1，
设置在晶体硅基体1一侧表面上且与晶体硅基体1直接接触的氧化镓层X，
设置在氧化镓层X上的第三覆盖层43，
设置在第三覆盖层43上、且与晶体硅基体1接触的第三电极53，
设置在晶体硅基体1与氧化镓层X相对一侧表面、且导电类型为N型的发射极层2，
设置在发射极层2上的隧穿钝化层6，
设置在隧穿钝化层6上、且导电类型为N型的掺杂硅层7，
设置在掺杂硅层7上的第四覆盖层44，以及，
设置在第四覆盖层44上、且与掺杂硅层7接触的第四电极54。
与上述第三种可选的实施方式相同，该实施方式提供的晶体硅太阳能电池中，也将氧化镓层X直接设置在P型的晶体硅基体1表面。并且，该实施方式提供的晶体硅太阳能电池在发射极层2一侧采用TOP-Con结构。
该实施方式中，晶体硅基体1的电阻率、发射极层2的方块电阻值、第三覆盖层43的组成及厚度、第四电极54的具体形式等可参考上述第三种可选的实施方式中的描述，在此不再赘述。
该实施方式中，氧化镓层X的厚度优选10纳米～90纳米，更优选20纳米～60纳米。
该实施方式中，掺杂硅层7可以为掺杂多晶硅层、掺杂非晶硅层或掺杂多晶硅/氧化硅混合层。其中，多晶硅/氧化硅混合层为多晶硅颗粒均匀分布在氧化硅薄膜中或多晶硅颗粒表面包裹着氧化硅薄膜。掺杂硅层7的厚度可以为20纳米～1000纳米，例如20纳米、50纳米、100纳米、150纳米、200纳米、250纳米、300纳米、350纳米、400纳米、450纳米、500纳米、550纳米、600纳米、750纳米、800纳米、850纳米、900纳米、950纳米、1000纳米等。
掺杂硅层7中掺杂的元素可以为第V族元素(包括但不限于磷)，掺杂的元素的掺杂浓度可以为5×10 18atoms/cm 3～9×10 20atoms/cm 3，例如5×10 18atoms/cm 3、6×10 18atoms/cm 3、7×10 18atoms/cm 3、8×10 18atoms/cm 3、9×10 18atoms/cm 3、1×10 19atoms/cm 3、2×10 19atoms/cm 3、3×10 19atoms/cm 3、4×10 19atoms/cm 3、5×10 19atoms/cm 3、6×10 19atoms/cm 3、7×10 19atoms/cm 3、8×10 19atoms/cm 3、9×10 19atoms/cm 3、1×10 20atoms/cm 3、2×10 20atoms/cm 3、3×10 20atoms/cm 3、4×10 20atoms/cm 3、5×10 20atoms/cm 3、6×10 20atoms/cm 3、7×10 20atoms/cm 3、8×10 20atoms/cm 3、9×10 20atoms/cm 3等。
相应地，设置在发射极层2上的隧穿钝化层6可以为电子遂穿钝化层，在高温下对第V族元素的扩散具有一定的阻挡作用，也即高温下第V族元素在遂穿钝化层中的扩散速率远小于其在掺杂硅层7中的扩散速率。隧穿钝化层6可以为氧化硅层、氮氧化硅层、氢化非晶氧化硅层中的至少一种。正面隧穿钝化层6 的厚度可以为1.2纳米～2.5纳米，例如1.2纳米、1.3纳米、1.4纳米、1.5纳米、1.6纳米、1.7纳米、1.8纳米、1.9纳米、2.0纳米、2.1纳米、2.2纳米、2.3纳米、2.4纳米、2.5纳米等。
第四覆盖层44可以包括氮化硅层、氮氧化硅层、氧化硅层、碳化硅层中的至少一种，即可以是单独的氮化硅层，单独的氮氧化硅层、单独的氧化硅层或者单独的碳化硅层，也可以是氮化硅层、氮氧化硅层、氧化硅层和碳化硅层中的两种或者两种以上层叠设置。第四覆盖层44的厚度可以为68纳米～100纳米(例如68纳米、70纳米、72纳米、74纳米、75纳米、76纳米、78纳米、80纳米、82纳米、84纳米、85纳米、86纳米、88纳米、90纳米、92纳米、94纳米、95纳米、96纳米、98纳米、100纳米等)。当第四覆盖层44为叠层结构时，每一层的厚度没有严格要求，可以根据需要进行设置，只要使第四覆盖层44整体的厚度满足要求即可。
该实施方式中，掺杂硅层7可以仅覆盖隧穿钝化层6的局部区域，同时隧穿钝化层6未设置掺杂硅层7的区域上也设置有第四覆盖层44。掺杂硅层7的图案可以与第四电极54的图案相对应。仅在隧穿钝化层6的局部区域设置掺杂硅层7，可以减少掺杂硅层7对光线的吸收，有利于晶体硅太阳能电池光电转换效率的提升，尤其适用于隧穿钝化层6和掺杂硅层7设置在晶体硅基体1正面的情况。
该实施方式中，氧化镓层X、第三覆盖层43及第三电极53也可设置为PERC结构，具体结构可参考上述第三种可选的实施方式的描述，在此不再赘述。
该实施方式提供的晶体硅太阳能电池的制备方法主要包括晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成隧穿钝化层6、形成掺杂硅层7、形成氧化镓层X、形成第三覆盖层43和第四覆盖层44、形成第三电极53和第四电极54等。
其中，晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成氧化镓层X、形成第三覆盖层43和第四覆盖层44、以及形成第三电极53和第四电极54等步骤的具体实现方式可参考上述第三种可选的实施方式中的描述，在此不再赘述。
该实施方式中，形成隧穿钝化层6和掺杂硅层7的步骤可参考上述第二种可选的实施方式中的描述；对于覆盖隧穿钝化层6局部区域的掺杂硅层7的制备来说，同样可参考上述第二种可选的实施方式中的描述，在此不再赘述。
第五种可选的实施方式
图9示出了再一种包括P型晶体硅基体1的晶体硅太阳能电池的结构，如图9所示，该晶体硅太阳能电池包括：
导电类型为P型的晶体硅基体1，
设置在晶体硅基体1一侧表面的第一隧穿钝化层61，
设置在第一隧穿钝化层61上、且导电类型为P型的第一掺杂硅层71，
设置在第一掺杂硅层71上的氧化镓层X，
设置在氧化镓层X上的第五覆盖层45，
设置在第五覆盖层45上、且与第一掺杂硅层71接触的第五电极55，
设置在晶体硅基体1与第一隧穿钝化层61相对一侧表面、且导电类型为N型的发射极层2，
设置在发射极层2上的第六覆盖层46，以及，
设置在第六覆盖层46上、且与发射极层2接触的第六电极56。
该实施方式提供的晶体硅太阳能电池中，在P型的晶体硅基体1与发射极层2相对的一侧采用TOP-Con结构，并且将氧化镓层X设置在P型的第一掺杂硅层71上，即该实施方式中，氧化镓层X与P型的第一掺杂硅层71直接接触。
该实施方式中，P型的晶体硅基体1可以为单晶硅，也可以为多晶硅，电阻率可以为0.1Ω·cm～10Ω·cm(例如0.1Ω·cm、0.2Ω·cm、0.3Ω·cm、0.4Ω·cm、0.5Ω·cm、0.6Ω·cm、0.7Ω·cm、0.8Ω·cm、0.9Ω·cm、1Ω·cm、2Ω·cm、3Ω·cm、4Ω·cm、5Ω·cm、6Ω·cm、7Ω·cm、8Ω·cm、9Ω·cm、10Ω·cm等)。
发射极层2可以位于晶体硅基体1的正面，也可以位于晶体硅基体1的背面，相应地，第一隧穿钝化层61第一掺杂硅层71和氧化镓层X可以位于晶体硅基体1的背面，也可以位于晶体硅基体1的正面。
发射极层2可通过对P型的晶体硅基体1掺杂第V族元素(包括但不限于磷)形成，其方块电阻值可 以为40Ω/□～200Ω/□(例如40Ω/□、50Ω/□、60Ω/□、70Ω/□、80Ω/□、90Ω/□、100Ω/□、110Ω/□、120Ω/□、130Ω/□、140Ω/□、150Ω/□、160Ω/□、170Ω/□、180Ω/□、190Ω/□、200Ω/□等)。
进一步地，该实施方式中，氧化镓层X的厚度可以为10纳米～90纳米，例如1纳米、5纳米、10纳米、15纳米、20纳米、25纳米、30纳米、35纳米、40纳米、45纳米、50纳米、55纳米、60纳米、65纳米、70纳米、75纳米、80纳米、85纳米、90纳米等。优选地，氧化镓层X的厚度可以为20纳米～60纳米。
第一掺杂硅层71可以为掺杂多晶硅层、掺杂非晶硅层或掺杂多晶硅/氧化硅混合层。其中，多晶硅/氧化硅混合层为多晶硅颗粒均匀分布在氧化硅薄膜中或多晶硅颗粒表面包裹着氧化硅薄膜。
第一掺杂硅层71中掺杂的元素可以为第III族元素(包括但不限于硼)，掺杂的元素的掺杂浓度可以为1×10 18atoms/cm 3～8×10 20atoms/cm 3，例如1×10 18atoms/cm 3、2×10 18atoms/cm 3、3×10 18atoms/cm 3、4×10 18atoms/cm 3、5×10 18atoms/cm 3、6×10 18atoms/cm 3、7×10 18atoms/cm 3、8×10 18atoms/cm 3、9×10 18atoms/cm 3、1×10 19atoms/cm 3、2×10 19atoms/cm 3、3×10 19atoms/cm 3、4×10 19atoms/cm 3、5×10 19atoms/cm 3、6×10 19atoms/cm 3、7×10 19atoms/cm 3、8×10 19atoms/cm 3、9×10 19atoms/cm 3、1×10 20atoms/cm 3、2×10 20atoms/cm 3、3×10 20atoms/cm 3、4×10 20atoms/cm 3、5×10 20atoms/cm 3、6×10 20atoms/cm 3、7×10 20atoms/cm 3、8×10 20atoms/cm 3等。第一掺杂硅层71的厚度可以为20纳米～1000纳米，例如20纳米、50纳米、100纳米、150纳米、200纳米、250纳米、300纳米、350纳米、400纳米、450纳米、500纳米、550纳米、600纳米、750纳米、800纳米、850纳米、900纳米、950纳米、1000纳米等。
相应地，第一隧穿钝化层61可以为空穴隧穿钝化层，在高温下对第III族元素的扩散具有一定的阻挡作用，也即高温下第III族元素在第一隧穿钝化层61中扩散的速率远小于其在第一掺杂硅层71中的扩散速率，第一隧穿钝化层61可以为氧化硅层、氧化铝层、氧化钒层、氧化钨层、氧化镍层、氧化钼层以及氯化亚铜层中的至少一种，第一隧穿钝化层61的厚度可以为1.2纳米～2.5纳米，例如1.2纳米、1.3纳米、1.4纳米、1.5纳米、1.6纳米、1.7纳米、1.8纳米、1.9纳米、2.0纳米、2.1纳米、2.2纳米、2.3纳米、2.4纳米、2.5纳米。
设置在氧化镓层X上的第五覆盖层45可以包括氮化硅层、氮氧化硅层、氧化硅层、碳化硅中的至少一种，既可以是单独的氮化硅层，单独的氮氧化硅层、单独的氧化硅层或者单独的碳化硅层，也可以是氮化硅层、氮氧化硅层、氧化硅层、碳化硅层中的两种或者两种以上层叠设置。第五覆盖层45整体的厚度可以为20纳米～200纳米，例如20纳米、30纳米、40纳米、50纳米、60纳米、70纳米、80纳米、90纳米、100纳米、110纳米、120纳米、130纳米、140纳米、150纳米、160纳米、170纳米、180纳米、190纳米、200纳米等。当第五覆盖层45为叠层结构时，每一层的厚度没有严格要求，可以根据需要进行设置，只要使第五覆盖层45整体的厚度满足要求即可。需要说明的是，本公开实施例中，也可不设置第五覆盖层45，第五电极55直接设置在氧化镓层X上。
该实施方式中，第一掺杂硅层71可以仅覆盖第一隧穿钝化层61的局部区域，同时第一隧穿钝化层61未设置第一掺杂硅层71的区域上也设置有氧化镓层X。第一掺杂硅层71的图案可以与第五电极55的图案相对应。
第六覆盖层46可以包括氮化硅层、氮氧化硅层、氧化硅层、碳化硅层中的至少一种，即可以是单独的氮化硅层，单独的氮氧化硅层、单独的氧化硅层或者单独的碳化硅层，也可以是氮化硅层、氮氧化硅层、氧化硅层和碳化硅层中的两种或者两种以上层叠设置。第六覆盖层46的厚度可以为68纳米～100纳米(例如68纳米、70纳米、72纳米、74纳米、75纳米、76纳米、78纳米、80纳米、82纳米、84纳米、85纳米、86纳米、88纳米、90纳米、92纳米、94纳米、95纳米、96纳米、98纳米、100纳米等)。当第六覆盖层46为叠层结构时，每一层的厚度没有严格要求，可以根据需要进行设置，只要使第六覆盖层46整体的厚度满足要求即可。
第五电极55和第六电极56均可为包括主栅线和副栅线的栅线结构的电极。相应地，第一掺杂硅层71呈网格状结构。网格状的第一掺杂硅层71与第五电极55的主栅线对应的部分的宽度略大于主栅线的宽度，与副栅线对应的部分的宽度略大于副栅线的宽度。
并且，发射极层2与第六电极56相对应的区域的方块电阻值可以大于其他区域的方块电阻值(即选择性发射极)，从而提升晶体硅太阳能电池的光电转换效率。
该实施方式提供的晶体硅太阳能电池的制备方法主要包括晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成第一隧穿钝化层61、形成第一掺杂硅层71、形成氧化镓层X、形成第五覆盖层45和第六覆盖层46、形成第五电极55和第六电极56等。
晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成氧化镓层X、形成第五覆盖层45和第六覆盖层46、以及形成第五电极55和第六电极56等步骤的具体实现方式可参考上述第三种可选的实施方式中的描述，在此不再赘述。
该实施方式中，形成第一隧穿钝化层61和第一掺杂硅层71的步骤可参考上述第二种可选的实施方式中的描述；对于覆盖第一隧穿钝化层61局部区域的第一掺杂硅层71的制备来说，同样可参考上述第二种可选的实施方式中的描述，在此不再赘述。
第六种可选的实施方式
图10示出了再一种包括P型晶体硅基体1的晶体硅太阳能电池的结构，如图10所示，该晶体硅太阳能电池包括：
导电类型为P型的晶体硅基体1，
设置在晶体硅基体1一侧表面的第一隧穿钝化层61，
设置在第一隧穿钝化层61上、且导电类型为P型的第一掺杂硅层71，
设置在第一掺杂硅层71上的氧化镓层X，
设置在氧化镓层X上的第五覆盖层45，
设置在第五覆盖层45上、且与第一掺杂硅层71接触的第五电极55，
设置在晶体硅基体1与第一隧穿钝化层61相对一侧表面、且导电类型为N型的发射极层2，
设置在发射极层2上的第二隧穿钝化层62，
设置在第二隧穿钝化层62上、且导电类型为N型的第二掺杂硅层72，
设置在第二掺杂硅层72上的第六覆盖层46，以及，
设置在第六覆盖层46上、且与第二掺杂硅层72接触的第六电极56。
该实施方式提供的晶体硅太阳能电池中，在P型的晶体硅基体1两侧均采用TOP-Con结构，并且将氧化镓层X设置在P型的第一掺杂硅层71上，即该实施方式中，氧化镓层X也是与P型的第一掺杂硅层71直接接触。
该实施方式中，晶体硅基体1的电阻率、发射极层2的方块电阻值、第五覆盖层45的组成及厚度、第六覆盖层46的组成及厚度、第一隧穿钝化层61、第一掺杂硅层71、第五电极55和第六电极56的具体形式等可参考上述第三种可选的实施方式中的描述，在此不再赘述。
第二掺杂硅层72可以为掺杂多晶硅层、掺杂非晶硅层或者掺杂多晶硅/氧化硅混合层。其中，多晶硅/氧化硅混合层为多晶硅颗粒均匀分布在氧化硅薄膜中或多晶硅颗粒表面包裹着氧化硅薄膜。第二掺杂硅层72的厚度可以为20纳米～1000纳米，例如20纳米、50纳米、100纳米、150纳米、200纳米、250纳米、300纳米、350纳米、400纳米、450纳米、500纳米、550纳米、600纳米、750纳米、800纳米、850纳米、900纳米、950纳米、1000纳米等。
第二掺杂硅层72中掺杂的元素可以为第V族元素(包括但不限于磷)，掺杂的元素的掺杂浓度可以为5×10 18atoms/cm 3～9×10 20atoms/cm 3，例如5×10 18atoms/cm 3、6×10 18atoms/cm 3、7×10 18atoms/cm 3、8×10 18atoms/cm 3、9×10 18atoms/cm 3、1×10 19atoms/cm 3、2×10 19atoms/cm 3、3×10 19atoms/cm 3、4×10 19atoms/cm 3、5×10 19atoms/cm 3、6×10 19atoms/cm 3、7×10 19atoms/cm 3、8×10 19atoms/cm 3、9×10 19atoms/cm 3、1×10 20atoms/cm 3、2×10 20atoms/cm 3、3×10 20atoms/cm 3、4×10 20atoms/cm 3、5×10 20atoms/cm 3、6×10 20atoms/cm 3、7×10 20atoms/cm 3、8×10 20atoms/cm 3、9×10 20atoms/cm 3等。
相应地，第二隧穿钝化层62可以为电子遂穿钝化层，在高温下对第V族元素的扩散具有一定的阻挡作用，也即高温下第V族元素在正面遂穿钝化层中的扩散速率远小于其在第二掺杂硅层72中的扩散速率。第二隧穿钝化层62可以为氧化硅层、氮氧化硅层、氢化非晶氧化硅层中的至少一种。第二隧穿钝化层62的厚度可以为1.2纳米～2.5纳米，例如1.2纳米、1.3纳米、1.4纳米、1.5纳米、1.6纳米、1.7纳米、1.8纳米、1.9纳米、2.0纳米、2.1纳米、2.2纳米、2.3纳米、2.4纳米、2.5纳米。
该实施方式中，第二掺杂硅层72也可以仅覆盖第二隧穿钝化层62的局部区域，同时第二隧穿钝化层 62未设置第二掺杂硅层72的区域上设置有第六覆盖层46。第二掺杂硅层72的图案可以与第六电极56的图案相对应。对于第六电极56为栅线结构的电极的情况来说，第二掺杂硅层72可以呈网格状结构。其与第六电极56的主栅线对应的部分的宽度略大于主栅线的宽度，与副栅线对应的部分的宽度略大于副栅线的宽度。
该实施方式提供的晶体硅太阳能电池的制备方法主要包括晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成第一隧穿钝化层61、形成第二隧穿钝化层62、形成第一掺杂硅层71、形成第二掺杂硅层72、形成氧化镓层X、形成第五覆盖层45和第六覆盖层46、形成第五电极55和第六电极56等。
晶体硅基体1正面清洗制绒、形成发射极层2、晶体硅基体1背表面平整、形成氧化镓层X、形成第五覆盖层45和第六覆盖层46、以及形成第五电极55和第六电极56等步骤的具体实现方式可参考上述第三种可选的实施方式中的描述，在此不再赘述。
该实施方式中，形成第一隧穿钝化层61、第二隧穿钝化层62、第一掺杂硅层71和第二掺杂硅层72的步骤可参考上述第二种可选的实施方式中的描述；对于覆盖第一隧穿钝化层61局部区域的第一掺杂硅层71，以及覆盖第二隧穿钝化层62局部区域的第二掺杂硅层72的制备来说，同样可参考上述第二种可选的实施方式中的描述，在此不再赘述。
基于上述晶体硅太阳能电池，本公开实施例提供了一种光伏组件，该光伏组件包括依次设置的盖板、第一封装胶膜、电池串、第二封装胶膜和背板，电池串包括多个太阳能电池，其中，太阳能电池为上述本公开实施例提供的晶体硅太阳能电池。
由于本公开实施例提供的晶体硅太阳能电池中设置了与P型硅层直接接触的氧化镓层X，利用氧化镓层X所带有的负电荷对P型硅表面进行化学钝化和场钝化，提升了太阳能电池的光电转换效率，因此，应用该晶体硅太阳能电池的光伏组件具有较高的输出功率，从而降低度电成本，提高光伏发电的性价比。
本公开实施例中，盖板通常为玻璃板，第一封装胶膜和第二封装胶膜的材料为EVA(乙烯—醋酸乙烯共聚物)，背板可以为玻璃板，也可以为TPT(PVF/PET/PVF)板。其中，当背板采用TPT板时，光伏组件还包括边框，边框内填充硅胶。
本公开实施例提供的光伏组件中，晶体硅太阳能电池可以是正方形或者带有圆角的正方形的整片电池片，也可以是对整片电池片进行切割得到的切片电池片。
本公开实施例提供的光伏组件可以包括多串电池串，每一串电池串中的电池片之间可以通过焊带连接，也可以通过导电胶或者其他导电材料连接。每一串电池串中，相邻的电池片之间可以留有一定间隙，也可以使相邻的电池片的边缘重叠，即采用叠瓦方式连接。
本公开实施例还提供了氧化镓在晶体硅太阳能电池中作为钝化物或钝化结构的应用，
具体来说，氧化镓与晶体硅太阳能电池的P型硅层直接接触。
如上文所述，本公开实施例中P型硅层具体可以是：
(1)P型的晶体硅基体的表面；
(2)设置在P型的晶体硅基体一侧的P型的掺杂硅层，并且掺杂硅层与晶体硅基体之间还可以设置有在高温下对第III族元素的扩散具有一定的阻挡作用的隧穿钝化层；
(3)设置在P型的晶体硅基体一侧的P型的表面场层；
(4)设置在N型的晶体硅基体一侧的发射极层；
(5)设置在N型的晶体硅基体的发射极层上的P型的掺杂硅层，其中，掺杂硅层与晶体硅基体的发射极层之间还可以设置有对第III族元素的扩散具有一定的阻挡作用的隧穿钝化层。
下面通过具体实例对本公开的技术方案做进一步说明。
为了便于描述，以下实施例中，将设置在晶体硅太阳能电池正面的电极、覆盖层、隧穿钝化层、掺杂硅层分别称为正面电极、正面覆盖层、正面隧穿钝化层、正面掺杂硅层；将设置在晶体硅太阳能电池背面的电极、覆盖层、隧穿钝化层、掺杂硅层分别称为背面电极、背面覆盖层、背面隧穿钝化层、背面掺杂硅 层。
实施例1
本实施例提供了一种氧化镓钝化的N型晶体硅双面太阳能电池，如图2所示，该太阳能电池包括由正面到背面依次设置的正面电极、正面覆盖层、氧化镓层、发射极层、N型晶体硅基体、N型表面场层、背面覆盖层以及背面电极。
其中，N型晶体硅基体为电阻率为2.0Ω·cm、尺寸为156.75mm×156.75mm的N型单晶硅片。
发射极层通过炉管硼扩散形成，掺杂后方块电阻值为80Ω/□。
氧化镓层厚度为20纳米。
正面覆盖层为氮化硅层，其厚度为65纳米。
位于N型晶体硅基体背面的N型表面场层通过磷离子注入法形成，掺杂后方块电阻为110Ω/□。
位于N型表面场层上的背面覆盖层为氮化硅层，其厚度为75纳米。
正面电极和背面电极均为栅线结构，其中主栅线4根，宽度为1.1毫米，副栅线102根，宽度为40微米，相邻两根副栅线之间的距离为1.5毫米，正面电极和背面电极均由贺利氏(Heraeus)SOL9360型银浆料形成。
本实施例提供的太阳能电池的制备方法如下：
步骤101，利用NaOH和H 2O 2的混合水溶液(NaOH、H 2O 2和H 2O按照质量比0.5％:1％:98.5％的比例混合)对N型单晶硅片进行清洗(清洗时间2min)，之后利用质量浓度3％的氢氧化钠水溶液在N型单晶硅片的正面制绒，制绒后，N型单晶硅片的正面的反射率为12％。
步骤102，通过炉管硼扩散的方法在制绒后的N型单晶硅片的正面进行硼掺杂制备发射极层，形成P-N结。其中，炉管硼扩散采用Tempress公司的TS-81255型扩散炉，扩散条件为：以BBr 3作为硼源，在940℃下向扩散炉内的石英管内通入BBr 3(通入时间20min)，之后停止通入BBr 3并在960℃下保温20min。
步骤103，将经过扩散后的N型单晶硅片在70℃、质量浓度为20％的TMAH溶液中浸泡5min，对N型单晶硅片背表面进行平整，之后用质量浓度为10％的HF水溶液清洗硅片2min。
步骤104，利用Kingston公司(上海凯世通半导体股份有限公司)的iPV-2000型离子注入机向N型单晶硅片的背面注入磷离子，进行磷掺杂形成N型表面场层，注入条件：离子加速电压10kV，加速后束流120mA，离子注入腔室真空度2×10 -5Torr。
步骤105，采用PEALD法在发射极层上沉积氧化镓薄膜，所用设备为芬兰倍耐克(Beneq)公司的TFS200型原子层沉积薄膜系统，沉积条件为：温度为75℃，压强为0.25Torr,三甲基镓(TMGa)的体积流量为70sccm(标准状态毫升/分)，O 2的体积流量为200sccm。
步骤106，采用PECVD法在发射极层上和N型表面场层上形成氮化硅薄膜，所用设备为ROTH&RAU公司的SINA型PECVD设备，沉积条件为：温度为400℃，压强为0.25mBar,SiH 4的体积流量为100sccm，NH 3的体积流量为180sccm。
步骤107，丝网印刷用于形成背面电极的浆料，所用丝网印刷机为Applied materials公司的Baccini speedy thinking型印刷机(下同)。
步骤108，丝网印刷用于形成正面电极的浆料。
步骤109，在820℃的温度下进行烧结，烧结时间为10秒；经烧结后正面金属银穿过氮化硅/氧化镓薄膜与发射极层形成局部欧姆接触，背面银浆料腐蚀氮化硅薄膜与N型掺杂层形成欧姆接触。
采用I-V测试方法(德国Halm公司的CetisPV-XF2-PB型I-V测试仪)对本实施例提供的太阳能电池的性能进行测试(测试条件为25℃，光谱条件AM1.5)，结果为：开路电压0.668V，短路电流9.77A，光电转换效率21.1％。
实施例2
本实施例提供了一种氧化镓钝化的N型晶体硅双面太阳能电池，本实施例提供的太阳能电池与实施例1提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为1纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.661V，短路电流9.79A，光电转换效率20.92％。
实施例3
本实施例提供了一种氧化镓钝化的N型晶体硅双面太阳能电池，本实施例提供的太阳能电池与实施例1提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为40纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.668V，短路电流9.75A，光电转换效率21.06％。
实施例4
本实施例提供了一种氧化镓钝化的N型晶体硅双面太阳能电池，本实施例提供的太阳能电池与实施例1提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为80纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.668V，短路电流9.73A，光电转换效率20.69％。
实施例5
本实施例提供了一种氧化镓钝化的N型晶体硅双面太阳能电池，本实施例提供的太阳能电池与实施例1提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为120纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.667V，短路电流9.58A，光电转换效率19.87％。
对比例1
本对比例提供了一种未设置氧化镓层的N型晶体硅双面太阳能电池，本对比例提供的太阳能电池与实施例1提供的太阳能电池的区别在于，本对比例提供的太阳能电池中未设置氧化镓层。在制备太阳能电池时，直接在发射极层上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.656V，短路电流9.8A，光电转换效率20.78％。
对比例2
本对比例提供了一种氧化锆钝化的N型晶体硅双面太阳能电池，本对比例提供的太阳能电池与实施例1提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化锆(ZrO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在发射极层上形成氧化锆薄膜，再在氧化锆薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.658V，短路电流9.62A，光电转换效率20.47％。
对比例3
本对比例提供了一种氧化钽钝化的N型晶体硅双面太阳能电池，本对比例提供的太阳能电池与实施例1提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化钽(TaO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在发射极层上形成氧化钽薄膜，再在氧化钽薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.66V，短路电流9.68A，光电转换效率20.66％。
对比例4
本对比例提供了一种氧化铪钝化的N型晶体硅双面太阳能电池，本对比例提供的太阳能电池与实施例1提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化铪(HfO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在发射极层上形成氧化铪薄膜，再在氧化铪薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.665V，短路电流9.73A，光电转换效率20.92％。
以下表1中，对以上实施例1～5和对比例1～4的太阳能电池的性能测试结果进行了汇总。
表1太阳性能测试结果汇总
序号 氧化物类型 氧化物薄膜厚度 开路电压 短路电流 光电转换效率
实施例1 氧化镓 20纳米 0.668V 9.77A 21.1％
实施例2 氧化镓 1纳米 0.661V 9.79A 20.92％
实施例3 氧化镓 40纳米 0.668V 9.75A 21.06％
实施例4 氧化镓 80纳米 0.668V 9.73A 20.69％
实施例5 氧化镓 120纳米 0.667V 9.58A 19.87％
对比例1 —— —— 0.656V 9.8A 20.78％
对比例2 氧化锆 20纳米 0.658V 9.62A 20.47％
对比例3 氧化钽 20纳米 0.66V 9.68A 20.66％
对比例4 氧化铪 20纳米 0.665V 9.73A 20.92％
实施例6
本实施例提供了一种氧化镓钝化的Topcon太阳能电池，如图3所示，该太阳能电池包括由正面到背面依次设置的正面电极、正面覆盖层、氧化镓层、发射极层、N型晶体硅基体、隧穿钝化层、掺杂多晶硅层、背面覆盖层以及背面电极。
其中，N型晶体硅基体为电阻率为2.0Ω·cm、尺寸为156.75mm×156.75mm的N型单晶硅片。
发射极层通过炉管硼扩散形成，掺杂后方块电阻值为80Ω/□。
氧化镓层的厚度为20纳米。
正面覆盖层为氮化硅层，其厚度为65纳米。
隧穿钝化层的厚度为1.8纳米；
掺杂多晶硅层的厚度为100纳米，为磷掺杂，掺杂后的方块电阻为38Ω/□。
背面钝化层为氮化硅层，其厚度为70纳米。
正面电极和背面电极均为栅线结构，其中主栅线4根，宽度为1.1毫米，副栅线102根，宽度为40微米，相邻两根副栅线之间的距离为1.5毫米，正面电极由贺利氏(Heraeus)SOL9360型银浆料形成，背面电极由贺利氏(Heraeus)SOL9621型银浆料形成。
本实施例提供的太阳能电池的制备方法如下：
步骤601，利用NaOH和H 2O 2的混合水溶液(NaOH、H 2O 2和H 2O按照质量比0.5％:1％:98.5％的比例混合)对N型单晶硅片进行清洗(清洗时间2min)，之后利用质量浓度3％的氢氧化钠水溶液在N型单晶硅片的正面制绒，制绒后，N型单晶硅片的正面的反射率为12％。
步骤602，通过炉管硼扩散的方法在制绒后的N型单晶硅片的正面进行硼掺杂制备发射极层，形成P-N结。其中，炉管硼扩散采用Tempress公司的TS-81255型扩散炉，扩散条件为：以BBr 3作为硼源，在940℃下向扩散炉内的石英管内通入BBr 3(通入时间20min)，之后停止通入BBr 3并在960℃下保温20min。
步骤603，将经过扩散后的N型单晶硅片在40℃、质量浓度为20％的TMAH溶液中浸泡30s，对N型单晶硅片背表面进行平整，之后用质量浓度为10％的HF水溶液清洗硅片2min。
步骤604，用热氧化法在N型单晶硅片的背面生长隧穿钝化层，具体工艺参数为：在氧气气氛下，加热温度为610℃，加热时间为2min。
步骤605，用LPCVD方法在隧穿钝化层上生长本征多晶硅层，并用磷离子注入的方式对本征多晶层进行磷掺杂，形成掺杂多晶硅层。
其中，生长本征多晶硅层的设备为Tempress公司的997-AAK型LPCVD设备，生长条件：温度为600℃，SiH 4的体积流量为600sccm，压强为0.25Torr。
磷离子注入的设备为Kingston公司的iPV-2000型离子注入机，注入条件：离子加速电压10kV，加速后束流120mA，离子注入腔室真空度2×10 -5Torr。
步骤606，采用PEALD的方式在发射极上沉积氧化镓薄膜，所用设备为芬兰倍耐克(Beneq)公司的TFS200型原子层沉积薄膜系统，沉积条件为：温度为75℃，压强为0.25Torr,三甲基镓(TMGa)的体积流量为70sccm(标准状态毫升/分)，O 2的体积流量为200sccm。
步骤607，采用PECVD的方式在发射极层上和掺杂多晶硅层上形成氮化硅薄膜，所用设备为 ROTH&RAU公司的SINA型PECVD设备，沉积条件为：温度为400℃，压强为0.25mBar,SiH 4的体积流量为100sccm，NH 3的体积流量为180sccm。
步骤608，丝网印刷用于形成背面电极的浆料，所用丝网印刷机为Applied materials公司的Baccini speedy thinking型印刷机。
步骤609，丝网印刷用于形成正面电极的浆料。
步骤610，在820℃的温度下烧结，烧结时间为10秒；经烧结后正面金属银穿过氮化硅/氧化镓薄膜与发射极形成局部欧姆接触，背面银浆料腐蚀氮化硅薄膜与掺杂多晶硅层形成欧姆接触。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.689V，短路电流9.98A，光电转换效率22.23％。
实施例7
本实施例提供了一种氧化镓钝化的Topcon太阳能电池，本实施例提供的太阳能电池与实施例6提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为1纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.687V，短路电流9.99A，光电转换效率22.19％。
实施例8
本实施例提供了一种氧化镓钝化的Topcon太阳能电池，本实施例提供的太阳能电池与实施例6提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为40纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.688V，短路电流9.896A，光电转换效率22.01％。
实施例9
本实施例提供了一种氧化镓钝化的Topcon太阳能电池，本实施例提供的太阳能电池与实施例6提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为80纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.688V，短路电流9.73A，光电转换效率21.64％。
实施例10
本实施例提供了一种氧化镓钝化的Topcon太阳能电池，本实施例提供的太阳能电池与实施例6提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为120纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.688V，短路电流9.48A，光电转换效率20.77％。
对比例5
本对比例提供了一种未设置氧化镓层的Topcon太阳能电池，本对比例提供的太阳能电池与实施例6提供的太阳能电池的区别在于，本对比例提供的太阳能电池中未设置氧化镓层。在制备太阳能电池时，直接在发射极层上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.682V，短路电流9.99A，光电转换效率22.03％。
对比例6
本对比例提供了一种氧化锆钝化的Topcon太阳能电池，本对比例提供的太阳能电池与实施例6提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化锆(ZrO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在发射极层上形成氧化锆薄膜，再在氧化锆薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.680V，短路电流9.86A，光电转换效率21.68％。
对比例7
本对比例提供了一种氧化钽钝化的Topcon太阳能电池，本对比例提供的太阳能电池与实施例6提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化钽(TaO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在发射极层上形成氧化钽薄膜，再在氧化钽薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.682V，短路电流9.97A，光电转换效率21.99％。
对比例8
本对比例提供了一种氧化铪钝化的Topcon太阳能电池，本对比例提供的太阳能电池与实施例6提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化铪(HfO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在发射极上层形成氧化铪薄膜，再在氧化铪薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.684V，短路电流9.95A，光电转换效率22.0％。
以下表2中，对以上实施例6～10和对比例5～8的太阳能电池的性能测试结果进行了汇总。
表2太阳性能测试结果汇总
序号 氧化物类型 氧化物薄膜厚度 开路电压 短路电流 光电转换效率
实施例6 氧化镓 20纳米 0.689V 9.98A 22.23％
实施例7 氧化镓 1纳米 0.687V 9.99A 22.19％
实施例8 氧化镓 40纳米 0.688V 9.896A 22.01％
实施例9 氧化镓 80纳米 0.688V 9.73A 21.64％
实施例10 氧化镓 120纳米 0.688V 9.48A 20.77％
对比例5 —— —— 0.682V 9.99A 22.03％
对比例6 氧化锆 20纳米 0.680V 9.86A 21.68％
对比例7 氧化钽 20纳米 0.682V 9.97A 21.99％
对比例8 氧化铪 20纳米 0.684V 9.95A 22.0％
实施例11
本实施例提供了一种氧化镓钝化的晶体硅PERC全铝背场太阳能电池，如图4所示，该太阳能电池包括由正面到背面依次设置的正面电极、正面覆盖层、发射极层、P型晶体硅基体、氧化镓层、背面覆盖层以及背面电极。
其中，P型晶体硅基体为电阻率为2.0Ω·cm、尺寸为156.75mm×156.75mm的P型单晶硅片。
氧化镓层的厚度为40纳米。
背面覆盖层为氮化硅层，其厚度为70纳米。
氧化镓层和背面覆盖层上对应开设有142×142个(即每行142个，共142行)圆形的过孔，过孔的孔径为50μm，相邻两个过孔的间距(圆心之间的距离)为1100微米。
背面电极包括第一部分和第二部分，其中第一部分呈线形，用于导电汇流和太阳能电池的串焊，由杜邦(Dupant)公司的PV56x型银浆料形成，数量为4条，宽度为1.6mm；第二部分为由杜邦(Dupant)公司的PV36x型铝浆料形成的铝电极，其覆盖背面覆盖层上第一部分以外的全部区域，且第二部分穿过过孔与P型晶体硅基体接触。
正面电极为栅线结构，由贺利氏(Heraeus)SOL9621型银浆料形成，其中主栅线4根，宽度1.1毫米，副栅线102根，宽度40微米，间距1.5毫米。
正面覆盖层为氮化硅层，其厚度为80纳米。
发射极层通过炉管磷扩散形成，掺杂后方块电阻值为100Ω/□。
本实施例提供的太阳能电池的制备方法如下：
步骤1101，利用NaOH和H 2O 2的混合水溶液(NaOH、H 2O 2和H 2O按照质量比0.5％:1％:98.5％的比 例混合)对P型单晶硅片进行清洗(清洗时间2min)，之后利用质量浓度3％的氢氧化钠水溶液在P型单晶硅片的正面制绒，制绒后，P型单晶硅片的正面的反射率为12％。
步骤1102，通过炉管磷扩散的方法在制绒后的P型单晶硅片的正面进行磷掺杂制备发射极，形成P-N结。其中，炉管硼扩散采用SevenStart公司的L4511II-40/ZM型扩散设备，扩散条件为：以POCl 3作为磷源，在820℃下向石英管内通入POCl 3(通入时间20min)，之后停止通入POCl 3并在840℃下保温20min。
步骤1103，将经过扩散后的P型单晶硅片在70℃、质量浓度为20％的TMAH溶液中浸泡5min，对N型单晶硅片背表面进行平整，之后用质量浓度为10％的HF水溶液清洗硅片2min。
步骤1104，采用PEALD法在P型单晶硅片的背面沉积氧化镓薄膜，所用设备为芬兰倍耐克(Beneq)公司的TFS 200型原子层沉积薄膜系统，沉积条件为：温度为75℃，压强为0.25Torr,三甲基镓(TMGa)的体积流量为70sccm(标准状态毫升/分)，O 2的体积流量为200sccm。
步骤1105，采用PECVD法在P型单晶硅片的正面的发射极层上以及背面的氧化镓薄膜上形成氮化硅薄膜，所用设备为ROTH&RAU公司的SINA型PECVD设备，沉积条件为：温度为400℃，压强为0.25mBar，SiH 4的体积流量为100sccm，NH 3的体积流量为180sccm。
步骤1106，利用激光在P型单晶硅片背面的氧化镓/氮化硅叠层结构上开孔。
步骤1107，丝网印刷用于形成背面电极中的第一部分的浆料，所用丝网印刷机为Applied materials公司的Baccini speedy thinking型印刷机。
步骤1108，丝网印刷用于形成背面电极中的第二部分的浆料。
步骤1109，丝网印刷用于形成正面电极的浆料。
步骤1110，在790℃的温度下进行烧结，烧结时间为10秒；经烧结后正面金属银部分烧穿氮化硅薄膜与发射极形成欧姆接触，背面铝颗粒和与过孔区域对应的硅基体形成铝硅合金和铝背场。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.668V，短路电流9.71A，光电转换效率20.73％。
实施例12
本实施例提供了一种氧化镓钝化的晶体硅PERC局部铝背场太阳能电池，如图5所示，该太阳能电池的结构与实施例11提供的太阳能电池的结构的区别在于，背面覆盖层有部分区域未被由铝浆形成的背面电极的第二部分覆盖。
其中，背面电极的第二部分呈线型，共102条，每条第二部分的宽度为70微米，相邻两条第二部分的距离为1.1毫米，第二部分与用于导电汇流、串焊的第一部分垂直。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.668V，短路电流9.78A，光电转换效率20.83％。
实施例13
本实施例提供了一种氧化镓钝化的晶体硅PERC局部铝背场太阳能电池，本实施例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为1纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.647V，短路电流9.1A，光电转换效率19.04％。
实施例14
本实施例提供了一种氧化镓钝化的晶体硅PERC局部铝背场太阳能电池，本实施例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为80纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.667V，短路电流9.7A，光电转换效率20.60％。
实施例15
本实施例提供了一种氧化镓钝化的晶体硅PERC局部铝背场太阳能电池，本实施例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为200纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.666V，短路电流9.68A，光电转换效率20.39％。
实施例16
本实施例提供了一种氧化镓钝化的晶体硅PERC局部铝背场太阳能电池，本实施例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为500纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.663V，短路电流9.51A，光电转换效率19.48％。
实施例17
本实施例提供了一种氧化镓钝化的晶体硅PERC局部铝背场太阳能电池，本实施例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为1000纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.660V，短路电流9.52A，光电转换效率18.82％。
对比例9
本对比例提供了一种未设置氧化镓层的晶体硅PERC局部铝背场太阳能电池，本对比例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本对比例提供的太阳能电池中未设置氧化镓层。在制备太阳能电池时，直接在P型单晶硅片的背面形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.642V，短路电流8.50A，光电转换效率17.29％。
对比例10
本对比例提供了一种氧化锆钝化的晶体硅PERC局部铝背场太阳能电池，本对比例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化锆(ZrO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在P型单晶硅片的背面形成氧化锆薄膜，再在氧化锆薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.658V，短路电流9.53A，光电转换效率20.04％。
对比例11
本对比例提供了一种氧化钽钝化的晶体硅PERC局部铝背场太阳能电池，本对比例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化钽(TaO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在P型单晶硅片的背面形成氧化钽薄膜，再在氧化钽薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.660V，短路电流9.63A，光电转换效率20.32％。
对比例12
本对比例提供了一种氧化铪钝化的晶体硅PERC局部铝背场太阳能电池，本对比例提供的太阳能电池与实施例12提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化铪(HfO x)薄膜替代氧化镓薄膜。在制备太阳能电池时，先在P型单晶硅片的背面形成氧化铪薄膜，再在氧化铪薄膜上形成SiN x薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.665V，短路电流9.65A，光电转换效率20.51％。
以下表3中，对以上实施例11～17和对比例9～12的太阳能电池的性能测试结果进行了汇总。
表3太阳性能测试结果汇总
序号 氧化物类型 氧化物薄膜厚度 开路电压 短路电流 光电转换效率
实施例11 氧化镓 40纳米 0.668V 9.71A 20.73％
实施例12 氧化镓 40纳米 0.668V 9.78A 20.83％
实施例13 氧化镓 1纳米 0.647V 9.1A 19.04％
实施例14 氧化镓 80纳米 0.667V 9.7A 20.60％
实施例15 氧化镓 200纳米 0.666V 9.68A 20.39％
实施例16 氧化镓 500纳米 0.663V 9.51A 19.48％
实施例17 氧化镓 1000纳米 0.660V 9.52A 18.82％
对比例9 —— —— 0.642V 8.50A 17.29％
对比例10 氧化锆 40纳米 0.658V 9.53A 20.04％
对比例11 氧化钽 40纳米 0.660V 9.63A 20.32％
对比例12 氧化铪 40纳米 0.665V 9.65A 20.51％
实施例18
本实施例提供了一种采用氧化镓钝化的晶体硅太阳能电池，如图9所示，该太阳能电池包括P型晶体硅基体，设置在P型晶体硅基体正面的发射极层，设置在发射极层上的正面覆盖层，设置在正面覆盖层上的正面电极，设置在P型晶体硅基体背面的背面隧穿钝化层，设置在背面隧穿钝化层上与背面电极对应区域的硼元素掺杂的背面掺杂多晶硅层，设置在背面掺杂多晶硅层上以及背面隧穿钝化层未设置背面掺杂多晶硅层区域的氧化镓层，设置在氧化镓层上的背面覆盖层，以及设置在背面覆盖层上的背面电极。
其中，P型晶体硅基体为电阻率为2.0Ω·cm、尺寸为156.75毫米×156.75毫米的P型单晶硅片；
发射极层的方阻为80Ω/□；
正面覆盖层为氮化硅层，其厚度为80纳米；
正面电极为栅线结构，由贺利氏(Heraeus)SOL9621型银浆料形成，其中主栅线4根，宽度1.1毫米，副栅线102根，宽度40微米，间距1.5毫米；
背面隧穿钝化层为氧化硅层，厚度为1.9纳米；
背面掺杂多晶硅层厚度为200纳米；
氧化镓层的厚度为20纳米；
背面覆盖层为氮化硅层，厚度为80纳米；
背面电极也为栅线结构，由贺利氏(Heraeus)SOL9360型银浆料形成，其中主栅线4根，宽度1.1毫米，副栅线102根，宽度40微米，间距1.5毫米；
本实施例提供的太阳能电池的制备方法如下：
步骤1801，利用NaOH和H 2O 2的混合水溶液(NaOH、H 2O 2和H 2O按照质量比0.5％:1％:98.5％的比例混合)对P型单晶硅片进行清洗(清洗时间2分钟)，之后利用质量浓度3％的氢氧化钠水溶液在P型单晶硅片的正面制绒，制绒后，P型单晶硅片的正面的反射率为12％。
步骤1802，通过炉管磷扩散的方法在制绒后的P型单晶硅片的正面进行磷掺杂制备发射极层，形成P-N结。其中，炉管磷扩散采用SevenStart公司的L4511II-40/ZM型扩散设备，扩散条件为：以POCl 3作为磷源，在820℃下向石英管内通入POCl 3(通入时间20分钟)，之后停止通入POCl 3并在840℃下保温20分钟。
步骤1803，将经过扩散后的P型单晶硅片在70℃、质量浓度为20％的TMAH溶液中浸泡5分钟，对P型单晶硅片背表面进行平整，之后用质量浓度为10％的HF水溶液清洗硅片2分钟。
步骤1804，采用炉管热氧化法在P型单晶硅片背表面生长氧化硅薄膜作为背面隧穿钝化层，工艺条件为：在氧气气氛下，加热温度为610℃，加热时间为2分钟。
步骤1805，用LPCVD方法在背面隧穿钝化层上生长本征多晶硅薄膜，并用硼离子注入的方式对本征多晶薄膜进行硼掺杂，形成背面掺杂多晶硅层。
其中，生长多晶硅薄膜的设备为Tempress公司的997-AAK型LPCVD设备，生长条件：温度为600℃，SiH 4的体积流量为600sccm，压强为0.25Torr。
硼离子注入的设备为Kingston公司的iPV-2000型离子注入机，注入条件：离子加速电压10kV，加速后束流120mA，离子注入腔室真空度2×10 -5Torr。
步骤1806，利用激光扫描照射背面掺杂多晶硅层与背面电极相对应的区域，在背面掺杂多晶硅层与背面电极相对应的区域形成BSG保护层，其中，激光扫描的图案与背面电极图案相同，所用激光为纳秒激光，激光能量为20瓦。
步骤1807，利用碱溶液去除背面掺杂多晶硅层未被BSG保护层覆盖的区域，形成与背面电极图案相同的背面掺杂多晶硅层(其中碱溶液为质量浓度7％的四甲基氢氧化铵溶液，在50摄氏度下清洗5分钟)，之后再利用氢氟酸去除BSG保护层(其中氢氟酸质量浓度为5％，在室温下清洗2分钟)。
步骤1808，采用原子层沉积工艺在步骤1807得到的背面掺杂多晶硅层以及背面隧穿钝化层未设置掺杂多晶硅层的区域上形成氧化镓薄膜，沉积条件为：温度为75℃，压强为0.25Torr,三甲基镓(TMGa)的体积流量为70sccm(标准状态毫升/分)，O 2的体积流量为200sccm。
步骤1809，在发射极层以及氧化镓层上形成氮化硅薄膜，所用设备为ROTH&RAU公司的SINA型PECVD设备，沉积条件为：温度为400℃，压强为0.25mBar，SiH 4的体积流量为100sccm，NH 3的体积流量为180sccm。
步骤1810，丝网印刷用于形成背面电极的银浆料，所用丝网印刷机为Applied materials公司的Baccini speedy thinking型印刷机(下同)。
步骤1811，丝网印刷用于形成正面电极的银浆料。
步骤1812，在820℃的温度下进行烧结，烧结时间为10秒；烧结过程中，正面银浆料腐蚀正面氮化硅层使得正面银电极穿过正面氮化硅层与发射极层形成欧姆接触；背面银浆料腐蚀氮化硅覆盖层5和氧化镓层4使得背面金属电极穿过氮化硅/氧化镓叠层结构与硼掺杂多晶硅层形成欧姆接触。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：结果为：开路电压0.668V，短路电流9.74A，光电转换效率20.76％。
实施例19
本实施例提供了一种采用氧化镓钝化的晶体硅太阳能电池，本实施例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为10纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.660V，短路电流9.72A，光电转换效率20.24％。
实施例20
本实施例提供了一种采用氧化镓钝化的晶体硅太阳能电池，本实施例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为40纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.669V，短路电流9.81A，光电转换效率20.87％。
实施例21
本实施例提供了一种采用氧化镓钝化的晶体硅太阳能电池，本实施例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为60纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.669V，短路电流9.79A，光电转换效率20.68％。
实施例22
本实施例提供了一种采用氧化镓钝化的晶体硅太阳能电池，本实施例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为75纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.668V，短路电流9.78A，光电转换效率20.58％。
实施例23
本实施例提供了一种采用氧化镓钝化的晶体硅太阳能电池，本实施例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本实施例提供的太阳能电池中氧化镓层的厚度为90纳米。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.668V，短路电流9.78A，光电转换效率20.49％。
对比例13
本对比例提供了一种未设置氧化镓层的晶体硅太阳能电池，本对比例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本对比例提供的太阳能电池中未设置氧化镓层。在制备太阳能电池时，直接在P型晶体硅基体背面的背面掺杂多晶硅层以及背面隧穿钝化层未设置掺杂多晶硅层的区域上形成氮化硅薄膜作为背面覆盖层。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.642V，短路电流8.5A，光电转换效率17.29％。
对比例14
本对比例提供了一种采用氧化锆(ZrO x)钝化的晶体硅太阳能电池，本对比例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化锆薄膜替代氧化镓薄膜。在制备太阳能电池时，先在P型晶体硅基体背面的背面掺杂多晶硅层以及背面隧穿钝化层未设置掺杂多晶硅层的区域上形成氧化锆薄膜，再在氧化锆薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.660V，短路电流9.54A，光电转换效率20.08％。
对比例15
本对比例提供了一种采用氧化钽(TaO x)钝化的晶体硅太阳能电池，本对比例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化钽薄膜替代氧化镓薄膜。在制备太阳能电池时，先在P型晶体硅基体背面的背面掺杂多晶硅层以及背面隧穿钝化层未设置掺杂多晶硅层的区域上形成氧化钽薄膜，再在氧化锆薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.661V，短路电流9.64A，光电转换效率20.39％。
对比例16
本对比例提供了一种采用氧化铪(HfO x)钝化的晶体硅太阳能电池，本对比例提供的太阳能电池与实施例18提供的太阳能电池的区别在于，本对比例提供的太阳能电池中采用氧化铪薄膜替代氧化镓薄膜。在制备太阳能电池时，先在P型晶体硅基体背面的背面掺杂多晶硅层以及背面隧穿钝化层未设置掺杂多晶硅层的区域上形成氧化铪薄膜，再在氧化铪薄膜上形成氮化硅薄膜。
按照实施例1的测试方法和测试条件对本实施例提供的太阳能电池的性能进行测试，结果为：开路电压0.668V，短路电流9.67A，光电转换效率20.62％。
以下表4中，对以上实施例18～23和对比例13～16的太阳能电池的性能测试结果进行了汇总。
表4太阳性能测试结果汇总
序号 氧化物类型 氧化物薄膜厚度 开路电压 短路电流 光电转换效率
实施例18 氧化镓 20纳米 0.668V 9.74A 20.76％
实施例19 氧化镓 10纳米 0.660V 9.72A 20.24％
实施例20 氧化镓 40纳米 0.669V 9.81A 20.87％
实施例21 氧化镓 60纳米 0.669V 9.79A 20.68％
实施例22 氧化镓 75纳米 0.668V 9.78A 20.58％
实施例23 氧化镓 90纳米 0.668V 9.78A 20.49％
对比例13 —— —— 0.642V 8.5A 17.29％
对比例14 氧化锆 20纳米 0.660V 9.54A 20.08％
对比例15 氧化钽 20纳米 0.661V 9.64A 20.39％
对比例16 氧化铪 20纳米 0.668V 9.67A 20.62％
通过以上实施例和对比例的测试数据可以看出，与未设置氧化镓层以及以其他氧化物代替氧化镓进行钝化的情况相比，采用氧化镓对P型硅表面进行钝化有利于提高晶体硅太阳能电池的光电转换效率。
以上所述仅是为了便于本领域的技术人员理解本公开的技术方案，并不用以限制本公开。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (23)

  1. 晶体硅太阳能电池，包括与所述晶体硅太阳能电池中P型硅层直接接触的氧化镓层。
  2. 根据权利要求1所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池包括：导电类型为N型的晶体硅基体，及设置在所述晶体硅基体一侧表面、且导电类型为P型的发射极层；
    所述氧化镓层设置在所述发射极层上且与所述发射极层直接接触。
  3. 根据权利要求2所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池还包括：
    设置在所述氧化镓层上的第一覆盖层，
    设置在所述第一覆盖层上、且与所述发射极层接触的第一电极，
    设置在所述晶体硅基体与所述发射极层相对一侧表面、且导电类型为N型的表面场层，
    设置在所述表面场层上的第二覆盖层，以及，
    设置在所述第二覆盖层上、且与所述表面场层接触的第二电极。
  4. 根据权利要求2所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池还包括：
    设置在所述氧化镓层上的第一覆盖层，
    设置在所述第一覆盖层上、且与所述发射极层接触的第一电极，
    设置在所述晶体硅基体与所述发射极层相对一侧表面的隧穿钝化层，
    设置在所述隧穿钝化层上、且导电类型为N型的掺杂硅层，
    设置在所述掺杂硅层上的第二覆盖层，以及，
    设置在所述第二覆盖层上、且与所述掺杂硅层接触的第二电极。
  5. 根据权利要求4所述的晶体硅太阳能电池，其特征在于，所述掺杂硅层覆盖所述隧穿钝化层的局部区域，所述隧穿钝化层未设置所述掺杂硅层的区域上也设置有所述第二覆盖层。
  6. 根据权利要求2～5任一项所述的晶体硅太阳能电池，其特征在于，所述氧化镓层的厚度为1纳米～120纳米。
  7. 根据权利要求1所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池包括：导电类型为P型的晶体硅基体；
    所述氧化镓层设置在所述晶体硅基体一侧表面上且与所述晶体硅基体直接接触。
  8. 根据权利要求7所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池还包括：
    设置在所述氧化镓层上的第三覆盖层，
    设置在所述第三覆盖层上、且与所述晶体硅基体接触的第三电极，
    设置在所述晶体硅基体与所述氧化镓层相对一侧表面、且导电类型为N型的发射极层，
    设置在所述发射极层上的第四覆盖层，以及，
    设置在所述第四覆盖层上、且与所述发射极层接触的第四电极。
  9. 根据权利要求7所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池还包括：
    设置在所述氧化镓层上的第三覆盖层，
    设置在所述第三覆盖层上、且与所述晶体硅基体接触的第三电极，
    设置在所述晶体硅基体与所述氧化镓层相对一侧表面、且导电类型为N型的发射极层，
    设置在所述发射极层上的隧穿钝化层，
    设置在所述隧穿钝化层上、且导电类型为N型的掺杂硅层，
    设置在所述掺杂硅层上的第四覆盖层，以及，
    设置在所述第四覆盖层上、且与所述掺杂硅层接触的第四电极。
  10. 根据权利要求9所述的晶体硅太阳能电池，其特征在于，所述掺杂硅层覆盖所述隧穿钝化层的局部区域，所述隧穿钝化层未设置所述掺杂硅层的区域上也设置有所述第四覆盖层。
  11. 根据权利要求8～10任一项所述的晶体硅太阳能电池，其特征在于，所述氧化镓层和所述第三覆盖层上对应设置有过孔；
    所述晶体硅基体表面与所述过孔对应的区域形成有导电类型为P型的表面场层。
  12. 根据权利要求11所述的晶体硅太阳能电池，其特征在于，所述第三电极包括第一部分和第二部分，所述第一部分呈线形，所述第二部分设置在所述第三覆盖层上位于所述第一部分以外的区域，且所述第二部分与所述第一部分接触；
    所述第二部分通过所述过孔与所述晶体硅基体接触，并在所述晶体硅基体表面与所述过孔对应的区域形成所述表面场层。
  13. 根据权利要求7～10任一项所述的晶体硅太阳能电池，其特征在于，所述氧化镓层的厚度为1纳米～1000纳米。
  14. 根据权利要求1所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池包括：
    导电类型为P型的晶体硅基体，
    设置在所述晶体硅基体一侧表面的第一隧穿钝化层，
    设置在所述第一隧穿钝化层上、且导电类型为P型的第一掺杂硅层，
    设置在所述第一掺杂硅层上的氧化镓层，
    设置在所述氧化镓层上的第五覆盖层，以及，
    设置在所述第五覆盖层上、且与所述第一掺杂硅层接触的第五电极。
  15. 根据权利要求14所述的晶体硅太阳能电池，其特征在于，所述第一掺杂硅层覆盖所述第一隧穿钝化层的局部区域，所述第一隧穿钝化层未设置所述第一掺杂硅层的区域上也设置有所述氧化镓层。
  16. 根据权利要求14或15所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池还包括：
    设置在所述晶体硅基体与所述第一隧穿钝化层相对一侧表面、且导电类型为N型的发射极层，
    设置在所述发射极层上的第六覆盖层，以及，
    设置在所述第六覆盖层上、且与所述发射极层接触的第六电极。
  17. 根据权利要求14或15所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池还包括：
    设置在所述晶体硅基体与所述第一隧穿钝化层相对一侧表面、且导电类型为N型的发射极层，
    设置在所述发射极层上的第二隧穿钝化层，
    设置在所述第二隧穿钝化层上、且导电类型为N型的第二掺杂硅层，
    设置在所述第二掺杂硅层上的第六覆盖层，以及，
    设置在所述第六覆盖层上、且与所述第二掺杂硅层接触的第六电极。
  18. 根据权利要求17所述的晶体硅太阳能电池，其特征在于，所述第二掺杂硅层覆盖所述第二隧穿钝化层的局部区域，所述第二隧穿钝化层未设置所述第二掺杂硅层的区域上也设置有所述第六覆盖层。
  19. 根据权利要求14或15所述的晶体硅太阳能电池，其特征在于，所述氧化镓层的厚度为10纳米～90纳米。
  20. 光伏组件，包括依次设置的盖板、第一封装胶膜，电池串、第二封装胶膜和背板，所述电池串包括多个太阳能电池，所述太阳能电池为权利要求1～19任一项所述的晶体硅太阳能电池。
  21. 晶体硅太阳能电池的制备方法，包括：形成与所述晶体硅太阳能电池中P型硅层直接接触的氧化镓层。
  22. 氧化镓在晶体硅太阳能电池中作为钝化物或钝化结构的应用。
  23. 根据权利要求22所述的应用，其特征在于，所述氧化镓与所述晶体硅太阳能电池的P型硅层直接接触。
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