WO2019233562A1 - Agencement de traitement de signal destiné à un émetteur, et procédé pour un tel agencement - Google Patents

Agencement de traitement de signal destiné à un émetteur, et procédé pour un tel agencement Download PDF

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Publication number
WO2019233562A1
WO2019233562A1 PCT/EP2018/064741 EP2018064741W WO2019233562A1 WO 2019233562 A1 WO2019233562 A1 WO 2019233562A1 EP 2018064741 W EP2018064741 W EP 2018064741W WO 2019233562 A1 WO2019233562 A1 WO 2019233562A1
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WO
WIPO (PCT)
Prior art keywords
signal
phase
converted
processing arrangement
signal processing
Prior art date
Application number
PCT/EP2018/064741
Other languages
English (en)
Inventor
Liang RONG
Bingxin Li
Chen Wang
Fuquan Zhang
Jinming WANG
Xun GU
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to CN201880093412.0A priority Critical patent/CN112119618B/zh
Priority to PCT/EP2018/064741 priority patent/WO2019233562A1/fr
Publication of WO2019233562A1 publication Critical patent/WO2019233562A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0483—Transmitters with multiple parallel paths
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/336—A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits

Definitions

  • aspects of the present invention relate to a signal processing arrangement for a transmitter. More specifically, aspects of the present invention relate to a signal processing arrangement configured to perform a part of a digital filtering. Aspects of the present invention also relate to a transmitter including a signal processing arrangement and to a method for a signal processing arrangement.
  • CMOS Complementary Metal Oxide Semiconductor
  • An objective of embodiments of the invention is to provide a solution which mitigates or solves the drawbacks and problems of conventional solutions.
  • Another objective of embodiments of the present invention is to provide an improved DTX/DPA architecture for a transmitter.
  • the above-mentioned and other objectives are attained by providing a signal processing arrangement for a transmitter, wherein the signal processing arrangement comprises:
  • an in-phase demodulator configured to receive a modulated in-phase signal, demodulate the modulated in-phase signal and output a demodulated in-phase signal
  • a quadrature demodulator configured to receive a modulated quadrature signal, demodulate the modulated quadrature signal and output a demodulated quadrature signal
  • a first up-conversion and mixing module configured to receive the demodulated in- phase signal and the demodulated quadrature signal, up-convert and mix the demodulated in-phase signal and the demodulated quadrature signal and output a first up-converted and mixed positive phase signal and a second up-converted and mixed positive phase signal
  • a second up-conversion and mixing module configured to receive the demodulated in-phase signal and the demodulated quadrature signal, up-convert and mix the demodulated in-phase signal and the demodulated quadrature signal and output a first up- converted and mixed negative phase signal and a second up-converted and mixed negative phase signal;
  • a first harmonic filter configured to receive the first up-converted and mixed positive phase signal and the second up-converted and mixed positive phase signal, perform a part of a digital filtering of the first up-converted and mixed positive phase signal and the second up-converted and mixed positive phase signal and output a first group of digital signals and a second group of digital signals;
  • a second harmonic filter configured to receive the first up-converted and mixed negative phase signal and the second up-converted and mixed negative phase signal, perform a part of a digital filtering of the first up-converted and mixed negative phase signal and the second up-converted and mixed negative phase signal and output a third group of digital signals and a fourth group of digital signals.
  • an improved DTX/DPA architecture for a transmitter is provided.
  • the up- conversion and mixing module/-s is/are placed after the harmonic filters and is/are thus receiving signals from the harmonic filters.
  • the up-conversion and mixing modules can use a lower frequency compared to conventional DTX/DPA architectures, and thus the power consumption can be reduced.
  • the number of digital building blocks in the up- conversion and mixing module and in a following serializer can be reduced, which reduces the power consumption and also saves more design area on the chip in relation to conventional DTX/DPA architectures.
  • the complexity of the structure of the following serializer can also be reduced, e.g. there is no need for channel combinations and cross overs in the serializer, and thus results in a reduction of the amount of manual work in favour of digital programming parts in the DTX/DPA architecture.
  • the performance of the DTX/DPA transmitter is improved.
  • the demodulation in the demodulators and the up-converting and mixing process in the up- conversion and mixing modules can be simplified.
  • the number of input signal groups to the up-conversion and mixing modules can be further reduced by the order of the digital filtering of the harmonic filters in relation to conventional technology, and the power consumption is further reduced by‘N’ times, where‘N’ is the digital filter order.
  • Each harmonic filter is configured to perform an at least a part of a digital filtering and hence not necessarily configured to perform the complete digital filtering of the signals. Further filtering steps are, or may be, performed by modules/blocks following the harmonic filters, e.g. as described in the detailed description hereinbelow.
  • the in-phase demodulator and the quadrature demodulator are configured to operate at a modulation frequency
  • the first up-conversion and mixing module and the second up-conversion and mixing module are configured to use the modulation frequency
  • the first harmonic filter and the second harmonic filter are configured to operate at a carrier frequency which exceeds the modulation frequency.
  • the wording“the first up-conversion and mixing module and the second up-conversion and mixing module are configured to use a frequency” can mean that they are configured to receive a signal at the frequency of the previous module.
  • the first harmonic filter and the second harmonic filter are configured to operate at a carrier frequency which is at least twice as high as the modulation frequency.
  • the signal processing arrangement comprises a serializer configured to receive the first and second groups of digital signals from the first harmonic filter and the third and fourth groups of digital signals from the second harmonic filter, serialize digital signals of the first, second, third and fourth groups of digital signals into serialized digital signals, and output the serialized digital signals.
  • the serializer can be directly connected to the harmonic filters. Further, by means of this implementation form, fully switching high-efficiency power amplifiers can be directly connected to the serializer.
  • the serializer is configured to operate at a local oscillator frequency which exceeds the carrier frequency.
  • the data rate speed can be matched to previous signal processing blocks, or modules, and an efficient signal processing is provided.
  • the serializer is configured to operate at a local oscillator frequency which is at least twice as high as the carrier frequency.
  • the serializer is configured to operate at a local oscillator frequency which is equal to the carrier frequency.
  • the same clock signal to the harmonic filter and the serializer can be used.
  • the signal processing arrangement comprises a plurality of power amplifiers, wherein each power amplifier of the plurality of power amplifiers is configured to receive a serialized digital signal among the serialized digital signals, power amplify the serialized digital signal and output a power-amplified digital signal.
  • each signal path may have a different power amplification level, and the plurality of power amplifiers may realize a part of the digital filtering.
  • the signal processing arrangement comprises:
  • an in-phase modulator configured to receive an in-phase signal, modulate the in- phase signal and output the modulated in-phase signal
  • a quadrature modulator configured to receive a quadrature signal, modulate the quadrature signal and output the modulated quadrature signal.
  • each of the in-phase modulator and the quadrature modulator is configured to perform Pulse Code Modulation.
  • each of the in-phase modulator and the quadrature modulator is configured to perform Pulse Width Modulation.
  • Pulse Code Modulation or Pulse Width Modulation in the in-phase modulator and the quadrature modulator simplifies the circuit design and increases the possible processing speed in comparison with modulators configured to perform sigma-delta modulation. Furthermore, the use of Pulse Code Modulation or Pulse Width Modulation in the in-phase modulator and the quadrature modulator improves the noise shaping performance in comparison with modulators configured to perform sigma-delta modulation.
  • each of the in-phase modulator and the quadrature modulator is configured to operate at the modulation frequency.
  • each of the in-phase demodulator and the quadrature demodulator is configured to perform Pulse Code Demodulation.
  • each of the in-phase demodulator and the quadrature demodulator is configured to perform Pulse Width Demodulation.
  • Pulse Code Modulation or Pulse Width Modulation in the in-phase demodulator and the quadrature demodulator simplifies the circuit design and increases the possible processing speed. Furthermore, the use of Pulse Code Modulation or Pulse Width Modulation in the in-phase demodulator and the quadrature demodulator improves the noise shaping performance.
  • each of the in-phase demodulator and the quadrature demodulator is configured to perform a linear mapping of Pulse Code Modulation or Pulse Width Modulation codes into different Pulse Width demodulation pulse width representations based on a Look-Up Table mapping.
  • each of the first harmonic filter and the second harmonic filter comprises at least one harmonic filter block having two inputs configured to receive signals from the respective up-conversion and mixing module, wherein each harmonic filter block comprises a plurality of first-phase data shifters and a plurality of second-phase data shifters, wherein a multiplexer is arranged between a first-phase data shifter of the plurality of first-phase data shifters and a previous first-phase data shifter of the plurality of first- phase data shifters, wherein a multiplexer is arranged between a second-phase data shifter of the plurality of second-phase data shifters and a previous second-phase data shifter of the plurality of second-phase data shifters except before a first first-phase data shifter of the plurality of first-phase data shifters and a first second-phase data shifter of the plurality of second-phase data shifters, and wherein the multiplexer is configured to output signals to only one of a first-phase data shift
  • a multiplexer is arranged between a first input of the two inputs of the harmonic filter block and each of the first-phase data shifters, and a multiplexer is arranged between a second input of the two inputs of the harmonic filter block and each of the second-phase data shifters except before the first first-phase data shifter and the first second-phase data shifter.
  • each first-phase data shifter of the first harmonic filter is configured to output a digital signal of the first group of digital signals
  • each second-phase data shifter of the first harmonic filter is configured to output a digital signal of the second group of digital signals
  • each first-phase data shifter of the second harmonic filter is configured to output a digital signal of the third group of digital signals
  • each second-phase data shifter of the second harmonic filter is configured to output a digital signal of the fourth group of digital signals.
  • the above-mentioned and other objectives are attained by providing a transmitter comprising a signal processing arrangement according to the first aspect.
  • the above-mentioned and other objectives are attained by providing a method for a signal processing arrangement, the method comprising:
  • an implementation form of the method comprises the feature(s) of the corresponding implementation form of the signal processing arrangement.
  • the invention also relates to a computer program, characterized in program code, which when run by at least one processor causes said at least one processor to execute any method according to embodiments of the invention. Further, the invention also relates to a computer program product comprising a computer readable medium and said mentioned computer program, wherein said computer program is included in the computer readable medium, and comprises of one or more from the group: ROM (Read-Only Memory), PROM (Programmable ROM), EPROM (Erasable PROM), Flash memory, EEPROM (Electrically EPROM) and hard disk drive.
  • ROM Read-Only Memory
  • PROM Programmable ROM
  • EPROM Erasable PROM
  • Flash memory Flash memory
  • EEPROM Electrically EPROM
  • Fig. 1 schematically illustrates a signal processing arrangement for a transmitter
  • Fig. 2 schematically illustrates a signal processing arrangement for a transmitter
  • Fig. 3 schematically illustrates a transmitter comprising a signal processing
  • Fig. 4 is a schematic diagram illustrating an embodiment of a harmonic filter block of the first harmonic filter or second harmonic filter
  • Fig. 5 is a schematic diagram illustrating a signal processing arrangement and a
  • Fig. 6 schematically illustrates a transmitter device in a wireless communication system including embodiments of the present invention.
  • Fig. 7 is a flow chart schematically illustrating aspects of a method according to the present invention.
  • CMOS technology provides the motivation for the inventors to realize a DTX/DPA in a pure digital style.
  • a DTX/DPA architecture according to conventional technology the demand of using digital signal processing as much as possible removes the use of a digital-to-analog converter (DAC).
  • the DAC is replaced by a digital up-sampling module to align the data flow bit rate with a digital carrier signal later in the DTX/DPA.
  • the analog channel bandwidth filter is also removed.
  • a noise shaping algorithm/module may be used to enhance the signal-to-noise performance, and during this stage different DPA modulation algorithms and different types of DPAs emerged.
  • ADC analog-to-digital
  • SDM sigma-delta modulation
  • PWM pulse width modulation
  • a DTX/DPA is a transmitter architecture which implements mostly digital switching blocks/modules for signal processing/modulation and switching power amplifiers (PA) as output stage to amplify output RF power.
  • a DTX/DPA is different from a traditional analog/RF transmitter because the internal signal flow has mostly on/off switching digital characteristics instead of a continuous analog/RF signal.
  • the digital signal with multiple level representation often needs to be further processed and mapped into a fully switching on/off (O’s or Ts) signal.
  • the digital demodulation module may be used.
  • the digital signal will finally be synchronized into bit rates for the digital carrier signal and is turned into a fully ones/zeros bit sequence.
  • the demodulation method can match the previous modulation algorithm but it is also possible to use a combination of modulation techniques.
  • SDM modulation may use ADC or PWM style demodulation methods.
  • digital up- conversion and mixing may also be realized in digital style.
  • ‘1010...10’ represents 0-degree phase carrier signal
  • its complementary signal ⁇ 101 ...0T represents 180-degree negative phase signal.
  • l-channel and Q- channel carrier frequency signals can be represented in digital bits. This greatly facilitates the RF digital up-conversion process since a simple‘AND’ logic operation is sufficient. Since the digital RF l/Q carrier signal has a fixed pattern for every baseband modulation cycle, a batch process can help to reduce the processing clock frequency, and parallel data bits are generated during this process.
  • a digital signal may be modulated into an in-phase signal and a quadrature signal.
  • SDM sigma-delta modulation
  • PWM pulse-width modulation
  • a digital demodulation module connected to the digital demodulation modules are repeaters configured to data-rate match the signal from PWM to the RF carrier signal.
  • an interleaver module Connected to the repeaters is an interleaver module which realizes digital up-conversion and mixing.
  • the mixed digital signal is then fed to a power amplifier (PA).
  • PA power amplifier
  • the power amplifier is connected to a load which is configured to radiate RF signal into the surrounding air.
  • DTX/DPA modulation harmonics
  • modulation harmonics are quite common for DTX/DPAs which use a different modulation processing frequency different from the carrier frequency.
  • modulation harmonics will be quite close to the band- of-interest and then the system bandpass filter may be quite hard to attenuate.
  • a DTX/DPA architecture such as a DTX/DPA architecture in a pure digital style, which provides a solution which mitigates or solves the drawbacks and problems of conventional solutions.
  • Fig. 1 schematically illustrates a signal processing arrangement 100 for a transmitter according to an embodiment of the invention.
  • the signal processing arrangement 100 includes an in-phase demodulator 106 configured to receive a modulated in-phase signal IM, demodulate the modulated in-phase signal IM and output a demodulated in-phase signal IDM.
  • the signal processing arrangement 100 includes a quadrature demodulator 108 configured to receive a modulated quadrature signal Q M , demodulate the modulated quadrature signal Q M and output a demodulated quadrature signal QDM-
  • the signal processing arrangement 100 of Fig. 1 also includes a first up-conversion and mixing module 1 1 0 configured to receive the demodulated in-phase signal I D M and the demodulated quadrature signal QDM, up-convert and mix the demodulated in-phase signal IDM and the demodulated quadrature signal QDM and output a first up-converted and mixed positive phase signal IQPA and a second up-converted and mixed positive phase signal IQPB.
  • a first up-conversion and mixing module 1 1 0 configured to receive the demodulated in-phase signal I D M and the demodulated quadrature signal QDM, up-convert and mix the demodulated in-phase signal IDM and the demodulated quadrature signal QDM and output a first up-converted and mixed positive phase signal IQPA and a second up-converted and mixed positive phase signal IQPB.
  • the signal processing arrangement 100 includes a second up-conversion and mixing module 1 1 2 configured to receive the demodulated in-phase signal IDM and the demodulated quadrature signal QDM, up-convert and mix the demodulated in-phase signal IDM and the demodulated quadrature signal QDM and output a first up-converted and mixed negative phase signal IQNA and a second up-converted and mixed negative phase signal IQNB.
  • a second up-conversion and mixing module 1 1 2 configured to receive the demodulated in-phase signal IDM and the demodulated quadrature signal QDM, up-convert and mix the demodulated in-phase signal IDM and the demodulated quadrature signal QDM and output a first up-converted and mixed negative phase signal IQNA and a second up-converted and mixed negative phase signal IQNB.
  • the signal processing arrangement 100 includes a first harmonic filter 1 14 configured to receive the first up-converted and mixed positive phase signal IQPA and the second up-converted and mixed positive phase signal IQPB, perform a part of a digital filtering of the first up-converted and mixed positive phase signal IQ PA and the second up- converted and mixed positive phase signal IQ PB and output a first group of digital signals IQPDAI , IQPDA2, , IQpDAn and a second group of digital signals IQPDEM , IQPDB2, . . . , IQPDB R .
  • the signal processing arrangement 100 also includes a second harmonic filter 1 16 configured to receive the first up-converted and mixed negative phase signal IQNA and the second up- converted and mixed negative phase signal IQNB, perform a part of a digital filtering of the first up-converted and mixed negative phase signal IQNA and the second up-converted and mixed negative phase signal IQNB and output a third group of digital signals IQNDAI , IQNDA2, . . , IQNDA H and a fourth group of digital signals IQNDBI , IQNDB2, . . . , IQNDB R .
  • Each harmonic filter 1 14, 1 16 is configured to perform at least pa/Tof a digital filtering.
  • the harmonic filter 1 14, 1 16 do not need to be configured to perform the complete digital filtering of the signals. Instead, further filtering steps are performed by modules/blocks, such as power amplifiers 130a, 130b,..., 130n and a power combination filter 136, following the harmonic filters 1 14, 1 16, as described below in connection with Fig. 3.
  • modules/blocks such as power amplifiers 130a, 130b,..., 130n and a power combination filter 136, following the harmonic filters 1 14, 1 16, as described below in connection with Fig. 3.
  • the in-phase demodulator 106 and the quadrature demodulator 108 are configured to operate at a modulation frequency f m
  • the first up-conversion and mixing module 1 10 and the second up-conversion and mixing module 1 12 are configured to use the modulation frequency f m
  • the first harmonic filter 1 14 and the second harmonic filter 1 16 are configured to operate at a carrier frequency f c which exceeds the modulation frequency f m .
  • the up-conversion and mixing modules 1 10, 1 12 can use a lower frequency compared to conventional DTX/DPA architectures, and thus the power consumption can be reduced.
  • the first harmonic filter 1 14 and the second harmonic filter 1 16 may even be configured to operate at a carrier frequency f c which is at least twice as high as the modulation frequency f m .
  • the first up- conversion and mixing module 1 10 is configured to up-convert and mix the demodulated in- phase signal IDM and the demodulated quadrature signal QDM based on at least one group of local oscillation, LO, patterns, e.g. two groups of LO patterns L01 and L02.
  • the second up-conversion and mixing module 1 12 is configured to up-convert and mix the demodulated in-phase signal IDM and the demodulated quadrature signal QDM based on the group/-s of LO patterns L01 , L02 used by the first up-conversion and mixing module 1 10.
  • the up-conversion and mixing is based on a group of LO patterns, one or more patterns/values of that group of LO patterns may be applied.
  • a first group of LO patterns according to an eight bits version may be as follows:
  • Q_lo1_negative 0001 .0001
  • a second group of LO patterns according to an eight bits version may be as follows:
  • the modulated in-phase signal IM value is +3, and the modulated quadrature signal QM value is -2.
  • +3 (IM) is demodulated into 0.01 1 1 .1 1 10 (I D M), where the first ⁇ ’ represents the“positive value”, and the last four digits‘1 1 10’ are the mirror of the 8-to-5 bits ⁇ 1 1 1’ in left-right-swap style.
  • -2 (Q M ) is demodulated into 1 .001 1 .1 100 (QDM) , where the first‘1’ represent the“negative value”.
  • the first up-conversion and mixing module 1 10 translates the input data from the in-phase demodulator 106 and the quadrature demodulator 108, but its purpose is only to up-convert and mix the input with positive phase LO and output positive phase values.
  • the first up-conversion and mixing module 1 10 receives the demodulated value 0.01 1 1 .1 1 10 (IDM) from the in-phase demodulator 106 and the demodulated value 1 .001 1 .1 100 (QDM) from the quadrature demodulator 108
  • the first up-conversion and mixing module 1 10 recognizes that the original modulated in-phase signal IM is a positive value and that there should be an up-conversion with the positive IJo pattern.
  • the first up-conversion and mixing module 1 10 ‘bit AND’- operates on the value 0.01 1 1 .1 1 10 (I DM) with 1000.1000 ( IJo 1 _positive) and obtains the temporary value/data 0000.1000. Further, the first up-conversion and mixing module 1 10 also needs to‘bit AND’-operate on the Q path value, but since the Q value is negative, the first up-conversion and mixing module 1 10 up-converts 001 1 .1 100 (QDM) with 0001 .0001 (Q_lo1_negative) and obtains the temporary data 0001 .0000.
  • the final operation in the first up-conversion and mixing module 1 10 is to mix the two temporary data 0000.1000 and 0001 .0000 by a ‘bit OR’ operation, and the first output 0001 .1000 from the first up- conversion and mixing module 1 10 is provided, i.e. the first up-converted and mixed positive phase signal IQ PA .
  • the second up-conversion and mixing module 1 12 also receives the data 0.01 1 1 .1 1 10 (I DM) and 1 .001 1 .1 100 (QDM) but are used for generating negative phase up-converted and mixed data.
  • the second up-conversion and mixing module 1 12 when the second up-conversion and mixing module 1 12 recognizes that the original modulated in-phase signal IM is a positive value and the original modulated quadrature signal QM is a negative value, the second up-conversion and mixing module 1 12 up-converts 01 1 1 .1 1 10 ( IDM) with 0010.0010 (IJo1_negative) and up- converts 001 1 .1 100 (QDM) with 0100.0100 (Q_lo1_positive). Then, the two temporary data in the second up-conversion and mixing module 1 12 are 0010.0010 and 0000.0100, and after‘bit OR’ mixing, the output 0010.01 10 is provided, i.e. the first up-converted and mixed negative phase signal IQNA.
  • the second group of LO patterns is applied in a corresponding manner.
  • the first up-conversion and mixing module 1 10 is used to translate input data/signals from the in-phase demodulator 106 and the quadrature demodulator 108.
  • the purpose of the first up-conversion and mixing module 1 10 is to up-convert and mix input signals with LO patterns and output the first up- converted and mixed positive phase signal IQ PA and the second up-converted and mixed positive phase signal IQ PB .
  • the second up-conversion and mixing module 1 12 is also used to translate input data/signals from the in-phase demodulator 106 and the quadrature demodulator 108.
  • the purpose of the second up-conversion and mixing module 1 12 is to up-convert and mix input signals with the LO patterns and output the first up-converted and mixed negative phase signal IQNA and the second up-converted and mixed negative phase signal IQNB.
  • Each of the in-phase demodulator 106 and the quadrature demodulator 108 may be configured to perform Pulse Code Demodulation. Alternatively, each of the in-phase demodulator 106 and the quadrature demodulator 108 may be configured to perform Pulse Width Demodulation. Each of the in-phase demodulator 106 and the quadrature demodulator 108 may be configured to perform a linear mapping of Pulse Code Modulation or Pulse Width Modulation codes into different Pulse Width demodulation pulse width representations based on a Look-Up Table, LUT, mapping, whereby an efficient signal processing is provided.
  • Fig. 2 schematically illustrates a signal processing arrangement 101 for a transmitter according to a further embodiment.
  • the signal processing arrangement 101 includes, in addition to the modules/blocks disclosed in Fig. 1 and described above, an in-phase modulator 102 configured to receive an in-phase signal I, modulate the in-phase signal I and output the modulated in-phase signal l M , and a quadrature modulator 104 configured to receive a quadrature signal Q, modulate the quadrature signal Q and output the modulated quadrature signal QM.
  • Each of the in-phase modulator 102 and the quadrature modulator 104 may be configured to perform Pulse Code Modulation, PCM.
  • each of the in-phase modulator 102 and the quadrature modulator 104 may be configured to perform Pulse Width Modulation, PWM.
  • PWM Pulse Width Modulation
  • Each of the in-phase modulator 102 and the quadrature modulator 104 is configured to operate at the modulation frequency f m at which the in-phase demodulator 106 and the quadrature demodulator 108 are configured to operate.
  • Fig. 3 schematically illustrates an embodiment of a transmitter 200 comprising the signal processing arrangement 101 as disclosed above in relation to Fig. 2.
  • the signal processing arrangement 101 includes a serializer 1 18 configured to receive the first and second groups of digital signals IQPDAI , IQPDA2, . . . , IQPDAH; IQPDBI , IQPDB2, . . . , IQPDBH from the first harmonic filter 1 14 and the third and fourth groups of digital signals IQNDAI , IQNDA2, . . .
  • the serializer 1 18 may be configured to operate at a local oscillator frequency f to which exceeds the carrier frequency f c .
  • the serializer 1 18 is configured to operate at a local oscillator frequency fi 0 which is at least twice as high as the carrier frequency f c .
  • the serializer 1 18 may be configured to operate at a local oscillator frequency fi 0 which is equal to the carrier frequency f c .
  • One aspect of the disclosed embodiments is that the processing delay can be more accurately controlled when the data is sent from the respective harmonic filter 1 14, 1 16 to the serializer 1 18, and the serializer 1 18, which may be a high-speed serializer, can accept data at a more accurate timing instead of conventional information-dependent delayed data.
  • the signal processing arrangement 101 of Fig. 3 includes a plurality of power amplifiers 130a, 130b,..., 130n.
  • Each power amplifier 130a, 130b,..., 130n of the plurality of power amplifiers 130a, 130b,..., 130n is configured to receive a serialized digital signal among the serialized digital signals from the serializer 1 18, power amplify the serialized digital signal and output a power-amplified digital signal.
  • the power amplifiers 130a, 130b,..., 130n connected to the serializer 1 18 are configured to perform a part of the digital filtering by adding signal weight (increasing/decreasing power level).
  • a switching capacitance power combination network may realize the final step of digital filtering and combine multiple power amplifiers output power into simple single-ended or differential output power.
  • the transmitter 200 may include a power combination filter 136 which realizes steps of the filtering and combines the power-amplified serialized digital signals into a combined output signal which is output to a load in the form of an antenna 138.
  • the power combination filter 136 may be realized in a large number of ways and its function is to combine the power amplified serialized digital signals from the power amplifiers 130a, 130b,..., 130n. With reference to Fig. 3, the final signal processing steps are made in the power combination filter 136.
  • the first harmonic filter 1 14 may be configured to realize a part of the signal processing steps necessary for filtering out modulation harmonics in the demodulated in-phase signal IDM and in the demodulated quadrature signal QDM.
  • the second harmonic filter 1 16 may be configured to realize a part of the signal processing steps necessary for filtering out modulation harmonics in the demodulated in-phase signal IDM and in the demodulated quadrature phase signal QDM.
  • the remainder of the steps needed for filtering out modulation harmonics in the demodulated in-phase signal IDM and in the demodulated quadrature signal QDM are performed in the power combination filter 136 after the serializer 1 18.
  • the antenna 138 is connected to the power combination filter 136.
  • the transmitter 200 includes a digital up-sampling device 132 comprising an input 134.
  • the digital up-sampling device 132 does not necessarily form part of the signal processing arrangement 101 .
  • the digital up-sampling device 132 is configured to receive a digital input signal SIN via the input 134 and up-sample and transform the digital input signal SIN into an in-phase signal I and a quadrature signal Q.
  • the digital up-sampling device 132 is driven by a first clock signal CLK1 .
  • the in-phase modulator 102 and the quadrature modulator 104 are driven by the first clock signal CLK1 .
  • the frequency of the first clock signal CLK1 is called the modulation frequency f m .
  • the in-phase demodulator 106 and the quadrature demodulator 108 are also driven by the first clock signal CLK1 .
  • the first harmonic filter 1 14 and the second harmonic filter 1 16 are driven by a second clock signal CLK2 of a first phase PH1 and a second phase PH2.
  • the frequency of the second clock signal CLK2 is called the carrier frequency f c .
  • the serializer 1 18 is driven by a third clock signal CLK3 having the local oscillator frequency fi 0 , which may be at least twice as high as the carrier frequency f c .
  • each of the first harmonic filter 1 14 and the second harmonic filter 1 16 is illustrated in more detail.
  • Each of the first harmonic filter 1 14 and the second harmonic filter 1 16 includes at least one harmonic filter block 140 which has two inputs 142, 144 configured to receive signals IQPA, IQPB; IQNA, IQNB from the first up-conversion and mixing module 1 10 or the second up-conversion and mixing module 1 12.
  • the harmonic filter block 140 includes a plurality of first-phase data shifters 148, 148’, 148” and a plurality of second- phase data shifters 150, 150’, 150”.
  • a multiplexer (MUX) 152, 152’ is arranged between a first-phase data shifter 148’, 148” of the plurality of first-phase data shifters 148, 148’, 148” and a previous first-phase data shifter 148, 148’ of the plurality of first-phase data shifters 148, 148’, 148”, and a MUX 154, 154’ is arranged between a second-phase data shifter 150’, 150” of the plurality of second-phase data shifters 150, 150’, 150” and a previous second-phase data shifter 150, 150’ of the plurality of second-phase data shifters 150, 150’, 150” except before a first-phase data shifter 148 of the plurality of first-phase data shifters 148, 148’, 148” and a first second-phase data shifter 150 of the plurality of second- phase data shifters 150, 150’, 150”.
  • the MUX 152, 152’, 154, 154’ is configured to output signals to only one of a first- phase data shifter 148’, 148” of the plurality of first-phase data shifters and a second-phase data shifter 150’, 150” of the plurality of second-phase data shifters.
  • a MUX 152, 152’ is arranged between a first input 142 of the two inputs 142, 144 of the harmonic filter block 140 and each of the first-phase data shifters 148’, 148”, and a MUX 154, 154’ is arranged between a second input 144 of the two inputs 142, 144 of the harmonic filter block 140 and each of the second-phase data shifters 150’, 150” except before the first first-phase data shifter 148 and the first second-phase data shifter 150.
  • the first first-phase data shifter 148 is connected to the first input 142 without any intermediate MUX
  • the first second-phase data shifter 150 is connected to the second input 144 without any intermediate MUX.
  • Each MUX 152, 152’, 154, 154’ may be configured to output the signal from the respective input 142, 144 of the harmonic filter block 140 or the signal from a previous data shifter 148, 148’, 150, 150’.
  • Each first-phase data shifter 148, 148’, 148” of the first harmonic filter 1 14 is configured to output a digital signal of the first group of digital signals IQPDAI , IQPDA2, . . . , IQPDA R .
  • Each second-phase data shifter 150, 150’, 150” of the first harmonic filter 1 14 is configured to output a digital signal of the second group of digital signals IQPDEM , IQPDB2. . . IQPDB R .
  • Each first-phase data shifter 148, 148’, 148” of the second harmonic filter 1 16 is configured to output a digital signal of the third group of digital signals IQNDAI , IQNDA2, . . . , IQNDA R .
  • Each second-phase data shifter 150, 150’, 150” of the second harmonic filter 1 16 is configured to output a digital signal of the fourth group of digital signals IQNDBI , IQNDB2, ⁇ ⁇ ⁇ , IQNDB R .
  • a first vertical line 156 with arrows represents the above-mentioned first phase PH1
  • a second vertical line 158 with arrows represents the above-mentioned second phase PH2.
  • each filter block 140 may include any suitable number of data shifters 148, 148’, 148”, 150, 150’, 150” and any suitable number of multiplexers 152, 152’, 154, 154’.
  • a first path can be defined by the in-phase modulator 102, the in- phase demodulator 106, the first up-conversion and mixing module 1 10 and the first harmonic filter 1 14, and a second path can be defined by the quadrature modulator 104, the quadrature demodulator 108, the second up-conversion and mixing module 1 12 and the second harmonic filter 1 16. It is to be understood that each path of the first and second paths of Fig. 2 may be configured in a cascaded manner, i.e. as a cascaded architecture.
  • Fig. 5 which schematically illustrates a signal processing arrangement 103 and a transmitter 201 according to embodiments
  • three cascaded in-phase modulator blocks 102’ and three cascaded in-phase demodulator blocks 106’ are provided.
  • three cascaded quadrature modulator blocks 104’ and three cascaded quadrature demodulator blocks 108’ are provided.
  • three up-conversion and mixing modules 1 10’ and three harmonic filter blocks 140’ are also provided.
  • a serializer 1 18 is connected to the harmonic filter blocks 140’ and the power amplifiers 130a, 130b,..., 130n.
  • the power amplifiers 130a, 130b,..., 130n are connected to a power combination filter 136, which in turn is connected to an antenna 138.
  • a digital up-sampling device 132 is connected to the modulator blocks 102’, 104’.
  • a digital baseband 160 may be connected to the digital up-sampling device 132.
  • Each demodulator block 106’, 108’ is connected to at least one modulator block 102’, 104’ and an up-conversion and mixing module 1 10’.
  • Each harmonic filter block 140’ is connected to an up-conversion and mixing module 1 10’ and the serializer 1 18.
  • each path of the above- mentioned first and second paths may include any suitable number of cascaded modulator blocks 102’, 104’, demodulator blocks 106’, 108’, up-conversion and mixing modules 1 10’ and harmonic filter blocks 140’.
  • cascaded architecture By means of the cascaded architecture, a lower flat noise floor is provided.
  • Fig. 6 schematically shows a transmitter device 300, e.g. a mobile phone, in a wireless communication system 400.
  • the transmitter device 300 comprises a transmitter 200; 201 according to Fig. 3 or Fig. 5.
  • the wireless communication system 400 also comprises a base station 500 which may also comprise a transmitter 200; 201 , e.g. according to any one of the embodiments described above.
  • the dotted arrow A1 represents transmissions from the transmitter device 300 to the base station 500, which are usually called up-link transmissions.
  • the full arrow A2 represents transmissions from the base station 500 to the transmitter device 300, which are usually called down-link transmissions.
  • the transmitter device 300 including the transmitter 200; 201 herein disclosed may be denoted as a user device, a User Equipment (UE), a mobile station, an internet of things (loT) device, a sensor device, a wireless terminal and/or a mobile terminal, and is enabled to communicate wirelessly in a wireless communication system, sometimes also referred to as a cellular radio system, especially an LTE or New Radio (NR/5G) communication system.
  • UE User Equipment
  • the UEs may further be referred to as mobile telephones, cellular telephones, computer tablets or laptops with wireless capability.
  • the UEs in the present context may be, e.g., portable, pocket-storable, hand-held, computer-comprised, or vehicle-mounted mobile devices, enabled to communicate voice and/or data, via the radio access network, with another entity, such as another receiver or a server.
  • the UE can be a Station (STA), which is any device that contains an IEEE 802.1 1 -conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM).
  • STA Station
  • MAC Media Access Control
  • PHY Physical Layer
  • the UE may also be configured for communication in 3GPP related LTE and LTE-Advanced, in WiMAX and its evolution, and in fifth generation wireless technologies, such as New Radio.
  • the transmitter device 300 may also be a radio client device, an access client device, an access point, or a base station, e.g., a Radio Base Station (RBS), which in some networks may be referred to as transmitter,“gNB”,“gNodeB”,“eNB”,“eNodeB”,“NodeB” or“B node”, depending on the technology and terminology used.
  • RBS Radio Base Station
  • the radio network nodes may be of different classes such as, e.g., macro eNodeB, home eNodeB or pico base station, based on transmission power and thereby also cell size.
  • the radio network node can be a Station (STA), which is any device that contains an IEEE 802.1 1 -conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM).
  • STA Station
  • MAC Media Access Control
  • PHY Physical Layer
  • the radio client device may also be a base station corresponding to the fifth generation (5G) wireless systems.
  • the method 300 comprises:
  • up-converting and mixing 312 the demodulated in-phase signal I DM and the demodulated quadrature signal Q DM and outputting a first up-converted and mixed negative phase signal IQ NA and a second up-converted and mixed negative phase signal IQ NB ; performing 314 a part of a digital filtering of the first up-converted and mixed signal positive phase IQPA and the second up-converted and mixed positive phase signal IQPB and outputting a first group of digital signals IQPDAI , IQPDA2, . . . , IQPDA H and a second group of digital signals IQ PD BI , IQPDB2, . ⁇ ⁇ , IQPDBH ; and
  • any method according to embodiments of the invention may be implemented in a computer program, having code means, which when run by processing means causes the processing means to execute the steps of the method.
  • the computer program is included in a computer readable medium of a computer program product.
  • the computer readable medium may comprise essentially any memory, such as a ROM (Read-Only Memory), a PROM (Programmable Read-Only Memory), an EPROM (Erasable PROM), a Flash memory, an EEPROM (Electrically Erasable PROM), or a hard disk drive.

Abstract

L'invention concerne un agencement de traitement de signal (100; 101; 103) destiné à un émetteur (200; 201). L'agencement de traitement de signal (100) comprend : un premier module de conversion par élévation et de mélange (110) configuré pour convertir par élévation et mélanger un signal en phase démodulé (IDM) et un signal en quadrature démodulé (QDM) et délivrer en sortie un premier signal de phase positive converti par élévation et mélangé (IQPA) et un second signal de phase positive converti par élévation et mélangé (IQPB) ; un second module de conversion par élévation et de mélange (112) configuré pour convertir par élévation et mélanger le signal en phase démodulé (IDM) et le signal de quadrature démodulé (QDM) et délivrer en sortie un premier signal de phase négative converti par élévation et mélangé (IQNA) et un second signal de phase négative converti par élévation et mélangé (IQNB) ; un premier filtre d'harmonique (114) configuré pour recevoir le premier signal de phase positive converti par élévation et mélangé (IQPA) et le second signal de phase positive converti par élévation et mélangé (IQPB) et délivrer en sortie un premier groupe de signaux numériques (IQPDA1, IQPDA2,..., IQPDAn) et un second groupe de signaux numériques (IQPDB1, IQPDB2,..., IQPDBn) ; et un second filtre d'harmonique (116) configuré pour recevoir le premier signal de phase négative converti par élévation et mélangé (IQNA) et le second signal de phase négative converti par élévation et mélangé (IQNB) et délivrer en sortie un troisième groupe de signaux numériques (IQNDA1, IQNDA2,..., IQNDAn) et un quatrième groupe de signaux numériques (IQNDB1, IQNDB2,..., IQNDBn). L'invention concerne également un émetteur (200; 201) et un procédé (300) pour un agencement de traitement de signal (100; 101; 103). Par des modes de réalisation de la présente invention, une architecture DTX/DPA améliorée pour un émetteur est fournie. Dans les architectures DTX/DPA classiques, les modules de conversion par élévation et de mélange sont placés après les filtres d'harmonique et reçoivent ainsi des signaux provenant des filtres d'harmonique. En plaçant les modules de conversion par élévation et de mélange avant les filtres d'harmonique, les modules de conversion par élévation et de mélange utilisent une fréquence inférieure par rapport aux architectures DTX/DPA classiques, et ainsi la consommation d'énergie peut être réduite.
PCT/EP2018/064741 2018-06-05 2018-06-05 Agencement de traitement de signal destiné à un émetteur, et procédé pour un tel agencement WO2019233562A1 (fr)

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PCT/EP2018/064741 WO2019233562A1 (fr) 2018-06-05 2018-06-05 Agencement de traitement de signal destiné à un émetteur, et procédé pour un tel agencement

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