WO2019233206A1 - 计算设备的芯片调频方法、装置、算力板、计算设备及存储介质 - Google Patents

计算设备的芯片调频方法、装置、算力板、计算设备及存储介质 Download PDF

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WO2019233206A1
WO2019233206A1 PCT/CN2019/084064 CN2019084064W WO2019233206A1 WO 2019233206 A1 WO2019233206 A1 WO 2019233206A1 CN 2019084064 W CN2019084064 W CN 2019084064W WO 2019233206 A1 WO2019233206 A1 WO 2019233206A1
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Prior art keywords
frequency
kernel
operating frequency
calculation
operating
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PCT/CN2019/084064
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English (en)
French (fr)
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张楠赓
徐英韬
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北京嘉楠捷思信息技术有限公司
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Application filed by 北京嘉楠捷思信息技术有限公司 filed Critical 北京嘉楠捷思信息技术有限公司
Priority to EP19814964.3A priority Critical patent/EP3805926A4/en
Priority to US17/250,071 priority patent/US11502693B2/en
Priority to CA3102424A priority patent/CA3102424A1/en
Priority to EA202092949A priority patent/EA202092949A1/ru
Publication of WO2019233206A1 publication Critical patent/WO2019233206A1/zh
Priority to US17/973,047 priority patent/US20230043419A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the technical field of chip frequency modulation of a computing device, and in particular, to a chip frequency modulation method, device, computing board, computing device, and storage medium of a computing device.
  • a large number of computing chips are usually integrated. Due to the limitations of the manufacturing process of computing chips, the performance, computing power, and frequency of different computing chips are different. At the same time, a single computing chip usually consists of multiple chips. It consists of two independent cores. The differences in process deviations and pressure drops at different positions in the computing chip also make the actual performance of each core different. Aiming at the difference in working performance of different computing chips and their cores, how to dynamically adjust the actual frequency required by the computing chips and set the adaptive scheme of each core is an urgent problem. In the existing computing equipment, the frequency provided for each computing chip and its core is the same, and the computing advantages of the core with better performance cannot be exerted. The weaker performance core affects the computing performance of the computing chip, and then the computing performance of the overall computing device.
  • Chinese patent application CN201611169618.6 discloses a series power supply chip, a system, a virtual digital mining machine and a server, including an adjustment circuit, which is connected to each series power supply chip to adjust the voltage, temperature or frequency of each series power supply chip. .
  • the adjustment unit performs frequency adjustment on each series power supply chip, it detects whether the working status of each power supply unit in the series power supply chip is normal according to a preset period for each series power supply chip; if the power status of the power supply unit is abnormal, Within the preset frequency range, the working frequency of the unit to be powered that is not working normally is increased or decreased according to the preset frequency step.
  • the status indicated by the status register includes: voltage status, temperature status, working frequency status;
  • the feedback data of the unit data determines whether the working state of the unit to be powered is normal.
  • a detector can be specifically used to detect the series connection of each series power supply chip according to a preset period. Whether the working status of each power supply unit in the power supply chip is normal; if the working status of the power supply unit is abnormal, you can specifically increase or decrease the working status by a regulator within a preset frequency range according to a preset frequency step. The operating frequency of the unit to be powered.
  • CN201611169618.6 discloses that the regulator can adjust the frequency of the chip, but it only adjusts the operating frequency of the chip according to whether the unit to be powered is normally transmitting and receiving data, voltage state, temperature state, frequency state and other operating states. The lack of accuracy of the mechanism does not give full play to the computing performance of the chip.
  • an object of the present invention is to provide a chip frequency modulation method, device, computing board, computing device, and storage medium of a computing device, which can automatically adjust according to the actual computing performance of each core in the computing chip of the computing device.
  • the frequency corresponding to each core so as to maximize the computing performance of the core, thereby improving the computing performance of the computing chip and the overall computing device.
  • the invention provides a chip frequency modulation method of a computing device.
  • the computing device is provided with at least one computing chip, and the computing chip is provided with multiple cores, and the steps include:
  • the operation chip of the computing device is provided with a plurality of the operating frequency points, and a plurality of the kernels in the operation chip are separately operated at each of the operations.
  • the steps of frequency points also include:
  • the step of increasing or decreasing the current operating frequency of the kernel according to the calculation performance indicator of the kernel further includes:
  • the current operating frequency of the kernel is adjusted up or down by the phase locked loop circuit.
  • the phase locked loop circuit is disposed inside or outside the computing chip.
  • a frequency difference between adjacent working frequency points is 1 to 10%.
  • the step of analyzing the calculation performance index of each of the cores at the current working frequency point further includes:
  • a predetermined adjustment period analyze whether the computing performance index of the kernel reaches a predetermined first index threshold, a second index threshold, and / or a third index threshold, where the first index threshold and the second index
  • the thresholds are the same or different;
  • the step of increasing or decreasing the current operating frequency of the kernel according to the calculation performance indicator of the kernel further includes:
  • the current operating frequency of the kernel is adjusted to the next operating frequency.
  • the method further includes the steps of:
  • the frequency modulation of the cores is stopped.
  • the step of analyzing the calculation performance index of each of the cores at the current working frequency point further includes:
  • the step of increasing or decreasing the current operating frequency of the kernel according to the calculation performance indicator of the kernel further includes:
  • the current operating frequency of the kernel is adjusted to the next operating frequency.
  • the step of analyzing whether the calculated accuracy rate of the kernel reaches the first accuracy rate threshold and / or the second accuracy rate threshold within a predetermined adjustment period further includes :
  • the number of correct random numbers and the number of incorrect random numbers calculate a random number calculation accuracy rate of the kernel within the adjustment period, and determine whether the random number calculation accuracy rate reaches a predetermined A first accuracy rate threshold and / or a second accuracy rate threshold;
  • the step of increasing or decreasing the current operating frequency of the kernel according to the calculation performance indicator of the kernel further includes:
  • the current operating frequency of the kernel is adjusted to the previous operating frequency; and / or
  • the current operating frequency of the kernel is adjusted to the next operating frequency.
  • the step of analyzing whether the random number submitted by the kernel is correct during the adjustment period further includes:
  • the kernel calculates a first result from the random number through a predetermined algorithm, and the first result includes a first feature
  • the verification unit of the computing chip calculates the random number through the same algorithm to calculate a second result, and the second result includes a second feature;
  • the checking unit determines that the random number is a correct random number, otherwise it determines that the random number is an incorrect random number.
  • the step of analyzing, within a predetermined period of the adjustment, whether the calculated correct rate of the kernel reaches a predetermined correct rate threshold further includes:
  • a preset real-time adjustment instruction analyzing in real time whether the calculated accuracy rate of the kernel in the adjustment period reaches the first accuracy rate threshold value and the second accuracy rate threshold value;
  • timing adjustment instruction within the adjustment time period set by the timing adjustment instruction, analyze whether the calculation accuracy rate of the kernel in the adjustment period reaches the first accuracy rate threshold value and the Second accuracy threshold; or
  • the step of increasing or decreasing the current operating frequency of the kernel according to the calculation performance indicator of the kernel further includes:
  • the current operating frequency of the kernel is raised to the previous operating frequency in real time;
  • the calculated correct rate within the adjustment period does not reach the second correct rate threshold, and the current operating frequency of the kernel is adjusted down to the next operating frequency in real time;
  • the current operating frequency of the kernel is adjusted to the previous operating frequency.
  • the current operating frequency of the kernel is adjusted downward A working frequency;
  • the current operating frequency of the kernel is raised to the previous operating frequency. ; If the calculation accuracy rate of the kernel within the adjustment period does not reach the second accuracy rate threshold, reduce the current operating frequency of the kernel to the next operating frequency; according to the stop of receiving An adjustment instruction to stop adjusting the current operating frequency of the kernel.
  • the step of analyzing the calculation performance index of each of the cores at the current working frequency point further includes:
  • Presetting a reference node value of the kernel calculating a correct weight value, calculating an error weight value, calculating a correct threshold value and calculating an error threshold value
  • the calculation correct weight value is added to the reference node value, and each time the kernel calculates incorrectly at least once, the calculation error weight value is reduced once on the reference node value.
  • the step of increasing or decreasing the current operating frequency of the kernel according to the calculation performance indicator of the kernel further includes:
  • the current operating frequency of the kernel is reduced to the next operating frequency.
  • the step of analyzing whether each calculation of the kernel is correct further includes:
  • the steps also include:
  • the calculation correct weight value is added to the reference node value once, and each time the kernel submits at least one wrong random number, the calculation is reduced by one on the reference node value Error weight value.
  • the step of analyzing whether the random number submitted by the kernel each time is correct further includes:
  • the kernel After the kernel submits the random number, the kernel calculates a first result from the random number by using a predetermined algorithm, and the first result includes a first feature;
  • the verification unit of the computing chip calculates the random number through the same algorithm to calculate a second result, and the second result includes a second feature;
  • the checking unit determines that the random number is a correct random number, otherwise it determines that the random number is an incorrect random number.
  • the method further includes:
  • the calculated correct weight value is the same as or different from the calculation error weight value
  • the calculation correct threshold value is the same or different from the calculation error threshold value
  • Controlling the resident error rate that the kernel expects to tolerate by controlling a ratio of the calculated correct weight value and the calculated error weight value;
  • Controlling the adjustment period by controlling the absolute value of the calculated correct weight value and the calculated incorrect weight value
  • the adjustment period is controlled by controlling the magnitude of the absolute value of the calculated correct threshold and the calculated incorrect threshold.
  • the step of determining whether the current reference node value of the kernel reaches the calculated correct threshold or the calculated incorrect threshold further includes:
  • the step of adjusting the current operating frequency of the kernel up or down according to the calculation performance indicator of the kernel further includes:
  • the current operating frequency point of the kernel is raised to the previous operating frequency in real time; if the current reference node value of the kernel reaches Calculating the error threshold, and real-timely reducing the current operating frequency of the kernel to the next operating frequency;
  • the current operating frequency of the kernel is adjusted to the previous operating frequency; during the adjustment time In the segment, if the current reference node value of the kernel reaches the calculation error threshold, the current operating frequency of the kernel is adjusted down to the next operating frequency; or
  • the current operating frequency of the kernel is raised to the previous operating frequency; if When the current reference node value reaches the calculation error threshold, the current operating frequency of the kernel is adjusted to the next operating frequency; according to the stop adjustment instruction received, the current operating frequency of the kernel is stopped. Adjustment.
  • the method further includes:
  • Adjusting the frequency at which the operating frequency is set according to the current distribution state of the kernel and a predetermined frequency adjustment mechanism, and the frequency adjustment mechanism is a correspondence between a kernel distribution state and frequency adjustment.
  • the operating frequency includes at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency.
  • the highest frequency among the high-frequency operating frequencies is The highest operating frequency, the lowest of the low-frequency operating frequencies is the lowest operating frequency;
  • the step of adjusting the frequency of setting the operating frequency according to the current distribution state and the frequency adjustment mechanism further includes:
  • the kernel exceeding a predetermined second ratio operates on at least one of the high-frequency operating frequencies, modifying at least one of the operating frequencies to at least one optimized high-frequency operating frequency, the optimized high-frequency operating The frequency of the frequency is higher than the frequency of the highest operating frequency; and / or
  • the kernel exceeding a predetermined third ratio operates on at least one of the low-frequency operating frequencies, modify at least one of the operating frequencies to at least one optimized low-frequency operating frequency.
  • the frequency is lower than the frequency of the lowest operating frequency.
  • the steps of optimizing the high-frequency operating frequency point further include:
  • the kernel exceeding the second ratio operates at the highest operating frequency, modifying one of the operating frequencies to one of the optimized high-frequency operating frequencies; and / or
  • the step of modifying and setting at least one of the operating frequency points to at least one of the optimized low-frequency operating frequencies if the kernel exceeding the predetermined third ratio operates on at least one of the low-frequency operating frequencies is also include:
  • the operating frequency includes at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency.
  • the highest frequency among the high-frequency operating frequencies is The highest operating frequency, the lowest of the low-frequency operating frequencies is the lowest operating frequency;
  • the step of adjusting the frequency of setting the operating frequency according to the current distribution state and the frequency adjustment mechanism further includes:
  • the number of the cores operating at least one of the high-frequency operating frequencies is the largest, modify at least one of the operating frequencies to at least one optimized high-frequency operating frequency, the frequency of the optimized high-frequency operating frequency Frequencies above the highest operating frequency; and / or
  • the number of the kernels operating at least one of the low-frequency operating frequencies is the largest, modify at least one of the operating frequencies to at least one optimized low-frequency operating frequency, and the frequency of the optimized low-frequency operating frequency is lower than the Describe the frequency of the lowest operating frequency.
  • the steps of working frequency also include:
  • a modification of one of the operating frequencies is set to one of the optimized low-frequency operating frequencies.
  • the operating frequency includes at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency;
  • the step of adjusting the frequency of setting the operating frequency according to the current distribution state and the frequency adjustment mechanism further includes:
  • the kernel exceeding a predetermined fourth ratio operates on at least one of the intermediate operating frequencies, stop adjusting the frequency of setting the operating frequencies;
  • the computing device is used to mine a virtual digital currency operation.
  • the present invention also provides a chip frequency modulation device of a computing device. At least one computing chip is provided on the computing board. The computing chip is provided with multiple cores.
  • the chip frequency modulation device includes:
  • a frequency point setting module configured to set a plurality of operating frequency points for a computing chip of the computing device, and respectively work a plurality of cores in the computing chip at each of the operating frequency points;
  • a calculation performance analysis module configured to analyze calculation performance indicators of each of the cores at a current working frequency point
  • a frequency adjustment module is configured to increase or decrease the current operating frequency of the kernel according to the calculation performance index of the kernel.
  • the frequency point setting module is configured to set a plurality of the operating frequency points for the computing chip through a plurality of phase-locked loop circuits, and the operating frequency points and the phase-locked loop The circuits are in one-to-one correspondence;
  • the frequency adjustment module is configured to increase or decrease the current operating frequency of the core through the phase-locked loop circuit according to the calculation performance index of the core.
  • the phase-locked loop circuit is disposed inside or outside the computing chip.
  • a frequency difference between adjacent working frequency points is 1 to 10%.
  • the calculation performance analysis module is configured to analyze, within a predetermined adjustment period, whether the calculation performance index of the kernel reaches a predetermined first index threshold, a second index threshold, and / Or a third indicator threshold, where the first indicator threshold is the same as or different from the second indicator threshold;
  • the frequency adjustment module is configured to adjust the current operating frequency of the kernel to a previous operating frequency if the calculation performance indicator of the kernel reaches the first indicator threshold;
  • the frequency adjustment module is configured to reduce the current operating frequency of the kernel to the next operating frequency if the calculation performance indicator of the kernel does not reach the second indicator threshold; and / or
  • the frequency adjustment module is configured to reduce the current operating frequency of the kernel to the next operating frequency if the calculation performance indicator of the kernel reaches the third indicator threshold.
  • the frequency adjustment module further includes:
  • a frequency adjustment sub-module is configured to increase or decrease the current operating frequency of the kernel according to the calculation performance index of the kernel.
  • a stop frequency adjustment sub-module configured to stop performing frequency modulation on the kernel if the kernel operating at a predetermined at least one optimized operating frequency exceeds a predetermined first ratio; or if the kernel is operating at least one of the optimized operations The number of the cores at the frequency point is the largest, and the frequency modulation of the cores is stopped.
  • the calculation performance analysis module is configured to analyze whether the calculation accuracy rate of the kernel reaches a predetermined first accuracy rate threshold and / or a second accuracy within a predetermined adjustment period.
  • Rate threshold, the first correct rate threshold is the same as or different from the second correct rate threshold;
  • the frequency adjustment module is configured to adjust the current operating frequency of the kernel to a previous operating frequency if the calculated correct rate of the kernel reaches the first correct rate threshold; and / or If the calculation accuracy rate of the kernel does not reach the second accuracy rate threshold, the current operating frequency of the kernel is adjusted to the next operating frequency.
  • the calculation performance analysis module further includes:
  • a first analysis submodule configured to analyze whether the random number submitted by the kernel is correct within the adjustment period
  • a statistics submodule configured to count the number of correct random numbers and the number of incorrect random numbers submitted by the kernel within the adjustment period
  • a first judging submodule configured to calculate a correct rate of the random number of the kernel in the adjustment period according to the number of the correct random number and the number of the incorrect random number, and judge the random number Calculating whether the correct rate reaches a predetermined first correct rate threshold and / or a second correct rate threshold;
  • the frequency adjustment module is configured to adjust the current operating frequency of the kernel to a previous operating frequency if the random number calculation correct rate of the kernel reaches the first correct rate threshold; and / or And for reducing the current operating frequency of the kernel to the next operating frequency if the random number calculation correct rate of the kernel does not reach the second correct rate threshold.
  • the first analysis sub-module further includes:
  • a first calculation unit configured to calculate the first result by using a predetermined algorithm after the kernel submits the random number within the adjustment period, and the first result includes the first result A feature, the first computing unit is disposed in the kernel;
  • a first checking unit configured to calculate the second result by using the same random algorithm, and the second result includes a second feature; if the first feature is the same as the second feature, It is determined that the random number is a correct random number, otherwise it is determined that the random number is an incorrect random number; the first verification unit is set in the operation chip.
  • the calculation performance analysis module is configured to analyze, in real time, whether the calculation accuracy rate of the kernel in the adjustment period reaches the first accuracy according to a preset real-time adjustment instruction.
  • the calculation performance analysis module is configured to analyze, according to a preset timing adjustment instruction, whether the calculation accuracy rate of the kernel in the adjustment period reaches the adjustment period within the adjustment time period set by the timing adjustment instruction.
  • the calculation performance analysis module is configured to analyze, according to the received immediate adjustment instruction, whether the calculation accuracy rate of the kernel in the adjustment period reaches the first accuracy rate threshold value and the second accuracy rate threshold value;
  • the frequency adjustment module is configured to increase the current operating frequency of the kernel to a previous operating frequency in real time if the calculation accuracy rate of the kernel within the adjustment period reaches the first accuracy rate threshold. Point; if the calculation accuracy rate of the kernel within the adjustment period does not reach the second accuracy rate threshold, reduce the current operating frequency of the kernel to the next operating frequency in real time;
  • the frequency adjustment module is configured to, within the adjustment period, if the calculation accuracy rate of the kernel within the adjustment period reaches the first accuracy rate threshold, the current operating frequency of the kernel is Point to the previous working frequency point; within the adjustment period, if the calculation accuracy rate of the kernel within the adjustment period does not reach the second accuracy rate threshold, the The current operating frequency is reduced to the next operating frequency; or
  • the frequency adjustment module is configured to, according to the received immediate adjustment instruction, if the calculation accuracy rate of the kernel within the adjustment period reaches the first accuracy rate threshold, adjust the current operating frequency of the kernel. Up to the previous working frequency; if the calculation accuracy rate of the kernel within the adjustment period does not reach the second accuracy rate threshold, reduce the current working frequency of the kernel to the next work frequency Frequency point; stop adjusting the current operating frequency point of the kernel according to the received stop adjustment instruction.
  • the calculation performance analysis module further includes:
  • a setting sub-module configured to preset a reference node value of the kernel, calculate a correct weight value, calculate an error weight value, calculate a correct threshold value, and calculate an error threshold value;
  • a second analysis submodule configured to analyze whether each calculation of the kernel is correct
  • a counting sub-module configured to add the calculated correct weight value to the reference node value at least once every time the kernel calculates correctly, and reduce the reference node value once at least once every time the kernel calculates incorrectly The calculation error weight value;
  • a second judging submodule configured to judge whether the current reference node value of the kernel reaches the calculation correct threshold or the calculation error threshold;
  • the frequency adjustment module is configured to adjust the current operating frequency of the kernel to a previous operating frequency if the current reference node value of the kernel reaches the calculation correct threshold; and The current reference node value of the kernel reaches the calculation error threshold, and the current operating frequency of the kernel is reduced to the next operating frequency.
  • the second analysis submodule is configured to analyze whether the random number submitted by the kernel each time is correct
  • the counting submodule is configured to submit a correct random number at least once each time in the kernel, and add the calculated correct weight value to the reference node value once, and the kernel may submit an incorrect random number at least once each time in the reference.
  • the node value is decremented by the calculation error weight value once.
  • the second analysis sub-module further includes:
  • a second calculation unit configured to, after the kernel submits the random number, the kernel calculates the first result by using a predetermined algorithm, where the first result includes a first feature
  • a second checking unit configured to calculate the second result by using the same random algorithm, and the second result includes a second feature; if the first feature is the same as the second feature, Then it is determined that the random number is a correct random number, otherwise it is determined that the random number is an incorrect random number.
  • the setting submodule is configured to set and adjust the reference node value of the kernel, the calculated correct weight value, the calculated error weight value, and the calculation according to actual needs.
  • the setting sub-module is configured to control a resident error rate expected to be tolerated by the kernel by controlling a ratio of the calculated correct weight value and the calculated error weight value;
  • the setting submodule is configured to control an adjustment period by controlling an absolute value size of the calculated correct weight value and the calculated incorrect weight value;
  • the setting submodule is configured to control the adjustment period by controlling an absolute value of the calculated correct threshold and the calculated incorrect threshold.
  • the computing performance analysis module is configured to determine, in real time, whether the current reference node of the kernel reaches the calculation correct threshold or the calculation error threshold according to a preset real-time adjustment instruction.
  • the computing performance analysis module is configured to determine, according to a preset timing adjustment instruction, within the adjustment time period set by the timing adjustment instruction, whether the current reference node of the kernel reaches the calculation correct threshold or the Calculating the error threshold; or
  • the calculation performance analysis module is configured to analyze, according to the received immediate adjustment instruction, whether the current reference node of the kernel reaches the calculation correct threshold or the calculation error threshold;
  • the frequency adjustment module is configured to adjust the current operating frequency of the kernel to a previous operating frequency in real time if the current reference node value of the kernel reaches the calculated correct threshold; if the kernel ’s The current reference node value reaches the calculation error threshold, and the current operating frequency of the kernel is adjusted down to the next operating frequency in real time;
  • the frequency adjustment module is configured to increase the current operating frequency of the kernel to the previous operating frequency if the current reference node value of the kernel reaches the calculated correct threshold within the adjustment time period. Within the adjustment time period, if the current reference node value of the kernel reaches the calculation error threshold, the current operating frequency of the kernel is reduced to the next operating frequency; or
  • the frequency adjustment module is configured to adjust the current operating frequency of the kernel to a previous operating frequency if the current reference node value of the kernel reaches the calculated correct threshold according to the received immediate adjustment instruction. ; If the current reference node value of the kernel reaches the calculation error threshold, reducing the current operating frequency of the kernel to the next operating frequency; and for stopping the adjustment according to the received stop adjustment instruction Adjusting the current operating frequency of the kernel.
  • the chip frequency modulation device further includes:
  • a frequency point statistics module configured to count the current distribution state of the kernel after being tuned at each of the working frequency points
  • a frequency adjustment module is configured to adjust the frequency of setting the operating frequency according to the current distribution state of the kernel and a predetermined frequency adjustment mechanism, and the frequency adjustment mechanism is adjusted by the kernel distribution state and frequency. Correspondence.
  • the operating frequency includes at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency.
  • the highest frequency among the high-frequency operating frequencies is The highest operating frequency, the lowest of the low-frequency operating frequencies is the lowest operating frequency;
  • the frequency point adjustment module further includes:
  • a first frequency adjustment sub-module configured to modify and set at least one of the operating frequency points to at least one optimized high frequency if the kernel exceeding a predetermined second ratio operates on at least one of the high frequency operating frequencies Operating frequency, the frequency of the optimized high-frequency operating frequency is higher than the frequency of the highest operating frequency; and / or
  • a second frequency adjustment sub-module configured to modify at least one of the operating frequencies to at least one optimized low-frequency operating frequency if the kernel exceeding a predetermined third ratio operates on at least one of the low-frequency operating frequencies Point, the frequency of the optimized low-frequency operating frequency is lower than the frequency of the lowest operating frequency.
  • the first frequency adjustment sub-module is configured to, if the kernel exceeding the second ratio operates on the highest operating frequency, convert one of the operating frequencies Modify the setting to one of the optimized high frequency operating frequency points; and / or
  • the second frequency adjustment sub-module is configured to modify one of the operating frequencies to one of the optimized low-frequency operating frequencies if the kernel exceeding the third ratio operates on the lowest operating frequency. point.
  • the operating frequency includes at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency.
  • the highest frequency among the high-frequency operating frequencies is The highest operating frequency, the lowest of the low-frequency operating frequencies is the lowest operating frequency;
  • the frequency point adjustment module further includes:
  • a third frequency adjustment sub-module configured to modify and set at least one of the operating frequencies to at least one optimized high-frequency operating frequency if the number of the kernels operating at least one of the high-frequency operating frequencies is the largest, The frequency of the optimized high-frequency operating frequency is higher than the frequency of the highest operating frequency; and / or
  • a fourth frequency adjustment sub-module configured to modify and set at least one of the operating frequencies to at least one optimized low-frequency operating frequency if the number of the kernels operating at least one of the low-frequency operating frequencies is the largest; The frequency of the optimized low-frequency operating frequency is lower than the frequency of the lowest operating frequency.
  • the third frequency adjustment sub-module is configured to modify one of the operating frequency points to be set if the number of the kernels operating at the highest operating frequency point is the largest.
  • the fourth frequency adjustment sub-module is configured to modify one of the operating frequencies to one of the optimized low-frequency operating frequencies if the number of the kernels operating at the lowest operating frequency is the largest.
  • the operating frequency includes at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency;
  • the frequency point adjustment module further includes:
  • a first stop adjustment sub-module configured to stop adjusting the frequency of setting the operating frequency if the kernel exceeding a predetermined fourth ratio operates on at least one of the intermediate operating frequencies
  • the second stop adjustment sub-module is configured to stop adjusting and setting the frequency of the operating frequency if the number of the kernels working on at least one of the intermediate operating frequencies is the largest.
  • the chip frequency modulation device is disposed inside or outside the computing chip.
  • the computing device is used to mine a virtual digital currency operation.
  • the invention also provides a computing board including any one of the chip frequency modulation devices.
  • the present invention also provides a computing device including any one of the chip frequency modulation devices.
  • the present invention also provides a storage medium for storing a computer program for a chip frequency modulation method of any one of the computing devices described above.
  • the present invention automatically adjusts the frequency of the core of the computing chip of a computing device.
  • a plurality of suitable operating frequency points are set, and the multiple cores in the computing chip are respectively operated at different operating frequency points, and then each core is currently working according to
  • the calculation performance index of frequency points is to increase or decrease the current operating frequency of the kernel, that is, to increase the frequency of the core with high computing performance, and to reduce the frequency of the core with low computing performance. Therefore, the present invention can automatically adjust the frequency corresponding to each core according to the actual computing performance of each core in the computing chip of the computing device, so as to maximize the computing performance of the core and further improve the computing performance of the computing chip and the overall computing device.
  • FIG. 1 is a schematic structural diagram of a chip frequency modulation device of a computing device of the present invention
  • FIG. 2 is a schematic structural diagram of a chip frequency modulation device of a computing device in a first embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a chip frequency modulation device of a computing device in a second embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a chip frequency modulation device of a computing device in a third embodiment of the present invention.
  • FIG. 5 is a diagram illustrating an example of parameter setting in a third embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a chip frequency modulation device of a computing device in a fourth embodiment of the present invention.
  • FIG. 7 is a distribution state diagram of the kernel working at various operating frequencies in the fourth embodiment of the present invention.
  • FIG. 8 is a flowchart of a chip frequency modulation method of a computing device of the present invention.
  • FIG. 9 is a flowchart of a chip frequency modulation method of a computing device in a first embodiment of the present invention.
  • FIG. 10 is a flowchart of a chip frequency modulation method of a computing device in a second embodiment of the present invention.
  • FIG. 11 is a flowchart of a preferred chip frequency modulation method of a computing device in a second embodiment of the present invention.
  • FIG. 12 is a flowchart of a chip frequency modulation method of a computing device in a third embodiment of the present invention.
  • FIG. 13 is a flowchart of a preferred chip frequency modulation method of a computing device in a third embodiment of the present invention.
  • FIG. 14 is a flowchart of a chip frequency modulation method of a computing device in a fourth embodiment of the present invention.
  • 15 is a first flowchart of a preferred chip frequency modulation method of a computing device in a fourth embodiment of the present invention.
  • 16 is a second flowchart of a preferred chip frequency modulation method for a computing device in a fourth embodiment of the present invention.
  • FIG. 17 is a schematic structural diagram of a computing device of the present invention.
  • references in this specification to "one embodiment”, “embodiment”, “example embodiment”, etc. refer to the described embodiment that may include specific features, structures, or characteristics, but not every Embodiments must include these specific features, structures, or characteristics. Moreover, such expressions do not refer to the same embodiment. Further, in describing specific features, structures, or characteristics in conjunction with the embodiments, whether or not there is a clear description, it has been shown that combining such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art. .
  • FIG. 1 is a schematic structural diagram of a chip frequency modulation device of a computing device according to the present invention.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currency.
  • the computing device is provided with at least one computing chip, and the computing chip is provided with a plurality of cores (Core) 80.
  • the computing device preferably includes a control board and a computing board connected to the control board.
  • the computing board is provided with at least one computing chip, and the computing chip is provided with a plurality of cores 80.
  • the computing device may further include a heat sink, a connection board, a power module, and the like.
  • the chip frequency modulation technology of the present invention actually involves two levels of frequency adjustment mechanisms: the frequency adjustment mechanism of the computing chip and the frequency adjustment mechanism at the core level.
  • the frequency adjustment mechanism of the computing chip refers to setting a number of suitable operating frequency points for each computing chip, and allowing each core 80 of the computing chip to work at each operating frequency point to fully exert the working performance of each core 80.
  • the kernel-level frequency adjustment mechanism refers to adjusting the core 80 to an appropriate operating frequency according to the actual computing performance of the kernel 80, increasing the frequency of the core 80 with high computing performance, and lowering the frequency of the core 80 with low computing performance, thereby Give full play to the computing performance of each core 80.
  • the chip frequency modulation device 100 includes at least a frequency point setting module 10, a calculation performance analysis module 20, and a frequency adjustment module 30, wherein:
  • the frequency point setting module 10 is configured to set a plurality of operating frequency points for a computing chip of a computing device, each operating frequency point has a different frequency, and a plurality of cores 80 in the computing chip respectively work at each operating frequency point.
  • each core 80 of the computing chip is allowed to work at each operating frequency point.
  • set 6 working frequency points 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz.
  • the number of operating frequency points and the gap between frequencies can be set according to actual needs. The more operating frequency points, the more the computing performance of each core 80 can be brought into full play.
  • the frequency modulation switch is activated (the frequency of the core 80 has not been tuned), the core 80 may be evenly distributed, unevenly distributed, or randomly distributed to work at the working frequency point according to a predetermined rule.
  • the frequency point setting module 10 can set a plurality of operating frequency points for the computing chip through a plurality of phase locked loop circuits (Phase, Locked Loop, PPL) 70 as shown in FIG. 2.
  • PPL phase locked loop circuits
  • the frequency point setting module 10 can also pass Other hardware or software sets multiple operating frequency points for the computing chip.
  • the computing performance analysis module 20 is configured to analyze a computing performance index of each core 80 at a current working frequency.
  • the calculation performance indicator represents the actual calculation performance of the kernel 80 at the current operating frequency, including but not limited to the calculation accuracy rate, the calculation accuracy number, the calculation speed, and the like. If the calculation performance index of the kernel 80 is high, it indicates that there may be room for improvement in the calculation performance of the kernel 80; if the calculation performance index of the kernel 80 is low, it indicates that the calculation performance of the kernel 80 may not be sufficient for the current work Work at the frequency corresponding to the frequency point.
  • the frequency adjustment module 30 is configured to increase or decrease the current operating frequency of the kernel 80 according to the calculation performance index of the kernel 80 at the current operating frequency. That is, according to the frequency adjustment mechanism at the kernel level, the kernel 80 will be adjusted to an appropriate operating frequency according to the actual computing performance of the kernel 80, the frequency of the core 80 with high computing performance will be increased, and the frequency of the core 80 with low computing performance will be reduced, thereby Give full play to the computing performance of each core 80.
  • the frequency of the kernel 80 is periodically adjusted. If the calculation accuracy rate of the kernel 80 within the frequency adjustment period reaches the first accuracy rate threshold, it indicates that the kernel 80 has not reached the optimal calculation performance.
  • the current operating frequency of the kernel is raised to a higher previous operating frequency; if the calculation accuracy rate of the kernel 80 within the frequency adjustment period does not reach the second accuracy rate threshold, it indicates that the calculation performance of the kernel 80 is not sufficient for Point work, so the current operating frequency of the core 80 is adjusted to a lower next operating frequency.
  • the chip frequency modulation device 100 of the present invention may be disposed inside or outside the computing chip.
  • the present invention evaluates the working performance of the core 80 according to the actual computing performance of each core 80 in the computing chip, adjusts the corresponding frequency of the core 80, gives full play to the computing advantages of the core 80 with better performance, and prevents the weak performance of the core 80 from affecting the computing performance of the computing chip. , Maximize the computing performance of each core 80, thereby improving the computing speed and accuracy of the computing chip and the overall computing device.
  • the core 80 of the computing chip of the present invention does not jump between different frequencies, and the operating frequency is relatively stable.
  • FIG. 2 is a schematic structural diagram of a chip frequency modulation device of a computing device in the first embodiment of the present invention.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currency.
  • the computing device preferably includes a control board and a computing board connected to the control board.
  • the computing board is provided with at least one computing chip, and the computing chip is provided with a plurality of cores (Core) 80.
  • the computing device may further include a heat sink, a connection board, a power module, and the like.
  • the chip frequency modulation device 100 includes at least a frequency point setting module 10, a calculation performance analysis module 20, and a frequency adjustment module 30, wherein:
  • the frequency point setting module 10 is configured to set a plurality of operating frequency points for a computing chip through a plurality of phase-locked loop circuits 70, and respectively operate a plurality of cores 80 in the computing chip at each operating frequency point.
  • the frequencies are different, and the operating frequency and the phase-locked loop circuit 70 are in a one-to-one correspondence relationship.
  • the phase-locked loop circuit 70 is provided inside or outside the computing chip.
  • the number of frequency points and the difference between frequencies can be set according to actual needs.
  • the more the working frequency points the more fully the computing performance of each core 80 can be brought into play. For example, set 6 working frequency points, 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz. Therefore, the present invention can set more phase-locked loop circuits 70 to set more operating frequency points, so that the computing performance of each core 80 can be brought into full play.
  • the frequency difference between the operating frequency points in the present invention needs to be controlled within a reasonable range. Because when the kernel 80 increases a working frequency point, the operating frequency of the kernel will increase a frequency difference value, which can improve certain computing performance due to the increase of the computing speed. At the same time, increasing the operating frequency of the kernel may result in a loss of computing performance due to a reduction in the accuracy of the calculation. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies, so that when the kernel 80 is adjusted from the current operating frequency to the previous operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss. Preferably, the frequency difference between adjacent operating frequency points is 1 to 10%.
  • the computing performance analysis module 20 is configured to analyze a computing performance index of each core 80 at a current working frequency.
  • the calculation performance indicator represents the actual calculation performance of the kernel 80 at the current operating frequency, including but not limited to the calculation accuracy rate, the calculation accuracy number, the calculation speed, and the like. If the calculation performance index of the kernel 80 is high, it indicates that there may be room for improvement in the calculation performance of the kernel 80; if the calculation performance index of the kernel 80 is low, it indicates that the calculation performance of the kernel 80 may not be sufficient for the current work Work at the frequency corresponding to the frequency point.
  • the calculation performance analysis module 20 is configured to analyze whether the calculation performance index of the kernel 80 reaches a predetermined first index threshold, a second index threshold, and / or a third index threshold within a predetermined adjustment period, where the first The indicator threshold is the same as or different from the second indicator threshold.
  • the frequency adjustment module 30 is configured to increase or decrease the current operating frequency of the core 80 through the phase-locked loop circuit 70 according to the calculation performance index of the core 80.
  • the frequency adjustment module 30 may also adjust the current operating frequency of the core 80 up or down through other hardware or software.
  • the frequency adjustment module 30 is configured to adjust the current working frequency of the core 80 to the previous working frequency if the computing performance index of the core 80 reaches the first index threshold; and / or, the frequency adjustment module 30 is configured to The computing performance index of the kernel 80 does not reach the second index threshold, and the current operating frequency of the kernel 80 is lowered to the next operating frequency; and / or the frequency adjustment module 30 is used for calculating the performance index of the kernel 80 if the third index threshold is reached. , Lowering the current operating frequency of the core 80 to the next operating frequency.
  • the calculation performance index is that the core 80 is adjusting In the calculation accuracy rate within the period, the first index threshold and the second index threshold are both 90%.
  • the calculation accuracy rate of the kernel 80 during the adjustment period reaches 90%, it means that the calculation performance of the kernel 80 is better, then the current operating frequency of the kernel 80 is increased from 600 MHz to the previous operating frequency of 650 MHz; if the kernel 80 is adjusting The calculation accuracy rate within the period does not reach 90%, which indicates that the computing performance of the core 80 is weak, and then the current operating frequency of the core 80 is reduced from 600 MHz to the next operating frequency of 550 MHz.
  • the last working frequency is not limited to the last adjacent working frequency, and more than one last adjacent working frequency can be set as the previous working frequency; the next working frequency It is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency may be set as the next operating frequency.
  • the current operating frequency of the core 80 is increased from 600 MHz to the previous operating frequency of 700 MHz; the current operating frequency of the core 80 is reduced to 600 MHz to the next operating frequency of 500 MHz.
  • the previous working frequency point and the spacing between the next working frequency point are not limited here.
  • the frequency difference between the current working frequency point and the previous working frequency point is 1 to 10%, and the frequency difference between the current working frequency point and the next working frequency point is 1 to 10%, so that the kernel 80 moves from the current When the operating frequency is adjusted to the previous operating frequency or the next operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss.
  • the calculation performance index is the calculation accuracy rate of the kernel 80 during the adjustment period
  • the first index threshold is 90%
  • the second index threshold is 80%. If the calculation accuracy rate of the kernel 80 during the adjustment period reaches 90%, it means that the calculation performance of the kernel 80 is better, then the current operating frequency of the kernel 80 is increased from 600 MHz to the previous operating frequency of 650 MHz; if the kernel 80 is adjusting The calculation accuracy rate within the period does not reach 80%, which indicates that the computing performance of the core 80 is weak, and then the current operating frequency of the core 80 is reduced from 600 MHz to the next operating frequency of 550 MHz.
  • the calculation performance index is the number of correct calculations and the number of incorrect settlements in the adjustment period of the kernel 80.
  • the first index threshold is 100
  • the second index threshold is 10. If the number of correct calculations of the kernel 80 in the adjustment cycle reaches 100, it indicates that the calculation performance of the kernel 80 is better, then the current operating frequency of the kernel 80 is raised to 600MHz from the previous operating frequency; if the kernel 80 is in the adjustment cycle The number of errors in the calculation reaches 10, which indicates that the computing performance of the core 80 is weak, and the current operating frequency of the core 80 is reduced from 600 MHz to the next operating frequency of 550 MHz.
  • the frequency adjustment module 30 further includes a frequency adjustment sub-module 31 and a stop frequency adjustment sub-module 32, wherein:
  • the frequency adjusting sub-module 31 is configured to increase or decrease the current operating frequency of the core 80 according to the calculation performance index of the core 80.
  • the frequency adjustment sub-module 31 adjusts the current operating frequency of the core 80 up or down according to the calculation performance index of the core 80 through the phase-locked loop circuit 70.
  • the frequency adjustment sub-module 31 may also be implemented by other hardware or software to increase or decrease the current operating frequency of the core 80.
  • the stop frequency adjustment sub-module 32 is configured to stop the frequency modulation of the core 80 if the core 80 operating at a predetermined at least one optimized operating frequency exceeds a predetermined first ratio; or if the core 80 operates at least one of the optimizations The number of cores 80 at the operating frequency is the largest, and frequency modulation of the cores 80 is stopped.
  • one or more optimized operating frequency points can be selected from several operating frequency points. If the operating frequency of most cores 80 has reached the optimized operating frequency point, it indicates that the operating frequency of the individual cores 80 in the computing chip has been optimized. In this state, the computing performance of each core 80 can be brought into full play, and no further frequency adjustment is required, so the adjustment of the operating frequency of the core 80 is stopped. For example, set 6 working frequency points, 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz, and choose two optimized working frequency points of 600Mhz and 650Mhz as the optimized working frequency point. And 650Mhz, the frequency modulation of the core 80 is stopped.
  • FIG. 3 is a schematic structural diagram of a chip frequency modulation device of a computing device in a second embodiment of the present invention.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currency.
  • the computing device preferably includes a control board and a computing board connected to the control board.
  • the computing board is provided with at least one computing chip, and the computing chip is provided with a plurality of cores (Core) 80.
  • the computing device may further include a heat sink, a connection board, a power module, and the like.
  • the chip frequency modulation device 100 includes at least a frequency point setting module 10, a calculation performance analysis module 20, and a frequency adjustment module 30, wherein:
  • the frequency point setting module 10 is configured to set a plurality of operating frequency points for a computing chip of a computing device, each operating frequency point has a different frequency, and a plurality of cores 80 in the computing chip respectively work at each operating frequency point. That is, according to the frequency adjustment mechanism at the level of the computing chip, several different frequency points are set for each computing chip, and each core 80 of the computing chip is allowed to work at each operating frequency point. For example, set 6 working frequency points: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz. The number of operating frequency points and the gap between frequencies can be set according to actual needs. The more operating frequency points, the more the computing performance of each core 80 can be brought into full play.
  • the core 80 When the frequency modulation switch is activated (the frequency of the core 80 has not been tuned), the core 80 may be evenly distributed, unevenly distributed, or randomly distributed to work at the working frequency point according to a predetermined rule.
  • the frequency point setting module 10 sets a plurality of operating frequency points for the computing chip through a plurality of phase-locked loop circuits 70 as shown in FIG. 2, and separately operates a plurality of cores 80 in the computing chip at each operating frequency point. There is a one-to-one correspondence between the operating frequency and the phase-locked loop circuit 70. In the present invention, more phase-locked loop circuits 70 can be provided to set more operating frequency points, so that the computing performance of each core 80 can be brought into full play.
  • the frequency point setting module 10 may also set multiple operating frequency points for the computing chip through other hardware or software.
  • the frequency difference between the operating frequency points in the present invention needs to be controlled within a reasonable range. Because when the kernel 80 increases a working frequency point, the operating frequency of the kernel will increase a frequency difference value, which can improve certain computing performance due to the increase of the computing speed. At the same time, increasing the operating frequency of the kernel may result in a loss of computing performance due to a reduction in the accuracy of the calculation. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies, so that when the kernel 80 is adjusted from the current operating frequency to the previous operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss. Preferably, the frequency difference between adjacent operating frequency points is 1 to 10%.
  • the calculation performance analysis module 20 is configured to analyze whether the calculation accuracy rate of the kernel 80 reaches a predetermined first accuracy rate threshold and / or a second accuracy rate threshold, and the first accuracy rate threshold and the second accuracy rate are within a predetermined adjustment period.
  • the accuracy thresholds are the same or different. If the calculation accuracy rate of the kernel 80 reaches a predetermined first accuracy rate threshold, it indicates that the calculation performance of the kernel 80 may still have room for improvement; if the calculation accuracy rate of the kernel 80 does not reach a predetermined second accuracy rate threshold, it indicates The computing performance of the kernel 80 may be insufficient to work at a frequency corresponding to the current operating frequency.
  • the frequency adjustment module 30 is configured to raise the current operating frequency of the kernel 80 to the previous operating frequency if the calculation accuracy rate of the kernel 80 reaches the first accuracy rate threshold, indicating that the kernel 80 has not yet reached the optimal calculation performance; And / or if the calculation accuracy rate of the kernel 80 does not reach the second accuracy rate threshold, it indicates that the calculation performance of the kernel 80 is insufficient to work at the current operating frequency, and the current operating frequency of the kernel 80 is reduced to the next work Frequency.
  • the frequency adjustment module 30 can tune the core 80 through the phase-locked loop circuit 70 or software as shown in FIG. 2.
  • the kernel 80 will be adjusted to an appropriate operating frequency according to the actual computing performance of the kernel 80, the frequency of the core 80 with high computing performance will be increased, and the frequency of the core 80 with low computing performance will be reduced, thereby Give full play to the computing performance of each core 80.
  • the first accuracy rate threshold and the second accuracy rate threshold are both 90%.
  • the current operating frequency of the kernel 80 is increased to 600MHz.
  • a working frequency that is, increasing its working frequency to 650MHz; if the calculation accuracy of the kernel 80 is lower than 90% (indicating that the computing performance of the kernel 80 is insufficient to work at the current operating frequency of 600MHz), the kernel The current operating frequency of 80 is reduced to the next operating frequency, that is, its operating frequency is reduced to 550MHz.
  • the last working frequency is not limited to the last adjacent working frequency, and more than one last adjacent working frequency can be set as the previous working frequency; the next working frequency It is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency may be set as the next operating frequency. That is, the current operating frequency of the core 80 is increased from 600 MHz to the previous operating frequency of 700 MHz; the current operating frequency of the core 80 is reduced to 600 MHz to the next operating frequency of 500 MHz.
  • the previous working frequency point and the spacing between the next working frequency point are not limited here.
  • the frequency difference between the current working frequency point and the previous working frequency point is 1 to 10%
  • the frequency difference between the current working frequency point and the next working frequency point is 1 to 10%
  • the first accuracy rate threshold is 90%
  • the second accuracy rate threshold is 80%.
  • the current operating frequency of the kernel 80 is increased to the previous one.
  • the operating frequency is to increase its operating frequency to 650MHz; if the calculation accuracy of the kernel 80 is less than 80% (indicating that the computing performance of the kernel 80 is insufficient to work at the current operating frequency of 600MHz), the kernel 80 The current operating frequency of the frequency is reduced to the next operating frequency, that is, its operating frequency is reduced to 550MHz.
  • the calculation correct rate may be a calculation correct rate of Nonce (Number, random number) submitted by the kernel 80 within the adjustment period. That is, the ratio of the correct Nonce among all the Nonces submitted by the kernel 80 within a predetermined time.
  • the block header in the regional chain includes the Nonce (4 bytes).
  • the Nonce is a random value.
  • the role of the miner is to guess the value of the Nonce, so that the hash of the block header can be less than the target value Target, so that Write to the blockchain. Specifically, this property is started from 0 and traversed to 2 ⁇ 32 to calculate the hash value of the block header. If the obtained hash result meets the conditions, mining is successful.
  • the computing performance analysis module 20 in FIG. 3 further includes:
  • the first analysis sub-module 21 is configured to analyze whether the Nonce submitted by the kernel 80 is correct within a predetermined adjustment period.
  • the statistics sub-module 22 is configured to count the number of correct Nonces and the number of incorrect Nonces submitted by the kernel 80 in the adjustment period.
  • the first judging submodule 23 is configured to calculate the Nonce calculation correct rate in the adjustment period of the kernel 80 according to the number of correct Nonces and the number of wrong Nonces, and judge whether the Nonce calculation correct rate reaches a predetermined first correct rate.
  • a threshold and / or a second correctness threshold are configured to calculate the Nonce calculation correct rate in the adjustment period of the kernel 80 according to the number of correct Nonces and the number of wrong Nonces, and judge whether the Nonce calculation correct rate reaches a predetermined first correct rate.
  • a threshold and / or a second correctness threshold are examples of the Nonce calculation correct rate.
  • the frequency adjusting module 30 is configured to adjust the current working frequency of the core 80 to the previous working frequency if the Nonce calculation correct rate of the kernel 80 reaches the first correct rate threshold; and / or to calculate the correct rate if the Nonce of the kernel 80 calculates If the second correct rate threshold is not reached, the current operating frequency of the core 80 is adjusted to the next operating frequency.
  • the first analysis sub-module 21 further includes:
  • a first calculation unit 211 is configured to calculate a first result by using a predetermined algorithm after the kernel 80 submits a Nonce within the adjustment period.
  • the first result includes a first feature.
  • the first calculation unit 211 It is preferably provided in the kernel 80.
  • the Nonce submitted by each core 80 includes identification information (ID) of the Nonce, so that the calculation result of each core 80 can be calculated.
  • a first checking unit 212 is configured to calculate a second result by using the same algorithm submitted by the kernel 80, and the second result includes a second feature. If the first feature is the same as the second feature, determine The Nonce is a correct Nonce, otherwise it is determined that the Nonce is a false Nonce.
  • the first checking unit 212 is preferably provided in a computing chip.
  • the kernel 80 calculates a Nonce and submits it, and embeds the Nonce in the block header to calculate a first hash result.
  • the first 20 bits of the first hash result are 0 (first feature).
  • the first checking unit 212 also calculates the Nonce embedded in the block header to obtain a second hash result. If the first 20 bits of the second hash result are also 0 (second feature), the Nonce is considered to be a correct submission.
  • the first verification unit 212 checks the nonce submitted by the kernel 80. If the hash calculated by the nonce submitted by the kernel 80 also passes the Target_Lite judgment, it is considered that the kernel 80 is correctly submitted, otherwise it is Incorrect submission.
  • the invention is not limited to the use of nonce that can be written into the final blockchain.
  • the nonce that interacts between the first verification unit 212 and the kernel 80 satisfies a lower threshold, has a high submission density, and is conducive to frequency adjustment.
  • the calculation performance analysis module 20 is configured to analyze, in real time, whether the calculation accuracy rate of the kernel 80 during the adjustment period reaches the first accuracy rate threshold and / or the second accuracy rate threshold according to a preset real-time adjustment instruction.
  • the first accuracy threshold is the same as or different from the second accuracy threshold.
  • the frequency adjustment module 30 is configured to increase the current operating frequency of the kernel 80 to the previous operating frequency in real time if the calculation accuracy rate of the kernel 80 within the adjustment period reaches the first accuracy rate threshold. If the calculation accuracy rate of the kernel 80 within the adjustment period does not reach the second accuracy rate threshold, the current operating frequency of the kernel 80 is reduced to the next operating frequency in real time, so that the operating frequency of the kernel 80 is dynamically adjusted in real time.
  • the calculation performance analysis module 20 is configured to, according to a preset timing adjustment instruction, analyze whether the calculation accuracy rate of the kernel 80 in the adjustment period reaches the first within an adjustment period set by the timing adjustment instruction.
  • the accuracy rate threshold and / or the second accuracy rate threshold, the first accuracy rate threshold being the same as or different from the second accuracy rate threshold.
  • the frequency adjustment module 30 is configured to adjust the current operating frequency of the kernel 80 to the previous operating frequency if the calculation accuracy rate of the kernel 80 during the adjustment period reaches the first accuracy rate threshold. In the time period, if the calculation accuracy rate of the kernel 80 during the adjustment period does not reach the second accuracy rate threshold, the current operating frequency of the kernel 80 is adjusted to the next operating frequency, so that the operating frequency of the kernel 80 is adjusted regularly. For example, only set the Saturday (24 hours) statistics kernel 80 to calculate the correct rate every week, and adjust the frequency according to the calculated correct rate.
  • the calculation performance analysis module 20 is configured to analyze whether the calculation accuracy rate of the kernel 80 within the adjustment period reaches the first accuracy rate threshold and / or the second accuracy rate threshold according to the received immediate adjustment instruction.
  • a correctness threshold is the same as or different from the second correctness threshold.
  • the frequency adjustment module 30 is configured to adjust the current operating frequency of the kernel 80 to the previous operating frequency if the calculation accuracy rate of the kernel 80 within the adjustment period reaches the first accuracy rate threshold according to the received immediate adjustment instruction. If the calculation accuracy rate of the kernel 80 within the adjustment period does not reach the second accuracy rate threshold, the current operating frequency of the kernel 80 is adjusted to the next operating frequency. According to the stop adjustment instruction received, the adjustment of the current operating frequency of the core 80 is stopped.
  • the user may send an instant adjustment instruction to the computing device at any time as needed.
  • the computing device immediately starts analyzing the calculation accuracy rate of the kernel 80 according to the instant adjustment instruction. If the calculation accuracy rate of the kernel 80 is within the adjustment period (for example, 10 minutes), If the first correct rate threshold is exceeded (for example, higher than 99%), the operating frequency of the core 80 is adjusted upward; if the adjustment period (for example, 10 minutes), the calculated correct rate of the core 80 is lower than the second correct rate threshold (For example, less than 99%), the working frequency of the core 80 is adjusted downward.
  • the user may send a stop adjustment instruction to the computing device at any time as needed. After receiving the stop adjustment instruction, the computing device immediately stops the frequency modulation of the core 80.
  • FIG. 4 is a schematic structural diagram of a chip frequency modulation device of a computing device in a third embodiment of the present invention.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currency.
  • the computing device preferably includes a control board and a computing board connected to the control board.
  • the computing board is provided with at least one computing chip, and the computing chip is provided with a plurality of cores (Core) 80.
  • the computing device may further include a heat sink, a connection board, a power module, and the like.
  • the chip frequency modulation device 100 includes a frequency point setting module 10, a calculation performance analysis module 20, and a frequency adjustment module 30, wherein:
  • the frequency point setting module 10 is configured to set a plurality of operating frequency points for a computing chip of a computing device, each operating frequency point has a different frequency, and a plurality of cores 80 in the computing chip respectively work at each operating frequency point. That is, according to the frequency adjustment mechanism of the computing chip, several different frequency points are set for each computing chip, and each core 80 of the computing chip is allowed to work at each operating frequency point. For example, set 6 working frequency points: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz. The number of operating frequency points and the gap between frequencies can be set according to actual needs. The more operating frequency points, the more the computing performance of each core 80 can be brought into full play.
  • the core 80 When the frequency modulation switch is activated (the frequency of the core 80 has not been tuned), the core 80 may be evenly distributed, unevenly distributed, or randomly distributed to work at the working frequency point according to a predetermined rule.
  • the frequency point setting module 10 can set a plurality of working frequency points for the computing chip through a plurality of phase-locked loop circuits 70 as shown in FIG. 2.
  • the frequency point setting module 10 can also use other hardware or software for the computing chip. Set multiple working frequency points.
  • the frequency difference between the operating frequency points in the present invention needs to be controlled within a reasonable range. Because when the kernel 80 increases a working frequency point, the operating frequency of the kernel will increase a frequency difference value, which can improve certain computing performance due to the increase of the computing speed. At the same time, increasing the operating frequency of the kernel may result in a loss of computing performance due to a reduction in the accuracy of the calculation. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies, so that when the kernel 80 is adjusted from the current operating frequency to the previous operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss. Preferably, the frequency difference between adjacent operating frequency points is 1 to 10%.
  • the computing performance analysis module 20 is configured to analyze a computing performance index of each core 80 at a current working frequency.
  • the computing performance analysis module 20 further includes:
  • a setting sub-module 24 is configured to preset a reference node value of the kernel 80, calculate a correct weight value, calculate an error weight value, calculate a correct threshold value, and calculate an error threshold value.
  • the calculated correct weight value and the calculated error weight value may be the same or different; the calculated correct threshold value and the calculated error threshold value may be the same or different.
  • the reference node value, the calculation of the correct weight value, the calculation of the error weight value, the calculation of the correct threshold value and the calculation of the error threshold value are all adjustable parameters, and can be optimized and set according to actual needs such as frequency adjustment speed.
  • the second analysis sub-module 25 is configured to analyze whether each calculation of the kernel 80 is correct.
  • the kernel 80 may perform various calculations, and may analyze whether each calculation or calculations of the kernel 80 are correct. It is preferable to analyze whether the Nonce calculated by the kernel 80 is correct.
  • the counting sub-module 26 is used for the kernel 80 to calculate the correct weight value on the reference node value every time it calculates correctly at least once, and the kernel 80 calculates the error weight value on the reference node value once for each calculation error.
  • the reference node value is added once to calculate the correct weight value.
  • N is a natural number greater than 1
  • the kernel 80 calculates the error weight once, and reduces the calculation error weight value on the reference node value.
  • the kernel 80 calculates N times for each error (N is a natural number greater than 1), and reduces the value of the calculation error weight once on the reference node value.
  • the second judging sub-module 27 is configured to judge whether the current reference node value of the kernel 80 reaches the calculation correct threshold value or the calculation error threshold value. If the current reference node value reaches the calculation correct threshold, it indicates that the computing performance of the kernel 80 is high and there may be room for improvement; if the current reference node value reaches the calculation error threshold, it indicates that the calculation performance of the kernel 80 is weak, It may not be enough to work at the frequency corresponding to the current operating frequency.
  • the frequency adjustment module 30 is configured to raise the current operating frequency of the kernel 80 to the previous operating frequency if the current reference node value of the kernel 80 reaches the calculation correct threshold, indicating that the kernel 80 has not yet reached the optimal computing performance; and If the current reference node value of the kernel 80 reaches the calculation error threshold, it indicates that the computing performance of the kernel 80 is insufficient to work at the current operating frequency, and the current operating frequency of the kernel 80 is adjusted to the next operating frequency.
  • the frequency adjustment module 30 can tune the core 80 through the phase-locked loop circuit 70 or software as shown in FIG. 2.
  • the kernel 80 will be adjusted to an appropriate operating frequency according to the actual computing performance of the kernel 80, the frequency of the core 80 with high computing performance will be increased, and the frequency of the core 80 with low computing performance will be reduced, thereby Give full play to the computing performance of each core 80.
  • the last working frequency is not limited to the last adjacent working frequency, and more than one last adjacent working frequency can be set as the previous working frequency; the next working frequency It is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency may be set as the next operating frequency.
  • the current operating frequency of the core 80 is increased from 600 MHz to the previous operating frequency of 700 MHz; the current operating frequency of the core 80 is reduced to 600 MHz to the next operating frequency of 500 MHz.
  • the previous working frequency point and the spacing between the next working frequency point are not limited here.
  • the frequency difference between the current working frequency point and the previous working frequency point is 1 to 10%, and the frequency difference between the current working frequency point and the next working frequency point is 1 to 10%, so that the kernel 80 moves from the current When the operating frequency is adjusted to the previous operating frequency or the next operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss.
  • 400000 is set as the reference node value
  • the calculated correct weight value is set to 180
  • the calculated error weight value is set to 9000
  • the calculated correct threshold value and the calculated error threshold value are both set to 100,000.
  • each time the kernel 80 calculates correctly add 180 to the reference node value (calculate the correct weight value); every time the kernel 80 calculates incorrectly, reduce 9000 (calculate the error weight value) to the reference node value; use the reference node value As a benchmark, for each increase or decrease of 100,000 (calculate the correct threshold and calculate the incorrect threshold), advance to the next frequency point or decrease the order to the next frequency point.
  • the current mechanism is similar to the wrong and correct tug of war mechanism, where right and wrong can have different weights.
  • Set the reference node value and calculate the correct weight value every time you receive a correct result. Reduce the error weight value once every time you receive an incorrect result. If the reward or punishment exceeds the corresponding side threshold, increase or decrease the frequency. It can be understood that the adjustment system has a marker, and the reference node value is the initial value of the maker. If there is a correct submission, maker + 180, and each time an error is submitted, maker-9000.
  • N is a natural number greater than or equal to 1
  • M is a natural number greater than or equal to 1
  • the marker should be in the position of 400000 + N * 180-M * 9000, if the marker exceeds a certain number
  • the side threshold is adjusted accordingly (that is, up or down). Then each time the frequency is adjusted to a new frequency, the value is initialized, that is, the current reference node value is reset to the initial reference node value.
  • the setting sub-module 24 is configured to set and adjust the reference node value of the kernel 80, calculate the correct weight value, calculate the error weight value, calculate the correct threshold value and / or calculate the error threshold value, calculate the correct weight value and
  • the calculation error weight values are the same or different, and the calculation correct threshold value and the calculation error threshold value are the same or different.
  • the setting sub-module 24 is used to control the resident error rate S that the kernel 80 expects to tolerate by controlling the ratio of calculating the correct weight value and calculating the incorrect weight value.
  • the setting sub-module 24 is configured to control the adjustment period by controlling the absolute value of calculating the correct weight value and calculating the incorrect weight value.
  • the setting sub-module 24 is configured to control the adjustment period by controlling the absolute value of the calculated correct threshold and the calculated incorrect threshold.
  • the correct calculation may be the correct calculation of Nonce by the kernel 80.
  • the second analysis sub-module 25 is used to analyze whether the Nonce submitted by the kernel 80 is correct.
  • the counting submodule 26 is configured to add a correct Nonce to the reference node value every time the kernel 80 submits the correct Nonce at least once; the kernel 80 reduces the reference node value to calculate the error weight value every time it submits the wrong Nonce at least once .
  • the reference node value is added once to calculate the correct weight value.
  • N is a natural number greater than 1
  • the reference node value is added once to calculate the correct weight value.
  • the reference node value is reduced by one to calculate the error weight value.
  • the kernel 80 submits N (N is a natural number greater than 1) error Nonce every time, and the reference node value is reduced to calculate the error weight value once.
  • the second analysis sub-module 25 further includes:
  • the second calculating unit 251 is configured to submit a Nonce by the kernel 80, and the kernel 80 calculates the Nonce through a predetermined algorithm to calculate a first result, where the first result includes a first feature.
  • a second checking unit 252 is configured to calculate a second result by Nonce through the same algorithm, and the second result includes a second feature. If the first feature is the same as the second feature, it is judged that Nonce is correct Nonce, otherwise it is judged that Nonce is wrong Nonce.
  • the kernel 80 calculates a Nonce and submits it, and embeds the Nonce into the block header to obtain a first hash result.
  • the first 20 bits of the first hash result are 0 (first feature).
  • the second checking unit 252 also calculates the Nonce embedded in the block header to obtain a second hash result. If the first 20 bits of the second hash result are also 0 (second feature), the Nonce is considered to be a correct submission.
  • the first verification unit 212 checks the nonce submitted by the kernel 80. If the hash calculated by the nonce submitted by the kernel 80 also passes the Target_Lite judgment, it is considered that the kernel 80 is correctly submitted, otherwise it is Incorrect submission.
  • the invention is not limited to the use of nonce that can be written into the final blockchain.
  • the nonce that interacts between the first verification unit 212 and the kernel 80 satisfies a lower threshold, has a high submission density, and is conducive to frequency adjustment.
  • phase-locked loop circuits 70 are used, and six operating frequency points are set: 500 MHz, 550 MHz, 600 MHz, 650 MHz, 700 MHz, and 750 MHz.
  • 400000 is set as the reference node value
  • the calculated correct weight value is set to 180
  • the calculated error weight value is set to 9000
  • the calculated correct threshold value and the calculated error threshold value are both set to 100,000.
  • the number of cores distributed on the corresponding frequencies according to the 4 hash boards is as follows:
  • Hashboard 0 [294, 26, 224, 1023, 1665]
  • Hashboard 1 [274, 47, 111, 212, 963, 1721]
  • Hashboard 2 [350, 25, 153, 369, 1381, 1050]
  • Hashboard 3 [488, 33, 184, 367, 1342, 950]
  • the mechanism will be further explained with data.
  • the core 80 works for a long time at a certain frequency point (because the expected step size is 0 at this time), and the working frequency will not be adjusted up or down.
  • the computing performance analysis module 20 is configured to determine, in real time, according to a preset real-time adjustment instruction, whether the current reference node of the kernel 80 reaches the calculation correct threshold or the calculation error threshold, and the calculation correct threshold or the calculation error threshold is the same or Not the same.
  • the frequency adjustment module 30 is configured to raise the current operating frequency of the kernel 80 to the previous operating frequency in real time if the current reference node value of the kernel 80 reaches the calculation correct threshold; if the current reference node value of the kernel 80 reaches the calculation error threshold , The current operating frequency of the core 80 is reduced to the next operating frequency in real time, so that the operating frequency of the core 80 is dynamically adjusted in real time.
  • the calculation performance analysis module 20 is configured to determine whether the current reference node of the kernel 80 reaches the calculation correct threshold value or the calculation error threshold value within the adjustment time period set by the timing adjustment instruction according to a preset timing adjustment instruction.
  • the calculated correct threshold or the calculated incorrect threshold are the same or different.
  • the frequency adjustment module 30 is configured to adjust the current working frequency of the kernel 80 to the previous working frequency if the current reference node value of the kernel 80 reaches the calculation correct threshold during the adjustment time period.
  • the current reference node value of the kernel 80 reaches the calculation error threshold, and the current operating frequency of the kernel 80 is reduced to the next operating frequency, so that the operating frequency of the kernel 80 is adjusted regularly. For example, if you set the number of correct Nonces in the kernel 80 within 24 hours of each Saturday only, set the frequency and adjust the frequency according to the calculation accuracy rate.
  • the calculation performance analysis module 20 is configured to analyze whether the current reference node of the kernel 80 reaches the calculation correct threshold or calculation error threshold according to the received immediate adjustment instruction, and the calculation correct threshold or calculation error threshold is the same or different .
  • the frequency adjustment module 30 is configured to adjust the current operating frequency of the kernel 80 to the previous operating frequency if the current reference node value of the kernel 80 reaches the calculation correct threshold according to the received immediate adjustment instruction. If the current reference node value of the kernel 80 reaches the calculation error threshold, the current operating frequency of the kernel 80 is reduced to the next operating frequency. And to stop adjusting the current operating frequency of the core 80 according to the received stop adjustment instruction.
  • the user can send an instant adjustment instruction to the computing device at any time as needed.
  • the user sets the kernel 80 to add a weight A to the reference node every time the correct Nonce is calculated, and the kernel 80 reduces the weight B to the reference node every time it calculates a wrong Nonce.
  • the kernel 80 is advanced to the next frequency point.
  • the current reduction value reaches the calculation error number threshold D, the kernel 80 is reduced to the next frequency point.
  • the user may send a stop adjustment instruction to the computing device at any time as needed. After receiving the stop adjustment instruction, the computing device immediately stops the frequency modulation of the core 80.
  • FIG. 6 is a schematic structural diagram of a chip frequency modulation device of a computing device in a fourth embodiment of the present invention.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currency.
  • the computing device preferably includes a control board and a computing board connected to the control board.
  • the computing board is provided with at least one computing chip, and the computing chip is provided with a plurality of cores (Core) 80.
  • the computing device may further include a heat sink, a connection board, a power module, and the like.
  • the chip frequency modulation device 100 includes a frequency point setting module 10, a calculation performance analysis module 20, a frequency adjustment module 30, a frequency point statistics module 50, and a frequency point adjustment module 60, wherein:
  • the frequency point setting module 10 is configured to set a plurality of operating frequency points for a computing chip of a computing device, and respectively operate a plurality of cores 80 in the computing chip at each operating frequency point. That is, a number of different frequency points are set for each computing chip according to the frequency adjustment mechanism of the computing chip level, and the core 80 of the computing chip is allowed to work at various operating frequency points. For example, set 6 working frequency points, 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz. The number of frequency points of each working frequency point and the gap between the frequencies can be set according to actual needs. The more working frequency points, the more fully the computing performance of each core 80 can be brought into full play.
  • the frequency point setting module 10 can set multiple operating frequency points for the computing chip through multiple phase-locked loop circuits (PPL) 70 as shown in FIG. 2.
  • PPL phase-locked loop circuits
  • the frequency point setting module 10 can also use other hardware or software. Set multiple operating frequency points for the computing chip.
  • the frequency difference between the operating frequency points in the present invention needs to be controlled within a reasonable range. Because when the kernel 80 increases a working frequency point, the operating frequency of the kernel will increase a frequency difference value, which can improve certain computing performance due to the increase of the computing speed. At the same time, increasing the operating frequency of the kernel may result in a loss of computing performance due to a reduction in the accuracy of the calculation. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies, so that when the kernel 80 is adjusted from the current operating frequency to the previous operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss. Preferably, the frequency difference between adjacent operating frequency points is 1 to 10%.
  • the computing performance analysis module 20 is configured to analyze a computing performance index of each core 80 at a current working frequency.
  • the calculation performance indicator represents the actual calculation performance of the kernel 80 at the current operating frequency, including but not limited to the calculation accuracy rate, the calculation accuracy number, the calculation speed, and the like. If the calculation performance index of the kernel 80 is high, it indicates that there may be room for improvement in the calculation performance of the kernel 80; if the calculation performance index of the kernel 80 is low, it indicates that the calculation performance of the kernel 80 may not be sufficient for the current work Work at the frequency corresponding to the frequency point.
  • the frequency adjustment module 30 is configured to increase or decrease the current operating frequency of the core 80 according to the calculation performance index of the core 80. That is, according to the frequency adjustment mechanism at the kernel level, the kernel 80 will be adjusted to an appropriate operating frequency according to the actual computing performance of the kernel 80, the frequency of the core 80 with high computing performance will be increased, and the frequency of the core 80 with low computing performance will be reduced, thereby Give full play to the computing performance of each core 80.
  • the frequency adjustment module 30 can tune the core 80 through the phase-locked loop circuit 70 or software as shown in FIG. 2.
  • the calculation accuracy rate of the kernel 80 within the adjustment period reaches the first accuracy rate threshold, it indicates that the kernel 80 has not yet reached the optimal calculation performance, so the current operating frequency of the kernel 80 is raised to the previous operating frequency; If the calculation accuracy rate of the kernel 80 within the adjustment period does not reach the second accuracy rate threshold, it indicates that the calculation performance of the kernel 80 is insufficient to work at the current operating frequency, so the current operating frequency of the kernel 80 is adjusted to the next operation. Frequency.
  • the last working frequency is not limited to the last adjacent working frequency, and more than one last adjacent working frequency can be set as the previous working frequency; the next working frequency It is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency may be set as the next operating frequency. That is, the current operating frequency of the core 80 is increased from 600 MHz to the previous operating frequency of 700 MHz; the current operating frequency of the core 80 is reduced to 600 MHz to the next operating frequency of 500 MHz.
  • the previous working frequency point and the spacing between the next working frequency point are not limited here.
  • the frequency difference between the current working frequency point and the previous working frequency point is 1 to 10%
  • the frequency difference between the current working frequency point and the next working frequency point is 1 to 10%
  • the frequency point statistics module 50 is configured to count the current distribution status of the frequency-modulated kernel 80 at each working frequency point. After the operating frequency of the core 80 is automatically tuned according to its own computing performance, it will be distributed to work at each operating frequency. The frequency point statistics module 50 counts the number of distributions of the tuned kernel 80 at each operating frequency. The current distribution status.
  • the operating frequency can be divided into at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency. The highest frequency among the high-frequency operating frequencies is the highest operating frequency, and the low-frequency The lowest operating frequency is the lowest operating frequency.
  • each operating frequency point is set, 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz.
  • the numbers of the six operating frequency points are: 100, 200, 100, 100. , 200, 300.
  • 500MHz, 550MHz is the low-frequency operating frequency
  • 600MHz, 650MHz is the intermediate operating frequency
  • 700MHz, 750MHz is the high-frequency operating frequency
  • 500MHz is the lowest operating frequency
  • 750MHz is the highest operating frequency.
  • the frequency adjustment module 60 is configured to adjust a frequency for setting a working frequency according to the current distribution state of the kernel 80 and a predetermined frequency adjustment mechanism.
  • the frequency adjustment mechanism is a correspondence between a kernel distribution state and a frequency adjustment.
  • the kernel distribution state refers to a distribution state in which the kernel 80 operates at various operating frequencies.
  • the adjusting and setting the frequency of the working frequency point refers to directly adjusting the frequency of the working frequency point.
  • the frequency adjustment module 60 preferably adjusts the frequency at which the operating frequency is set by the phase-locked loop circuit 70 shown in FIG. 2.
  • the adjustment mode of the frequency point adjustment module 50 for setting the working frequency point is not limited to this.
  • the ideal state of the present invention is that it is desired to exceed a predetermined ratio (such as 50%) or the maximum number of cores 80 to fall to the intermediate operating frequency point, so that the frequency of the cores 80 has more room for upward adjustment.
  • a core 80 exceeding a predetermined ratio (such as 30%) operates at the highest operating frequency (750MHz), it may result in the core 80 not exhibiting the maximum computing performance (because it may be higher).
  • the operating frequency (600MHz) is modified to be set to at least one optimized high-frequency operating frequency (800MHz), and the core 80 originally operating at the operating frequency (600MHz) will all be transferred to the highest operating frequency (750MHz) to work.
  • the frequency of the optimized high-frequency operating frequency is higher than the frequency of the highest operating frequency, so as to give full play to the computing performance of each core 80.
  • the frequency adjustment module 60 further includes a first frequency adjustment sub-module 61 and / or a second frequency adjustment sub-module 62, wherein:
  • the first frequency adjustment sub-module 61 is configured to, if the core 80 exceeding a predetermined second ratio operates on at least one high-frequency operating frequency, the core 80 may not perform the maximum computing performance (because Higher), modify at least one operating frequency to at least one optimized high-frequency operating frequency, and the frequency of the optimized high-frequency operating frequency is higher than the frequency of the highest operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the first frequency adjustment sub-module 61 is used for the core 80 that exceeds the second ratio to operate at the highest operating frequency, which may cause the core 80 to not exert the maximum computing performance (because it may be higher), Modify an operating frequency to an optimized high-frequency operating frequency, and the frequency of the optimized high-frequency operating frequency is higher than the frequency of the highest operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the core 80 works at the highest operating frequency (750MHz), modify a low-frequency operating frequency (500MHz) to optimize the high-frequency operating frequency (800MHz), or set an intermediate frequency Modify the operating frequency (600MHz) to optimize the high-frequency operating frequency (800MHz); or modify the highest operating frequency (750MHz) to optimize the high-frequency operating frequency (800MHz).
  • the second frequency adjustment sub-module 62 is configured to, if the core 80 exceeding a predetermined third ratio operates on at least one low-frequency operating frequency, it indicates that the computing power of the core 80 is insufficient to work at the low frequency.
  • At the operating frequency at least one operating frequency is modified to be at least one optimized low-frequency operating frequency, and the frequency of the optimized low-frequency operating frequency is lower than the frequency of the lowest operating frequency, so as to prevent the computing core with poor performance from affecting the computing chip.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the second frequency adjustment sub-module 62 is used for the core 80 that exceeds the third ratio to work at the lowest operating frequency, indicating that the computing power of the kernel 80 is too poor to work at the lowest operating frequency. Therefore, a working frequency point modification is set to an optimized low frequency working frequency point. Optimize the frequency of the low-frequency operating frequency to be lower than the frequency of the lowest operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the core 80 works at the lowest operating frequency (500MHz), modify a low-frequency operating frequency (500MHz) to optimize the low-frequency operating frequency (450MHz), or set an intermediate-frequency operation Modify the frequency (600MHz) to optimize the low-frequency operating frequency (450MHz); or modify the highest operating frequency (750MHz) to optimize the low-frequency operating frequency (450MHz).
  • phase-locked loop circuits 70 are used, and six operating frequency points are set: 500 MHz, 550 MHz, 600 MHz, 650 MHz, 700 MHz, and 750 MHz.
  • the number of cores distributed on the corresponding frequencies according to the 4 hash boards is as follows:
  • Hashboard 0 [294, 26, 224, 1023, 1665]
  • Hashboard 1 [274, 47, 111, 212, 963, 1721]
  • Hashboard 2 [350, 25, 153, 369, 1381, 1050]
  • Hashboard 3 [488, 33, 184, 367, 1342, 950]
  • the data roughly conforms to the normal distribution, and the minimum operating frequency (500Mhz) is the lowest frequency at which a single core 80 works, and it cannot be adjusted downwards (if the error Rate is too high, you can consider turning off the lowest frequency); while the highest operating frequency (750Mhz) accumulates a core 80 that exceeds a predetermined ratio (for example, 50%), it means that the maximum efficiency is not exerted (because it may be higher) There is still room for further improvement in the entire computing chip.
  • a predetermined ratio such as 50%
  • the maximum number of cores 80 falls on one or more intermediate operating frequencies, such as the third operating frequency (600 MHz).
  • the long tail on the high-capacity side should be considered rather than the long tail on the low-frequency point.
  • the 550Mhz frequency point is set to the right above 800Mhz frequency point by the phase-locked loop circuit 70 shown in FIG. 2. It is expected that hundreds of cores 80 will be increased to 800M or more, which brings about an improvement in overall computing performance.
  • the frequency adjustment module 60 further includes a third frequency adjustment sub-module 63 and / or a fourth frequency adjustment sub-module 64, wherein:
  • the third frequency adjustment sub-module 63 is configured to, if the number of the cores 80 operating at least one high-frequency operating frequency is the largest, the core 80 may not perform the maximum computing performance (because it may be higher), Therefore, at least one operating frequency is modified to be at least one optimized high-frequency operating frequency, and the frequency of the optimized high-frequency operating frequency is higher than the frequency of the highest operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the maximum number of cores 80 will work at two high-frequency operating frequencies (700MHz and 750MHz), then two low-frequency operating frequencies ( 500MHz and 550MHz) to two optimized high-frequency operating frequencies (800MHz and 850MHz), or one low-frequency operating frequency (500MHz) and one intermediate-frequency operating frequency (600MHz) to two optimized high-frequency operating frequencies Points (800MHz and 850MHz).
  • the third frequency adjustment sub-module 63 is used for the maximum number of cores 80 operating at the highest operating frequency, which may result in the core 80 not exhibiting the maximum computing performance (because it may be higher) , So a working frequency modification is set to an optimized high frequency working frequency.
  • the frequency of the optimized high-frequency operating frequency is higher than the frequency of the highest operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • a low-frequency operating frequency 500MHz is modified to optimize the high-frequency operating frequency (800MHz), or an intermediate-frequency operating frequency (600MHz) Modify the setting to optimize the high-frequency operating frequency (800MHz); or set the highest operating frequency (750MHz) to optimize the high-frequency operating frequency (800MHz).
  • the fourth frequency adjustment sub-module 64 is configured to, if the number of cores 80 operating at least one low-frequency operating frequency is the largest, it indicates that the computing power of the core 80 is too poor to be sufficient to operate at the low-frequency operating frequency. Therefore, the at least one operating frequency point is modified to be at least one optimized low frequency operating frequency point, and the frequency of the optimized low frequency operating frequency point is lower than the frequency of the lowest operating frequency point, so as to avoid the core 80 with poor computing ability from affecting the overall computing chip. Computing performance.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the most cores 80 work at two low frequency working frequencies (500MHz and 550MHz), then two low frequency working frequencies (500MHz And 550MHz) to two optimized low-frequency operating frequencies (400MHz and 450MHz), or one low-frequency operating frequency (500MHz) and one intermediate-frequency operating frequency (600MHz) to two optimized low-frequency operating frequencies (400MHz) And 450MHz).
  • the fourth frequency adjustment sub-module 64 is used for the maximum number of cores 80 operating at the lowest operating frequency, indicating that the computing power of the kernel 80 is too poor to operate at the lowest operating frequency. Therefore, a working frequency point modification is set to an optimized low frequency working frequency point. Optimize the frequency of the low-frequency operating frequency to be lower than the frequency of the lowest operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the largest number of cores 80 work at the lowest operating frequency (500MHz)
  • modify an intermediate-frequency operating frequency (600MHz) Set it to optimize the low frequency operating frequency (450MHz); or modify the highest working frequency (750MHz) to optimize the low frequency operating frequency (450MHz).
  • phase-locked loop circuits 70 are used, and six operating frequency points are set: 500 MHz, 550 MHz, 600 MHz, 650 MHz, 700 MHz, and 750 MHz.
  • the number of cores distributed on the corresponding frequencies according to the 4 hash boards is as follows:
  • Hashboard 0 [294, 26, 224, 1023, 1665]
  • Hashboard 1 [274, 47, 111, 212, 963, 1721]
  • Hashboard 2 [350, 25, 153, 369, 1381, 1050]
  • Hashboard 3 [488, 33, 184, 367, 1342, 950]
  • the data roughly conforms to the normal distribution, and the minimum operating frequency (500Mhz) is the lowest frequency at which a single core 80 works, and it cannot be adjusted downwards (if the error Rate is too high, you can consider turning off the lowest frequency); while the maximum number of cores 80 accumulated at the highest operating frequency (750Mhz) means that the maximum efficiency has not been exerted (because it may be higher), the entire computing chip is also There is room for further improvement.
  • a more ideal state is that a predetermined ratio (such as 50%) or the maximum number of cores 80 falls on one or more intermediate operating frequencies, such as the third operating frequency (600 MHz).
  • the long tail on the high-capacity side should be considered rather than the long tail on the low-frequency point.
  • the frequency adjustment module 60 further includes a first stop adjustment sub-module 65 or a second stop adjustment sub-module 66, where:
  • the first stop adjustment sub-module 65 is configured to stop adjusting the frequency of the set operating frequency if the core 80 exceeding a predetermined fourth ratio operates on at least one intermediate operating frequency. Because the ideal state is that the core 80 that exceeds a predetermined fourth ratio (such as 50%) falls on one or more intermediate operating frequency points, such as the third operating frequency point (600MHz), which can give full play to the work of the core 80 Performance, so no need to tune the core 80 at this time.
  • a predetermined fourth ratio such as 50%
  • the second stop adjustment sub-module 66 is configured to stop adjusting the frequency at which the operating frequency is set if the number of cores 80 operating at least one intermediate operating frequency is the largest. Because the ideal state is that the maximum number of cores 80 falls on one or more intermediate operating frequency points, such as the third operating frequency (600MHz), which can give full play to the operating performance of the core 80, so there is no need to 80 for frequency modulation.
  • the third operating frequency 600MHz
  • the invention also provides a computing board including the chip frequency modulation device 100.
  • the invention also provides a computing device including the chip frequency modulation device 100.
  • the computing device includes at least one computing chip, and the computing chip is provided with multiple cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies.
  • the chip frequency modulation technology of the present invention actually involves two levels of frequency adjustment mechanisms: the frequency adjustment mechanism at the level of the computing chip and the frequency adjustment mechanism at the core level.
  • the frequency adjustment mechanism at the level of a computing chip refers to setting a number of suitable operating frequency points for each computing chip, and allowing each core 80 of the computing chip to work at each operating frequency point to fully exert the working performance of each core 80.
  • the kernel-level frequency adjustment mechanism refers to adjusting the core 80 to an appropriate operating frequency according to the actual computing performance of the kernel 80, increasing the frequency of the core 80 with high computing performance, and lowering the frequency of the core 80 with low computing performance, thereby Give full play to the computing performance of each core 80.
  • the method includes the steps of:
  • step S801 a plurality of operating frequency points are set for a computing chip of a computing device, and a plurality of cores 80 in the computing chip are respectively operated at each operating frequency point.
  • each core 80 of the computing chip is allowed to work at each operating frequency point.
  • set 6 working frequency points 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz.
  • the number of operating frequency points and the gap between frequencies can be set according to actual needs. The more operating frequency points, the more the computing performance of each core 80 can be brought into full play.
  • the frequency modulation switch is activated (the frequency of the core 80 has not been tuned)
  • the core 80 may be evenly distributed, unevenly distributed, or randomly distributed to work at the working frequency point according to a predetermined rule.
  • multiple operating frequency points can be set for the computing chip through multiple phase-locked loop circuits 70 as shown in FIG. 2.
  • multiple operating frequency points can also be set for the computing chip through other hardware or software.
  • step S802 the calculation performance index of each core 80 at the current operating frequency is analyzed.
  • the calculation performance indicator represents the actual calculation performance of the kernel 80 at the current operating frequency, including but not limited to the calculation accuracy rate, the calculation accuracy number, the calculation speed, and the like. If the calculation performance index of the kernel 80 is high, it indicates that there may be room for improvement in the calculation performance of the kernel 80; if the calculation performance index of the kernel 80 is low, it indicates that the calculation performance of the kernel 80 may not be sufficient for the current work Work at the frequency corresponding to the frequency point.
  • step S803 the current operating frequency of the core 80 is adjusted up or down according to the calculation performance index of the core 80.
  • the kernel 80 is adjusted to an appropriate operating frequency according to the actual calculation performance of the kernel 80, the frequency of the kernel 80 with high calculation performance is raised, and the frequency of the kernel 80 with low calculation performance is adjusted, thereby Give full play to the computing performance of each core 80.
  • the calculation accuracy rate of the kernel 80 within the adjustment period reaches the first accuracy rate threshold, it indicates that the kernel 80 has not yet reached the optimal calculation performance, so the current operating frequency of the kernel 80 is raised to the previous operating frequency; If the calculation accuracy rate of the kernel 80 within the adjustment period does not reach the second accuracy rate threshold, it indicates that the calculation performance of the kernel 80 is insufficient to work at the current operating frequency, so the current operating frequency of the kernel 80 is adjusted to the next operation. Frequency.
  • the present invention evaluates the working performance of the core 80 according to the actual computing performance of each core 80 in the computing chip, adjusts the corresponding frequency of the core 80, gives full play to the computing advantages of the core 80 with better performance, and prevents the weak performance of the core 80 from affecting the computing performance of the computing chip. , Maximize the computing performance of each core 80, thereby improving the computing speed and accuracy of the computing chip and the overall computing device.
  • the core 80 of the computing chip of the present invention does not fluctuate back and forth, and the operating frequency is relatively stable.
  • FIG. 9 is a flowchart of a chip frequency modulation method of a computing device in the first embodiment of the present invention, which can be implemented by the chip frequency modulation device 100 of the computing device shown in FIG. 2, where the computing device includes at least one computing chip, and The computing chip is provided with multiple cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies. The method includes the steps of:
  • step S901 a plurality of operating frequency points are set for the computing chip through a plurality of phase-locked loop circuits 70, and the operating frequency points and the phase-locked loop circuit 70 have a one-to-one correspondence relationship.
  • the phase-locked loop circuit 70 shown in FIG. 2 is provided inside or outside the computing chip.
  • the number of frequency points and the difference between frequencies can be set according to actual needs. The more the working frequency points, the more fully the computing performance of each core 80 can be brought into play. For example, set 6 working frequency points, 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz. Therefore, the present invention can set more phase-locked loop circuits 70 to set more operating frequency points, so that the computing performance of each core 80 can be brought into full play.
  • the frequency difference between the operating frequency points in the present invention needs to be controlled within a reasonable range. Because when the kernel 80 increases a working frequency point, the operating frequency of the kernel will increase a frequency difference value, which can improve certain computing performance due to the increase of the computing speed. At the same time, increasing the operating frequency of the kernel may result in a loss of computing performance due to a reduction in the accuracy of the calculation. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies, so that when the kernel 80 is adjusted from the current operating frequency to the previous operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss. Preferably, the frequency difference between adjacent operating frequency points is 1 to 10%.
  • step S902 the calculation performance index of each core 80 at the current working frequency is analyzed.
  • the calculation performance indicator represents the actual calculation performance of the kernel 80 at the current operating frequency, including but not limited to the calculation accuracy rate, the calculation accuracy number, the calculation speed, and the like. If the calculation performance index of the kernel 80 is high, it indicates that there may be room for improvement in the calculation performance of the kernel 80; if the calculation performance index of the kernel 80 is low, it indicates that the calculation performance of the kernel 80 may not be sufficient for the current work Work at the frequency corresponding to the frequency point.
  • this step preferably, within a predetermined adjustment period, it is analyzed whether the calculation performance index of the kernel 80 reaches a predetermined first index threshold, a second index threshold, and / or a third index threshold, the first index threshold and the second index threshold. Same or different.
  • step S903 according to the calculation performance index of the core 80, the current operating frequency of the core 80 is adjusted up or down through the phase-locked loop circuit 70 shown in FIG.
  • the current operating frequency of the core 80 may also be adjusted up or down by using other hardware or software.
  • This step preferably further includes:
  • the calculation performance index is that the core 80 is adjusting In the calculation accuracy rate within the period, the first index threshold and the second index threshold are both 90%.
  • the calculation accuracy rate of the kernel 80 during the adjustment period reaches 90%, it means that the calculation performance of the kernel 80 is better, then the current operating frequency of the kernel 80 is increased from 600 MHz to the previous operating frequency of 650 MHz; if the kernel 80 is adjusting The calculation accuracy rate within the period does not reach 90%, which indicates that the computing performance of the core 80 is weak, and then the current operating frequency of the core 80 is reduced from 600 MHz to the next operating frequency of 550 MHz.
  • the last working frequency is not limited to the last adjacent working frequency, and more than one last adjacent working frequency can be set as the previous working frequency; the next working frequency It is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency may be set as the next operating frequency.
  • the frequency difference between the current working frequency point and the previous working frequency point is 1 to 10%, and the frequency difference between the current working frequency point and the next working frequency point is 1 to 10%, so that the kernel 80 moves from the current
  • the benefit of the computing performance of the kernel 80 should be greater than the loss. That is, the current operating frequency of the core 80 is increased from 600 MHz to the previous operating frequency of 700 MHz; the current operating frequency of the core 80 is reduced to 600 MHz to the next operating frequency of 500 MHz.
  • the previous working frequency point and the spacing between the next working frequency point are not limited here.
  • the calculation performance index is the calculation accuracy rate of the kernel 80 during the adjustment period
  • the first index threshold is 90%
  • the second index threshold is 80%. If the calculation accuracy rate of the kernel 80 during the adjustment period reaches 90%, it means that the calculation performance of the kernel 80 is better, then the current operating frequency of the kernel 80 is increased from 600 MHz to the previous operating frequency of 650 MHz; if the kernel 80 is adjusting The calculation accuracy rate within the period does not reach 80%, which indicates that the computing performance of the core 80 is weak, and then the current operating frequency of the core 80 is reduced from 600 MHz to the next operating frequency of 550 MHz.
  • the calculation performance index is the number of correct calculations and the number of incorrect settlements in the adjustment period of the kernel 80.
  • the first index threshold is 100
  • the second index threshold is 10. If the number of correct calculations of the kernel 80 in the adjustment cycle reaches 100, it indicates that the calculation performance of the kernel 80 is better, then the current operating frequency of the kernel 80 is raised to 600MHz from the previous operating frequency; if the kernel 80 is in the adjustment cycle The number of errors in the calculation reaches 10, which indicates that the computing performance of the core 80 is weak, and the current operating frequency of the core 80 is reduced from 600 MHz to the next operating frequency of 550 MHz.
  • step S904 if the core 80 operating at the predetermined at least one optimized operating frequency exceeds the predetermined first ratio, the frequency modulation of the core 80 is stopped; or if the number of the core 80 operating at the at least one optimized operating frequency is the largest, stop The core 80 is frequency-modulated.
  • one or more optimized operating frequency points can be selected from several operating frequency points. If the operating frequency of most cores 80 has reached the optimized operating frequency point, it indicates that the operating frequency of the individual cores 80 in the computing chip has been optimized. In this state, the computing performance of each core 80 can be brought into full play, and no further frequency adjustment is required, so the adjustment of the operating frequency of the core 80 is stopped. For example, set 6 working frequency points, 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz, and choose two optimized working frequency points of 600Mhz and 650Mhz as the optimized working frequency point. If more than 50% of the core 80 works at the operating frequency point of 600Mhz And 650Mhz, the frequency modulation of the core 80 is stopped.
  • FIG. 10 is a flowchart of a chip frequency modulation method of a computing device in a second embodiment of the present invention, which can be implemented by the chip frequency modulation device 100 of the computing device shown in FIG. 3, where the computing device includes at least one computing chip, and The computing chip is provided with multiple cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies. The method includes the steps of:
  • step S1001 a plurality of operating frequency points are set for the computing chip of the computing device, and the multiple cores 80 in the computing chip are respectively operated at each operating frequency point.
  • a number of different frequency points are set for each operation chip according to the frequency adjustment mechanism at the operation chip level, and each core 80 of the operation chip is allowed to work at each operation frequency point.
  • set 6 working frequency points 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz.
  • the number of operating frequency points and the gap between frequencies can be set according to actual needs. The more operating frequency points, the more the computing performance of each core 80 can be brought into full play.
  • the frequency modulation switch is activated (the frequency of the core 80 has not been tuned), the core 80 may be evenly distributed, unevenly distributed, or randomly distributed to work at the working frequency point according to a predetermined rule.
  • phase-locked loop circuits 70 As shown in FIG. 2, it is preferable to set a plurality of operating frequency points for the computing chip through a plurality of phase-locked loop circuits 70 as shown in FIG. 2, and respectively operate a plurality of cores 80 in the computing chip at each operating frequency point.
  • phase-locked loop circuit 70 One-to-one correspondence with the phase-locked loop circuit 70.
  • more phase-locked loop circuits 70 can be provided to set more operating frequency points, so that the computing performance of each core 80 can be brought into full play.
  • multiple operating frequency points can also be set for the computing chip through other hardware or software.
  • the frequency difference between the operating frequency points in the present invention needs to be controlled within a reasonable range. Because when the kernel 80 increases a working frequency point, the operating frequency of the kernel will increase a frequency difference value, which can improve certain computing performance due to the increase of the computing speed. At the same time, increasing the operating frequency of the kernel may result in a loss of computing performance due to a reduction in the accuracy of the calculation. Therefore, the frequency difference between adjacent operating frequency points should be controlled reasonably, so that when the kernel 80 is adjusted from the current operating frequency point to the previous operating frequency point, the benefit of the computing performance of the kernel 80 should outweigh the loss. Preferably, the frequency difference between adjacent operating frequency points is 1 to 10%.
  • Step S1002 within a predetermined adjustment period, analyze whether the calculation accuracy rate of the kernel 80 reaches a predetermined first accuracy rate threshold and / or a second accuracy rate threshold.
  • the first accuracy rate threshold is the same as or different from the second accuracy rate threshold. If the calculation accuracy rate of the kernel 80 reaches a predetermined first accuracy rate threshold, it indicates that the calculation performance of the kernel 80 may still have room for improvement; if the calculation accuracy rate of the kernel 80 does not reach a predetermined second accuracy rate threshold, it indicates The computing performance of the kernel 80 may be insufficient to work at a frequency corresponding to the current operating frequency.
  • step S1002 further includes:
  • step S1003 if the calculation accuracy rate of the kernel 80 reaches the first accuracy rate threshold, it indicates that the kernel 80 has not reached the optimal calculation performance, and the current operating frequency of the kernel 80 is raised to the previous operating frequency.
  • this step further includes:
  • the user may send an instant adjustment instruction to the computing device at any time as needed.
  • the computing device immediately starts analyzing the calculation accuracy rate of the kernel 80 according to the instant adjustment instruction. If the calculation accuracy rate of the kernel 80 is within the adjustment period (for example, 10 minutes), If the first correct rate threshold is exceeded (for example, higher than 99%), the operating frequency of the core 80 is adjusted upward; if the adjustment period (for example, 10 minutes), the calculated correct rate of the core 80 is lower than the second correct rate threshold (For example, less than 99%), the working frequency of the core 80 is adjusted downward.
  • the user may send a stop adjustment instruction to the computing device at any time as needed. After receiving the stop adjustment instruction, the computing device immediately stops the frequency modulation of the core 80.
  • step S1004 if the calculation accuracy rate of the kernel 80 does not reach the second accuracy rate threshold, it indicates that the calculation performance of the kernel 80 is insufficient to work at the current operating frequency, and the current operating frequency of the kernel 80 is adjusted to the next operating frequency .
  • this step further includes:
  • the core 80 can be frequency-modulated by a phase-locked loop circuit 70 or software as shown in FIG. 2. That is, according to the frequency adjustment mechanism at the kernel level, the kernel 80 will be adjusted to an appropriate operating frequency according to the actual computing performance of the kernel 80, the frequency of the core 80 with high computing performance will be increased, and the frequency of the core 80 with low computing performance will be reduced, thereby Give full play to the computing performance of each core 80.
  • the first accuracy rate threshold and the second accuracy rate threshold are both 90%.
  • the current operating frequency of the kernel 80 is increased to 600MHz.
  • a working frequency that is, increasing its working frequency to 650MHz; if the calculation accuracy of the kernel 80 is lower than 90% (indicating that the computing performance of the kernel 80 is insufficient to work at the current operating frequency of 600MHz), the kernel The current operating frequency of 80 is reduced to the next operating frequency, that is, its operating frequency is reduced to 550MHz.
  • the last working frequency is not limited to the last adjacent working frequency, and more than one last adjacent working frequency can be set as the previous working frequency; the next working frequency It is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency may be set as the next operating frequency.
  • the frequency difference between the current working frequency point and the previous working frequency point is 1 to 10%, and the frequency difference between the current working frequency point and the next working frequency point is 1 to 10%, so that the kernel 80 moves from the current When the operating frequency is adjusted to the previous operating frequency or the next operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss.
  • the current operating frequency of the core 80 is increased from 600 MHz to the previous operating frequency of 700 MHz; the current operating frequency of the core 80 is reduced to 600 MHz to the next operating frequency of 500 MHz.
  • the previous working frequency point and the spacing between the next working frequency point are not limited here.
  • the first accuracy rate threshold is 90%
  • the second accuracy rate threshold is 80%.
  • the current operating frequency of the kernel 80 is increased to the previous one.
  • the operating frequency is to increase its operating frequency to 650MHz; if the calculation accuracy of the kernel 80 is less than 80% (indicating that the computing performance of the kernel 80 is insufficient to work at the current operating frequency of 600MHz), the kernel 80 The current operating frequency of the frequency is reduced to the next operating frequency, that is, its operating frequency is reduced to 550MHz.
  • FIG. 11 is a flowchart of a preferred chip frequency modulation method of a computing device in a second embodiment of the present invention, which can be implemented by the chip frequency modulation device 100 of the computing device shown in FIG. 3, where the computing device includes at least one computing chip.
  • the computing chip is provided with a plurality of cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies.
  • the calculation correct rate may be the calculation correct rate of Nonce submitted by the kernel 80 within the adjustment period. That is, the ratio of the correct Nonce among all the Nonces submitted by the kernel 80 within a predetermined time.
  • the block header includes the Nonce (4 bytes).
  • the Nonce is a random value.
  • the role of the miner is to guess the value of the Nonce, so that the hash of the block header can be smaller than the target value, which can be written into the blockchain. . Specifically, this property is started from 0 and traversed to 2 ⁇ 32 to calculate the hash value of the block header. If the obtained hash result meets the conditions, mining is successful.
  • the method includes the steps of:
  • step S1101 a plurality of operating frequency points are set for the computing chip of the computing device, and the multiple cores 80 in the computing chip are respectively operated at each operating frequency point.
  • Step S1102 during the adjustment period, analyze whether the Nonce submitted by the kernel 80 is correct.
  • This step preferably includes:
  • each time the kernel 80 submits a Nonce the kernel 80 calculates the first result from the Nonce through a predetermined algorithm, and the first result includes a first feature.
  • the Nonce submitted by each core 80 includes identification information (ID) of the Nonce, so that the calculation result of each core 80 can be calculated.
  • the verification unit of the computing chip calculates the second result of Nonce through the same algorithm, and the second result includes the second feature.
  • the checking unit determines that Nonce is correct Nonce, otherwise it determines that Nonce is false Nonce.
  • the kernel 80 calculates a Nonce and submits it, and embeds the Nonce into the block header to obtain a first hash result.
  • the first 20 bits of the first hash result are 0 (first feature).
  • the first checking unit 212 also calculates the Nonce embedded in the block header to obtain a second hash result. If the first 20 bits of the second hash result are also 0 (second feature), the Nonce is considered to be a correct submission.
  • step S1103 the number of correct Nonces submitted by the kernel 80 in the adjustment period is counted.
  • step S1104 according to the number of correct Nonces and the number of wrong Nonces, the Nonce calculation accuracy rate of the kernel 80 in the adjustment period is calculated.
  • Step S1105 it is determined whether the Nonce calculation accuracy rate reaches a predetermined first accuracy rate threshold and / or a second accuracy rate threshold. If the Nonce calculation accuracy rate of the kernel 80 reaches the first accuracy rate threshold, step S1106 is performed. If the calculated accuracy rate does not reach the second accuracy rate threshold, step S1107 is performed.
  • step S1106 if the Nonce calculation accuracy rate of the kernel 80 reaches the first accuracy rate threshold, the current operating frequency of the kernel 80 is adjusted to the previous operating frequency.
  • step S1107 if the Nonce calculation accuracy rate of the kernel 80 does not reach the second accuracy rate threshold, the current operating frequency of the kernel 80 is adjusted to the next operating frequency.
  • FIG. 12 is a flowchart of a chip frequency modulation method of a computing device in a third embodiment of the present invention, which can be implemented by the chip frequency modulation device 100 of the computing device shown in FIG. 4, where the computing device includes at least one computing chip, and The computing chip is provided with multiple cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies. The method includes the steps of:
  • step S1201 multiple operating frequency points are set for the computing chip of the computing device, and the multiple cores 80 in the computing chip are respectively operated at each operating frequency point.
  • a number of different frequency points are set for each operation chip according to the frequency adjustment mechanism at the operation chip level, and each core 80 of the operation chip is allowed to work at each operation frequency point.
  • set 6 working frequency points 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz.
  • the number of operating frequency points and the gap between frequencies can be set according to actual needs. The more operating frequency points, the more the computing performance of each core 80 can be brought into full play.
  • the frequency modulation switch is activated (the frequency of the core 80 has not been tuned)
  • the core 80 may be evenly distributed, unevenly distributed, or randomly distributed to work at the working frequency point according to a predetermined rule.
  • multiple operating frequency points may be set for the computing chip through multiple phase-locked loop circuits 70 as shown in FIG. 2, and of course, multiple operating frequency points may be set for the computing chip through other hardware or software.
  • the frequency difference between the operating frequency points in the present invention needs to be controlled within a reasonable range. Because when the kernel 80 increases a working frequency point, the operating frequency of the kernel will increase a frequency difference value, which can improve certain computing performance due to the increase of the computing speed. At the same time, increasing the operating frequency of the kernel may result in a loss of computing performance due to a reduction in the accuracy of the calculation. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies, so that when the kernel 80 is adjusted from the current operating frequency to the previous operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss. Preferably, the frequency difference between adjacent operating frequency points is 1 to 10%.
  • step S1202 the reference node value of the kernel 80, the calculation of the correct weight value, the calculation of the error weight value, the calculation of the correct threshold value and the calculation of the error threshold value are set in advance.
  • the calculated correct weight value and the calculated error weight value may be the same or different; the calculated correct threshold value and the calculated error threshold value may be the same or different.
  • the reference node value, the calculation of the correct weight value, the calculation of the error weight value, the calculation of the correct threshold value and the calculation of the error threshold value are all adjustable parameters, and can be optimized and set according to actual needs such as frequency adjustment speed.
  • the reference node value of the kernel 80 is set and adjusted according to actual requirements, the correct weight value is calculated, the incorrect weight value is calculated, the correct threshold value is calculated, and / or the incorrect threshold value is calculated.
  • the calculation of the correct threshold and the calculation of the wrong threshold are the same or different.
  • the resident error rate that the kernel 80 expects to tolerate is controlled.
  • Control the adjustment period by controlling the absolute value of calculating the correct weight value and calculating the incorrect weight value.
  • Control the adjustment cycle by controlling the absolute value of the calculated correct threshold and the calculated incorrect threshold.
  • step S1203 it is analyzed whether each calculation of the kernel 80 is correct.
  • the kernel 80 may perform various calculations, and may analyze whether each calculation or calculations of the kernel 80 are correct. It is preferable to analyze whether the Nonce calculated by the kernel 80 is correct.
  • the kernel 80 calculates the correct weight value on the reference node value every time it calculates correctly at least once, and the kernel 80 calculates the error weight value on the reference node value once every time it calculates it incorrectly.
  • the reference node value is added once to calculate the correct weight value.
  • N is a natural number greater than 1
  • the reference node value is added once to calculate the correct weight value.
  • the kernel 80 calculates the error weight once, and reduces the calculation error weight value on the reference node value.
  • the kernel 80 calculates N times for each error (N is a natural number greater than 1), and reduces the value of the calculation error weight once on the reference node value.
  • step S1205 it is determined whether the current reference node value of the kernel 80 reaches the calculation correct threshold value or the calculation error threshold value. If the current reference node value of the kernel 80 reaches the calculation correct threshold, step S1206 is performed; if the current reference node value of the kernel 80 reaches the calculation error threshold, step S1207 is performed.
  • This step preferably includes:
  • step S1206 if the current reference node value of the kernel 80 reaches the calculation correct threshold, it indicates that the kernel 80 has not reached the optimal computing performance, and the current operating frequency of the kernel 80 is adjusted to the previous operating frequency.
  • This step preferably includes:
  • step S1207 if the current reference node value of the kernel 80 reaches the calculation error threshold, it indicates that the computing performance of the kernel 80 is insufficient to work at the current operating frequency, and the current operating frequency of the kernel 80 is adjusted to the next operating frequency.
  • This step preferably includes:
  • the user can send an instant adjustment instruction to the computing device at any time as needed.
  • the user sets the kernel 80 to add a weight A to the reference node every time the correct Nonce is calculated, and the kernel 80 reduces the weight B to the reference node every time it calculates a wrong Nonce.
  • the kernel 80 is advanced to the next frequency point.
  • the current reduction value reaches the calculation error number threshold D, the kernel 80 is reduced to the next frequency point.
  • the user may send a stop adjustment instruction to the computing device at any time as needed. After receiving the stop adjustment instruction, the computing device immediately stops the frequency modulation of the core 80.
  • the last working frequency is not limited to the last adjacent working frequency, and more than one last adjacent working frequency can be set as the previous working frequency; the next working frequency It is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency may be set as the next operating frequency.
  • the frequency difference between the current working frequency point and the previous working frequency point is 1 to 10%, and the frequency difference between the current working frequency point and the next working frequency point is 1 to 10%, so that the kernel 80 moves from the current When the operating frequency is adjusted to the previous operating frequency or the next operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss.
  • the current operating frequency of the core 80 is increased from 600 MHz to the previous operating frequency of 700 MHz; the current operating frequency of the core 80 is reduced to 600 MHz to the next operating frequency of 500 MHz.
  • the previous working frequency point and the spacing between the next working frequency point are not limited here.
  • the core 80 may be frequency-modulated by a phase-locked loop circuit 70 or software as shown in FIG. 2. That is, according to the frequency adjustment mechanism at the kernel level, the kernel 80 will be adjusted to an appropriate operating frequency according to the actual computing performance of the kernel 80, the frequency of the core 80 with high computing performance will be increased, and the frequency of the core 80 with low computing performance will be reduced, thereby Give full play to the computing performance of each core 80.
  • 400000 is set as the reference node value
  • the calculated correct weight value is set to 180
  • the calculated error weight value is set to 9000
  • the calculated correct threshold value and the calculated error threshold value are both set to 100,000.
  • each time the kernel 80 calculates correctly at least once add 180 to the reference node value (calculate the correct weight value); every time the kernel 80 calculates incorrectly at least once, reduce the reference node value by 9000 (calculate the error weight value); The node value is the benchmark. For each increase or decrease of 100,000 (the calculation of the correct threshold and the calculation of the error threshold), it advances to the next frequency point or decreases to the next frequency point.
  • the current mechanism is similar to the wrong and correct tug of war mechanism, where right and wrong can have different weights.
  • Set the reference node value and calculate the correct weight value every time you receive a correct result. Reduce the error weight value once every time you receive an incorrect result. If the reward or punishment exceeds the corresponding side threshold, increase or decrease the frequency. It can be understood that the adjustment system has a marker, and the reference node value is the initial value of the maker. If there is a correct submission, maker + 180, and each time an error is submitted, maker-9000.
  • N is a natural number greater than or equal to 1
  • M is a natural number greater than or equal to 1
  • the marker should be in the position of 400000 + N * 180-M * 9000, if the marker exceeds a certain number
  • the side threshold is adjusted accordingly (up or down). Then each time the frequency is adjusted to a new frequency, the value is initialized, that is, the current reference node value is reset to the initial reference node value.
  • FIG. 13 is a flowchart of a preferred chip frequency modulation method of a computing device in a third embodiment of the present invention, which can be implemented by the chip frequency modulation device 100 of the computing device shown in FIG. 4, where the computing device includes at least one computing chip.
  • the computing chip is provided with a plurality of cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies. The method includes the steps of:
  • step S1301 multiple operating frequency points are set for the computing chip of the computing device, and the multiple cores 80 in the computing chip are respectively operated at each operating frequency point.
  • step S1302 the reference node value of the kernel 80, the calculation of the correct weight value, the calculation of the error weight value, the calculation of the correct threshold value and the calculation of the error threshold value are set in advance.
  • step S1303 it is analyzed whether the Nonce submitted by the kernel 80 is correct.
  • this step further includes:
  • the kernel 80 calculates the first result from the Nonce through a predetermined algorithm, and the first result includes a first feature.
  • the verification unit of the computing chip calculates the second result of Nonce through the same algorithm, and the second result includes the second feature.
  • the checking unit determines that Nonce is correct Nonce, otherwise it determines that Nonce is false Nonce.
  • the kernel 80 calculates a Nonce and submits it, and embeds the Nonce into the block header to obtain a first hash result.
  • the first 20 bits of the first hash result are 0 (first feature).
  • the second checking unit 252 also calculates the Nonce embedded in the block header to obtain a second hash result. If the first 20 bits of the second hash result are also 0 (second feature), the Nonce is considered to be a correct submission.
  • step S1304 each time the kernel 80 submits the correct Nonce at least once, the correct weight value is added to the reference node value, and every time the kernel 80 submits the wrong Nonce at least once, the error weight value is reduced from the reference node value.
  • the reference node value is added once to calculate the correct weight value.
  • N N is a natural number greater than 1
  • the reference node value is added once to calculate the correct weight value.
  • the kernel 80 submits an error Nonce the reference node value is reduced by one to calculate the error weight value.
  • the kernel 80 submits N (N is a natural number greater than 1) error Nonce every time, and the reference node value is reduced to calculate the error weight value once.
  • step S1305 it is determined whether the current reference node value of the kernel 80 reaches the calculation correct threshold value or the calculation error threshold value. If the current reference node value of the kernel 80 reaches the calculation correct threshold, step S1206 is performed; if the current reference node value of the kernel 80 reaches the calculation error threshold, step S1207 is performed.
  • step S1306 if the current reference node value of the kernel 80 reaches the calculation correct threshold, the current operating frequency of the kernel 80 is adjusted to the previous operating frequency.
  • step S1307 if the current reference node value of the kernel 80 reaches the calculation error threshold, the current operating frequency of the kernel 80 is adjusted to the next operating frequency.
  • phase-locked loop circuits 70 are used, and six operating frequency points are set: 500 MHz, 550 MHz, 600 MHz, 650 MHz, 700 MHz, and 750 MHz.
  • the calculated correct weight value is set to 180
  • the calculated error weight value is set to 9000
  • the calculated correct threshold value and the calculated error threshold value are both set to 100,000.
  • the number of cores distributed on the corresponding frequencies according to the 4 hash boards is as follows:
  • Hashboard 0 [294, 26, 224, 1023, 1665]
  • Hashboard 1 [274, 47, 111, 212, 963, 1721]
  • Hashboard 2 [350, 25, 153, 369, 1381, 1050]
  • Hashboard 3 [488, 33, 184, 367, 1342, 950]
  • the mechanism will be further explained with data.
  • the core 80 works for a long time at a certain frequency point (because the expected step size is 0 at this time), and the working frequency will not be adjusted up or down.
  • FIG. 14 is a flowchart of a chip frequency modulation method of a computing device in a fourth embodiment of the present invention, which can be implemented by the chip frequency modulation device 100 of the computing device, where the computing device includes at least one computing chip, and the computing chip is provided with Multiple cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies. The method includes the steps of:
  • step S1401 multiple operating frequency points are set for the computing chip of the computing device, and the multiple cores 80 in the computing chip are respectively operated at each operating frequency point.
  • this step according to the frequency adjustment mechanism at the level of the computing chip, several different frequency points are set for each computing chip, and the core 80 of the computing chip is allowed to work at each working frequency point. For example, set 6 working frequency points, 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz. The number of frequency points of each working frequency point and the gap between the frequencies can be set according to actual needs. The more working frequency points, the more fully the computing performance of each core 80 can be brought into full play. When the frequency modulation switch is activated (before the core 80 is not frequency-modulated), the core 80 may be evenly distributed, unevenly distributed, or randomly distributed at the working frequency point according to a predetermined rule. In this step, multiple operating frequency points can be set for the computing chip through multiple phase-locked loop circuits 70 shown in FIG. 2. Of course, this step can also be used to set multiple operating frequency points for the computing chip through other hardware or software.
  • the frequency difference between the operating frequency points in the present invention needs to be controlled within a reasonable range. Because when the kernel 80 increases a working frequency point, the operating frequency of the kernel will increase a frequency difference value, which can improve certain computing performance due to the increase of the computing speed. At the same time, increasing the operating frequency of the kernel may result in a loss of computing performance due to a reduction in the accuracy of the calculation. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies, so that when the kernel 80 is adjusted from the current operating frequency to the previous operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss. Preferably, the frequency difference between adjacent operating frequency points is 1 to 10%.
  • Step S1402 Analyze the calculation performance index of each core 80 at the current operating frequency.
  • the calculation performance indicator represents the actual calculation performance of the kernel 80 at the current operating frequency, including but not limited to the calculation accuracy rate, the calculation accuracy number, the calculation speed, and the like. If the calculation performance index of the kernel 80 is high, it indicates that there may be room for improvement in the calculation performance of the kernel 80; if the calculation performance index of the kernel 80 is low, it indicates that the calculation performance of the kernel 80 may not be sufficient for the current work Work at the frequency corresponding to the frequency point.
  • step S1403 the current operating frequency of the core 80 is adjusted up or down according to the calculation performance index of the core 80.
  • the kernel 80 is adjusted to an appropriate operating frequency according to the actual calculation performance of the kernel 80, the frequency of the core 80 with high calculation performance is raised, and the frequency of the core 80 with low calculation performance is adjusted down. Thereby, the computing performance of each core 80 is fully utilized.
  • the core 80 can be frequency-modulated by the phase-locked loop circuit 70 or software shown in FIG. 2.
  • the calculation accuracy rate of the kernel 80 within the adjustment period reaches the first accuracy rate threshold, it indicates that the kernel 80 has not yet reached the optimal calculation performance, so the current operating frequency of the kernel 80 is raised to the previous operating frequency; If the calculation accuracy rate of the kernel 80 within the adjustment period does not reach the second accuracy rate threshold, it indicates that the calculation performance of the kernel 80 is insufficient to work at the current operating frequency, so the current operating frequency of the kernel 80 is adjusted to the next operation. Frequency.
  • the last working frequency is not limited to the last adjacent working frequency, and more than one last adjacent working frequency can be set as the previous working frequency; the next working frequency It is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency may be set as the next operating frequency.
  • the frequency difference between the current working frequency point and the previous working frequency point is 1 to 10%, and the frequency difference between the current working frequency point and the next working frequency point is 1 to 10%, so that the kernel 80 moves from the current When the operating frequency is adjusted to the previous operating frequency or the next operating frequency, the benefit of the computing performance of the kernel 80 should be greater than the loss.
  • the current operating frequency of the core 80 is increased from 600 MHz to the previous operating frequency of 700 MHz; the current operating frequency of the core 80 is reduced to 600 MHz to the next operating frequency of 500 MHz.
  • the previous working frequency point and the spacing between the next working frequency point are not limited here.
  • step S1404 the current distribution status of the frequency-modulated kernel 80 at each operating frequency is counted.
  • the working frequency of the core 80 After the working frequency of the core 80 is automatically tuned according to its own computing performance, it will be distributed to work at each working frequency.
  • the current distribution status can be obtained by counting the number of distributions of the tuned core 80 at each working frequency.
  • the operating frequency can be divided into at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency.
  • the highest frequency among the high-frequency operating frequencies is the highest operating frequency
  • the low-frequency The lowest operating frequency is the lowest operating frequency.
  • the numbers of the six operating frequency points are: 100, 200, 100, 100. , 200, 300. Among them, 500MHz, 550MHz is the low-frequency operating frequency, 600MHz, 650MHz is the intermediate operating frequency, 700MHz, 750MHz is the high-frequency operating frequency, 500MHz is the lowest operating frequency, and 750MHz
  • step S1405 the frequency of the set operating frequency is adjusted according to the current distribution state and a predetermined frequency adjustment mechanism.
  • the frequency adjustment mechanism is a correspondence between the distribution status of the kernel 80 and the frequency adjustment.
  • the frequency adjustment mechanism is a correspondence between a kernel distribution state and a frequency adjustment.
  • the kernel distribution state refers to a distribution state in which the kernel 80 operates at various operating frequencies.
  • the adjusting and setting the frequency of the working frequency point refers to directly adjusting the frequency of the working frequency point.
  • the frequency of setting the operating frequency is preferably adjusted by the phase-locked loop circuit 70 shown in FIG. 2.
  • the ideal state of the present invention is that it is desired to exceed a predetermined ratio (e.g., 50%) or the maximum number of cores 80 to fall to the intermediate operating frequency, so that the frequency of the cores 80 has more room for upward adjustment.
  • a core 80 exceeding a predetermined ratio (such as 30%) operates at the highest operating frequency (750MHz), it may result in the core 80 not exhibiting the maximum computing performance (because it may be higher).
  • the operating frequency (600MHz) is modified to be set to at least one optimized high-frequency operating frequency (800MHz), and the core 80 originally operating at the operating frequency (600MHz) will all be transferred to the highest operating frequency (750MHz) to work.
  • the frequency of the optimized high-frequency operating frequency is higher than the frequency of the highest operating frequency, so as to give full play to the computing performance of each core 80.
  • the method may further include:
  • the core 80 exceeding the predetermined fourth ratio operates on at least one intermediate operating frequency, stop adjusting the frequency of setting the operating frequency; or, if the number of cores 80 operating on at least one intermediate operating frequency is the largest, stop Adjust the frequency of the set operating frequency.
  • the ideal state is that the core 80 that exceeds the predetermined fourth ratio (such as 50%) or the largest number falls on one or more intermediate operating frequencies, such as the third operating frequency (600MHz), so it is not necessary to correct the The core 80 performs frequency modulation.
  • FIG. 15 is one of the flowcharts of a preferred chip frequency modulation method of a computing device in a fourth embodiment of the present invention, which can be implemented by the chip frequency modulation device 100 of the computing device, where the computing device includes at least one computing chip, and the computing The chip has multiple cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies. The method includes the steps of:
  • step S1501 a plurality of operating frequency points are set for the computing chip of the computing device, and the multiple cores 80 in the computing chip are respectively operated at each operating frequency point.
  • step S1502 the calculation performance index of each core 80 at the current operating frequency is analyzed.
  • step S1503 the current operating frequency of the core 80 is adjusted up or down according to the calculation performance index of the core 80.
  • step S1504 the current distribution state of the frequency-modulated kernel 80 at each operating frequency point is counted.
  • the operating frequency includes at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency.
  • the highest frequency among the high-frequency operating frequencies is the highest operating frequency, and the lowest frequency among the low-frequency operating frequencies is Minimum operating frequency.
  • step S1505 if the core 80 exceeding the predetermined second ratio operates on at least one high-frequency operating frequency, it may result in the core 80 not exerting the maximum computing performance (because it may be higher), and the at least one operating frequency will be reduced. Modify the setting to at least one optimized high frequency operating frequency, and the frequency of the optimized high frequency operating frequency is higher than the frequency of the highest operating frequency.
  • the modified operating frequency can be a low frequency operating frequency, an intermediate frequency operating frequency and / or a high frequency operating frequency.
  • a working frequency is modified to be an optimized high-frequency operating frequency, and the frequency of the optimized high-frequency operating frequency is higher than the highest operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the core 80 works at the highest operating frequency (750MHz), modify a low-frequency operating frequency (500MHz) to optimize the high-frequency operating frequency (800MHz), or set an intermediate frequency Modify the operating frequency (600MHz) to optimize the high-frequency operating frequency (800MHz); or modify the highest operating frequency (750MHz) to optimize the high-frequency operating frequency (800MHz).
  • step S1506 if the core 80 exceeding the predetermined third ratio operates on at least one low-frequency operating frequency, it indicates that the computing power of the core 80 is insufficient to operate on the low-frequency operating frequency, and therefore at least one operation will be performed.
  • the frequency modification is set to at least one optimized low frequency operating frequency, and the frequency of the optimized low frequency operating frequency is lower than the frequency of the lowest operating frequency. It is worth noting that this step can be omitted, that is, the at least one operating frequency point is not modified to be set to at least one optimized low-frequency operating frequency point.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency. For example, if 6 operating frequencies are set, 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, 750MHz, more than 30% (third ratio) of the core 80 works at two low frequency operating frequencies (500MHz and 550MHz), then two Modify the low frequency operating frequency (500MHz and 550MHz) to two optimized low frequency operating frequencies (400MHz and 450MHz), or modify one low frequency operating frequency (500MHz) and one intermediate frequency operating frequency (600MHz) to two optimizations Low frequency (400MHz and 450MHz).
  • a working frequency is modified and set to an optimized low-frequency operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the core 80 works at the lowest operating frequency (500MHz)
  • set an intermediate-frequency operation Modify the frequency (600MHz) to optimize the low-frequency operating frequency (450MHz); or modify the highest operating frequency (750MHz) to optimize the low-frequency operating frequency (450MHz).
  • the method further includes:
  • the core 80 exceeding the predetermined fourth ratio operates on at least one intermediate operating frequency, stop adjusting the frequency of setting the operating frequency; because the ideal state is that the core 80 exceeding the predetermined fourth ratio (for example, 50%) falls on At one or more intermediate operating frequency points, such as the third operating frequency point (600 MHz), it can give full play to the operating performance of the core 80, so it is not necessary to tune the core 80 at this time. or
  • the number of cores 80 operating at at least one intermediate operating frequency is the largest, stop adjusting the frequency of setting the operating frequency. Because the ideal state is that the maximum number of cores 80 falls on one or more intermediate operating frequency points, such as the third operating frequency (600MHz), which can give full play to the operating performance of the core 80, so there is no need to 80 for frequency modulation.
  • the third operating frequency 600MHz
  • phase-locked loop circuits 70 are used, and six operating frequency points are set: 500 MHz, 550 MHz, 600 MHz, 650 MHz, 700 MHz, and 750 MHz.
  • the number of cores distributed on the corresponding frequencies according to the 4 hash boards is as follows:
  • Hashboard 0 [294, 26, 224, 1023, 1665]
  • Hashboard 1 [274, 47, 111, 212, 963, 1721]
  • Hashboard 2 [350, 25, 153, 369, 1381, 1050]
  • Hashboard 3 [488, 33, 184, 367, 1342, 950]
  • the data roughly conforms to the normal distribution, and the minimum operating frequency (500Mhz) is the lowest frequency at which a single core 80 works, and it cannot be adjusted downwards (if the error Rate is too high, you can consider turning off the lowest frequency); while the highest operating frequency (750Mhz) accumulates a core 80 that exceeds a predetermined ratio (for example, 50%), it means that the maximum efficiency is not exerted (because it may be higher) There is still room for further improvement in the entire computing chip.
  • a predetermined ratio such as 50%
  • the maximum number of cores 80 falls on one or more intermediate operating frequencies, such as the third operating frequency (600 MHz).
  • the long tail on the high-capacity side should be considered rather than the long tail on the low-frequency point.
  • FIG. 16 is a second flowchart of a preferred chip frequency modulation method of a computing device in a fourth embodiment of the present invention, which can be implemented by the chip frequency modulation device 100 of the computing device, where the computing device includes at least one computing chip, and the computing The chip has multiple cores.
  • the computing device is preferably used for massive operations, such as operations for mining virtual digital currencies. The method includes the steps of:
  • step S1601 multiple operating frequency points are set for the computing chip of the computing device, and the multiple cores 80 in the computing chip are respectively operated at each operating frequency point.
  • step S1602 the calculation performance index of each core 80 at the current operating frequency is analyzed.
  • step S1603 the current operating frequency of the core 80 is adjusted up or down according to the calculation performance index of the core 80.
  • step S1604 the current distribution status of the frequency-modulated kernel 80 at each operating frequency is counted.
  • the operating frequency includes at least one high-frequency operating frequency, at least one intermediate operating frequency, and at least one low-frequency operating frequency.
  • the highest frequency among the high-frequency operating frequencies is the highest operating frequency, and the lowest frequency among the low-frequency operating frequencies is Minimum operating frequency.
  • step S1605 if the number of cores 80 operating at least one high-frequency operating frequency is the largest, the core 80 may not perform the maximum computing performance (because it may be higher). Therefore, at least one operating frequency is modified and set to At least one optimized high-frequency operating frequency point, the frequency of the optimized high-frequency operating frequency point is higher than the frequency of the highest operating frequency point.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the maximum number of cores 80 will work at two high-frequency operating frequencies (700MHz and 750MHz), then two low-frequency operating frequencies ( 500MHz and 550MHz) to two optimized high-frequency operating frequencies (800MHz and 850MHz), or one low-frequency operating frequency (500MHz) and one intermediate-frequency operating frequency (600MHz) to two optimized high-frequency operating frequencies Points (800MHz and 850MHz).
  • one operating frequency is modified and set to an optimized high-frequency operating frequency.
  • the modified operating frequency can be a low frequency operating frequency, an intermediate frequency operating frequency and / or a high frequency operating frequency.
  • a low-frequency operating frequency 500MHz is modified to optimize the high-frequency operating frequency (800MHz), or an intermediate-frequency operating frequency (600MHz) Modify the setting to optimize the high-frequency operating frequency (800MHz); or set the highest operating frequency (750MHz) to optimize the high-frequency operating frequency (800MHz).
  • step S1606 if the number of the cores 80 operating at least one low-frequency operating frequency is the largest, it indicates that the computing power of the core 80 is too poor to work at the low-frequency operating frequency. Therefore, the setting of at least one operating frequency is modified. For at least one optimization of the low-frequency operating frequency, the frequency of the low-frequency operating frequency is optimized to be lower than the frequency of the lowest operating frequency, so as to avoid the core 80 with poor computing ability from affecting the overall computing performance of the computing chip. This step can be omitted, that is, the at least one operating frequency point is not modified to be set to at least one optimized low-frequency operating frequency point.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency.
  • the most cores 80 work at two low frequency working frequencies (500MHz and 550MHz), then two low frequency working frequencies (500MHz And 550MHz) to two optimized low-frequency operating frequencies (400MHz and 450MHz), or one low-frequency operating frequency (500MHz) and one intermediate-frequency operating frequency (600MHz) to two optimized low-frequency operating frequencies (400MHz) And 450MHz).
  • one operating frequency is modified to be an optimized low-frequency operating frequency.
  • the modified operating frequency may be a low-frequency operating frequency, an intermediate-frequency operating frequency, and / or a high-frequency operating frequency. For example, if the largest number of cores 80 work at the lowest operating frequency (500MHz), then modify a low-frequency operating frequency (500MHz) to optimize the low-frequency operating frequency (450MHz), or modify an intermediate-frequency operating frequency (600MHz). Set it to optimize the low frequency operating frequency (450MHz); or modify the highest working frequency (750MHz) to optimize the low frequency operating frequency (450MHz).
  • step S1606 the method further includes:
  • phase-locked loop circuits 70 are used, and six operating frequency points are set: 500 MHz, 550 MHz, 600 MHz, 650 MHz, 700 MHz, and 750 MHz.
  • the number of cores distributed on the corresponding frequencies according to the 4 hash boards is as follows:
  • Hashboard 0 [294, 26, 224, 1023, 1665]
  • Hashboard 1 [274, 47, 111, 212, 963, 1721]
  • Hashboard 2 [350, 25, 153, 369, 1381, 1050]
  • Hashboard 3 [488, 33, 184, 367, 1342, 950]
  • the data roughly conforms to the normal distribution, and the minimum operating frequency (500Mhz) is the lowest frequency at which a single core 80 works, and it cannot be adjusted downwards (if the error Rate is too high, you can consider turning off the lowest frequency); while the maximum number of cores 80 accumulated at the highest operating frequency (750Mhz) means that the maximum efficiency has not been exerted (because it may be higher), the entire computing chip is also There is room for further improvement.
  • a more ideal state is that a predetermined ratio (such as 50%) or the maximum number of cores 80 falls on one or more intermediate operating frequencies, such as the third operating frequency (600 MHz).
  • the long tail on the high-capacity side should be considered rather than the long tail on the low-frequency point.
  • the present invention also provides a storage medium for storing a computer program of a chip frequency modulation method of any computing device as shown in FIG. 8 to FIG. 16.
  • a computer program instruction when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer.
  • the program instructions that call the method of the present application may be stored in a fixed or removable storage medium, and / or transmitted via a data stream in a broadcast or other signal bearing medium, and / or stored in accordance with the program instructions In the memory of a running computing device.
  • an embodiment according to the present application includes a computing device as shown in FIG. 17.
  • the computing device preferably includes a control board and at least one computing board connected to the control board, and the control board is provided with a process.
  • a plurality of computing chips for computing are provided on the computing board, and a plurality of cores are arranged in the computing chips;
  • the device includes a storage medium for storing computer program instructions and a process for executing program instructions A processor, wherein when the computer program instructions are executed by the processor, the computing device is triggered to execute a method and / or a technical solution based on the foregoing multiple embodiments.
  • this application may be implemented in software and / or a combination of software and hardware, for example, it may be implemented using an application specific integrated circuit (ASIC), a general purpose computer, or any other similar hardware device.
  • ASIC application specific integrated circuit
  • the software program of the present application may be executed by a processor to implement the above steps or functions.
  • the software program (including related data structures) of the present application can be stored in a computer-readable recording medium, such as a RAM memory, a magnetic or optical drive or a floppy disk and the like.
  • some steps or functions of this application may be implemented by hardware, for example, as a circuit that cooperates with a processor to perform each step or function.
  • the method according to the present invention can be implemented on a computer as a computer-implemented method, or in dedicated hardware, or in a combination of the two.
  • the executable code or parts thereof for use in the method according to the invention may be stored on a computer program product.
  • Examples of computer program products include memory devices, optical storage devices, integrated circuits, servers, online software, and the like.
  • the computer program product comprises non-transitory program code components stored on a computer-readable medium for performing the method according to the invention when said program product is executed on a computer.
  • the computer program comprises computer program code means adapted to perform all the steps of the method according to the invention when the computer program is run on a computer.
  • the computer program is embodied on a computer-readable medium.
  • the present invention automatically adjusts the frequency of the core of the computing chip of the computing device.
  • a plurality of suitable operating frequency points are set, and the multiple cores in the computing chip are respectively operated at different operating frequency points.
  • the calculation performance index of each kernel at the current operating frequency point is to increase or decrease the current operating frequency point of the kernel, that is, to increase the frequency of the core with high computing performance and to reduce the frequency of the core with low computing performance. Therefore, the present invention can automatically adjust the frequency corresponding to each core according to the actual computing performance of each core in the computing chip of the computing device, so as to maximize the computing performance of the core and further improve the computing performance of the computing chip and the overall computing device.
  • the chip frequency modulation method, device, computing board, computing device and storage medium of the computing device of the present invention have the following beneficial effects:

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Abstract

本发明提供了一种计算设备的芯片调频方法、装置、算力板、计算设备及存储介质。所述计算设备设置有至少一运算芯片，所述运算芯片设置有多个内核。所述芯片调频方法包括有：为所述计算设备的运算芯片设置多个工作频点，将所述运算芯片中的多个内核分别工作于各所述工作频点；分析每个所述内核在当前工作频点的计算性能指标；根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调，即上调计算性能高的内核的频率，下调计算性能低的内核的频率。借此，本发明能够根据计算设备的运算芯片中各个内核的实际计算性能，自动调节各个内核对应的频率，从而最大程度发挥内核的计算性能，进而提高运算芯片及整体运算设备的运算性能。

Description

计算设备的芯片调频方法、装置、算力板、计算设备及存储介质 技术领域
本发明涉及计算设备的芯片调频技术领域，尤其涉及一种计算设备的芯片调频方法、装置、算力板、计算设备及存储介质。
背景技术
用于海量数据运算的计算设备中，通常集成了大量运算芯片，由于运算芯片制造工艺的限制，不同运算芯片的工作性能、算力、频率不尽相同；同时，单颗运算芯片也通常由多个相互独立的内核(Core)组成，运算芯片内不同位置工艺偏差、压降等差异也使得各个内核的实际工作性能不尽相同。针对不同运算芯片及其内核的工作性能差异，如何动态调节运算芯片实际所需频率并设定各个内核的自适应方案，为亟待解决的问题。现有计算设备中为每颗运算芯片及其内核提供的频率一致，无法发挥性能较优的内核的计算优势，性能较弱内核影响运算芯片的运算性能，进而影响整体计算设备的运算性能。
另外，中国专利申请CN201611169618.6公开了一种串联供电芯片、系统、虚拟数字挖矿机及服务器，包括调整电路，分别与各串联供电芯片连接，对各串联供电芯片进行电压、温度或频率调整。所述调整单元对各串联供电芯片进行频率调整时，分别针对各串联供电芯片，按照预设周期检测串联供电芯片中各待供电单元的工作状态是否正常；若有待供电单元的工作状态不正常，在预设频率范围内按照预设频率步长提高或降低工作状态不正常的待供电单元的工作频率。根据待供电单元的状态寄存器指示的状态判断待供电单元的工作状态是否正常，所述状态寄存器指示的状态包括：电压状态、温度状态、工作频率状态；或者根据待供电单元对发送给该待供电单元的数据的反馈数据，判断待供电单元的工作状态是否正常。
中国专利申请CN201611169618.6公开的一个实施例中，调整电路对各串联供电芯片进行频率调整时，作为频率调整电路，具体可以通过一个检测器，分别针对各串联供电芯片，按照预设周期检测串联供电芯片中各待供电单元的工作状态是否正常；若有待供电单元的工作状态不正常，具体可以通过一个调节器，在预设频率范围内按照预设频率步长提高或降低工作状态不正常的待供 电单元的工作频率。可见，CN201611169618.6公开了调节器可以对芯片进行频率调整，但其仅仅是根据待供电单元的是否正常收发数据、电压状态、温度状态、频率状态等工作状态来调整芯片的工作频率，频率调整机制缺乏准确性，并不能充分发挥芯片的运算性能。
综上可知，现有技术在实际使用上显然存在不便与缺陷，所以有必要加以改进。
发明公开
针对上述的缺陷，本发明的目的在于提供一种计算设备的芯片调频方法、装置、算力板、计算设备及存储介质，其能够根据计算设备的运算芯片中各个内核的实际计算性能，自动调节各个内核对应的频率，从而最大程度发挥内核的计算性能，进而提高运算芯片及整体运算设备的运算性能。
本发明提供一种计算设备的芯片调频方法，所述计算设备设置有至少一运算芯片，所述运算芯片设置有多个内核，包括步骤有：
为所述计算设备的所述运算芯片设置多个工作频点，将所述运算芯片中的多个内核分别工作于各所述工作频点；
分析每个所述内核在当前工作频点的计算性能指标；
根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调。
根据本发明所述的芯片调频方法，所述为所述计算设备的所述运算芯片设置多个所述工作频点，将所述运算芯片中的多个所述内核分别工作于各所述工作频点的步骤还包括：
通过多个锁相环电路为所述运算芯片设置多个所述工作频点，所述工作频点与所述锁相环电路为一一对应关系；
所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
根据所述内核的所述计算性能指标，通过所述锁相环电路对所述内核的所述当前工作频点进行上调或下调。
根据本发明所述的芯片调频方法，所述锁相环电路设置于所述运算芯片的内部或外部。
根据本发明所述的芯片调频方法，相邻的所述工作频点之间的频差为1～10％。
根据本发明所述的芯片调频方法，所述分析每个所述内核在所述当前工作频点的所述计算性能指标的步骤还包括：
在预定的调整周期内，分析所述内核的所述计算性能指标是否达到预定的第一指标阈值、第二指标阈值和/或第三指标阈值，所述第一指标阈值与所述第二指标阈值相同或者不相同；
所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
若所述内核的所述计算性能指标达到所述第一指标阈值，将所述内核的所述当前工作频点上调到上一个工作频点；
若所述内核的所述计算性能指标未达到所述第二指标阈值，将所述内核的所述当前工作频点下调到下一个工作频点；和/或
若所述内核的所述计算性能指标达到所述第三指标阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
根据本发明所述的芯片调频方法，还包括步骤有：
若工作于预定的至少一个优化工作频点的所述内核超过预定的第一比率，停止对所述内核进行调频；或者
若工作于至少一所述优化工作频点上的所述内核的数目最多，停止对所述内核进行调频。
根据本发明所述的芯片调频方法，所述分析每个所述内核在所述当前工作频点的所述计算性能指标的步骤还包括：
在预定的调整周期内，分析所述内核的所述计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值，所述第一正确率阈值与所述第二正确率阈值相同或者不相同；
所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
若所述内核的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；和/或
若所述内核的所述计算正确率未达到所述第二正确率阈值，将所述内核的 所述当前工作频点下调到下一个工作频点。
根据本发明所述的芯片调频方法，所述在预定的调整周期内，分析所述内核的所述计算正确率是否达到所述第一正确率阈值和/或第二正确率阈值的步骤还包括：
在所述调整周期内，分析所述内核提交的随机数是否正确；
统计所述内核在所述调整周期内提交的正确随机数的个数和错误随机数的个数；
根据所述正确随机数的个数和所述错误随机数的个数，计算出所述内核在所述调整周期内的随机数计算正确率，并判断所述随机数计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值；
所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
若所述内核的所述随机数计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；和/或
若所述内核的所述随机数计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
根据本发明所述的芯片调频方法，所述在所述调整周期内，分析所述内核提交的所述随机数是否正确的步骤还包括：
在所述调整周期内，所述内核每递交一个所述随机数后，所述内核将所述随机数通过预定的算法计算出第一结果，所述第一结果中包含有第一特征；
所述运算芯片的验算单元将所述随机数通过相同的所述算法计算出第二结果，所述第二结果中包含有第二特征；
若所述第一特征与所述第二特征相同，则所述验算单元判定所述随机数是正确随机数，否则判定所述随机数是错误随机数。
根据本发明所述的芯片调频方法，所述在预定的所述调整周期内，分析所述内核的所述计算正确率是否达到预定的所述正确率阈值的步骤还包括：
根据预设的实时调整指令，实时分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；
根据预设的定时调整指令，在所述定时调整指令设定的调整时间段内，分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈 值与所述第二正确率阈值；或者
根据接收的即时调整指令，分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；
所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，实时将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，实时将所述内核的所述当前工作频点下调到下一个工作频点；
在所述调整时间段内，若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；在所述调整时间段内，若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点；或者
根据接收的即时调整指令，若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点；根据接收的停止调整指令，停止对所述内核的所述当前工作频点的调整。
根据本发明所述的芯片调频方法，所述分析每个所述内核在所述当前工作频点的所述计算性能指标的步骤还包括：
预先设置所述内核的参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和计算错误阈值；
分析所述内核的每次计算是否正确；
所述内核每正确计算至少一次，在所述参考节点值上增加一次所述计算正确权重值，并且所述内核每错误计算至少一次，在所述参考节点值上减少一次所述计算错误权重值；
判断所述内核的当前参考节点值是否达到所述计算正确阈值或所述计算错误阈值；
所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点 进行上调或下调的步骤还包括：
若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；
若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
根据本发明所述的芯片调频方法，所述分析所述内核的每次计算是否正确的步骤还包括：
分析所述内核每次提交的随机数是否正确；
所述内核每正确计算至少一次，在所述参考节点值上增加一次所述计算正确权重值，并且所述内核每错误计算至少一次，在所述参考节点值上增加一次所述计算错误权重值的步骤还包括：
所述内核每提交至少一次正确随机数，在所述参考节点值上增加一次所述计算正确权重值，所述内核每提交至少一次错误随机数，在所述参考节点值上减少一次所述计算错误权重值。
根据本发明所述的芯片调频方法，所述分析所述内核每次提交的所述随机数是否正确的步骤还包括：
所述内核递交一个所述随机数后，所述内核将所述随机数通过预定的算法计算出第一结果，所述第一结果中包含有第一特征；
所述运算芯片的验算单元将所述随机数通过相同的所述算法计算出第二结果，所述第二结果中包含有第二特征；
若所述第一特征与所述第二特征相同，则所述验算单元判定所述随机数是正确随机数，否则判定所述随机数是错误随机数。
根据本发明所述的芯片调频方法，所述方法还包括：
根据实际需求设置和调整所述内核的所述参考节点值、所述计算正确权重值、所述计算错误权重值、所述计算正确阈值和/或所述计算错误阈值，所述计算正确权重值和所述计算错误权重值相同或者不相同，所述计算正确阈值和所述计算错误阈值相同或者不相同；
通过控制所述计算正确权重值和所述计算错误权重值的比值控制所述内核期望容忍的驻留差错率；
通过控制所述计算正确权重值和所述计算错误权重值的绝对值大小控制 调整周期；
通过控制所述计算正确阈值和所述计算错误阈值的绝对值大小控制所述调整周期。
根据本发明所述的芯片调频方法，所述驻留差错率的计算公式为：驻留差错率＝计算正确权重值/(计算正确权重值+计算错误权重值)。
根据本发明所述的芯片调频方法，所述判断所述内核的当前参考节点值是否达到所述计算正确阈值或所述计算错误阈值的步骤还包括：
根据预设的实时调整指令，实时判断所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；
根据预设的定时调整指令，在所述定时调整指令设定的调整时间段内，判断所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；或者
根据接收的即时调整指令，分析所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；
所述根据所述内核的所述计算性能指标，将所述内核的所述当前工作频点进行上调或下调的步骤还包括：
若所述内核的所述当前参考节点值达到所述计算正确阈值，实时将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核的所述当前参考节点值达到所述计算错误阈值，实时将所述内核的所述当前工作频点下调到下一个工作频点；
在所述调整时间段内，若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；在所述调整时间段内，若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点；或者
根据接收的即时调整指令，若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点；根据接收的停止调整指令，停止对所述内核的所述当前工作频点的调整。
根据本发明所述的芯片调频方法，所述根据所述内核的所述计算性能指 标，对所述内核的所述当前工作频点进行上调或下调的步骤之后还包括：
统计被调频后的所述内核在各所述工作频点上的当前分布状态；
根据所述内核的所述当前分布状态和预定的频点调整机制，调整设置所述工作频点的频率，所述频点调整机制是内核分布状态与频点调整的对应关系。
根据本发明所述的芯片调频方法，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，所述高频工作频点中频率最高的是最高工作频点，所述低频工作频点中频率最低的是最低工作频点；
所述根据所述当前分布状态和所述频点调整机制，调整设置所述工作频点的频率的步骤还包括：
若超过预定的第二比率的所述内核工作于至少一所述高频工作频点上，将至少一所述工作频点修改设置为至少一优化高频工作频点，所述优化高频工作频点的频率高于所述最高工作频点的频率；和/或
若超过预定的第三比率的所述内核工作于至少一所述低频工作频点上，将至少一所述工作频点修改设置为至少一优化低频工作频点，所述优化低频工作频点的频率低于所述最低工作频点的频率。
根据本发明所述的芯片调频方法，所述若超过所述第二比率的所述内核工作于至少一所述高频工作频点上，将至少一所述工作频点修改设置为至少一所述优化高频工作频点的步骤还包括：
若超过所述第二比率的所述内核工作于所述最高工作频点上，将一个所述工作频点修改设置为一个所述优化高频工作频点；和/或
所述若超过预定的所述第三比率的所述内核工作于至少一所述低频工作频点上，将至少一所述工作频点修改设置为至少一所述优化低频工作频点的步骤还包括：
若超过所述第三比率的所述内核工作于所述最低工作频点上，将一个所述工作频点修改设置为一个所述优化低频工作频点。
根据本发明所述的芯片调频方法，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，所述高频工作频点中频率最高的是最高工作频点，所述低频工作频点中频率最低的是最低工作频点；
所述根据所述当前分布状态和所述频点调整机制，调整设置所述工作频点的频率的步骤还包括：
若工作于至少一所述高频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一优化高频工作频点，所述优化高频工作频点的频率高于所述最高工作频点的频率；和/或
若工作于至少一所述低频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一优化低频工作频点，所述优化低频工作频点的频率低于所述最低工作频点的频率。
根据本发明所述的芯片调频方法，所述若工作于至少一所述高频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一所述优化高频工作频点的步骤还包括：
若工作于所述最高工作频点上的所述内核的数目最多，将一个所述工作频点修改设置为一个所述优化高频工作频点；和/或
所述若工作于至少一所述低频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一所述优化低频工作频点的步骤还包括：
若工作于所述最低工作频点的所述内核的数目最多，将一个所述工作频点修改设置为一个所述优化低频工作频点。
根据本发明所述的芯片调频方法，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点；
所述根据所述当前分布状态和所述频点调整机制，调整设置所述工作频点的频率的步骤还包括：
若超过预定的第四比率的所述内核工作于至少一所述中间工作频点上，停止调整设置所述工作频点的频率；或者
若工作于在至少一所述中间工作频点上的所述内核的数目最多，停止调整设置所述工作频点的频率。
根据本发明所述的芯片调频方法，所述计算设备用于挖掘虚拟数字货币的运算。
本发明还提供一种计算设备的芯片调频装置，所述算力板上设置有至少一个运算芯片，所述运算芯片中设置有多个内核，所述芯片调频装置包括：
频点设置模块，用于为所述计算设备的运算芯片设置多个工作频点，将所述运算芯片中的多个内核分别工作于各所述工作频点；
计算性能分析模块，用于分析每个所述内核在当前工作频点的计算性能指 标；
频率调整模块，用于根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调。
根据本发明所述的芯片调频装置，所述频点设置模块用于通过多个锁相环电路为所述运算芯片设置多个所述工作频点，所述工作频点与所述锁相环电路为一一对应关系；
所述频率调整模块，用于根据所述内核的所述计算性能指标，通过所述锁相环电路对所述内核的所述当前工作频点进行上调或下调。
根据本发明所述的芯片调频装置，所述锁相环电路设置于所述运算芯片的内部或外部。
根据本发明所述的芯片调频装置，相邻的所述工作频点之间的频差为1～10％。
根据本发明所述的芯片调频装置，所述计算性能分析模块用于在预定的调整周期内，分析所述内核的所述计算性能指标是否达到预定的第一指标阈值、第二指标阈值和/或第三指标阈值，所述第一指标阈值与所述第二指标阈值相同或者不相同；
所述频率调整模块用于若所述内核的所述计算性能指标达到所述第一指标阈值，将所述内核的所述当前工作频点上调到上一个工作频点；
所述频率调整模块用于若所述内核的所述计算性能指标未达到所述第二指标阈值，将所述内核的所述当前工作频点下调到下一个工作频点；和/或
所述频率调整模块用于若所述内核的所述计算性能指标达到所述第三指标阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
根据本发明所述的芯片调频装置，所述频率调整模块还包括有：
频率调整子模块，用于根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调。
停止频率调整子模块，用于若工作于预定的至少一个优化工作频点的所述内核超过预定的第一比率，停止对所述内核进行调频；或者用于若工作于至少一所述优化工作频点上的所述内核的数目最多，停止对所述内核进行调频。
根据本发明所述的芯片调频装置，所述计算性能分析模块用于在预定的调整周期内，分析所述内核的所述计算正确率是否达到预定的第一正确率阈值和 /或第二正确率阈值，所述第一正确率阈值与所述第二正确率阈值相同或者不相同；
所述频率调整模块用于若所述内核的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；和/或用于若所述内核的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
根据本发明所述的芯片调频装置，所述计算性能分析模块进一步包括有：
第一分析子模块，用于在所述调整周期内，分析所述内核提交的随机数是否正确；
统计子模块，用于统计所述内核在所述调整周期内提交的正确随机数的个数和错误随机数的个数；
第一判断子模块，用于根据所述正确随机数的个数和所述错误随机数的个数，计算出所述内核在所述调整周期内的随机数计算正确率，并判断所述随机数计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值；
所述频率调整模块用于若所述内核的所述随机数计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；和/或用于若所述内核的所述随机数计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
根据本发明所述的芯片调频装置，所述第一分析子模块进一步包括：
第一计算单元，用于在所述调整周期内，所述内核每递交一个所述随机数后，将所述随机数通过预定的算法计算出第一结果，所述第一结果中包含有第一特征，所述第一计算单元设置于所述内核中；
第一验算单元，用于将所述随机数通过相同的所述算法计算出第二结果，所述第二结果中包含有第二特征，若所述第一特征与所述第二特征相同，则判定所述随机数是正确随机数，否则判定所述随机数是错误随机数；所述第一验算单元设置于所述运算芯片中。
根据本发明所述的芯片调频装置，所述计算性能分析模块用于根据预设的实时调整指令，实时分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；
所述计算性能分析模块用于根据预设的定时调整指令，在所述定时调整指 令设定的调整时间段内，分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；或者
所述计算性能分析模块用于根据接收的即时调整指令，分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；
所述频率调整模块用于若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，实时将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，实时将所述内核的所述当前工作频点下调到下一个工作频点；
所述频率调整模块用于在所述调整时间段内，若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；在所述调整时间段内，若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点；或者
所述频率调整模块用于根据接收的即时调整指令，若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点；根据接收的停止调整指令，停止对所述内核的所述当前工作频点的调整。
根据本发明所述的芯片调频装置，所述计算性能分析模块进一步包括有：
设置子模块，用于预先设置所述内核的参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和计算错误阈值；
第二分析子模块，用于分析所述内核的每次计算是否正确；
计数子模块，用于所述内核每正确计算至少一次，在所述参考节点值上增加一次所述计算正确权重值，并且所述内核每错误计算至少一次，在所述参考节点值上减少一次所述计算错误权重值；
第二判断子模块，用于判断所述内核的当前参考节点值是否达到所述计算正确阈值或所述计算错误阈值；
所述频率调整模块用于若所述内核的所述当前参考节点值达到所述计算 正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；以及用于若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
根据本发明所述的芯片调频装置，所述第二分析子模块用于分析所述内核每次提交的随机数是否正确；
所述计数子模块用于在所述内核每提交至少一次正确随机数，在所述参考节点值上增加一次所述计算正确权重值，所述内核每提交至少一次错误随机数，在所述参考节点值上减少一次所述计算错误权重值。
根据本发明所述的芯片调频装置，所述第二分析子模块进一步包括：
第二计算单元，用于所述内核递交一个所述随机数后，所述内核将所述随机数通过预定的算法计算出第一结果，所述第一结果中包含有第一特征；
第二验算单元，用于将所述随机数通过相同的所述算法计算出第二结果，所述第二结果中包含有第二特征；若所述第一特征与所述第二特征相同，则判定所述随机数是正确随机数，否则判定所述随机数是错误随机数。
根据本发明所述的芯片调频装置，所述设置子模块用于根据实际需求设置和调整所述内核的所述参考节点值、所述计算正确权重值、所述计算错误权重值、所述计算正确阈值和/或所述计算错误阈值，所述计算正确权重值和所述计算错误权重值相同或者不相同，所述计算正确阈值和所述计算错误阈值相同或者不相同；
所述设置子模块用于通过控制所述计算正确权重值和所述计算错误权重值的比值控制所述内核期望容忍的驻留差错率；
所述设置子模块用于通过控制所述计算正确权重值和所述计算错误权重值的绝对值大小控制调整周期；
所述设置子模块用于通过控制所述计算正确阈值和所述计算错误阈值的绝对值大小控制所述调整周期。
根据本发明所述的芯片调频装置，所述驻留差错率的计算公式为：驻留差错率＝计算正确权重值/(计算正确权重值+计算错误权重值)。
根据本发明所述的芯片调频装置，所述计算性能分析模块用于根据预设的实时调整指令，实时判断所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；
所述计算性能分析模块用于根据预设的定时调整指令，在所述定时调整指令设定的调整时间段内，判断所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；或者
所述计算性能分析模块用于根据接收的即时调整指令，分析所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；
所述频率调整模块用于若所述内核的所述当前参考节点值达到所述计算正确阈值，实时将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核的所述当前参考节点值达到所述计算错误阈值，实时将所述内核的所述当前工作频点下调到下一个工作频点；
所述频率调整模块用于在所述调整时间段内，若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；在所述调整时间段内，若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点；或者
所述频率调整模块用于根据接收的即时调整指令，若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点；以及用于根据接收的停止调整指令，停止对所述内核的所述当前工作频点的调整。
根据本发明所述的芯片调频装置，还包括有：
频点统计模块，用于统计被调频后的所述内核在各所述工作频点上的当前分布状态；
频点调整模块，用于根据所述内核的所述当前分布状态和预定的频点调整机制，调整设置所述工作频点的频率，所述频点调整机制是内核分布状态与频点调整的对应关系。
根据本发明所述的芯片调频装置，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，所述高频工作频点中频率最高的是最高工作频点，所述低频工作频点中频率最低的是最低工作频点；
所述频点调整模块还包括：
第一频点调整子模块，用于若超过预定的第二比率的所述内核工作于至少一所述高频工作频点上，将至少一所述工作频点修改设置为至少一优化高频工 作频点，所述优化高频工作频点的频率高于所述最高工作频点的频率；和/或
第二频点调整子模块，用于若超过预定的第三比率的所述内核工作于至少一所述低频工作频点上，将至少一所述工作频点修改设置为至少一优化低频工作频点，所述优化低频工作频点的频率低于所述最低工作频点的频率。
根据本发明所述的芯片调频装置，所述第一频点调整子模块，用于若超过所述第二比率的所述内核工作于所述最高工作频点上，将一个所述工作频点修改设置为一个所述优化高频工作频点；和/或
所述第二频点调整子模块，用于若超过所述第三比率的所述内核工作于所述最低工作频点上，将一个所述工作频点修改设置为一个所述优化低频工作频点。
根据本发明所述的芯片调频装置，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，所述高频工作频点中频率最高的是最高工作频点，所述低频工作频点中频率最低的是最低工作频点；
所述频点调整模块还包括：
第三频点调整子模块，用于若工作于至少一所述高频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一优化高频工作频点，所述优化高频工作频点的频率高于所述最高工作频点的频率；和/或
第四频点调整子模块，用于若工作于至少一所述低频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一优化低频工作频点，所述优化低频工作频点的频率低于所述最低工作频点的频率。
根据本发明所述的芯片调频装置，所述第三频点调整子模块，用于若工作于所述最高工作频点上的所述内核的数目最多，将一个所述工作频点修改设置为一个所述优化高频工作频点；和/或
所述第四频点调整子模块，用于若工作于所述最低工作频点的所述内核的数目最多，将一个所述工作频点修改设置为一个所述优化低频工作频点。
根据本发明所述的芯片调频装置，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点；
所述频点调整模块还包括：
第一停止调整子模块，用于若超过预定的第四比率的所述内核工作于至少一所述中间工作频点上，停止调整设置所述工作频点的频率；或者
第二停止调整子模块，用于若工作于在至少一所述中间工作频点上的所述内核的数目最多，停止调整设置所述工作频点的频率。
根据本发明所述的芯片调频装置，所述芯片调频装置设置于所述运算芯片的内部或外部。
根据本发明所述的芯片调频装置，所述计算设备用于挖掘虚拟数字货币的运算。
本发明还提供一种包括有上述任意一种所述芯片调频装置的算力板。
本发明还提供一种包括有上述任意一种所述芯片调频装置的计算设备。
本发明还提供一种存储介质，用于存储一种用于上述任意一种所述计算设备的芯片调频方法的计算机程序。
本发明针对计算设备的运算芯片的内核进行自动调频，先设置多个合适的工作频点，将运算芯片中的多个内核分别工作于不同的工作频点上，然后根据每个内核在当前工作频点的计算性能指标，对内核的当前工作频点进行上调或下调，即上调计算性能高的内核的频率，下调计算性能低的内核的频率。借此，本发明能够根据计算设备的运算芯片中各个内核的实际计算性能，自动调节各个内核对应的频率，从而最大程度发挥内核的计算性能，进而提高运算芯片及整体运算设备的运算性能。
附图简要说明
图1是本发明计算设备的芯片调频装置的结构示意图；
图2是本发明第一实施例中计算设备的芯片调频装置的结构示意图；
图3是本发明第二实施例中计算设备的芯片调频装置的结构示意图；
图4是本发明第三实施例中计算设备的芯片调频装置的结构示意图；
图5是本发明第三实施例中参数设置的实例图；
图6是本发明第四实施例中计算设备的芯片调频装置的结构示意图；
图7是本发明第四实施例中内核在各个工作频点工作的分布状态图；
图8是本发明计算设备的芯片调频方法的流程图；
图9是本发明第一实施例中计算设备的芯片调频方法的流程图；
图10是本发明第二实施例中计算设备的芯片调频方法的流程图；
图11是本发明第二实施例中计算设备的优选芯片调频方法的流程图；
图12是本发明第三实施例中计算设备的芯片调频方法的流程图；
图13是本发明第三实施例中计算设备的优选芯片调频方法的流程图；
图14是本发明第四实施例中计算设备的芯片调频方法的流程图；
图15是本发明第四实施例中计算设备的优选芯片调频方法的流程图之一；
图16是本发明第四实施例中计算设备的优选芯片调频方法的流程图之二；
图17是本发明计算设备的结构示意图。
附图标记：
100-计算设备的芯片调频装置
10-频点设置模块
20-计算性能分析模块
21-第一分析子模块
211-第一计算单元         212-第一验算单元
22-统计子模块            23-第一判断子模块
24-设置子模块            25-第二分析子模块
251-第二计算单元         252-第二验算单元
26-计数子模块            27-第二判断子模块
30-频率调整模块
31-频率调整子模块        32-停止频率调整子模块
50-频点统计模块          60-频点调整模块
61-第一频点调整子模块    62-第二频点调整子模块
63-第三频点调整子模块    64-第四频点调整子模块
65-第一停止调整子模块    66-第二停止调整子模块
70-锁相环电路            80-内核
实现本发明的最佳方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
需要说明的，本说明书中针对“一个实施例”、“实施例”、“示例实施例”等的引用，指的是描述的该实施例可包括特定的特征、结构或特性，但是 不是每个实施例必须包含这些特定特征、结构或特性。此外，这样的表述并非指的是同一个实施例。进一步，在结合实施例描述特定的特征、结构或特性时，不管有没有明确的描述，已经表明将这样的特征、结构或特性结合到其它实施例中是在本领域技术人员的知识范围内的。
此外，在说明书及后续的权利要求当中使用了某些词汇来指称特定组件或部件，所属领域中具有通常知识者应可理解，制造商可以用不同的名词或术语来称呼同一个组件或部件。本说明书及后续的权利要求并不以名称的差异来作为区分组件或部件的方式，而是以组件或部件在功能上的差异来作为区分的准则。在通篇说明书及后续的权利要求书中所提及的“包括”和“包含”为一开放式的用语，故应解释成“包含但不限定于”。以外，“连接”一词在此系包含任何直接及间接的电性连接手段。间接的电性连接手段包括通过其它装置进行连接。
图1是本发明计算设备的芯片调频装置的结构示意图，所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述计算设备上设置有至少一个运算芯片，所述运算芯片中设置有多个内核(Core)80。所述计算设备优选包括控制板、与控制板连接的算力板，所述算力板上设置有至少一个运算芯片，运算芯片中设置有多个内核80。当然，所述计算设备还可以包括散热器、连接板、电源模块等。
需指出的是，本发明芯片调频技术实际涉及两个层级的频率调整机制：运算芯片的频率调整机制和内核层面的频率调整机制。所述运算芯片的频率调整机制是指为每个运算芯片设置若干合适的工作频点，并让运算芯片的各个内核80工作于各个工作频点，充分发挥每个内核80的工作性能。所述内核层面的频率调整机制是指根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。
所述芯片调频装置100至少包括有频点设置模块10、计算性能分析模块20和频率调整模块30，其中：
所述频点设置模块10，用于为计算设备的运算芯片设置多个工作频点，每个工作频点的频率不同，并将运算芯片中的多个内核80分别工作于各工作频点。
即根据运算芯片的频率调整机制，为每个运算芯片设置若干不同的频点，并让运算芯片的各个内核80工作于各个工作频点。例如设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。本发明工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。在启动调频开关时(尚未对内核80进行调频)，内核80可以按照预定规则被平均分布、不平均分布或随机分布于所述工作频点上工作。优选的是，频点设置模块10可以通过如图2所示的多个锁相环电路(Phase Locked Loop，PPL)70为运算芯片设置多个工作频点，当然频点设置模块10也可以通过其他硬件或软件为运算芯片设置多个工作频点。
所述计算性能分析模块20，用于分析每个内核80在当前工作频点的计算性能指标。所述计算性能指标代表内核80在当前工作频点的实际计算性能，包括但不限于计算正确率、计算正确数量、计算速度等。若内核80的计算性能指标较高，则表示所述内核80的计算性能可能还有提升空间；若内核80的计算性能指标较低，则表示所述内核80的计算性能可能不足以在当前工作频点对应的频率下工作。
所述频率调整模块30，用于根据内核80在当前工作频点的计算性能指标，对内核80的当前工作频点进行上调或下调。即根据内核层面的频率调整机制，将根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。优选的是，周期性地对内核80的频率进行调节，若内核80在频率的调整周期内的计算正确率达到第一正确率阈值，表明该内核80尚未达到最佳计算性能，因此将内核80的当前工作频点上调到较高的上一个工作频点；若内核80在频率的调整周期内的计算正确率未达到第二正确率阈值，表明该内核80的计算性能不足以在当前工作频点上工作，因此将内核80的当前工作频点下调到较低的下一个工作频点。
本发明芯片调频装置100可设置于运算芯片的内部或外部。本发明根据运算芯片中各个内核80的实际计算性能评价内核80的工作性能，调节内核80对应频率，充分发挥性能较优内核80的计算优势，并避免性能较弱内核80影响运算芯片的运算性能，最大程度发挥各个内核80的计算性能，进而提高 运算芯片及整体计算设备的计算速度和计算正确率。并且，本发明运算芯片的内核80不会在不同频率间跳转，工作频率相对稳定。
图2是本发明第一实施例中计算设备的芯片调频装置的结构示意图，所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述计算设备优选包括控制板、与控制板连接的算力板，所述算力板上设置有至少一个运算芯片，运算芯片中设置有多个内核(Core)80。当然，所述计算设备还可以包括散热器、连接板、电源模块等。所述芯片调频装置100至少包括有频点设置模块10、计算性能分析模块20和频率调整模块30，其中：
所述频点设置模块10，用于通过多个锁相环电路70为运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点，各个工作频点的频率不同，且所述工作频点与锁相环电路70为一一对应关系。优选的是，锁相环电路70设置于运算芯片的内部或外部。本发明中各工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。例如设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。因此，本发明可以设置更多的锁相环电路70来设置更多的工作频点，以使得各个内核80的计算性能充分发挥。
值得提醒的是，本发明中工作频点之间的频差需要控制在合理范围。因为当内核80提高一个工作频点，该内核的工作频率将提高一个频差值，其可以因为计算速度的提高进而提升一定的计算性能。于此同时，提升内核的工作频率，其可能因为计算正确率的降低进而损耗一定的计算性能。所以频点设置模块10应该合理控制相邻的工作频点之间的频差，使得内核80从当前工作频点上调到上一个工作频点时，内核80的计算性能的受益应大于损失。优选的是，相邻的工作频点之间的频差为1～10％。
所述计算性能分析模块20，用于分析每个内核80在当前工作频点的计算性能指标。所述计算性能指标代表内核80在当前工作频点的实际计算性能，包括但不限于计算正确率、计算正确数量、计算速度等。若内核80的计算性能指标较高，则表示所述内核80的计算性能可能还有提升空间；若内核80的计算性能指标较低，则表示所述内核80的计算性能可能不足以在当前工作频点对应的频率下工作。优选的是，计算性能分析模块20用于在预定的调整周期内，分析内核80的计算性能指标是否达到预定的第一指标阈值、第二指 标阈值和/或第三指标阈值，其中，第一指标阈值与第二指标阈值相同或者不相同。
所述频率调整模块30，用于根据内核80的计算性能指标，通过锁相环电路70对内核80的当前工作频点进行上调或下调。当然，频率调整模块30也可以通过其他硬件或软件实现对内核80的当前工作频点进行上调或下调。优选的是，频率调整模块30用于若内核80的计算性能指标达到第一指标阈值，将内核80的当前工作频点上调到上一个工作频点；和/或，频率调整模块30用于若内核80的计算性能指标未达到第二指标阈值，将内核80的当前工作频点下调到下一个工作频点；和/或频率调整模块30用于若内核80的计算性能指标达到第三指标阈值，将内核80的当前工作频点下调到下一个工作频点。
例如，结合上述“例如设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。”，以及内核80的当前工作频点为600MHz为例，所述计算性能指标为内核80在调整周期内的计算正确率，第一指标阈值和第二指标阈值均为90％。若内核80在调整周期内的计算正确率达到90％，表示所述内核80的计算性能较好，则将内核80的当前工作频点600MHz上调到上一个工作频点650MHz；若内核80在调整周期内的计算正确率未达到90％，表示所述内核80的计算性能较弱，则将内核80的当前工作频点600MHz下调到下一个工作频点550MHz。本领域技术人员可以理解的是，上一个工作频点并不仅限于上一相邻工作频点，也可设置一个以上的上一相邻工作频点作为上一个工作频点；下一个工作频点并不仅限于下一相邻工作频点，也可设置一个以上的下一相邻工作频点作为下一个工作频点。即为，将内核80的当前工作频点600MHz上调到上一个工作频点700MHz；将内核80的当前工作频点600MHz下调到下一个工作频点500MHz。以此类推，此处不对上一工作频点，下一工作频点的间距作限定。优选的是，当前工作频点与上一个工作频点之间的频差为1～10％，以及当前工作频点与下一个工作频点的频差为1～10％，使得内核80从当前工作频点上调到上一个工作频点或下一个工作频点时，内核80的计算性能的受益应大于损失。
再例如，所述计算性能指标为内核80在调整周期内的计算正确率，第一指标阈值为90％，第二指标阈值为80％。若内核80在调整周期内的计算正确率达到90％，表示所述内核80的计算性能较好，则将内核80的当前工作频点 600MHz上调到上一个工作频点650MHz；若内核80在调整周期内的计算正确率未达到80％，表示所述内核80的计算性能较弱，则将内核80的当前工作频点600MHz下调到下一个工作频点550MHz。
又例如，所述计算性能指标为内核80在调整周期内的正确计算次数和错误结算次数，第一指标阈值为100，第二指标阈值为10。若内核80在调整周期内的正确计算次数达到100，表示所述内核80的计算性能较好，则将内核80的当前工作频点600MHz上调到上一个工作频点650MHz；若内核80在调整周期内的错误计算次数达到10，表示所述内核80的计算性能较弱，则将内核80的当前工作频点600MHz下调到下一个工作频点550MHz。
优选的是，所述频率调整模块30还包括有频率调整子模块31和停止频率调整子模块32，其中：
所述频率调整子模块31，用于根据内核80的计算性能指标，对内核80的当前工作频点进行上调或下调。优选的是，频率调整子模块31根据内核80的计算性能指标，通过锁相环电路70对内核80的当前工作频点进行上调或下调。当然，频率调整子模块31也可以通过其他硬件或软件实现对内核80的当前工作频点进行上调或下调。
所述停止频率调整子模块32，用于若工作于预定的至少一个优化工作频点的内核80超过预定的第一比率，停止对内核80进行调频；或者用于若工作于至少一所述优化工作频点上的内核80的数目最多，停止对内核80进行调频。
例如，可在若干工作频点中选择预设一个或多个优化工作频点，若大多数内核80的工作频率已经到达该优化工作频点，表明运算芯片中个内核80的工作频率已经处于优化状态，可充分发挥各个内核80的计算性能，不再需要进一步调频，因此停止内核80工作频率的调整。例如设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，选择其中两个优化工作频点600Mhz和650Mhz为优化工作频点，若超过80％的内核80工作于工作频点600Mhz和650Mhz，则停止对内核80进行调频。
图3是本发明第二实施例中计算设备的芯片调频装置的结构示意图，所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述计算设备优选包括控制板、与控制板连接的算力板，所述算力板上设置有至少一个运算芯片，运算芯片中设置有多个内核(Core)80。当然，所述计算设备还可以 包括散热器、连接板、电源模块等。所述芯片调频装置100至少包括有频点设置模块10、计算性能分析模块20和频率调整模块30，其中：
所述频点设置模块10，用于为计算设备的运算芯片设置多个工作频点，每个工作频点的频率不同，并将运算芯片中的多个内核80分别工作于各工作频点。即根据运算芯片层面的频率调整机制，为每个运算芯片设置若干不同的频点，并让运算芯片的各个内核80工作于各个工作频点。例如设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。本发明工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。在启动调频开关时(尚未对内核80进行调频)，内核80可以按照预定规则被平均分布、不平均分布或随机分布于所述工作频点上工作。优选的是，频点设置模块10通过如图2所示的多个锁相环电路70为运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点，工作频点与锁相环电路70为一一对应关系。本发明可以设置更多的锁相环电路70来设置更多的工作频点，以使得各个内核80的计算性能充分发挥。当然频点设置模块10也可以通过其他硬件或软件为运算芯片设置多个工作频点。
值得提醒的是，本发明中工作频点之间的频差需要控制在合理范围。因为当内核80提高一个工作频点，该内核的工作频率将提高一个频差值，其可以因为计算速度的提高进而提升一定的计算性能。于此同时，提升内核的工作频率，其可能因为计算正确率的降低进而损耗一定的计算性能。所以频点设置模块10应该合理控制相邻的工作频点之间的频差，使得内核80从当前工作频点上调到上一个工作频点时，内核80的计算性能的受益应大于损失。优选的是，相邻的工作频点之间的频差为1～10％。
所述计算性能分析模块20，用于在预定的调整周期内，分析内核80的计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值，第一正确率阈值与第二正确率阈值相同或者不相同。若内核80的计算正确率达到预定的第一正确率阈值，则表示所述内核80的计算性能可能还有提升空间；若内核80的计算正确率未达到预定的第二正确率阈值，则表示所述内核80的计算性能可能不足以在当前工作频点对应的频率下工作。
所述频率调整模块30，用于若内核80的计算正确率达到第一正确率阈值， 表明该内核80尚未达到最佳计算性能，将内核80的当前工作频点上调到上一个工作频点；和/或用于若内核80的计算正确率未达到第二正确率阈值，表明该内核80的计算性能不足以在当前工作频点上工作，将内核80的当前工作频点下调到下一个工作频点。所述频率调整模块30可通过如图2所示的锁相环电路70或软件对内核80进行调频。即根据内核层面的频率调整机制，将根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。
例如，第一正确率阈值和第二正确率阈值均为90％。当内核80工作在600MHz时，若内核80在预定的调整周期内的计算正确率超过90％(表明该内核80尚未达到最佳计算性能)，则将内核80的当前工作频点600MHz上调到上一个工作频点，即提高其工作频率至650MHz；若内核80的计算正确率低于90％(表明该内核80的计算性能不足以在该当前工作频点600MHz的频率下工作)，则将内核80的当前工作频点下调到下一个工作频点，即降低其工作频率至550MHz。本领域技术人员可以理解的是，上一个工作频点并不仅限于上一相邻工作频点，也可设置一个以上的上一相邻工作频点作为上一个工作频点；下一个工作频点并不仅限于下一相邻工作频点，也可设置一个以上的下一相邻工作频点作为下一个工作频点。即为，将内核80的当前工作频点600MHz上调到上一个工作频点700MHz；将内核80的当前工作频点600MHz下调到下一个工作频点500MHz。以此类推，此处不对上一工作频点，下一工作频点的间距作限定。优选的是，当前工作频点与上一个工作频点之间的频差为1～10％，以及当前工作频点与下一个工作频点的频差为1～10％，使得内核80从当前工作频点上调到上一个工作频点或下一个工作频点时，内核80的计算性能的受益应大于损失。
再例如，第一正确率阈值为90％，第二正确率阈值均为80％。当内核80工作在600MHz时，若内核80在预定的调整周期内的计算正确率超过90％(表明该内核80尚未达到最佳计算性能)，则将内核80的当前工作频点上调到上一个工作频点，即提高其工作频率至650MHz；若内核80的计算正确率低于80％(表明该内核80的计算性能不足以在该当前工作频点600MHz的频率下工作)，则将内核80的当前工作频点下调到下一个工作频点，即降低其工作 频率至550MHz。
优选的是，所述计算正确率可为内核80在调整周期内提交的Nonce(Number once，随机数)的计算正确率。即预定时间内，内核80所提交的全部Nonce中，正确Nonce所占的比率。区域链中的区块头包括所述Nonce(4字节)，Nonce是一个随机值，矿工的作用其实就是猜出Nonce的值，使得区块头的哈希(Hash)可以小于目标值Target，从而能够写入区块链。具体而言，将这个属性从0开始，遍历到2^32，来计算区块头的哈希值，如果得到的哈希结果符合条件，则挖矿成功。
优选的是，图3中的计算性能分析模块20进一步包括有：
第一分析子模块21，用于在预定的调整周期内，分析内核80提交的Nonce是否正确。
统计子模块22，用于统计内核80在调整周期内提交的正确Nonce的个数和错误Nonce的个数。
第一判断子模块23，用于根据正确Nonce的个数和错误Nonce的个数，计算出内核80在调整周期内的Nonce计算正确率，并判断Nonce计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值。
频率调整模块30用于若内核80的Nonce计算正确率达到第一正确率阈值，将内核80的当前工作频点上调到上一个工作频点；和/或用于若内核80的Nonce计算正确率未达到第二正确率阈值，将内核80的当前工作频点下调到下一个工作频点。
更好的是，第一分析子模块21进一步包括：
第一计算单元211，用于在调整周期内，内核80每递交一个Nonce后，将Nonce通过预定的算法计算出第一结果，所述第一结果中包含有第一特征，第一计算单元211优选设置于内核80中。每个内核80提交的Nonce中，包含Nonce的标识信息(ID)，从而可实现对每个内核80的计算结果进行统计。
第一验算单元212，用于将内核80递交的所述Nonce通过相同的算法计算出第二结果，所述第二结果中包含有第二特征，若第一特征与第二特征相同，则判定所述Nonce是正确Nonce，否则判定所述Nonce是错误Nonce。第一验算单元212优选设置于运算芯片中。
例如，内核80计算出一个Nonce后提交，将所述Nonce嵌入区块头计算 得到第一哈希结果，第一哈希结果的前20位的值是0(第一特征)。第一验算单元212也将该Nonce嵌入区块头计算得到第二哈希结果，若第二哈希结果的前20位的也是0(第二特征)，则认为该Nonce是一次正确提交。
需指出的是，为了提高单个内核80计算出可满足写入区块链的nonce值的概率，也可以采用比上述“目标值Target”要容易的多Target_Lite来判断Hash，每个内核80要提交可以更加频繁的提交nonce，第一验算单元212对内核80提交的nonce进行验算，如果其使用内核80提交的nonce计算出的Hash同样通过Target_Lite的判定，即认为内核80的正确提交，否则即为错误提交。本发明并不局限于使用可写入最终区块链的nonce。第一验算单元212和内核80之间交互的nonce是满足更低门限，提交密度高，可利于频率调整。
优选的是，所述计算性能分析模块20用于根据预设的实时调整指令，实时分析内核80在调整周期内的计算正确率是否达到第一正确率阈值和/或第二正确率阈值，所述第一正确率阈值与第二正确率阈值相同或者不相同。
所述频率调整模块30用于若内核80在调整周期内的计算正确率达到第一正确率阈值，实时将内核80的当前工作频点上调到上一个工作频点。若内核80在调整周期内的计算正确率未达到第二正确率阈值，实时将内核80的当前工作频点下调到下一个工作频点，使得内核80的工作频率得到实时动态调整。
优选的是，所述计算性能分析模块20用于根据预设的定时调整指令，在所述定时调整指令设定的调整时间段内，分析内核80在调整周期内的计算正确率是否达到第一正确率阈值和/或第二正确率阈值，所述第一正确率阈值与第二正确率阈值相同或者不相同。
所述频率调整模块30用于在调整时间段内，若内核80在调整周期内的计算正确率达到第一正确率阈值，将内核80的当前工作频点上调到上一个工作频点；在调整时间段内，若内核80在调整周期内的计算正确率未达到第二正确率阈值，将内核80的当前工作频点下调到下一个工作频点，使得内核80的工作频率得到定时调整。如设定每周仅设置周六(24小时)统计内核80计算正确率，并根据计算正确率进行频率调整。
优选的是，所述计算性能分析模块20用于根据接收的即时调整指令，分析内核80在调整周期内的计算正确率是否达到第一正确率阈值和/或第二正确率阈值，所述第一正确率阈值与第二正确率阈值相同或者不相同。
所述频率调整模块30用于根据接收的即时调整指令，若内核80在调整周期内的计算正确率达到第一正确率阈值，将内核80的当前工作频点上调到上一个工作频点。若内核80在调整周期内的计算正确率未达到第二正确率阈值，将内核80的当前工作频点下调到下一个工作频点。根据接收的停止调整指令，停止对内核80的当前工作频点的调整。
例如，用户可根据需要随时向计算设备发送即时调整指令，计算设备根据该即时调整指令立即开始分析内核80的计算正确率，若在调整周期(例如10分钟)内，若内核80的计算正确率超过第一正确率阈值(例如高于99％)，则将内核80的工作频率向上调整；若在调整周期(例如10分钟)内，所述内核80的计算正确率低于第二正确率阈值(例如低于99％)，则将内核80的工作频率向下调整。此外，用户可根据需要随时向计算设备发送停止调整指令，计算设备收到该停止调整指令后，立即停止对内核80的调频。
图4是本发明第三实施例中计算设备的芯片调频装置的结构示意图，所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述计算设备优选包括控制板、与控制板连接的算力板，所述算力板上设置有至少一个运算芯片，运算芯片中设置有多个内核(Core)80。当然，所述计算设备还可以包括散热器、连接板、电源模块等。所述芯片调频装置100包括频点设置模块10、计算性能分析模块20、频率调整模块30，其中：
所述频点设置模块10，用于为计算设备的运算芯片设置多个工作频点，每个工作频点的频率不同，并将运算芯片中的多个内核80分别工作于各工作频点。即根据运算芯片的频率调整机制，为每个运算芯片设置若干不同的频点，并让运算芯片的各个内核80工作于各个工作频点。例如设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。本发明工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。在启动调频开关时(尚未对内核80进行调频)，内核80可以按照预定规则被平均分布、不平均分布或随机分布于所述工作频点上工作。优选的是，频点设置模块10可以通过如图2所示的多个锁相环电路70为运算芯片设置多个工作频点，当然频点设置模块10也可以通过其他硬件或软件为运算芯片设置多个工作频点。
值得提醒的是，本发明中工作频点之间的频差需要控制在合理范围。因为 当内核80提高一个工作频点，该内核的工作频率将提高一个频差值，其可以因为计算速度的提高进而提升一定的计算性能。于此同时，提升内核的工作频率，其可能因为计算正确率的降低进而损耗一定的计算性能。所以频点设置模块10应该合理控制相邻的工作频点之间的频差，使得内核80从当前工作频点上调到上一个工作频点时，内核80的计算性能的受益应大于损失。优选的是，相邻的工作频点之间的频差为1～10％。
所述计算性能分析模块20，用于分析每个内核80在当前工作频点的计算性能指标。所述计算性能分析模块20进一步包括有：
设置子模块24，用于预先设置内核80的参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和计算错误阈值。所述计算正确权重值和计算错误权重值可以相同或不相同；所述计算正确阈值和计算错误阈值可以相同或不相同。所述参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和计算错误阈值均属于可调参数，可根据频率调节快慢等实际需要进行优化设置。
第二分析子模块25，用于分析内核80的每次计算是否正确。内核80可以进行各种不同的计算，可分析内核80的每次某种或几种计算是否正确。优选为分析内核80计算出的Nonce是否正确。
计数子模块26，用于内核80每正确计算至少一次，在参考节点值上增加一次计算正确权重值，并且内核80每错误计算至少一次，在参考节点值上减少一次计算错误权重值。优选的是，内核80每正确计算一次，在参考节点值上增加一次计算正确权重值。当然，可以设置为内核80每正确计算N次(N为大于1的自然数)，在参考节点值上增加一次计算正确权重值。内核80每错误计算一次，在参考节点值上减少一次计算错误权重值。当然，可以设置为内核80每错误计算N次(N为大于1的自然数)，在参考节点值上减少一次计算错误权重值。
第二判断子模块27，用于判断内核80的当前参考节点值是否达到计算正确阈值或计算错误阈值。若当前参考节点值达到计算正确阈值，则表示所述内核80的计算性能较高且可能还有提升空间；若当前参考节点值达到计算错误阈值，则表示所述内核80的计算性能较弱，可能不足以在当前工作频点对应的频率下工作。
所述频率调整模块30，用于若内核80的当前参考节点值达到计算正确阈值，表明该内核80尚未达到最佳计算性能，将内核80的当前工作频点上调到上一个工作频点；以及用于若内核80的当前参考节点值达到计算错误阈值，表明该内核80的计算性能不足以在当前工作频点上工作，将内核80的当前工作频点下调到下一个工作频点。所述频率调整模块30可通过如图2所示的锁相环电路70或软件对内核80进行调频。即根据内核层面的频率调整机制，将根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。本领域技术人员可以理解的是，上一个工作频点并不仅限于上一相邻工作频点，也可设置一个以上的上一相邻工作频点作为上一个工作频点；下一个工作频点并不仅限于下一相邻工作频点，也可设置一个以上的下一相邻工作频点作为下一个工作频点。即为，将内核80的当前工作频点600MHz上调到上一个工作频点700MHz；将内核80的当前工作频点600MHz下调到下一个工作频点500MHz。以此类推，此处不对上一工作频点，下一工作频点的间距作限定。优选的是，当前工作频点与上一个工作频点之间的频差为1～10％，以及当前工作频点与下一个工作频点的频差为1～10％，使得内核80从当前工作频点上调到上一个工作频点或下一个工作频点时，内核80的计算性能的受益应大于损失。
例如，如图5所示，设置400000作为参考节点值，计算正确权重值设为180，计算错误权重值设为9000，计算正确阈值和计算错误阈值均设为100000。
内核80每正确计算一次，在该参考节点值上加180(计算正确权重值)；内核80每错误计算一次，在该参考节点值上减少9000(计算错误权重值)；以所述参考节点值为基准，每增加或减少100000(计算正确阈值和计算错误阈值)，向上一频点进阶或向下一频点降阶。
当前机制类似于错误和正确的拔河比赛机制，正确和错误可具有不同的权重。设置参考节点值，每收到一次正确结果，增加一次计算正确权重值，每收到一个错误结果，减少一次计算错误权重值，如果奖励或惩罚超过对应侧门限，则进行频率的上调或下调。可以理解调整系统有一个marker，参考节点值是maker的初始值，如果有正确提交则maker+180，每次错误提交则maker-9000。经过N次正确(N为大于或等于1的自然数)，M次错误后(M为大 于或等于1的自然数)，marker应该处在400000+N*180-M*9000的位置，如果Marker超过某侧门限则进行相应频率调整(即上调或下调)。然后每次频率调整到新的频点上都初始化该值，即将当前参考节点值重新设置为初始的参考节点值。
优选的是，所述设置子模块24用于根据实际需求设置和调整内核80的参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和/或计算错误阈值，计算正确权重值和计算错误权重值相同或者不相同，计算正确阈值和计算错误阈值相同或者不相同。
优选的是，设置子模块24用于通过控制计算正确权重值和计算错误权重值的比值控制内核80期望容忍的驻留差错率S。驻留差错率S的计算公式为：驻留差错率S＝计算正确权重值/(计算正确权重值+计算错误权重值)。
优选的是，设置子模块24用于通过控制计算正确权重值和计算错误权重值的绝对值大小控制调整周期。
优选的是，设置子模块24用于通过控制计算正确阈值和计算错误阈值的绝对值大小控制调整周期。
优选的是，所述正确计算可为内核80正确计算Nonce。
所述第二分析子模块25用于分析内核80每次提交的Nonce是否正确。
所述计数子模块26用于在内核80每提交至少一次正确Nonce，在参考节点值上增加一次计算正确权重值；内核80每提交至少一次错误Nonce，在参考节点值上减少一次计算错误权重值。优选的是，在内核80每提交一次正确Nonce，在参考节点值上增加一次计算正确权重值。当然，也可以设置为内核80每提交N(N为大于1的自然数)次正确Nonce，在参考节点值上增加一次计算正确权重值。内核80每提交一次错误Nonce，在参考节点值上减少一次计算错误权重值。当然，也可以设置为内核80每提交N(N为大于1的自然数)次错误Nonce，在参考节点值上减少一次计算错误权重值。
更好的是，第二分析子模块25进一步包括：
第二计算单元251，用于内核80递交一个Nonce后，内核80将Nonce通过预定的算法计算出第一结果，所述第一结果中包含有第一特征。
第二验算单元252，用于将Nonce通过相同的算法计算出第二结果，所述第二结果中包含有第二特征。若第一特征与第二特征相同，则判定Nonce是正 确Nonce，否则判定Nonce是错误Nonce。
例如，内核80计算出一个Nonce后提交，将所述Nonce嵌入区块头计算得到第一哈希结果，第一哈希结果的前20位的值是0(第一特征)。第二验算单元252也将该Nonce嵌入区块头计算得到第二哈希结果，若第二哈希结果的前20位的也是0(第二特征)，则认为该Nonce是一次正确提交。
需指出的是，为了提高单个内核80计算出可满足写入区块链的nonce值的概率，也可以采用比上述“目标值Target”要容易的多Target_Lite来判断Hash，每个内核80要提交可以更加频繁的提交nonce，第一验算单元212对内核80提交的nonce进行验算，如果其使用内核80提交的nonce计算出的Hash同样通过Target_Lite的判定，即认为内核80的正确提交，否则即为错误提交。本发明并不局限于使用可写入最终区块链的nonce。第一验算单元212和内核80之间交互的nonce是满足更低门限，提交密度高，可利于频率调整。
在本发明一个具体应用实施例中：使用6个锁相环电路70，设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。如图5所示，设置400000作为参考节点值，计算正确权重值设为180，计算错误权重值设为9000，计算正确阈值和计算错误阈值均设为100000。
按照4块算力板统计出的各对应频率上分布的内核数目如下：
算力板0：[294 26 96  224 1023 1665]
算力板1：[274 47 111 212  963 1721]
算力板2：[350 25 153 369 1381 1050]
算力板3：[488 33 184 367 1342  950]
首先，结合数据进一步说明机制。根据驻留差错率S＝计算正确权重值/(计算正确权重值+计算错误权重值)，并通过给定的数据可以推算出内核80的驻留差错率S(理解为可长期驻留在某个频点)为180/(180+9000)＝1.29％，此时内核80长久的工作在某个频点上(因为此时期望步长为0)，工作频率不会上调或下调。可以推知，若内核80的计算错误率大于1.29％(驻留差错率S)，其工作频率将被上调；若内核80的计算错误率小于1.29％(驻留差错率S)，其工作频率将被下调。
依据设置的难度(该难度与检验基准有关，对内核80计算正确率有影响，难度系数越大，正确率越低；反之则正确率越高)，可以推算出错误上升时调 整的大致周期，假定错误率为e，则每个Nonce的期望步长为：(1-e)*180-e*9000＝180-9180e。以e＝0.5％为例，期望步长＝134.1；以e＝1％为例，期望步长＝88.2；以e＝2％为例，期望步长＝-3.6。
以650MHz计算，内核80提交单个Nonce的期望为1.3个/秒(即1秒递交1.3个Nonce)。以e为0.5％的场景进行解释，即在746次的Nonce提交过程后，就可以预期向上调整一次；e为1.0％需要1134次提交，预期向上调整一次，如果错误概率为2.0％，则需要27778次提交，预期向下调整一次，其他类推。
优选的是，所述计算性能分析模块20用于根据预设的实时调整指令，实时判断内核80的当前参考节点是否达到计算正确阈值或计算错误阈值，所述计算正确阈值或计算错误阈值相同或不相同。
所述频率调整模块30用于若内核80的当前参考节点值达到计算正确阈值，实时将内核80的当前工作频点上调到上一个工作频点；若内核80的当前参考节点值达到计算错误阈值，实时将内核80的当前工作频点下调到下一个工作频点，使得内核80的工作频率得到实时动态调整。
优选的是，所述计算性能分析模块20用于根据预设的定时调整指令，在定时调整指令设定的调整时间段内，判断内核80的当前参考节点是否达到计算正确阈值或计算错误阈值，所述计算正确阈值或计算错误阈值相同或不相同。
所述频率调整模块30用于在调整时间段内，若内核80的当前参考节点值达到计算正确阈值，将内核80的当前工作频点上调到上一个工作频点；在调整时间段内，若内核80的当前参考节点值达到计算错误阈值，将内核80的当前工作频点下调到下一个工作频点，使得内核80的工作频率得到定时调整。如设定每周仅设置周六的24小时内统计内核80出正确Nonce的个数，并根据计算正确率进行频率调整。
优选的是，所述计算性能分析模块20用于根据接收的即时调整指令，分析内核80的当前参考节点是否达到计算正确阈值或计算错误阈值，所述计算正确阈值或计算错误阈值相同或不相同。
所述频率调整模块30用于根据接收的即时调整指令，若内核80的当前参考节点值达到计算正确阈值，将内核80的当前工作频点上调到上一个工作频 点。若内核80的当前参考节点值达到计算错误阈值，将内核80的当前工作频点下调到下一个工作频点。以及用于根据接收的停止调整指令，停止对内核80的当前工作频点的调整。
例如，用户可根据需要随时向计算设备发送即时调整指令，用户设置内核80每计算正确Nonce一次，在参考节点上增加权重A，内核80每计算错误Nonce一次，在该参考节点上减少权重B。当前增加数值达到计算正确数量阈值C时，将内核80向上一频点进阶。当前减少数值达到计算错误数阈值D时，将内核80向下一个频点降阶。此外，用户可根据需要随时向计算设备发送停止调整指令，计算设备收到该停止调整指令后，立即停止对内核80的调频。
图6是本发明第四实施例中计算设备的芯片调频装置的结构示意图，所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述计算设备优选包括控制板、与控制板连接的算力板，所述算力板上设置有至少一个运算芯片，运算芯片中设置有多个内核(Core)80。当然，所述计算设备还可以包括散热器、连接板、电源模块等。所述芯片调频装置100包括频点设置模块10、计算性能分析模块20、频率调整模块30、频点统计模块50以及频点调整模块60，其中：
所述频点设置模块10，用于为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。即根据运算芯片层面的频率调整机制为每个运算芯片设置若干不同的频点，并让运算芯片的内核80工作于各个工作频点。例如设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。各工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。在启动调频开关时(尚未对内核80进行调频之前)，内核80可以按照预定规则平均分布、不平均分布或随机分布于所述工作频点。频点设置模块10可以通过如图2所示的多个锁相环电路(Phase Locked Loop，PPL)70为运算芯片设置多个工作频点，当然频点设置模块10也可以通过其他硬件或软件为运算芯片设置多个工作频点。
值得提醒的是，本发明中工作频点之间的频差需要控制在合理范围。因为当内核80提高一个工作频点，该内核的工作频率将提高一个频差值，其可以因为计算速度的提高进而提升一定的计算性能。于此同时，提升内核的工作频 率，其可能因为计算正确率的降低进而损耗一定的计算性能。所以频点设置模块10应该合理控制相邻的工作频点之间的频差，使得内核80从当前工作频点上调到上一个工作频点时，内核80的计算性能的受益应大于损失。优选的是，相邻的工作频点之间的频差为1～10％。
所述计算性能分析模块20，用于分析每个内核80在当前工作频点的计算性能指标。所述计算性能指标代表内核80在当前工作频点的实际计算性能，包括但不限于计算正确率、计算正确数量、计算速度等。若内核80的计算性能指标较高，则表示所述内核80的计算性能可能还有提升空间；若内核80的计算性能指标较低，则表示所述内核80的计算性能可能不足以在当前工作频点对应的频率下工作。
所述频率调整模块30，用于根据内核80的计算性能指标，对内核80的当前工作频点进行上调或下调。即根据内核层面的频率调整机制，将根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。所述频率调整模块30可通过如图2所示的锁相环电路70或软件对内核80进行调频。优选的是，若内核80在调整周期内的计算正确率达到第一正确率阈值，表明该内核80尚未达到最佳计算性能，因此将内核80的当前工作频点上调到上一个工作频点；若内核80在调整周期内的计算正确率未达到第二正确率阈值，表明该内核80的计算性能不足以在当前工作频点上工作，因此将内核80的当前工作频点下调到下一个工作频点。本领域技术人员可以理解的是，上一个工作频点并不仅限于上一相邻工作频点，也可设置一个以上的上一相邻工作频点作为上一个工作频点；下一个工作频点并不仅限于下一相邻工作频点，也可设置一个以上的下一相邻工作频点作为下一个工作频点。即为，将内核80的当前工作频点600MHz上调到上一个工作频点700MHz；将内核80的当前工作频点600MHz下调到下一个工作频点500MHz。以此类推，此处不对上一工作频点，下一工作频点的间距作限定。优选的是，当前工作频点与上一个工作频点之间的频差为1～10％，以及当前工作频点与下一个工作频点的频差为1～10％，使得内核80从当前工作频点上调到上一个工作频点或下一个工作频点时，内核80的计算性能的受益应大于损失。
所述频点统计模块50，用于统计被调频后的内核80在各工作频点上的当 前分布状态。内核80的工作频点根据自身计算性能被自动调频后，会分布在各工作频点上工作，频点统计模块50统计被调频后的内核80在各工作频点上的分布个数可得出当前分布状态。优选的是，可将工作频点划分为包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，高频工作频点中频率最高的是最高工作频点，低频工作频点中频率最低的是最低工作频点。例如一共有1000个内核80，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，依次其分布在上述6个工作频点的个数分别为：100，200，100，100，200，300。其中，500MHz，550MHz为低频工作频点，600MHz，650MHz为中间工作频点，700MHz，750MHz为高频工作频点，500MHz为最低工作频点，750MHz为最高工作频点。
所述频点调整模块60，用于根据内核80的所述当前分布状态和预定的频点调整机制，调整设置工作频点的频率。所述频点调整机制是内核分布状态与频点调整的对应关系。所述内核分布状态是指内核80在各个工作频点上工作的分布状态。所述调整设置工作频点的频率，是指直接将工作频点的频率进行调整。所述频点调整模块60优选通过如图2所示的锁相环电路70调整设置工作频点的频率。本领域技术人员可以理解的是，频点调整模块50的调整设置工作频点的调整方式并不仅限于此。本发明理想状态是希望超过预定的比率(如50％)或最多数目的内核80落到中间工作频点，这样内核80的频率有更大的上调空间。
例如，若超过预定的比率(如30％)的内核80工作于最高工作频点(750MHz)上，可能导致所述内核80没有发挥出最大的计算性能(因可能更高)，则需要将一工作频点(600MHz)修改设置为至少一优化高频工作频点(800MHz)，原工作于工作频点(600MHz)上的内核80将全部转移到最高工作频点(750MHz)上工作。所述优化高频工作频点的频率高于所述最高工作频点的频率，以充分发挥各内核80的计算性能。
在本发明一具体实例中，所述频点调整模块60还包括第一频点调整子模块61和/或第二频点调整子模块62，其中：
所述第一频点调整子模块61，用于若超过预定的第二比率的内核80工作于至少一高频工作频点上，可能导致所述内核80没有发挥出最大的计算性能(因可能更高)，将至少一工作频点修改设置为至少一优化高频工作频点，优 化高频工作频点的频率高于最高工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，超过30％(第二比率)的内核80工作在两个高频工作频点(700MHz和750MHz)，则将两个低频工作频点(500MHz和550MHz)修改设置为两个优化高频工作频点(800MHz和850MHz)，或者将一个低频工作频点(500MHz)和一个中频工作频点(600MHz)修改设置为两个优化高频工作频点(800MHz和850MHz)。
优选的是，第一频点调整子模块61用于若超过第二比率的内核80工作于最高工作频点上，可能导致所述内核80没有发挥出最大的计算性能(因可能更高)，将一个工作频点修改设置为一个优化高频工作频点，优化高频工作频点的频率高于最高工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，超过30％(第二比率)的内核80工作在最高工作频点(750MHz)，则将一个低频工作频点(500MHz)修改设置为优化高频工作频点(800MHz)，或者将一个中频工作频点(600MHz)修改设置为优化高频工作频点(800MHz)；或者将最高工作频点(750MHz)修改设置为优化高频工作频点(800MHz)。
所述第二频点调整子模块62，用于若超过预定的第三比率的内核80工作于至少一低频工作频点上，说明所述内核80的计算能力过差不足以工作在所述低频工作频点上，因此将至少一工作频点修改设置为至少一优化低频工作频点，优化低频工作频点的频率低于最低工作频点的频率，以避免计算性能差的内核80影响运算芯片的整体计算性能。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，超过30％(第三比率)的内核80工作在两个低频工作频点(500MHz和550MHz)，则将两个低频工作频点(500MHz和550MHz)修改设置为两个优化低频工作频点(400MHz和450MHz)，或者将一个低频工作频点(500MHz)和一个中频工作频点(600MHz)修改设置为两个优化低频工作频点(400MHz和450MHz)。
优选的是，第二频点调整子模块62用于若超过第三比率的内核80工作于 最低工作频点上，说明所述内核80的计算能力过差不足以工作在所述最低工作频点上，因此将一个工作频点修改设置为一个优化低频工作频点。优化低频工作频点的频率低于最低工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，超过30％(第三比率)的内核80工作在最低工作频点(500MHz)，则将一个低频工作频点(500MHz)修改设置为优化低频工作频点(450MHz)，或者将一个中频工作频点(600MHz)修改设置为优化低频工作频点(450MHz)；或者将最高工作频点(750MHz)修改设置为优化低频工作频点(450MHz)。
在本发明一个具体应用实施例中：使用6个锁相环电路70，设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。
按照4块算力板统计出的各对应频率上分布的内核数目如下：
算力板0：[294 26 96  224 1023 1665]
算力板1：[274 47 111 212  963 1721]
算力板2：[350 25 153 369 1381 1050]
算力板3：[488 33 184 367 1342  950]
以上述四块算力板0～3为例，如图7所示，数据大致符合正态分布，最低工作频点(500Mhz)为单个内核80工作的最低频率，无法再向下调整(如果错误率过高，可以考虑关闭该最低频点)；而最高工作频点(750Mhz)上积累超过预定比率(例如50％)的内核80，则意味着没有发挥出最大的效率(因可能更高)，整个运算芯片还有进一步提升的空间。比较理想状态是超过预定的比率(如50％)或最多数目的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)。为充分利用内核80的计算性能，更应该考虑高能力侧的长尾，而不是低频点长尾。
以算力板0～1为例，可以看出，若将600Mhz频点去除，此时若采用整体左移，大概有100个内核80频点落到550频点上，当前的频率设置明显在左侧低频区，不利于充分发挥内核80的计算性能。故更适合整体右移，即采用整体偏移方式，通过如图2所示的锁相环电路70将550Mhz频点整体向右设置为800Mhz频点以上，则有望使得数百个内核80提高到800M以上，从而带来整体计算性能的提升。
在本发明另一具体实例中，所述频点调整模块60还包括第三频点调整子 模块63和/或第四频点调整子模块64，其中：
所述第三频点调整子模块63，用于若工作于至少一高频工作频点的内核80的数目最多，可能导致所述内核80没有发挥出最大的计算性能(因可能更高)，因此将至少一工作频点修改设置为至少一优化高频工作频点，优化高频工作频点的频率高于最高工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，最多数目的内核80工作在两个高频工作频点(700MHz和750MHz)，则将两个低频工作频点(500MHz和550MHz)修改设置为两个优化高频工作频点(800MHz和850MHz)，或者将一个低频工作频点(500MHz)和一个中频工作频点(600MHz)修改设置为两个优化高频工作频点(800MHz和850MHz)。
优选的是，所述第三频点调整子模块63用于若工作于最高工作频点上的内核80的数目最多，可能导致所述内核80没有发挥出最大的计算性能(因可能更高)，因此将一个工作频点修改设置为一个优化高频工作频点。优化高频工作频点的频率高于最高工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，数目最多的内核80工作在最高工作频点(750MHz)，则将一个低频工作频点(500MHz)修改设置为优化高频工作频点(800MHz)，或者将一个中频工作频点(600MHz)修改设置为优化高频工作频点(800MHz)；或者将最高工作频点(750MHz)修改设置为优化高频工作频点(800MHz)。
所述第四频点调整子模块64，用于若工作于至少一低频工作频点的内核80的数目最多，说明所述内核80的计算能力过差，其不足以工作在所述低频工作频点上，因此将至少一工作频点修改设置为至少一优化低频工作频点，优化低频工作频点的频率低于最低工作频点的频率，以避免计算能力差的内核80影响运算芯片的整体计算性能。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，数目最多的内核80工作在两个低频工作频点(500MHz和550MHz)，则将两个低频工作频点(500MHz和550MHz)修改设置为两个优化低频工作 频点(400MHz和450MHz)，或者将一个低频工作频点(500MHz)和一个中频工作频点(600MHz)修改设置为两个优化低频工作频点(400MHz和450MHz)。
优选的是，第四频点调整子模块64用于若工作于最低工作频点的内核80的数目最多，说明所述内核80的计算能力过差不足以工作在所述最低工作频点上，因此将一个工作频点修改设置为一个优化低频工作频点。优化低频工作频点的频率低于最低工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，数目最多的内核80工作在最低工作频点(500MHz)，则将一个低频工作频点(500MHz)修改设置为优化低频工作频点(450MHz)，或者将一个中频工作频点(600MHz)修改设置为优化低频工作频点(450MHz)；或者将最高工作频点(750MHz)修改设置为优化低频工作频点(450MHz)。
在本发明一个具体应用实施例中：使用6个锁相环电路70，设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。
按照4块算力板统计出的各对应频率上分布的内核数目如下：
算力板0：[294 26 96  224 1023 1665]
算力板1：[274 47 111 212  963 1721]
算力板2：[350 25 153 369 1381 1050]
算力板3：[488 33 184 367 1342  950]
以上述四块算力板0～3为例，如图7所示，数据大致符合正态分布，最低工作频点(500Mhz)为单个内核80工作的最低频率，无法再向下调整(如果错误率过高，可以考虑关闭该最低频点)；而最高工作频点(750Mhz)上积累的内核80的数目最多，则意味着没有发挥出最大的效率(因可能更高)，整个运算芯片还有进一步提升的空间。比较理想状态是超过预定的比率(如50％)或最多数目的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)。为充分利用内核80的计算性能，更应该考虑高能力侧的长尾，而不是低频点长尾。
以算力板0～1为例，可以看出，如果将600Mhz频点去除，大概有100个内核80频点落到550频点上，当前的频率设置明显在左侧低频区，更适合整体右移，即采用整体偏移方式，通过如图2所示的锁相环电路70将550Mhz 频点整体向右设置为800Mhz频点以上，则有望使得数百个内核80提高到800M以上，从而带来整体性能的提升。
在本发明又一具体实例中，所述频点调整模块60还包括第一停止调整子模块65或者第二停止调整子模块66，其中：
第一停止调整子模块65，用于若超过预定的第四比率的内核80工作于至少一中间工作频点上，停止调整设置工作频点的频率。因为比较理想状态就是超过预定的第四比率(如50％)的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)，其能充分发挥内核80的工作性能，故此时不需要再对内核80进行调频。
第二停止调整子模块66，用于若工作于在至少一中间工作频点上的内核80的数目最多，停止调整设置工作频点的频率。因为比较理想状态就是最多数目的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)，其能充分发挥内核80的工作性能，故此时不需要再对内核80进行调频。
本发明还提供一种包括有如所述芯片调频装置100的算力板。
本发明还提供一种包括有所述芯片调频装置100的计算设备。
图8是本发明计算设备的芯片调频方法的流程图，其可通过所述计算设备的芯片调频装置100实现，所述计算设备包括至少一个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。需指出的是，本发明芯片调频技术实际涉及两个层级的频率调整机制：运算芯片层面的频率调整机制和内核层面的频率调整机制。所述运算芯片层面的频率调整机制是指为每个运算芯片设置若干合适的工作频点，并让运算芯片的各个内核80工作于各个工作频点，充分发挥每个内核80的工作性能。所述内核层面的频率调整机制是指根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。所述方法包括步骤有：
步骤S801，为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。
本步骤根据运算芯片的频率调整机制，为每个运算芯片设置若干不同的频 点，并让运算芯片的各个内核80工作于各个工作频点。例如设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。本发明工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。在启动调频开关时(尚未对内核80进行调频)，内核80可以按照预定规则被平均分布、不平均分布或随机分布于所述工作频点上工作。优选的是，本步骤可以通过如图2所示的多个锁相环电路70为运算芯片设置多个工作频点，当然也可以通过其他硬件或软件为运算芯片设置多个工作频点。
步骤S802，分析每个内核80在当前工作频点的计算性能指标。
所述计算性能指标代表内核80在当前工作频点的实际计算性能，包括但不限于计算正确率、计算正确数量、计算速度等。若内核80的计算性能指标较高，则表示所述内核80的计算性能可能还有提升空间；若内核80的计算性能指标较低，则表示所述内核80的计算性能可能不足以在当前工作频点对应的频率下工作。
步骤S803，根据内核80的计算性能指标，对内核80的当前工作频点进行上调或下调。
本步骤根据内核的频率调整机制，将根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。优选的是，若内核80在调整周期内的计算正确率达到第一正确率阈值，表明该内核80尚未达到最佳计算性能，因此将内核80的当前工作频点上调到上一个工作频点；若内核80在调整周期内的计算正确率未达到第二正确率阈值，表明该内核80的计算性能不足以在当前工作频点上工作，因此将内核80的当前工作频点下调到下一个工作频点。
本发明根据运算芯片中各个内核80的实际计算性能评价内核80的工作性能，调节内核80对应频率，充分发挥性能较优内核80的计算优势，并避免性能较弱内核80影响运算芯片的运算性能，最大程度发挥各个内核80的计算性能，进而提高运算芯片及整体计算设备的计算速度和计算正确率。并且，本发明运算芯片的内核80不会来回变动频率，工作频率相对稳定。
图9是本发明第一实施例中计算设备的芯片调频方法的流程图，其可通过 如图2所示的计算设备的芯片调频装置100实现，所述计算设备包括至少一个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述方法包括步骤有：
步骤S901，通过多个锁相环电路70为运算芯片设置多个工作频点，工作频点与锁相环电路70为一一对应关系。
优选的是，如图2所示的锁相环电路70设置于运算芯片的内部或外部。本发明中各工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。例如设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。因此，本发明可以设置更多的锁相环电路70来设置更多的工作频点，以使得各个内核80的计算性能充分发挥。
值得提醒的是，本发明中工作频点之间的频差需要控制在合理范围。因为当内核80提高一个工作频点，该内核的工作频率将提高一个频差值，其可以因为计算速度的提高进而提升一定的计算性能。于此同时，提升内核的工作频率，其可能因为计算正确率的降低进而损耗一定的计算性能。所以频点设置模块10应该合理控制相邻的工作频点之间的频差，使得内核80从当前工作频点上调到上一个工作频点时，内核80的计算性能的受益应大于损失。优选的是，相邻的工作频点之间的频差为1～10％。
步骤S902，分析每个内核80在当前工作频点的计算性能指标。
所述计算性能指标代表内核80在当前工作频点的实际计算性能，包括但不限于计算正确率、计算正确数量、计算速度等。若内核80的计算性能指标较高，则表示所述内核80的计算性能可能还有提升空间；若内核80的计算性能指标较低，则表示所述内核80的计算性能可能不足以在当前工作频点对应的频率下工作。
本步骤优选的是，在预定的调整周期内，分析内核80的计算性能指标是否达到预定的第一指标阈值、第二指标阈值和/或第三指标阈值，第一指标阈值与第二指标阈值相同或者不相同。
步骤S903，根据内核80的计算性能指标，通过如图2所示的锁相环电路70对内核80的当前工作频点进行上调或下调。当然，本步骤也可以通过其他硬件或软件实现对内核80的当前工作频点进行上调或下调。
本步骤优选进一步包括：
(1)若内核80的计算性能指标达到第一指标阈值，将内核80的当前工作频点上调到上一个工作频点；
(2)若内核80的计算性能指标未达到第二指标阈值，将内核80的当前工作频点下调到下一个工作频点；和/或
(3)若内核80的计算性能指标达到第三指标阈值，将内核80的当前工作频点下调到下一个工作频点。
例如，结合上述“例如设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。”，以及内核80的当前工作频点为600MHz为例，所述计算性能指标为内核80在调整周期内的计算正确率，第一指标阈值和第二指标阈值均为90％。若内核80在调整周期内的计算正确率达到90％，表示所述内核80的计算性能较好，则将内核80的当前工作频点600MHz上调到上一个工作频点650MHz；若内核80在调整周期内的计算正确率未达到90％，表示所述内核80的计算性能较弱，则将内核80的当前工作频点600MHz下调到下一个工作频点550MHz。本领域技术人员可以理解的是，上一个工作频点并不仅限于上一相邻工作频点，也可设置一个以上的上一相邻工作频点作为上一个工作频点；下一个工作频点并不仅限于下一相邻工作频点，也可设置一个以上的下一相邻工作频点作为下一个工作频点。优选的是，当前工作频点与上一个工作频点之间的频差为1～10％，以及当前工作频点与下一个工作频点的频差为1～10％，使得内核80从当前工作频点上调到上一个工作频点或下一个工作频点时，内核80的计算性能的受益应大于损失。即为，将内核80的当前工作频点600MHz上调到上一个工作频点700MHz；将内核80的当前工作频点600MHz下调到下一个工作频点500MHz。以此类推，此处不对上一工作频点，下一工作频点的间距作限定。
再例如，所述计算性能指标为内核80在调整周期内的计算正确率，第一指标阈值为90％，第二指标阈值为80％。若内核80在调整周期内的计算正确率达到90％，表示所述内核80的计算性能较好，则将内核80的当前工作频点600MHz上调到上一个工作频点650MHz；若内核80在调整周期内的计算正确率未达到80％，表示所述内核80的计算性能较弱，则将内核80的当前工作频点600MHz下调到下一个工作频点550MHz。
又例如，所述计算性能指标为内核80在调整周期内的正确计算次数和错误结算次数，第一指标阈值为100，第二指标阈值为10。若内核80在调整周期内的正确计算次数达到100，表示所述内核80的计算性能较好，则将内核80的当前工作频点600MHz上调到上一个工作频点650MHz；若内核80在调整周期内的错误计算次数达到10，表示所述内核80的计算性能较弱，则将内核80的当前工作频点600MHz下调到下一个工作频点550MHz。
步骤S904，若工作于预定的至少一个优化工作频点的内核80超过预定的第一比率，停止对内核80进行调频；或者若工作于至少一优化工作频点上的内核80的数目最多，停止对内核80进行调频。
例如，可在若干工作频点中选择预设一个或多个优化工作频点，若大多数内核80的工作频率已经到达该优化工作频点，表明运算芯片中个内核80的工作频率已经处于优化状态，可充分发挥各个内核80的计算性能，不再需要进一步调频，因此停止内核80工作频率的调整。例如设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，选择其中两个优化工作频点600Mhz和650Mhz为优化工作频点，若超过50％的内核80工作于工作频点600Mhz和650Mhz，则停止对内核80进行调频。
图10是本发明第二实施例中计算设备的芯片调频方法的流程图，其可通过如图3所示的计算设备的芯片调频装置100实现，所述计算设备包括至少一个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述方法包括步骤有：
步骤S1001，为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。
本步骤根据运算芯片层面的频率调整机制，为每个运算芯片设置若干不同的频点，并让运算芯片的各个内核80工作于各个工作频点。例如设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。本发明工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。在启动调频开关时(尚未对内核80进行调频)，内核80可以按照预定规则被平均分布、不平均分布或随机分布于所述工作频点上工作。
本步骤优选的是，通过如图2所示的多个锁相环电路70为运算芯片设置 多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点，工作频点与锁相环电路70为一一对应关系。本发明可以设置更多的锁相环电路70来设置更多的工作频点，以使得各个内核80的计算性能充分发挥。当然也可以通过其他硬件或软件为运算芯片设置多个工作频点。
值得提醒的是，本发明中工作频点之间的频差需要控制在合理范围。因为当内核80提高一个工作频点，该内核的工作频率将提高一个频差值，其可以因为计算速度的提高进而提升一定的计算性能。于此同时，提升内核的工作频率，其可能因为计算正确率的降低进而损耗一定的计算性能。所以应该合理控制相邻的工作频点之间的频差，使得内核80从当前工作频点上调到上一个工作频点时，内核80的计算性能的受益应大于损失。优选的是，相邻的工作频点之间的频差为1～10％。
步骤S1002，在预定的调整周期内，分析内核80的计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值。所述第一正确率阈值与第二正确率阈值相同或者不相同。若内核80的计算正确率达到预定的第一正确率阈值，则表示所述内核80的计算性能可能还有提升空间；若内核80的计算正确率未达到预定的第二正确率阈值，则表示所述内核80的计算性能可能不足以在当前工作频点对应的频率下工作。
优选的是，本步骤S1002进一步包括：
(1)根据预设的实时调整指令，实时分析内核80在调整周期内的计算正确率是否达到第一正确率阈值和/或第二正确率阈值；
(2)根据预设的定时调整指令，在定时调整指令设定的调整时间段内，分析内核80在调整周期内的计算正确率是否达到第一正确率阈值和/或第二正确率阈值；或者
(3)根据接收的即时调整指令，分析内核80在调整周期内的计算正确率是否达到第一正确率阈值和/或第二正确率阈值。
步骤S1003，若内核80的计算正确率达到第一正确率阈值，表明该内核80尚未达到最佳计算性能，将内核80的当前工作频点上调到上一个工作频点。
优选的是，本步骤进一步包括：
(1)若内核80在调整周期内的计算正确率达到第一正确率阈值，实时将内核80的当前工作频点上调到上一个工作频点；
(2)在调整时间段内，若内核80在调整周期内的计算正确率达到第一正确率阈值，将内核80的当前工作频点上调到上一个工作频点；或者
(3)根据接收的即时调整指令，若内核80在调整周期内的计算正确率达到第一正确率阈值，将内核80的当前工作频点上调到上一个工作频点。并根据接收的停止调整指令，停止对内核80的当前工作频点的调整。
例如，用户可根据需要随时向计算设备发送即时调整指令，计算设备根据该即时调整指令立即开始分析内核80的计算正确率，若在调整周期(例如10分钟)内，若内核80的计算正确率超过第一正确率阈值(例如高于99％)，则将内核80的工作频率向上调整；若在调整周期(例如10分钟)内，所述内核80的计算正确率低于第二正确率阈值(例如低于99％)，则将内核80的工作频率向下调整。此外，用户可根据需要随时向计算设备发送停止调整指令，计算设备收到该停止调整指令后，立即停止对内核80的调频。
步骤S1004，若内核80的计算正确率未达到第二正确率阈值，表明该内核80的计算性能不足以在当前工作频点上工作，将内核80的当前工作频点下调到下一个工作频点。
优选的是，本步骤进一步包括：
(1)若内核80在调整周期内的计算正确率未达到第二正确率阈值，实时将内核80的当前工作频点下调到下一个工作频点；
(2)在调整时间段内，若内核80在调整周期内的计算正确率未达到第二正确率阈值，将内核80的当前工作频点下调到下一个工作频点；或者
(3)若内核80在调整周期内的计算正确率未达到第二正确率阈值，将内核80的当前工作频点下调到下一个工作频点。并根据接收的停止调整指令，停止对内核80的当前工作频点的调整。
本发明可通过如图2所示的锁相环电路70或软件对内核80进行调频。即根据内核层面的频率调整机制，将根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。
例如，第一正确率阈值和第二正确率阈值均为90％。当内核80工作在600MHz时，若内核80在预定的调整周期内的计算正确率超过90％(表明该内核80尚未达到最佳计算性能)，则将内核80的当前工作频点600MHz上调 到上一个工作频点，即提高其工作频率至650MHz；若内核80的计算正确率低于90％(表明该内核80的计算性能不足以在该当前工作频点600MHz的频率下工作)，则将内核80的当前工作频点下调到下一个工作频点，即降低其工作频率至550MHz。本领域技术人员可以理解的是，上一个工作频点并不仅限于上一相邻工作频点，也可设置一个以上的上一相邻工作频点作为上一个工作频点；下一个工作频点并不仅限于下一相邻工作频点，也可设置一个以上的下一相邻工作频点作为下一个工作频点。优选的是，当前工作频点与上一个工作频点之间的频差为1～10％，以及当前工作频点与下一个工作频点的频差为1～10％，使得内核80从当前工作频点上调到上一个工作频点或下一个工作频点时，内核80的计算性能的受益应大于损失。即为，将内核80的当前工作频点600MHz上调到上一个工作频点700MHz；将内核80的当前工作频点600MHz下调到下一个工作频点500MHz。以此类推，此处不对上一工作频点，下一工作频点的间距作限定。
再例如，第一正确率阈值为90％，第二正确率阈值均为80％。当内核80工作在600MHz时，若内核80在预定的调整周期内的计算正确率超过90％(表明该内核80尚未达到最佳计算性能)，则将内核80的当前工作频点上调到上一个工作频点，即提高其工作频率至650MHz；若内核80的计算正确率低于80％(表明该内核80的计算性能不足以在该当前工作频点600MHz的频率下工作)，则将内核80的当前工作频点下调到下一个工作频点，即降低其工作频率至550MHz。
图11是本发明第二实施例中计算设备的优选芯片调频方法的流程图，其可通过如图3所示的计算设备的芯片调频装置100实现，所述计算设备包括至少一个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。优选的是，所述计算正确率可为内核80在调整周期内提交的Nonce的计算正确率。即预定时间内，内核80所提交的全部Nonce中，正确Nonce所占的比率。区块头包括所述Nonce(4字节)，Nonce是一个随机值，矿工的作用其实就是猜出Nonce的值，使得区块头的哈希(Hash)可以小于目标值，从而能够写入区块链。具体而言，将这个属性从0开始，遍历到2^32，来计算区块头的哈希值，如果得到的哈希结果符合条件，则挖矿成功。所述方法包括步骤有：
步骤S1101，为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。
步骤S1102，在调整周期内，分析内核80提交的Nonce是否正确。
本步骤优选包括：
(1)在调整周期内，内核80每递交一个Nonce后，内核80将Nonce通过预定的算法计算出第一结果，第一结果中包含有第一特征。每个内核80提交的Nonce中，包含Nonce的标识信息(ID)，从而可实现对每个内核80的计算结果进行统计。
(2)运算芯片的验算单元将Nonce通过相同的算法计算出第二结果，第二结果中包含有第二特征。
(3)若第一特征与第二特征相同，则验算单元判定Nonce是正确Nonce，否则判定Nonce是错误Nonce。
例如，内核80计算出一个Nonce后提交，将所述Nonce嵌入区块头计算得到第一哈希结果，第一哈希结果的前20位的值是0(第一特征)。第一验算单元212也将该Nonce嵌入区块头计算得到第二哈希结果，若第二哈希结果的前20位的也是0(第二特征)，则认为该Nonce是一次正确提交。
步骤S1103，统计内核80在调整周期内提交的正确Nonce的个数和错误Nonce的个数。
步骤S1104，根据正确Nonce的个数和错误Nonce的个数，计算出内核80在调整周期内的Nonce计算正确率。
步骤S1105，判断Nonce计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值，若内核80的Nonce计算正确率达到第一正确率阈值则执行步骤S1106，若内核80的Nonce计算正确率未达到第二正确率阈值则执行步骤S1107。
步骤S1106，若内核80的Nonce计算正确率达到第一正确率阈值，将内核80的当前工作频点上调到上一个工作频点。
步骤S1107，若内核80的Nonce计算正确率未达到第二正确率阈值，将内核80的当前工作频点下调到下一个工作频点。
图12是本发明第三实施例中计算设备的芯片调频方法的流程图，其可通过如图4所示的计算设备的芯片调频装置100实现，所述计算设备包括至少一 个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述方法包括步骤有：
步骤S1201，为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。
本步骤根据运算芯片层面的频率调整机制，为每个运算芯片设置若干不同的频点，并让运算芯片的各个内核80工作于各个工作频点。例如设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。本发明工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。在启动调频开关时(尚未对内核80进行调频)，内核80可以按照预定规则被平均分布、不平均分布或随机分布于所述工作频点上工作。优选的是，可以通过如图2所示的多个锁相环电路70为运算芯片设置多个工作频点，当然也可以通过其他硬件或软件为运算芯片设置多个工作频点。
值得提醒的是，本发明中工作频点之间的频差需要控制在合理范围。因为当内核80提高一个工作频点，该内核的工作频率将提高一个频差值，其可以因为计算速度的提高进而提升一定的计算性能。于此同时，提升内核的工作频率，其可能因为计算正确率的降低进而损耗一定的计算性能。所以频点设置模块10应该合理控制相邻的工作频点之间的频差，使得内核80从当前工作频点上调到上一个工作频点时，内核80的计算性能的受益应大于损失。优选的是，相邻的工作频点之间的频差为1～10％。
步骤S1202，预先设置内核80的参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和计算错误阈值。
优选的是，所述计算正确权重值和计算错误权重值可以相同或不相同；所述计算正确阈值和计算错误阈值可以相同或不相同。所述参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和计算错误阈值均属于可调参数，可根据频率调节快慢等实际需要进行优化设置。
优选的是，根据实际需求设置和调整内核80的参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和/或计算错误阈值，计算正确权重值和计算错误权重值相同或者不相同，计算正确阈值和计算错误阈值相同或者不相同。
通过控制计算正确权重值和计算错误权重值的比值控制内核80期望容忍的驻留差错率。驻留差错率的计算公式为：驻留差错率＝计算正确权重值/(计算正确权重值+计算错误权重值)。
通过控制计算正确权重值和计算错误权重值的绝对值大小控制调整周期。
通过控制计算正确阈值和计算错误阈值的绝对值大小控制调整周期。
步骤S1203，分析内核80的每次计算是否正确。
内核80可以进行各种不同的计算，可分析内核80的每次某种或几种计算是否正确。优选为分析内核80计算出的Nonce是否正确。
步骤S1204，内核80每正确计算至少一次，在参考节点值上增加一次计算正确权重值，并且内核80每错误计算至少一次，在参考节点值上减少一次计算错误权重值。优选的是，内核80每正确计算一次，在参考节点值上增加一次计算正确权重值。当然，也可以设置为内核80每正确计算N次(N为大于1的自然数)，在参考节点值上增加一次计算正确权重值。内核80每错误计算一次，在参考节点值上减少一次计算错误权重值。当然，可以设置为内核80每错误计算N次(N为大于1的自然数)，在参考节点值上减少一次计算错误权重值。
步骤S1205，判断内核80的当前参考节点值是否达到计算正确阈值或计算错误阈值。若内核80的当前参考节点值达到计算正确阈值，则执行步骤S1206，若内核80的当前参考节点值达到计算错误阈值，则执行步骤S1207。
本步骤优选包括：
(1)根据预设的实时调整指令，实时判断内核80的当前参考节点是否达到计算正确阈值或计算错误阈值；或者
(2)根据预设的定时调整指令，在定时调整指令设定的调整时间段内，判断内核80的当前参考节点是否达到计算正确阈值或计算错误阈值；或者
(3)根据接收的即时调整指令，分析内核80的当前参考节点是否达到计算正确阈值或计算错误阈值。
步骤S1206，若内核80的当前参考节点值达到计算正确阈值，表明该内核80尚未达到最佳计算性能，将内核80的当前工作频点上调到上一个工作频点。
本步骤优选包括：
(1)若内核80的当前参考节点值达到计算正确阈值，实时将内核80的 当前工作频点上调到上一个工作频点；或者
(2)在调整时间段内，若内核80的当前参考节点值达到计算正确阈值，将内核80的当前工作频点上调到上一个工作频点；或者
(3)根据接收的即时调整指令，若内核80的当前参考节点值达到计算正确阈值，将内核80的当前工作频点上调到上一个工作频点。并且根据接收的停止调整指令，停止对内核80的当前工作频点的调整。
步骤S1207，若内核80的当前参考节点值达到计算错误阈值，表明该内核80的计算性能不足以在当前工作频点上工作，将内核80的当前工作频点下调到下一个工作频点。
本步骤优选包括：
(1)若内核80的当前参考节点值达到计算错误阈值，实时将内核80的当前工作频点下调到下一个工作频点；或者
(2)在调整时间段内，若内核80的当前参考节点值达到计算错误阈值，将内核80的当前工作频点下调到下一个工作频点；或者
(3)若内核80的当前参考节点值达到计算错误阈值，将内核80的当前工作频点下调到下一个工作频点。并且根据接收的停止调整指令，停止对内核80的当前工作频点的调整。
例如，用户可根据需要随时向计算设备发送即时调整指令，用户设置内核80每计算正确Nonce一次，在参考节点上增加权重A，内核80每计算错误Nonce一次，在该参考节点上减少权重B。当前增加数值达到计算正确数量阈值C时，将内核80向上一频点进阶。当前减少数值达到计算错误数阈值D时，将内核80向下一个频点降阶。此外，用户可根据需要随时向计算设备发送停止调整指令，计算设备收到该停止调整指令后，立即停止对内核80的调频。
本领域技术人员可以理解的是，上一个工作频点并不仅限于上一相邻工作频点，也可设置一个以上的上一相邻工作频点作为上一个工作频点；下一个工作频点并不仅限于下一相邻工作频点，也可设置一个以上的下一相邻工作频点作为下一个工作频点。优选的是，当前工作频点与上一个工作频点之间的频差为1～10％，以及当前工作频点与下一个工作频点的频差为1～10％，使得内核80从当前工作频点上调到上一个工作频点或下一个工作频点时，内核80的计算性能的受益应大于损失。即为，将内核80的当前工作频点600MHz上调到 上一个工作频点700MHz；将内核80的当前工作频点600MHz下调到下一个工作频点500MHz。以此类推，此处不对上一工作频点，下一工作频点的间距作限定。
本步骤优选可通过如图2所示的锁相环电路70或软件对内核80进行调频。即根据内核层面的频率调整机制，将根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。
例如，如图5所示，设置400000作为参考节点值，计算正确权重值设为180，计算错误权重值设为9000，计算正确阈值和计算错误阈值均设为100000。
内核80每正确计算至少一次，在该参考节点值上加180(计算正确权重值)；内核80每错误计算至少一次，在该参考节点值上减少9000(计算错误权重值)；以所述参考节点值为基准，每增加或减少100000(计算正确阈值和计算错误阈值)，向上一频点进阶或向下一频点降阶。
当前机制类似于错误和正确的拔河比赛机制，正确和错误可具有不同的权重。设置参考节点值，每收到一次正确结果，增加一次计算正确权重值，每收到一个错误结果，减少一次计算错误权重值，如果奖励或惩罚超过对应侧门限，则进行频率的上调或下调。可以理解调整系统有一个marker，参考节点值是maker的初始值，如果有正确提交则maker+180，每次错误提交则maker-9000。经过N次正确(N为大于或等于1的自然数)，M次错误后(M为大于或等于1的自然数)，marker应该处在400000+N*180-M*9000的位置，如果Marker超过某侧门限则进行相应频率调整(上调或下调)。然后每次频率调整到新的频点上都初始化该值，即将当前参考节点值重新设置为初始的参考节点值。
图13是本发明第三实施例中计算设备的优选芯片调频方法的流程图，其可通过如图4所示的计算设备的芯片调频装置100实现，所述计算设备包括至少一个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述方法包括步骤有：
步骤S1301，为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。
步骤S1302，预先设置内核80的参考节点值、计算正确权重值、计算错误 权重值、计算正确阈值和计算错误阈值。
步骤S1303，分析内核80每次提交的Nonce是否正确。
优选的是，本步骤进一步包括：
(1)内核80递交一个Nonce后，内核80将Nonce通过预定的算法计算出第一结果，第一结果中包含有第一特征。
(2)运算芯片的验算单元将Nonce通过相同的算法计算出第二结果，第二结果中包含有第二特征。
(3)若第一特征与第二特征相同，则验算单元判定Nonce是正确Nonce，否则判定Nonce是错误Nonce。
例如，内核80计算出一个Nonce后提交，将所述Nonce嵌入区块头计算得到第一哈希结果，第一哈希结果的前20位的值是0(第一特征)。第二验算单元252也将该Nonce嵌入区块头计算得到第二哈希结果，若第二哈希结果的前20位的也是0(第二特征)，则认为该Nonce是一次正确提交。
步骤S1304，内核80每提交至少一次正确Nonce，在参考节点值上增加一次计算正确权重值，内核80每提交至少一次错误Nonce，在参考节点值上减少一次计算错误权重值。优选的是，在内核80每提交一次正确Nonce，在参考节点值上增加一次计算正确权重值。当然，也可以设置为内核80每提交N(N为大于1的自然数)次正确Nonce，在参考节点值上增加一次计算正确权重值。内核80每提交一次错误Nonce，在参考节点值上减少一次计算错误权重值。当然，也可以设置为内核80每提交N(N为大于1的自然数)次错误Nonce，在参考节点值上减少一次计算错误权重值。
步骤S1305，判断内核80的当前参考节点值是否达到计算正确阈值或计算错误阈值。若内核80的当前参考节点值达到计算正确阈值，则执行步骤S1206，若内核80的当前参考节点值达到计算错误阈值，则执行步骤S1207。
步骤S1306，若内核80的当前参考节点值达到计算正确阈值，将内核80的当前工作频点上调到上一个工作频点。
步骤S1307，若内核80的当前参考节点值达到计算错误阈值，将内核80的当前工作频点下调到下一个工作频点。
在本发明一个具体应用实施例中：使用6个锁相环电路70，设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。如图5 所示，并设置400000作为参考节点值，计算正确权重值设为180，计算错误权重值设为9000，计算正确阈值和计算错误阈值均设为100000。
按照4块算力板统计出的各对应频率上分布的内核数目如下：
算力板0：[294 26 96  224 1023 1665]
算力板1：[274 47 111 212  963 1721]
算力板2：[350 25 153 369 1381 1050]
算力板3：[488 33 184 367 1342  950]
首先，结合数据进一步说明机制。根据驻留差错率S＝计算正确权重值/(计算正确权重值+计算错误权重值)，并通过给定的数据可以推算出内核80的驻留差错率S(理解为可长期驻留在某个频点)为180/(180+9000)＝1.29％，此时内核80长久的工作在某个频点上(因为此时期望步长为0)，工作频率不会上调或下调。可以推知，若内核80的计算错误率大于1.29％(驻留差错率S)，其工作频率将被上调；若内核80的计算错误率小于1.29％(驻留差错率S)，其工作频率将被下调。
依据设置的难度(该难度与检验基准有关，对内核80计算正确率有影响，难度系数越大，正确率越低；反之则正确率越高)，可以推算出错误上升时调整的大致周期，假定错误率为e，则每个Nonce的期望步长为：(1-e)*180-e*9000＝180-9180e。以e＝0.5％为例，期望步长＝134.1；以e＝1％为例，期望步长＝88.2；以e＝2％为例，期望步长＝-3.6。
以650MHz计算，内核80提交单个Nonce的期望为1.3个/秒(即1秒递交1.3个Nonce)。以e为0.5％的场景进行解释，即在746次的Nonce提交过程后，就可以预期向上调整一次；e为1.0％需要1134次提交，预期向上调整一次，如果错误概率为2.0％，则需要27778次提交，预期向下调整一次，其他类推。
图14是本发明第四实施例中计算设备的芯片调频方法的流程图，其可通过所述计算设备的芯片调频装置100实现，所述计算设备包括至少一个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述方法包括步骤有：
步骤S1401，为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。
本步骤根据运算芯片层面的频率调整机制，为每个运算芯片设置若干不同的频点，并让运算芯片的内核80工作于各个工作频点。例如设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。各工作频点的频点个数、频率之间差距可根据实际需要设置，工作频点越多越能充分发挥各个内核80的计算性能。在启动调频开关时(尚未对内核80进行调频之前)，内核80可以按照预定规则平均分布、不平均分布或随机分布于所述工作频点。本步骤可以通过多个如图2所示的锁相环电路70为运算芯片设置多个工作频点，当然本步骤也可以通过其他硬件或软件为运算芯片设置多个工作频点。
值得提醒的是，本发明中工作频点之间的频差需要控制在合理范围。因为当内核80提高一个工作频点，该内核的工作频率将提高一个频差值，其可以因为计算速度的提高进而提升一定的计算性能。于此同时，提升内核的工作频率，其可能因为计算正确率的降低进而损耗一定的计算性能。所以频点设置模块10应该合理控制相邻的工作频点之间的频差，使得内核80从当前工作频点上调到上一个工作频点时，内核80的计算性能的受益应大于损失。优选的是，相邻的工作频点之间的频差为1～10％。
步骤S1402，分析每个内核80在当前工作频点的计算性能指标。
所述计算性能指标代表内核80在当前工作频点的实际计算性能，包括但不限于计算正确率、计算正确数量、计算速度等。若内核80的计算性能指标较高，则表示所述内核80的计算性能可能还有提升空间；若内核80的计算性能指标较低，则表示所述内核80的计算性能可能不足以在当前工作频点对应的频率下工作。
步骤S1403，根据内核80的计算性能指标，对内核80的当前工作频点进行上调或下调。
本步骤根据内核层面的频率调整机制，将根据内核80的实际计算性能，将内核80调整到合适的工作频点，上调计算性能高的内核80的频率，下调计算性能低的内核80的频率，从而充分发挥每个内核80的计算性能。本步骤可通过如图2所示的锁相环电路70或软件对内核80进行调频。优选的是，若内核80在调整周期内的计算正确率达到第一正确率阈值，表明该内核80尚未达到最佳计算性能，因此将内核80的当前工作频点上调到上一个工作频点；若内核80在调整周期内的计算正确率未达到第二正确率阈值，表明该内核80 的计算性能不足以在当前工作频点上工作，因此将内核80的当前工作频点下调到下一个工作频点。
本领域技术人员可以理解的是，上一个工作频点并不仅限于上一相邻工作频点，也可设置一个以上的上一相邻工作频点作为上一个工作频点；下一个工作频点并不仅限于下一相邻工作频点，也可设置一个以上的下一相邻工作频点作为下一个工作频点。优选的是，当前工作频点与上一个工作频点之间的频差为1～10％，以及当前工作频点与下一个工作频点的频差为1～10％，使得内核80从当前工作频点上调到上一个工作频点或下一个工作频点时，内核80的计算性能的受益应大于损失。即为，将内核80的当前工作频点600MHz上调到上一个工作频点700MHz；将内核80的当前工作频点600MHz下调到下一个工作频点500MHz。以此类推，此处不对上一工作频点，下一工作频点的间距作限定。
步骤S1404，统计被调频后的内核80在各工作频点上的当前分布状态。
内核80的工作频点根据自身计算性能被自动调频后，会分布在各工作频点上工作，统计被调频后的内核80在各工作频点上的分布个数可得出当前分布状态。优选的是，可将工作频点划分为包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，高频工作频点中频率最高的是最高工作频点，低频工作频点中频率最低的是最低工作频点。例如一共有1000个内核80，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，依次其分布在上述6个工作频点的个数分别为：100，200，100，100，200，300。其中，500MHz，550MHz为低频工作频点，600MHz，650MHz为中间工作频点，700MHz，750MHz为高频工作频点，500MHz为最低工作频点，750MHz为最高工作频点。
步骤S1405，根据当前分布状态和预定的频点调整机制，调整设置工作频点的频率，所述频点调整机制是内核80分布状态与频点调整的对应关系。
所述频点调整机制是内核分布状态与频点调整的对应关系。所述内核分布状态是指内核80在各个工作频点上工作的分布状态。所述调整设置工作频点的频率，是指直接将工作频点的频率进行调整。优选通过如图2所示的锁相环电路70调整设置工作频点的频率。本发明理想状态是希望超过预定的比率(如50％)或最多数目的内核80落到中间工作频点，这样内核80的频率有更大的 上调空间。
例如，若超过预定的比率(如30％)的内核80工作于最高工作频点(750MHz)上，可能导致所述内核80没有发挥出最大的计算性能(因可能更高)，则需要将一工作频点(600MHz)修改设置为至少一优化高频工作频点(800MHz)，原工作于工作频点(600MHz)上的内核80将全部转移到最高工作频点(750MHz)上工作。所述优化高频工作频点的频率高于所述最高工作频点的频率，以充分发挥各内核80的计算性能。
优选的是，所述步骤S1405之后可进一步包括：
若超过预定的第四比率的内核80工作于至少一中间工作频点上，停止调整设置工作频点的频率；或者，若工作于在至少一中间工作频点上的内核80的数目最多，停止调整设置工作频点的频率。比较理想状态是超过预定的第四比率(如50％)或数目最多的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)，故此时不需要再对内核80进行调频。
图15是本发明第四实施例中计算设备的优选芯片调频方法的流程图之一，其可通过所述计算设备的芯片调频装置100实现，所述计算设备包括至少一个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述方法包括步骤有：
步骤S1501，为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。
步骤S1502，分析每个内核80在当前工作频点的计算性能指标。
步骤S1503，根据内核80的计算性能指标，对内核80的当前工作频点进行上调或下调。
步骤S1504，统计被调频后的内核80在各工作频点上的当前分布状态。工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，高频工作频点中频率最高的是最高工作频点，低频工作频点中频率最低的是最低工作频点。
步骤S1505，若超过预定的第二比率的内核80工作于至少一高频工作频点上，可能导致所述内核80没有发挥出最大的计算性能(因可能更高)，将至少一工作频点修改设置为至少一优化高频工作频点，优化高频工作频点的频率高于最高工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作 频点和/或高频工作频点。
例如，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，超过30％(第二比率)的内核80工作在两个高频工作频点(700MHz和750MHz)，则将两个低频工作频点(500MHz和550MHz)修改设置为两个优化高频工作频点(800MHz和850MHz)，或者将一个低频工作频点(500MHz)和一个中频工作频点(600MHz)修改设置为两个优化高频工作频点(800MHz和850MHz)。
本步骤优选的是，若超过第二比率的内核80工作于最高工作频点上，将一个工作频点修改设置为一个优化高频工作频点，优化高频工作频点的频率高于最高工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，超过30％(第二比率)的内核80工作在最高工作频点(750MHz)，则将一个低频工作频点(500MHz)修改设置为优化高频工作频点(800MHz)，或者将一个中频工作频点(600MHz)修改设置为优化高频工作频点(800MHz)；或者将最高工作频点(750MHz)修改设置为优化高频工作频点(800MHz)。
步骤S1506，若超过预定的第三比率的内核80工作于至少一低频工作频点上，说明所述内核80的计算能力过差不足以工作在所述低频工作频点上，因此将至少一工作频点修改设置为至少一优化低频工作频点，优化低频工作频点的频率低于最低工作频点的频率。值得注意的是，本步骤可以省略，即并不将至少一工作频点修改设置为至少一优化低频工作频点。
被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。例如，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，超过30％(第三比率)的内核80工作在两个低频工作频点(500MHz和550MHz)，则将两个低频工作频点(500MHz和550MHz)修改设置为两个优化低频工作频点(400MHz和450MHz)，或者将一个低频工作频点(500MHz)和一个中频工作频点(600MHz)修改设置为两个优化低频工作频点(400MHz和450MHz)。
本步骤优选的是，若超过第三比率的内核80工作于最低工作频点上，将一个工作频点修改设置为一个优化低频工作频点。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。例如，超过30％(第三比率) 的内核80工作在最低工作频点(500MHz)，则将一个低频工作频点(500MHz)修改设置为优化低频工作频点(450MHz)，或者将一个中频工作频点(600MHz)修改设置为优化低频工作频点(450MHz)；或者将最高工作频点(750MHz)修改设置为优化低频工作频点(450MHz)。
优选的是，所述步骤S1506之后进一步包括：
若超过预定的第四比率的内核80工作于至少一中间工作频点上，停止调整设置工作频点的频率；因为比较理想状态就是超过预定的第四比率(如50％)的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)，其能充分发挥内核80的工作性能，故此时不需要再对内核80进行调频。或者
若工作于在至少一中间工作频点上的内核80的数目最多，停止调整设置工作频点的频率。因为比较理想状态就是最多数目的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)，其能充分发挥内核80的工作性能，故此时不需要再对内核80进行调频。
在本发明一个具体应用实施例中：使用6个锁相环电路70，设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。
按照4块算力板统计出的各对应频率上分布的内核数目如下：
算力板0：[294 26 96  224 1023 1665]
算力板1：[274 47 111 212  963 1721]
算力板2：[350 25 153 369 1381 1050]
算力板3：[488 33 184 367 1342  950]
以上述四块算力板0～3为例，如图7所示，数据大致符合正态分布，最低工作频点(500Mhz)为单个内核80工作的最低频率，无法再向下调整(如果错误率过高，可以考虑关闭该最低频点)；而最高工作频点(750Mhz)上积累超过预定比率(例如50％)的内核80，则意味着没有发挥出最大的效率(因可能更高)，整个运算芯片还有进一步提升的空间。比较理想状态是超过预定的比率(如50％)或最多数目的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)。为充分利用内核80的计算性能，更应该考虑高能力侧的长尾，而不是低频点长尾。
以算力板0～1为例，可以看出，若将600Mhz频点去除，此时若采用整体左移，大概有100个内核80频点落到550频点上，当前的频率设置明显在左 侧低频区，不利于充分发挥内核80的计算性能。故更适合整体右移，即采用整体偏移方式，通过锁相环电路70将550Mhz频点整体向右设置为800Mhz频点以上，则有望使得数百个内核80提高到800M以上，从而带来整体计算性能的提升。
图16是本发明第四实施例中计算设备的优选芯片调频方法的流程图之二，其可通过所述计算设备的芯片调频装置100实现，所述计算设备包括至少一个运算芯片，所述运算芯片设置有多个内核。所述计算设备优选用于海量运算，例如用于挖掘虚拟数字货币的运算。所述方法包括步骤有：
步骤S1601，为计算设备的运算芯片设置多个工作频点，将运算芯片中的多个内核80分别工作于各工作频点。
步骤S1602，分析每个内核80在当前工作频点的计算性能指标。
步骤S1603，根据内核80的计算性能指标，对内核80的当前工作频点进行上调或下调。
步骤S1604，统计被调频后的内核80在各工作频点上的当前分布状态。工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，高频工作频点中频率最高的是最高工作频点，低频工作频点中频率最低的是最低工作频点。
步骤S1605，若工作于至少一高频工作频点的内核80的数目最多，可能导致所述内核80没有发挥出最大的计算性能(因可能更高)，因此将至少一工作频点修改设置为至少一优化高频工作频点，优化高频工作频点的频率高于最高工作频点的频率。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，最多数目的内核80工作在两个高频工作频点(700MHz和750MHz)，则将两个低频工作频点(500MHz和550MHz)修改设置为两个优化高频工作频点(800MHz和850MHz)，或者将一个低频工作频点(500MHz)和一个中频工作频点(600MHz)修改设置为两个优化高频工作频点(800MHz和850MHz)。
本步骤优选的是，若工作于最高工作频点上的内核80的数目最多，将一个工作频点修改设置为一个优化高频工作频点。被修改的工作频点可以是低频 工作频点、中频工作频点和/或高频工作频点。
例如，数目最多的内核80工作在最高工作频点(750MHz)，则将一个低频工作频点(500MHz)修改设置为优化高频工作频点(800MHz)，或者将一个中频工作频点(600MHz)修改设置为优化高频工作频点(800MHz)；或者将最高工作频点(750MHz)修改设置为优化高频工作频点(800MHz)。
步骤S1606，若工作于至少一低频工作频点的内核80的数目最多，说明所述内核80的计算能力过差不足以工作在所述低频工作频点上，因此将至少一工作频点修改设置为至少一优化低频工作频点，优化低频工作频点的频率低于最低工作频点的频率，以避免计算能力差的内核80影响运算芯片的整体计算性能。本步骤可以省略，即并不将至少一工作频点修改设置为至少一优化低频工作频点。
被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。
例如，设置6个工作频点，500MHz，550MHz，600MHz，650MHz，700MHz，750MHz，数目最多的内核80工作在两个低频工作频点(500MHz和550MHz)，则将两个低频工作频点(500MHz和550MHz)修改设置为两个优化低频工作频点(400MHz和450MHz)，或者将一个低频工作频点(500MHz)和一个中频工作频点(600MHz)修改设置为两个优化低频工作频点(400MHz和450MHz)。
本步骤优选的是，若工作于最低工作频点的内核80的数目最多，将一个工作频点修改设置为一个优化低频工作频点。被修改的工作频点可以是低频工作频点、中频工作频点和/或高频工作频点。例如，数目最多的内核80工作在最低工作频点(500MHz)，则将一个低频工作频点(500MHz)修改设置为优化低频工作频点(450MHz)，或者将一个中频工作频点(600MHz)修改设置为优化低频工作频点(450MHz)；或者将最高工作频点(750MHz)修改设置为优化低频工作频点(450MHz)。
优选的是，所述步骤S1606之后进一步包括：
若超过预定的第四比率的内核80工作于至少一中间工作频点上，停止调整设置工作频点的频率；或者
若工作于在至少一中间工作频点上的内核80的数目最多，停止调整设置 工作频点的频率。
在本发明一个具体应用实施例中：使用6个锁相环电路70，设置6个工作频点：500MHz，550MHz，600MHz，650MHz，700MHz，750MHz。
按照4块算力板统计出的各对应频率上分布的内核数目如下：
算力板0：[294 26 96  224 1023 1665]
算力板1：[274 47 111 212  963 1721]
算力板2：[350 25 153 369 1381 1050]
算力板3：[488 33 184 367 1342  950]
以上述四块算力板0～3为例，如图7所示，数据大致符合正态分布，最低工作频点(500Mhz)为单个内核80工作的最低频率，无法再向下调整(如果错误率过高，可以考虑关闭该最低频点)；而最高工作频点(750Mhz)上积累的内核80的数目最多，则意味着没有发挥出最大的效率(因可能更高)，整个运算芯片还有进一步提升的空间。比较理想状态是超过预定的比率(如50％)或最多数目的内核80落在一个或多个中间工作频点上，例如第3个工作频点(600MHz)。为充分利用内核80的计算性能，更应该考虑高能力侧的长尾，而不是低频点长尾。
以算力板0～1为例，可以看出，如果将600Mhz频点去除，大概有100个内核80频点落到550频点上，当前的频率设置明显在左侧低频区，更适合整体右移，即采用整体偏移方式，通过锁相环电路70将550Mhz频点整体向右设置为800Mhz频点以上，则有望使得数百个内核80提高到800M以上，从而带来整体性能的提升。
本发明还提供一种存储介质，用于存储如图8～图16所述任意一种计算设备的芯片调频方法的计算机程序。例如计算机程序指令，当其被计算机执行时，通过该计算机的操作，可以调用或提供根据本申请的方法和/或技术方案。而调用本申请的方法的程序指令，可能被存储在固定的或可移动的存储介质中，和/或通过广播或其他信号承载媒体中的数据流而被传输和/或被存储在根据程序指令运行的计算设备的存储器中。在此，根据本申请的一个实施例包括一个如图17所示的计算设备，所述计算设备优选包括控制板、与所述控制板连接的至少一算力板，所述控制板设置有处理器，所述算力板上设置有多个用于运算的运算芯片，所述运算芯片中设置有多个内核；该设备包括用于存储计算机 程序指令的存储介质和用于执行程序指令的处理器，其中，当该计算机程序指令被该处理器执行时，触发该计算设备执行基于前述多个实施例中的方法和/或技术方案。
需要注意的是，本申请可在软件和/或软件与硬件的组合体中被实施，例如，可采用专用集成电路(ASIC)、通用目的计算机或任何其他类似硬件设备来实现。在一个实施例中，本申请的软件程序可以通过处理器执行以实现上文步骤或功能。同样地，本申请的软件程序(包括相关的数据结构)可以被存储到计算机可读记录介质中，例如，RAM存储器，磁或光驱动器或软磁盘及类似设备。另外，本申请的一些步骤或功能可采用硬件来实现，例如，作为与处理器配合从而执行各个步骤或功能的电路。
根据本发明的方法可以作为计算机实现方法在计算机上实现、或者在专用硬件中实现、或以两者的组合的方式实现。用于根据本发明的方法的可执行代码或其部分可以存储在计算机程序产品上。计算机程序产品的示例包括存储器设备、光学存储设备、集成电路、服务器、在线软件等。优选地，计算机程序产品包括存储在计算机可读介质上以便当所述程序产品在计算机上执行时执行根据本发明的方法的非临时程序代码部件。
在优选实施例中，计算机程序包括适合于当计算机程序在计算机上运行时执行根据本发明的方法的所有步骤的计算机程序代码部件。优选地，在计算机可读介质上体现计算机程序。
综上所述，本发明针对计算设备的运算芯片的内核进行自动调频，先设置多个合适的工作频点，将运算芯片中的多个内核分别工作于不同的工作频点上，然后根据每个内核在当前工作频点的计算性能指标，对内核的当前工作频点进行上调或下调，即上调计算性能高的内核的频率，下调计算性能低的内核的频率。借此，本发明能够根据计算设备的运算芯片中各个内核的实际计算性能，自动调节各个内核对应的频率，从而最大程度发挥内核的计算性能，进而提高运算芯片及整体运算设备的运算性能。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业应用性
采用本发明计算设备的芯片调频方法、装置、算力板、计算设备及存储介质，具有以下有益效果：
能够根据计算设备的运算芯片中各个内核的实际计算性能，自动调节各个内核对应的频率，从而最大程度发挥内核的计算性能，进而提高运算芯片及整体运算设备的运算性能。

Claims (50)

  1. 一种计算设备的芯片调频方法，所述计算设备设置有至少一运算芯片，所述运算芯片设置有多个内核，其特征在于，包括步骤有：
    为所述计算设备的所述运算芯片设置多个工作频点，将所述运算芯片中的多个内核分别工作于各所述工作频点；
    分析每个所述内核在当前工作频点的计算性能指标；
    根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调。
  2. 根据权利要求1所述的芯片调频方法，其特征在于，所述为所述计算设备的所述运算芯片设置多个所述工作频点，将所述运算芯片中的多个所述内核分别工作于各所述工作频点的步骤还包括：
    通过多个锁相环电路为所述运算芯片设置多个所述工作频点，所述工作频点与所述锁相环电路为一一对应关系；
    所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
    根据所述内核的所述计算性能指标，通过所述锁相环电路对所述内核的所述当前工作频点进行上调或下调。
  3. 根据权利要求2所述的芯片调频方法，其特征在于，所述锁相环电路设置于所述运算芯片的内部或外部。
  4. 根据权利要求1所述的芯片调频方法，其特征在于，相邻的所述工作频点之间的频差为1～10％。
  5. 根据权利要求1所述的芯片调频方法，其特征在于，所述分析每个所述内核在所述当前工作频点的所述计算性能指标的步骤还包括：
    在预定的调整周期内，分析所述内核的所述计算性能指标是否达到预定的第一指标阈值、第二指标阈值和/或第三指标阈值，所述第一指标阈值与所述第二指标阈值相同或者不相同；
    所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
    若所述内核的所述计算性能指标达到所述第一指标阈值，将所述内核的所 述当前工作频点上调到上一个工作频点；
    若所述内核的所述计算性能指标未达到所述第二指标阈值，将所述内核的所述当前工作频点下调到下一个工作频点；和/或
    若所述内核的所述计算性能指标达到所述第三指标阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
  6. 根据权利要求1所述的芯片调频方法，其特征在于，还包括步骤有：
    若工作于预定的至少一个优化工作频点的所述内核超过预定的第一比率，停止对所述内核进行调频；或者
    若工作于至少一所述优化工作频点上的所述内核的数目最多，停止对所述内核进行调频。
  7. 根据权利要求1所述的芯片调频方法，其特征在于，所述分析每个所述内核在所述当前工作频点的所述计算性能指标的步骤还包括：
    在预定的调整周期内，分析所述内核的计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值，所述第一正确率阈值与所述第二正确率阈值相同或者不相同；
    所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
    若所述内核的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；和/或
    若所述内核的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
  8. 根据权利要求7所述的芯片调频方法，其特征在于，所述在预定的调整周期内，分析所述内核的所述计算正确率是否达到所述第一正确率阈值和/或第二正确率阈值的步骤还包括：
    在所述调整周期内，分析所述内核提交的随机数是否正确；
    统计所述内核在所述调整周期内提交的正确随机数的个数和错误随机数的个数；
    根据所述正确随机数的个数和所述错误随机数的个数，计算出所述内核在所述调整周期内的随机数计算正确率，并判断所述随机数计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值；
    所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
    若所述内核的所述随机数计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；
    若所述内核的所述随机数计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
  9. 根据权利要求8所述的芯片调频方法，其特征在于，所述在所述调整周期内，分析所述内核提交的所述随机数是否正确的步骤还包括：
    在所述调整周期内，所述内核每递交一个所述随机数后，所述内核将所述随机数通过预定的算法计算出第一结果，所述第一结果中包含有第一特征；
    所述运算芯片的验算单元将所述随机数通过相同的所述算法计算出第二结果，所述第二结果中包含有第二特征；
    若所述第一特征与所述第二特征相同，则所述验算单元判定所述随机数是正确随机数，否则判定所述随机数是错误随机数。
  10. 根据权利要求7所述的芯片调频方法，其特征在于，所述在预定的所述调整周期内，分析所述内核的所述计算正确率是否达到预定的所述正确率阈值的步骤还包括：
    根据预设的实时调整指令，实时分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；
    根据预设的定时调整指令，在所述定时调整指令设定的调整时间段内，分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；或者
    根据接收的即时调整指令，分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；
    所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
    若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，实时将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，实时将所述内核的所述当前工作频点下调到下一个工作频点；
    在所述调整时间段内，若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；在所述调整时间段内，若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点；或者
    根据接收的即时调整指令，若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点；根据接收的停止调整指令，停止对所述内核的所述当前工作频点的调整。
  11. 根据权利要求1所述的芯片调频方法，其特征在于，所述分析每个所述内核在所述当前工作频点的所述计算性能指标的步骤还包括：
    预先设置所述内核的参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和计算错误阈值；
    分析所述内核的每次计算是否正确；
    所述内核每正确计算至少一次，在所述参考节点值上增加一次所述计算正确权重值，并且所述内核每错误计算至少一次，在所述参考节点值上减少一次所述计算错误权重值；
    判断所述内核的当前参考节点值是否达到所述计算正确阈值或所述计算错误阈值；
    所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤还包括：
    若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；
    若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
  12. 根据权利要求11所述的芯片调频方法，其特征在于，所述分析所述内核的每次计算是否正确的步骤还包括：
    分析所述内核每次提交的随机数是否正确；
    所述内核每正确计算至少一次，在所述参考节点值上增加一次所述计算正 确权重值，并且所述内核每错误计算至少一次，在所述参考节点值上增加一次所述计算错误权重值的步骤还包括：
    所述内核每提交至少一次正确随机数，在所述参考节点值上增加一次所述计算正确权重值，所述内核每提交至少一次错误随机数，在所述参考节点值上减少一次所述计算错误权重值。
  13. 根据权利要求12所述的芯片调频方法，其特征在于，所述分析所述内核每次提交的所述随机数是否正确的步骤还包括：
    所述内核递交一个所述随机数后，所述内核将所述随机数通过预定的算法计算出第一结果，所述第一结果中包含有第一特征；
    所述运算芯片的验算单元将所述随机数通过相同的所述算法计算出第二结果，所述第二结果中包含有第二特征；
    若所述第一特征与所述第二特征相同，则所述验算单元判定所述随机数是正确随机数，否则判定所述随机数是错误随机数。
  14. 根据权利要求11所述的芯片调频方法，其特征在于，所述方法还包括：
    根据实际需求设置和调整所述内核的所述参考节点值、所述计算正确权重值、所述计算错误权重值、所述计算正确阈值和/或所述计算错误阈值，所述计算正确权重值和所述计算错误权重值相同或者不相同，所述计算正确阈值和所述计算错误阈值相同或者不相同；
    通过控制所述计算正确权重值和所述计算错误权重值的比值控制所述内核期望容忍的驻留差错率；
    通过控制所述计算正确权重值和所述计算错误权重值的绝对值大小控制调整周期；
    通过控制所述计算正确阈值和所述计算错误阈值的绝对值大小控制所述调整周期。
  15. 根据权利要求14所述的芯片调频方法，其特征在于，所述驻留差错率的计算公式为：驻留差错率＝计算正确权重值/(计算正确权重值+计算错误权重值)。
  16. 根据权利要求11所述的芯片调频方法，其特征在于，所述判断所述内核的当前参考节点值是否达到所述计算正确阈值或所述计算错误阈值的步 骤还包括：
    根据预设的实时调整指令，实时判断所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；
    根据预设的定时调整指令，在所述定时调整指令设定的调整时间段内，判断所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；或者
    根据接收的即时调整指令，分析所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；
    所述根据所述内核的所述计算性能指标，将所述内核的所述当前工作频点进行上调或下调的步骤还包括：
    若所述内核的所述当前参考节点值达到所述计算正确阈值，实时将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核的所述当前参考节点值达到所述计算错误阈值，实时将所述内核的所述当前工作频点下调到下一个工作频点；
    在所述调整时间段内，若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；在所述调整时间段内，若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点；或者
    根据接收的即时调整指令，若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点；根据接收的停止调整指令，停止对所述内核的所述当前工作频点的调整。
  17. 根据权利要求1所述的芯片调频方法，其特征在于，所述根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调的步骤之后还包括：
    统计被调频后的所述内核在各所述工作频点上的当前分布状态；
    根据所述内核的所述当前分布状态和预定的频点调整机制，调整设置所述工作频点的频率，所述频点调整机制是内核分布状态与频点调整的对应关系。
  18. 根据权利要求17所述的芯片调频方法，其特征在于，所述工作频点 包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，所述高频工作频点中频率最高的是最高工作频点，所述低频工作频点中频率最低的是最低工作频点；
    所述根据所述内核的所述当前分布状态和所述频点调整机制，调整设置所述工作频点的频率的步骤还包括：
    若超过预定的第二比率的所述内核工作于至少一所述高频工作频点上，将至少一所述工作频点修改设置为至少一优化高频工作频点，所述优化高频工作频点的频率高于所述最高工作频点的频率；和/或
    若超过预定的第三比率的所述内核工作于至少一所述低频工作频点上，将至少一所述工作频点修改设置为至少一优化低频工作频点，所述优化低频工作频点的频率低于所述最低工作频点的频率。
  19. 根据权利要求18所述的芯片调频方法，其特征在于，所述若超过所述第二比率的所述内核工作于至少一所述高频工作频点上，将至少一所述工作频点修改设置为至少一所述优化高频工作频点的步骤还包括：
    若超过所述第二比率的所述内核工作于所述最高工作频点上，将一个所述工作频点修改设置为一个所述优化高频工作频点；和/或
    所述若超过预定的所述第三比率的所述内核工作于至少一所述低频工作频点上，将至少一所述工作频点修改设置为至少一所述优化低频工作频点的步骤还包括：
    若超过所述第三比率的所述内核工作于所述最低工作频点上，将一个所述工作频点修改设置为一个所述优化低频工作频点。
  20. 根据权利要求17所述的芯片调频方法，其特征在于，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，所述高频工作频点中频率最高的是最高工作频点，所述低频工作频点中频率最低的是最低工作频点；
    所述根据所述当前分布状态和所述频点调整机制，调整设置所述工作频点的频率的步骤还包括：
    若工作于至少一所述高频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一优化高频工作频点，所述优化高频工作频点的频率高于所述最高工作频点的频率；和/或
    若工作于至少一所述低频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一优化低频工作频点，所述优化低频工作频点的频率低于所述最低工作频点的频率。
  21. 根据权利要求20所述的芯片调频方法，其特征在于，所述若工作于至少一所述高频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一所述优化高频工作频点的步骤还包括：
    若工作于所述最高工作频点上的所述内核的数目最多，将一个所述工作频点修改设置为一个所述优化高频工作频点；和/或
    所述若工作于至少一所述低频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一所述优化低频工作频点的步骤还包括：
    若工作于所述最低工作频点的所述内核的数目最多，将一个所述工作频点修改设置为一个所述优化低频工作频点。
  22. 根据权利要求17所述的芯片调频方法，其特征在于，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点；
    所述根据所述当前分布状态和所述频点调整机制，调整设置所述工作频点的频率的步骤还包括：
    若超过预定的第四比率的所述内核工作于至少一所述中间工作频点上，停止调整设置所述工作频点的频率；或者
    若工作于在至少一所述中间工作频点上的所述内核的数目最多，停止调整设置所述工作频点的频率。
  23. 根据权利要求1所述的芯片调频方法，其特征在于，所述计算设备用于挖掘虚拟数字货币的运算。
  24. 一种计算设备的芯片调频装置，所述计算设备上设置有至少一个运算芯片，所述运算芯片中设置有多个内核，其特征在于，所述芯片调频装置包括：
    频点设置模块，用于为所述计算设备的运算芯片设置多个工作频点，将所述运算芯片中的多个内核分别工作于各所述工作频点；
    计算性能分析模块，用于分析每个所述内核在当前工作频点的计算性能指标；
    频率调整模块，用于根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调。
  25. 根据权利要求24所述的芯片调频装置，其特征在于，所述频点设置模块用于通过多个锁相环电路为所述运算芯片设置多个所述工作频点，所述工作频点与所述锁相环电路为一一对应关系；
    所述频率调整模块，用于根据所述内核的所述计算性能指标，通过所述锁相环电路对所述内核的所述当前工作频点进行上调或下调。
  26. 根据权利要求25所述的芯片调频装置，其特征在于，所述锁相环电路设置于所述运算芯片的内部或外部。
  27. 根据权利要求24所述的芯片调频装置，其特征在于，相邻的所述工作频点之间的频差为1～10％。
  28. 根据权利要求24所述的芯片调频装置，其特征在于，所述计算性能分析模块用于在预定的调整周期内，分析所述内核的所述计算性能指标是否达到预定的第一指标阈值、第二指标阈值和/或第三指标阈值，所述第一指标阈值与所述第二指标阈值相同或者不相同；
    所述频率调整模块用于若所述内核的所述计算性能指标达到所述第一指标阈值，将所述内核的所述当前工作频点上调到上一个工作频点；
    所述频率调整模块用于若所述内核的所述计算性能指标未达到所述第二指标阈值，将所述内核的所述当前工作频点下调到下一个工作频点；和/或
    所述频率调整模块用于若所述内核的所述计算性能指标达到所述第三指标阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
  29. 根据权利要求24所述的芯片调频装置，其特征在于，所述频率调整模块还包括有：
    频率调整子模块，用于根据所述内核的所述计算性能指标，对所述内核的所述当前工作频点进行上调或下调；
    停止频率调整子模块，用于若工作于预定的至少一个优化工作频点的所述内核超过预定的第一比率，停止对所述内核进行调频；或者用于若工作于至少一所述优化工作频点上的所述内核的数目最多，停止对所述内核进行调频。
  30. 根据权利要求24所述的芯片调频装置，其特征在于，所述计算性能分析模块用于在预定的调整周期内，分析所述内核的计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值，所述第一正确率阈值与所述第二正确率阈值相同或者不相同；
    所述频率调整模块用于若所述内核的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；和/或用于若所述内核的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
  31. 根据权利要求30所述的芯片调频装置，其特征在于，所述计算性能分析模块进一步包括有：
    第一分析子模块，用于在所述调整周期内，分析所述内核提交的随机数是否正确；
    统计子模块，用于统计所述内核在所述调整周期内提交的正确随机数的个数和错误随机数的个数；
    第一判断子模块，用于根据所述正确随机数的个数和所述错误随机数的个数，计算出所述内核在所述调整周期内的随机数计算正确率，并判断所述随机数计算正确率是否达到预定的第一正确率阈值和/或第二正确率阈值；
    所述频率调整模块用于若所述内核的所述随机数计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；和/或用于若所述内核的所述随机数计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
  32. 根据权利要求31所述的芯片调频装置，其特征在于，所述第一分析子模块进一步包括：
    第一计算单元，用于在所述调整周期内，所述内核每递交一个所述随机数后，将所述随机数通过预定的算法计算出第一结果，所述第一结果中包含有第一特征，所述第一计算单元设置于所述内核中；
    第一验算单元，用于将所述随机数通过相同的所述算法计算出第二结果，所述第二结果中包含有第二特征，若所述第一特征与所述第二特征相同，则判定所述随机数是正确随机数，否则判定所述随机数是错误随机数；所述第一验算单元设置于所述运算芯片中。
  33. 根据权利要求30所述的芯片调频装置，其特征在于，所述计算性能分析模块用于根据预设的实时调整指令，实时分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；
    所述计算性能分析模块用于根据预设的定时调整指令，在所述定时调整指 令设定的调整时间段内，分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；或者
    所述计算性能分析模块用于根据接收的即时调整指令，分析所述内核在所述调整周期内的所述计算正确率是否达到所述第一正确率阈值与所述第二正确率阈值；
    所述频率调整模块用于若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，实时将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，实时将所述内核的所述当前工作频点下调到下一个工作频点；
    所述频率调整模块用于在所述调整时间段内，若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；在所述调整时间段内，若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点；或者
    所述频率调整模块用于根据接收的即时调整指令，若所述内核在所述调整周期内的所述计算正确率达到所述第一正确率阈值，将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核在所述调整周期内的所述计算正确率未达到所述第二正确率阈值，将所述内核的所述当前工作频点下调到下一个工作频点；根据接收的停止调整指令，停止对所述内核的所述当前工作频点的调整。
  34. 根据权利要求24所述的芯片调频装置，其特征在于，所述计算性能分析模块进一步包括有：
    设置子模块，用于预先设置所述内核的参考节点值、计算正确权重值、计算错误权重值、计算正确阈值和计算错误阈值；
    第二分析子模块，用于分析所述内核的每次计算是否正确；
    计数子模块，用于所述内核每正确计算至少一次，在所述参考节点值上增加一次所述计算正确权重值，并且所述内核每错误计算至少一次，在所述参考节点值上减少一次所述计算错误权重值；
    第二判断子模块，用于判断所述内核的当前参考节点值是否达到所述计算正确阈值或所述计算错误阈值；
    所述频率调整模块用于若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；以及用于若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点。
  35. 根据权利要求34所述的芯片调频装置，其特征在于，所述第二分析子模块用于分析所述内核每次提交的随机数是否正确；
    所述计数子模块用于在所述内核每提交至少一次正确随机数，在所述参考节点值上增加一次所述计算正确权重值，所述内核每提交至少一次错误随机数，在所述参考节点值上减少一次所述计算错误权重值。
  36. 根据权利要求35所述的芯片调频装置，其特征在于，所述第二分析子模块进一步包括：
    第二计算单元，用于所述内核递交一个所述随机数后，所述内核将所述随机数通过预定的算法计算出第一结果，所述第一结果中包含有第一特征；
    第二验算单元，用于将所述随机数通过相同的所述算法计算出第二结果，所述第二结果中包含有第二特征；若所述第一特征与所述第二特征相同，则判定所述随机数是正确随机数，否则判定所述随机数是错误随机数。
  37. 根据权利要求24所述的芯片调频装置，其特征在于，所述设置子模块用于根据实际需求设置和调整所述内核的所述参考节点值、所述计算正确权重值、所述计算错误权重值、所述计算正确阈值和/或所述计算错误阈值，所述计算正确权重值和所述计算错误权重值相同或者不相同，所述计算正确阈值和所述计算错误阈值相同或者不相同；
    所述设置子模块用于通过控制所述计算正确权重值和所述计算错误权重值的比值控制所述内核期望容忍的驻留差错率；
    所述设置子模块用于通过控制所述计算正确权重值和所述计算错误权重值的绝对值大小控制调整周期；
    所述设置子模块用于通过控制所述计算正确阈值和所述计算错误阈值的绝对值大小控制所述调整周期。
  38. 根据权利要求37所述的芯片调频装置，其特征在于，所述驻留差错率的计算公式为：驻留差错率＝计算正确权重值/(计算正确权重值+计算错误权重值)。
  39. 根据权利要求34所述的芯片调频装置，其特征在于，所述计算性能分析模块用于根据预设的实时调整指令，实时判断所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；
    所述计算性能分析模块用于根据预设的定时调整指令，在所述定时调整指令设定的调整时间段内，判断所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；或者
    所述计算性能分析模块用于根据接收的即时调整指令，分析所述内核的所述当前参考节点是否达到所述计算正确阈值或所述计算错误阈值；
    所述频率调整模块用于若所述内核的所述当前参考节点值达到所述计算正确阈值，实时将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核的所述当前参考节点值达到所述计算错误阈值，实时将所述内核的所述当前工作频点下调到下一个工作频点；
    所述频率调整模块用于在所述调整时间段内，若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；在所述调整时间段内，若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点；或者
    所述频率调整模块用于根据接收的即时调整指令，若所述内核的所述当前参考节点值达到所述计算正确阈值，将所述内核的所述当前工作频点上调到上一个工作频点；若所述内核的所述当前参考节点值达到所述计算错误阈值，将所述内核的所述当前工作频点下调到下一个工作频点；以及用于根据接收的停止调整指令，停止对所述内核的所述当前工作频点的调整。
  40. 根据权利要求24所述的芯片调频装置，其特征在于，还包括有：
    频点统计模块，用于统计被调频后的所述内核在各所述工作频点上的当前分布状态；
    频点调整模块，用于根据所述内核的所述当前分布状态和预定的频点调整机制，调整设置所述工作频点的频率，所述频点调整机制是内核分布状态与频点调整的对应关系。
  41. 根据权利要求40所述的芯片调频装置，其特征在于，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，所述高频工作频点中频率最高的是最高工作频点，所述低频工作频点中频率最低的 是最低工作频点；
    所述频点调整模块还包括：
    第一频点调整子模块，用于若超过预定的第二比率的所述内核工作于至少一所述高频工作频点上，将至少一所述工作频点修改设置为至少一优化高频工作频点，所述优化高频工作频点的频率高于所述最高工作频点的频率；和/或
    第二频点调整子模块，用于若超过预定的第三比率的所述内核工作于至少一所述低频工作频点上，将至少一所述工作频点修改设置为至少一优化低频工作频点，所述优化低频工作频点的频率低于所述最低工作频点的频率。
  42. 根据权利要求41所述的芯片调频装置，其特征在于，所述第一频点调整子模块，用于若超过所述第二比率的所述内核工作于所述最高工作频点上，将一个所述工作频点修改设置为一个所述优化高频工作频点；和/或
    所述第二频点调整子模块，用于若超过所述第三比率的所述内核工作于所述最低工作频点上，将一个所述工作频点修改设置为一个所述优化低频工作频点。
  43. 根据权利要求40所述的芯片调频装置，其特征在于，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点，所述高频工作频点中频率最高的是最高工作频点，所述低频工作频点中频率最低的是最低工作频点；
    所述频点调整模块还包括：
    第三频点调整子模块，用于若工作于至少一所述高频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一优化高频工作频点，所述优化高频工作频点的频率高于所述最高工作频点的频率；和/或
    第四频点调整子模块，用于若工作于至少一所述低频工作频点的所述内核的数目最多，将至少一所述工作频点修改设置为至少一优化低频工作频点，所述优化低频工作频点的频率低于所述最低工作频点的频率。
  44. 根据权利要求43所述的芯片调频装置，其特征在于，所述第三频点调整子模块，用于若工作于所述最高工作频点上的所述内核的数目最多，将一个所述工作频点修改设置为一个所述优化高频工作频点；和/或
    所述第四频点调整子模块，用于若工作于所述最低工作频点的所述内核的数目最多，将一个所述工作频点修改设置为一个所述优化低频工作频点。
  45. 根据权利要求40所述的芯片调频装置，其特征在于，所述工作频点包括至少一高频工作频点、至少一中间工作频点和至少一低频工作频点；
    所述频点调整模块还包括：
    第一停止调整子模块，用于若超过预定的第四比率的所述内核工作于至少一所述中间工作频点上，停止调整设置所述工作频点的频率；或者
    第二停止调整子模块，用于若工作于在至少一所述中间工作频点上的所述内核的数目最多，停止调整设置所述工作频点的频率。
  46. 根据权利要求24所述的芯片调频装置，其特征在于，所述芯片调频装置设置于所述运算芯片的内部或外部。
  47. 根据权利要求24所述的芯片调频装置，其特征在于，所述计算设备用于挖掘虚拟数字货币的运算。
  48. 一种包括有权利要求24～47中任意一种所述芯片调频装置的算力板。
  49. 一种包括有权利要求24～47中任意一种所述芯片调频装置的计算设备。
  50. 一种存储介质，用于存储一种用于执行权利要求1～23中任意一种所述计算设备的芯片调频方法的计算机程序。
PCT/CN2019/084064 2018-06-06 2019-04-24 计算设备的芯片调频方法、装置、算力板、计算设备及存储介质 WO2019233206A1 (zh)

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