WO2019227440A1 - Procédé et dispositif de commande d'affichage d'image à ultra haute définition - Google Patents

Procédé et dispositif de commande d'affichage d'image à ultra haute définition Download PDF

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Publication number
WO2019227440A1
WO2019227440A1 PCT/CN2018/089381 CN2018089381W WO2019227440A1 WO 2019227440 A1 WO2019227440 A1 WO 2019227440A1 CN 2018089381 W CN2018089381 W CN 2018089381W WO 2019227440 A1 WO2019227440 A1 WO 2019227440A1
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Prior art keywords
video data
lines
ultra
line
definition
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PCT/CN2018/089381
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English (en)
Chinese (zh)
Inventor
黎守新
于军胜
陈珉
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成都晶砂科技有限公司
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Priority to PCT/CN2018/089381 priority Critical patent/WO2019227440A1/fr
Publication of WO2019227440A1 publication Critical patent/WO2019227440A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
    • G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
    • G02B26/10—Scanning systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems

Definitions

  • the present invention relates to an ultra-high-definition image display driving technology, and in particular, to an ultra-high-definition image display driving method and device.
  • the mainstream high-resolution screen is full high-definition resolution 1920x1080 (FHD).
  • FHD resolutions include 3840x2160 (4K), 7680x4320 (8K), 10240x4320 (10K), 15360x8640 (16K), and even higher resolutions.
  • Adopting a single video interface, such as HDMI2.0 interface or DP1.2 interface can realize the transmission of ultra high-definition video data, but the transmission distance is quite limited, which greatly reduces the ease of use.
  • the traditional scanning method is progressive scanning or interlaced scanning (as shown in Figure 1), and only one row in the pixel array is selected during each scanning.
  • the technical problem to be solved by the present invention is to provide an ultra high-definition image display driving method and device, which can reduce the video data rate and ensure the grayscale accuracy of the displayed image.
  • the present invention adopts the following technical solutions.
  • An ultra high-definition image display driving method includes the following steps:
  • a frame of ultra-high-definition image is divided into several lines of video data by line; during interlaced scanning, a field of ultra-high-definition images is divided into several lines of video data by line;
  • K is a natural number greater than or equal to 2 and K is less than or equal to the number of lines of line video data into which one frame / field of ultra-high-definition image is divided into lines;
  • the K-line video data corresponds to K lines adjacent to each other in the ultra-high-definition display array; when interlaced scanning, the K-line video data corresponds to K lines of one line in the ultra-high-definition display array .
  • step S3 the buffered K lines of video data are output in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces; said step In S5, the buffered video data of the other K lines is output in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces.
  • the line video data includes video image data Data, a data clock Clock, a data valid signal DE, a line synchronization signal Hsync, and a frame / field synchronization signal Vsync.
  • An ultra high-definition image display driving device includes:
  • a segmentation unit which is used to progressively divide a frame of ultra-high-definition image into several lines of video data during progressive scanning; and a segmentation unit, which is used to deinterleave a field of ultra-high-definition images into several lines of video data during progressive scanning;
  • the buffer unit is configured to buffer K lines of video data in the plurality of lines of video data, and buffer the other K lines of video data in the plurality of lines of video data after the K lines of video data are output in parallel, and so on, Until the last K lines of video data in the plurality of lines of video data are cached;
  • a receiving output driving unit configured to output the received K-line video data output in parallel by the buffer unit to an ultra-high-definition display array and drive the ultra-high-definition display array corresponding to the K-line video data Lines are simultaneously displayed, and then the other K lines of video data output in parallel by the buffer unit are received in parallel to the ultra high definition display array and the lines corresponding to the other K lines of video data are driven in the ultra high definition display array Simultaneous display, and so on, until all the lines corresponding to the several lines of video data of the one frame / field ultra high-definition image of the ultra-high-definition display array are completely displayed.
  • the K-line video data corresponds to K lines adjacent to each other in the ultra-high-definition display array; when interlaced scanning, the K-line video data corresponds to K lines of one line in the ultra-high-definition display array .
  • the buffer unit transmits the K-line video data to the receiving output driving unit in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces. .
  • the line video data includes video image data Data, a data clock Clock, a data valid signal DE, a line synchronization signal Hsync, and a frame / field synchronization signal Vsync.
  • the invention has the following beneficial technical effects.
  • the present invention divides a frame of ultra-high-definition image into several lines of video data line by line during progressive scanning; in an interlaced scan, divides a field of ultra-high-definition image into lines of video data line by line; caches the K in the several lines of video data Line video data; output the buffered K line video data to the UHD display array in parallel and drive the UHD display array corresponding to the K line video data at the same time; wait for the K line video data After parallel output, another K lines of video data in the plurality of lines of video data are buffered; the buffered K lines of video data are output in parallel to the UHD display array and drive the UHD display array with the other K The lines corresponding to the line of video data are displayed simultaneously; and so on, until the lines corresponding to the lines of video data of the one-frame / field ultra-high-definition image of the ultra-high-definition display array are all displayed.
  • FIG. 1 schematically illustrates a conventional progressive scan structure.
  • FIG. 2 schematically illustrates a structural diagram of an ultra-high-definition image display driving device of the present invention.
  • FIG. 3 schematically illustrates a progressive scanning structure of the present invention.
  • FIG. 4 schematically illustrates a structure of an interlaced scan according to the present invention.
  • FIG. 5 schematically illustrates a gate driving timing chart of progressive scanning according to the present invention.
  • FIG. 6 schematically illustrates a gate driving timing chart of interlaced scanning according to the present invention.
  • FIG. 7 is a schematic flowchart of a method of the present invention.
  • the present invention can be applied to, but not limited to, ultra-high-definition display devices and devices such as LCD, OLED, QLCD, QLED, Mini-LED, Micro-LED, Nano-LED, and Micro-OLED.
  • ultra-high-definition display devices and devices such as LCD, OLED, QLCD, QLED, Mini-LED, Micro-LED, Nano-LED, and Micro-OLED.
  • the ultra-high-definition display array 4 includes a plurality of pixel units arranged in a matrix manner to form an M ⁇ N pixel array, where M is the number of rows and N is the number of columns.
  • the value range of the row number m of the M ⁇ N pixel array is 0, 1, 2, ..., M-1, and the value range of the column number n is 0, 1, 2, ..., N-1.
  • an ultra-high-definition image display driving device includes a dividing unit 1, a buffer unit 2, and a receiving output driving unit 3.
  • the segmentation unit 1 is used for segmenting one frame of ultra-high-definition image into several lines of video data during progressive scanning.
  • the segmentation unit 1 is also used to segment a field of ultra-high-definition images into several lines of video data during interlaced scanning.
  • (1) In the progressive scanning mode, the one ultra-high-definition image is divided into several lines of video data line by line: line video data 0, line video data 1, line video data 2, ..., line video data M-1.
  • line 0 of the ultra-high-definition display array 4 displays the image contained in the foregoing line of video data 0, that is, the phase of the ultra-high-definition display array 4 and the line of video data 0
  • the corresponding line 0 displays the image contained in line video data 0
  • line 1 of the ultra-high-definition display array 4 displays the image contained in the foregoing line video data 1, that is, the image corresponding to line video data 1 of the ultra-high-definition display array 4.
  • line 0 of the ultra-high-definition display array 4 displays the image contained in the foregoing line of video data 0, that is, the phase of the ultra-high-definition display array 4 and the line of video data 0
  • the corresponding 0 line displays the image contained in the line video data 0
  • the 2 lines of the UHD display array 4 display the image contained in the aforementioned line video data 1, that is, the corresponding image of the UHD display array 4 corresponding to the line video data 1
  • 2 lines display images contained in line video data 1
  • 4 lines of UHD display array 4 display the images contained in the aforementioned line video data 2, that is, 4 lines corresponding to line video data 2 of UHD display array 4
  • the image contained in the line video data 2 is displayed; the others are the same.
  • one line of the UHD display array 4 displays the image contained in the foregoing line of video data 0, that is, the phase of the UHD display array 4 and the line video data 0
  • the corresponding 1 line displays the image contained in the line video data 0
  • the 3 lines of the UHD display array 4 display the images contained in the aforementioned line video data 1, that is, the image corresponding to the line video data 1 of the UHD display array 4 3 lines display the images contained in line video data 1
  • 5 lines of UHD display array 4 display the images contained in the aforementioned line video data 2, that is, 5 lines corresponding to line video data 2 of UHD display array 4
  • the image contained in the line video data 2 is displayed; the others are the same.
  • the buffer unit 2 is configured to buffer K line video data among the foregoing lines of video data.
  • the K line video data is: line video data 0, line video data 1, line video data 2, line video data 3; After the K lines of video data are output in parallel, the other K lines of video data in the lines of video data are cached.
  • the other K lines of video data are: line video data 4, line video data 5, line Video data 6, line video data 7, or the other K lines of video data are: line video data 8, line video data 9, line video data 10, line video data 11; and so on, until the lines of video are cached
  • the last K lines of video data in the data when progressive scanning, the last K lines of video data are: line video data M-4, line video data M-3, line video data M-2, line video data M-1; in interlaced scanning, the last K lines of video data are: line video data (M / 2) -4, line video data (M / 2) -3, line video data (M / 2)- 2.
  • the buffer unit 2 outputs K lines of video data to the receiving output driving unit 3 in parallel, and the control unit in the receiving output driving unit 3 generates digital gate driving signals and digital source driving signals by using the corresponding line video data and sends them to the corresponding gate driving respectively.
  • K gate drive units and K source drive units load K rows of video data into the UHD display array 4 at the same time to display UHD video images with correct and high dynamic range.
  • K is a natural number greater than or equal to 2
  • K is less than or equal to the number of lines of line video data into which one frame / field ultra-high-definition image is divided into lines. For example, in the embodiment shown in FIG.
  • the number of channels for the buffer unit 2 to output K lines of video data to the receiving output driving unit 3 in parallel is K
  • the receiving output driving unit 3 includes K control units and K source driving units.
  • K gate driving units, the channels of the buffer unit 2 and the control unit of the receiving output driving unit 3 are in one-to-one correspondence.
  • channel 0 of buffer unit 2 is connected to control unit 0 of receiving output driving unit 3
  • channel 1 of buffer unit 2 is connected to control unit 1 of receiving output driving unit 3, and so on.
  • the control unit 0 receives the line video data output by the buffer unit 2 from the channel 0 of the buffer unit 2, and the control unit 0 generates a digital source driving signal and a digital gate driving signal according to the line of video data and respectively Corresponding output to the source drive unit 0 and the gate drive unit 0;
  • the control unit 1 receives the line video data output from the buffer unit 2 through the channel 1 of the buffer unit 2, and the control unit 1 generates a digital source drive signal and a digital gate according to the line video data
  • the driving signals are correspondingly output to the source driving unit 1 and the gate driving unit 1 respectively; and so on.
  • the receiving output driving unit 3 is configured to output the received K-line video data output in parallel by the buffer unit 2 to the ultra-high-definition display array 4 in parallel and drive the ultra-high-definition display array 4 with the K-line video data.
  • the corresponding rows are displayed at the same time, and the other K lines of video data output in parallel by the buffer unit 2 are received and output to the UHD display array 4 in parallel and the UHD video data of the UHD display array 4 is driven
  • the corresponding rows are displayed simultaneously, and so on, until all the rows corresponding to the video data of the one frame / field ultra high-definition image of the ultra-high-definition display array 4 are completely displayed.
  • the K lines of video data are: line video data 0, line video data 1, line video data 2, line video data 3, and the other K lines of video data are: Line video data 4, line video data 5, line video data 6, line video data 7, and the last K lines of line video data are: line video data M-4, line video data M-3, line video data M-2, Line video data M-1.
  • the receiving output driving unit 3 outputs the K lines of video data output in parallel from the received buffer unit 2, that is, line video data 0, line video data 1, line video data 2, and line video data 3 in parallel to the UHD display array 4,
  • line video data 0 is output from channel 0 of buffer unit 2 to control unit 0 of receiving output driving unit 3
  • line video data 1 is output from channel 1 of buffer unit 2 to control unit 1 of receiving output driving unit 3
  • line video Data 2 is output from the channel 2 of the buffer unit 2 to the control unit 2 receiving the output driving unit 3
  • line video data 3 is output from the channel 3 of the buffer unit 2 to the control unit 3 receiving the output driving unit 3.
  • the receiving output driving unit 3 drives the lines corresponding to the K line of video data of the UHD display array 4 to be displayed simultaneously, that is, the image contained in the 0 line display video data 0 of the UHD display array 4 and the UHD display array
  • the image contained in the 1 line display line 4 of the video data 1 the image contained in the 2 line display of the ultra-high-definition display array 4 includes the image contained in the video data 2
  • the 3 line displayed in the ultra-high-definition display array 4 contains the image included in the video data 3.
  • line video data 1 line video data 1, line video data 2, and line video data 3 are output to the UHD display array 4 in parallel and drive 0-3 lines of display at the same time
  • the receiving output driving unit 3 then outputs the received
  • the other K lines of video data output in parallel by the buffer unit 2 are line video data 4, line video data 5, line video data 6, and line video data 7 and are output to the UHD display array 4 in parallel.
  • the line video data 4 is output from the cache unit Channel 0 of 2 is output to control unit 0 of receiving output drive unit 3.
  • Line video data 5 is output from channel 1 of buffer unit 2 to control unit 1 of receiving output drive unit 3.
  • Line video data 6 is from channel 2 of cache unit 2.
  • the output is sent to the control unit 2 receiving the output driving unit 3, and the line video data 7 is output from the channel 3 of the buffer unit 2 to the control unit 3 receiving the output driving unit 3.
  • the receiving output driving unit 3 then drives the lines corresponding to the other K lines of video data of the UHD display array 4 to display simultaneously, that is, the images contained in the 4 lines of the UHD display array 4 and the video data 4, UHD
  • the last K lines of video data are: line video data M-4, line video data M-3, line video data M-2, and line video data M-1 corresponding to the AND of the UHD display array 4.
  • the lines corresponding to the last K lines of video data are displayed simultaneously. And so on, until the lines corresponding to the several lines of video data of the one frame of ultra-high-definition image of the ultra-high-definition display array 4 are completely displayed.
  • the K-line video data of even / odd field ultra high-definition images are: line video data 0, line video data 1, line video data 2, line video data 3, and the other K lines
  • the line video data is: line video data 4, line video data 5, line video data 6, line video data 7, and the last K line video data is: line video data (M / 2) -4, line video data ( M / 2) -3, line video data (M / 2) -2, line video data (M / 2) -1.
  • the receiving output driving unit 3 outputs the K lines of video data output in parallel from the received buffer unit 2, that is, line video data 0, line video data 1, line video data 2, and line video data 3 in parallel to the UHD display array 4,
  • line video data 0 is output from channel 0 of buffer unit 2 to control unit 0 of receiving output driving unit 3
  • line video data 1 is output from channel 1 of buffer unit 2 to control unit 1 of receiving output driving unit 3
  • line video Data 2 is output from the channel 2 of the buffer unit 2 to the control unit 2 receiving the output driving unit 3
  • line video data 3 is output from the channel 3 of the buffer unit 2 to the control unit 3 receiving the output driving unit 3.
  • the receiving output driving unit 3 drives the ultra-high-definition display array 4 to display lines corresponding to the K-line video data at the same time.
  • 0 lines of the UHD display array 4 display the images contained in the video data
  • 2 lines of the UHD display array 4 display the images contained in the video data 1 and the UHD display
  • the 4 rows of the array 4 display the images contained in the video data 2
  • the 6 rows of the UHD display array 4 display the images contained in the video data 3.
  • the output drive unit 3 receives the The other K lines of video data output in parallel by the buffer unit 2 are line video data 4, line video data 5, line video data 6, and line video data 7 and output to the UHD display array 4 in parallel, for example, line video data.
  • the receiving output driving unit 3 then drives the lines corresponding to the other K lines of video data of the UHD display array 4 to display at the same time, that is, the images contained in the 8 lines of the UHD display array 4 and the video data 4, UHD The image contained in 10 rows of display array video data 5 of display array 4, the image contained in 12 rows of display array video 4 of ultra high definition display array 4 and the image contained in video data 7 of 14 rows of ultra high definition display array 4 image. And so on, until the lines corresponding to the several lines of video data of the even-field ultra-high-definition image driving the ultra-high-definition display array 4 are all displayed.
  • one line of the UHD display array 4 displays the image contained in the video data 0, and the three lines of the UHD display array 4 displays the image contained in the video data 1 and the UHD display
  • the 5 rows of the array 4 display the images contained in the video data 2
  • the 7 rows of the UHD display array 4 display the images contained in the video data 3.
  • line video data 1 line video data 1, line video data 2, and line video data 3 are output to the UHD display array 4 in parallel and drive 1, 3, 5, and 7 lines of display at the same time
  • the receiving output driving unit 3 then outputs all
  • the other K lines of video data output in parallel by the buffer unit 2 are line video data 4, line video data 5, line video data 6, and line video data 7 and output to the UHD display array 4 in parallel, for example, line video data.
  • the receiving output driving unit 3 then drives the lines corresponding to the other K lines of video data of the UHD display array 4 to display at the same time, that is, the 9 lines of the UHD display array 4 display the images contained in the video data 4 and the UHD 11 images of display array 4 include images contained in video data 5, 13 images of UHD display array 4 contain images contained in video data 6, 15 images of UHD display array 4 contain images contained in video data 7 image. And so on, until all the lines corresponding to the several lines of video data of the odd-field ultra-high-definition image driving the ultra-high-definition display array 4 are completely displayed.
  • the foregoing K-line video data should correspond to K lines adjacent to each other in the UHD display array; during interlaced scanning, the K-line video data should correspond to each other in the UHD display array. K lines apart.
  • the buffer unit 2 transmits the K-line video data to the receiver in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces.
  • the foregoing line of video data includes video image data Data, a data clock Clock, a data valid signal DE, a line synchronization signal Hsync, and a frame / field synchronization signal Vsync.
  • a method for driving an ultra-high-definition image display of the present invention includes the following steps:
  • a frame of ultra-high-definition image is divided into several lines of video data by line; during interlaced scanning, a field of ultra-high-definition images is divided into several lines of video data by line;
  • the K-line video data should correspond to the K lines adjacent to each other in the ultra-high-definition display array; during interlaced scanning, the K-line video data should correspond to the ultra-high-definition display array. K rows separated from each other.
  • step S3 the buffered K lines of video data are output in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces.
  • step S5 the buffered video data of the other K lines are output in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces.
  • the foregoing line of video data includes video image data Data, a data clock Clock, a data valid signal DE, a line synchronization signal Hsync, and a frame / field synchronization signal Vsync.
  • K 4 that is, the four gate drive units are gate drive unit 0, gate drive unit 1, gate drive unit 2, and gate drive unit 3, and the four source drive units are source drive unit 0, Source drive unit 1, source drive unit 2, source drive unit 3.
  • the progressive video data is taken as an example, and the present invention is further specifically described according to a scanning method (progressive scanning or interlaced scanning).
  • the dividing unit 1 divides one frame of ultra-high-definition image into M lines of video data.
  • the buffer unit 2 buffers 4 lines of video data among the foregoing M lines of video data, such as line video data 0, line video data 1, line video data 2, line video data 3.
  • the receiving output driving unit 3 is configured to output the received 4 lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 with the 4 lines of video data.
  • the corresponding lines are displayed at the same time.
  • the 4 lines of line video data output in parallel by 4 channels are line video data 0, line video data 1, line video data 2, line video data 3 (each line of line video data includes corresponding video data Data, data clock Clock, data valid signal DE, line synchronization signal Hsync, and frame synchronization signal Vsync) are input to the four control units 0, control unit 1, control unit 2, and control unit 3 respectively.
  • the ultra-high-definition display array 4 supports 8K resolution of progressive scanning.
  • the row number satisfies m 4 * i + 3
  • the pixel unit is connected to the gate driving unit 3 and the source driving unit 3.
  • the pixel units with row number 2 and column number 3 are connected to the gate driving unit 2 and the source driving unit 2.
  • the control unit 0 includes a clock, a data valid signal DE, and a line synchronization signal included in the line video data 0 output from the channel 0 of the buffer unit 2 as received by itself.
  • Hsync and frame synchronization signal Vsync generate corresponding digital gate drive signals and digital source drive signals and send them to gate drive unit 0 and source drive unit 0, respectively.
  • Gate drive unit 0 and source drive unit 0 scan the corresponding data Data to the gate drive.
  • the pixel unit with row number 0 of the ultra high-definition display array 4 selected by unit 0 displays the image contained in the video data 0 of the line 0 of the ultra-high-definition display array 4.
  • the control unit 1 generates a corresponding digital gate driving signal according to the clock Clock, data valid signal DE, line synchronization signal Hsync, and frame synchronization signal Vsync included in the line video data 1 output from the channel 1 of the buffer unit 2 received by the control unit 1.
  • the digital source driving signals are sent to the gate driving unit 1 and the source driving unit 1, respectively.
  • the gate driving unit 1 and the source driving unit 1 scan the corresponding data Data to the corresponding pixel unit on the row number 1 selected by the gate driving unit 1.
  • One line of the ultra-high-definition display array 4 displays the images included in the video data 1.
  • the control unit 2 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the frame synchronization signal Vsync included in the line video data 2 output from the channel 2 of the buffer unit 2 received by itself.
  • the digital source driving signals are sent to the gate driving unit 2 and the source driving unit 2, respectively.
  • the gate driving unit 2 and the source driving unit 2 scan the corresponding data Data to the corresponding pixel unit on the row number 2 selected by the gate driving unit 2.
  • the two lines of the ultra-high-definition display array 4 display the images contained in the video data 2.
  • the control unit 3 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the frame synchronization signal Vsync included in the line video data 3 output from the channel 3 of the buffer unit 2 received by itself.
  • the digital source driving signals are sent to the gate driving unit 3 and the source driving unit 3, respectively.
  • the gate driving unit 3 and the source driving unit 3 scan the corresponding data Data to the corresponding pixel unit on the row number 3 selected by the gate driving unit 3.
  • the images contained in the video data 3 of the 3 lines of the ultra high definition display array 4 are displayed.
  • the buffer unit 2 buffers the other four lines of video data in the foregoing M lines of video data, such as line video data 4. , Line video data 5, line video data 6, line video data 7.
  • the receiving output driving unit 3 is configured to output the received additional four lines of video data output in parallel by the buffer unit 2 to the ultra high definition display array 4 and drive the ultra high definition display array 4 and the other four lines of video.
  • the rows corresponding to the data are displayed at the same time.
  • the 4, 5, 6, and 7 lines of the ultra-high-definition display array 4 correspond to the images contained in the video data lines 4, 5, 6, and 7 at the same time.
  • the buffer unit 2 buffers the other four lines of video data in the foregoing M lines of video data, such as line video data 8, Line video data 9, line video data 10, line video data 11.
  • the above-mentioned gate driving timing when performing progressive scanning on the ultra high-definition display array is shown in FIG. 5.
  • the gate driving signal corresponding to the four rows is high, it indicates that the four rows are selected and corresponding source driving is performed.
  • the UHD display array 4 supports 8K resolution for interlaced scanning.
  • the pixel units with row number 2 and column number 3 are connected to the gate driving unit 1 and the source
  • the segmenting unit 1 divides a field of ultra-high-definition images into M / 2 lines of video data line by line.
  • the buffer unit 2 buffers 4 lines of video data among the foregoing M / 2 lines of video data, such as line video data 0, line video data 1, line video data 2, line video data 3.
  • the receiving output driving unit 3 is configured to output the received 4 lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 and the 4 lines of video data.
  • the corresponding rows are displayed at the same time.
  • the 4 lines of line video data output in parallel by 4 channels are line video data 0, line video data 1, line video data 2, line video data 3 (each line of line video data includes corresponding video data Data, data clock Clock, data valid signal DE, line synchronization signal Hsync, and field synchronization signal Vsync) are input to the four control units 0, control unit 1, control unit 2, and control unit 3 respectively.
  • the control unit 0 includes a clock, a data valid signal DE, a line synchronization signal Hsync, and a field included in the line video data 0 output from the channel 0 of the buffer unit 2 received by itself.
  • the synchronization signal Vsync generates corresponding digital gate driving signals and digital source driving signals and sends them to the gate driving unit 0 and the source driving unit 0, respectively.
  • the gate driving unit 0 and the source driving unit 0 scan the corresponding data Data to the gate driving unit 0 and select them.
  • the row number is the corresponding pixel unit on 0, and the row 0 of the ultra high-definition display array 4 displays the image contained in the row video data 0.
  • control unit 1 At the same time, the control unit 1 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 1 output from the channel 1 of the buffer unit 2 received by the control unit 1. And digital source drive signals are sent to the gate drive unit 1 and source drive unit 1, respectively.
  • the gate drive unit 1 and source drive unit 1 scan the corresponding data Data to the corresponding pixel unit on the row number 2 selected by the gate drive unit 1. The images contained in the video data 1 of the 2 lines of the ultra high definition display array 4 are displayed.
  • the control unit 2 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 2 output from the channel 2 of the buffer unit 2 received by itself.
  • the digital source driving signals are sent to the gate driving unit 2 and the source driving unit 2, respectively.
  • the gate driving unit 2 and the source driving unit 2 scan the corresponding data Data to the corresponding pixel unit on the row number 4 selected by the gate driving unit 2.
  • the control unit 3 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 3 output from the channel 3 of the buffer unit 2 received by itself.
  • the digital source driving signals are sent to the gate driving unit 3 and the source driving unit 3, respectively.
  • the gate driving unit 3 and the source driving unit 3 scan the corresponding data Data to the corresponding pixel unit on the row number 6 selected by the gate driving unit 3.
  • the buffer unit 2 buffers the other four lines of video data in the foregoing M / 2 line video data, such as line video Data 4, line video data 5, line video data 6, line video data 7.
  • the receiving output driving unit 3 is configured to output the received four other lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 and the other 4 lines.
  • the lines corresponding to the video data are displayed simultaneously.
  • the 8, 10, 12, and 14 lines of the ultra-high-definition display array 4 correspond to the images contained in the video data lines 4, 5, 6, and 7 at the same time.
  • the segmenting unit 1 divides a field of ultra-high-definition images into M / 2 lines of video data line by line.
  • the buffer unit 2 buffers 4 lines of video data among the foregoing M / 2 lines of video data, such as line video data 0, line video data 1, line video data 2, line video data 3.
  • the receiving output driving unit 3 is configured to output the received 4 lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 and the 4 lines of video data.
  • the corresponding rows are displayed at the same time.
  • the 4 lines of line video data output in parallel by 4 channels are line video data 0, line video data 1, line video data 2, line video data 3 (each line of line video data includes corresponding video data Data, data clock Clock, data valid signal DE, line synchronization signal Hsync, and field synchronization signal Vsync) are input to four control units 0, control unit 1, control unit 2, and control unit 3.
  • the control unit 0 includes a clock, a data valid signal DE, a line synchronization signal Hsync, and a field included in the line video data 0 output from the channel 0 of the buffer unit 2 received by itself.
  • the synchronization signal Vsync generates corresponding digital gate driving signals and digital source driving signals and sends them to the gate driving unit 0 and the source driving unit 0, respectively.
  • the gate driving unit 0 and the source driving unit 0 scan the corresponding data Data to the gate driving unit 0 and select them.
  • the row number is 1 corresponding to the pixel unit, and one row of the ultra-high-definition display array 4 displays the image contained in the video data 0.
  • control unit 1 At the same time, the control unit 1 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 1 output from the channel 1 of the buffer unit 2 received by the control unit 1. And digital source drive signals are sent to the gate drive unit 1 and source drive unit 1, respectively.
  • the gate drive unit 1 and source drive unit 1 scan the corresponding data Data to the corresponding pixel unit on the row number 3 selected by the gate drive unit 1. The images contained in the three-line display line video data 1 of the ultra-high-definition display array 4.
  • control unit 2 At the same time, the control unit 2 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 2 output from the channel 2 of the buffer unit 2 received by itself. And digital source drive signals are sent to the gate drive unit 2 and source drive unit 2, respectively.
  • the gate drive unit 2 and source drive unit 2 scan the corresponding data Data to the corresponding pixel unit on the row number 5 selected by the gate drive unit 2. The images contained in the video data 2 of the 5 lines of the UHD display array 4 are displayed.
  • the control unit 3 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 3 output from the channel 3 of the buffer unit 2 received by itself.
  • the digital source drive signals are sent to the gate drive unit 3 and the source drive unit 3, respectively.
  • the gate drive unit 3 and the source drive unit 3 scan the corresponding data Data to the corresponding pixel unit on the row number 7 selected by the gate drive unit 3.
  • the 7-line display image of the ultra-high-definition display array 4 contains the video data 3.
  • the buffer unit 2 buffers the other four lines of video data in the foregoing M / 2 line video data, such as line video Data 4, line video data 5, line video data 6, line video data 7.
  • the receiving output driving unit 3 is configured to output the received four other lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 and the other 4 lines.
  • the lines corresponding to the video data are displayed simultaneously.
  • the 9, 11, 13, and 15 lines of the ultra-high-definition display array 4 correspond to the images contained in the video data lines 4, 5, 6, and 7 at the same time.
  • the above-mentioned gate driving timing when the interlace scanning is performed on the ultra high-definition display array is shown in FIG. 6.
  • the gate driving signal corresponding to the 4 rows is high, it indicates that the 4 rows are selected and corresponding source driving is performed.
  • the disclosed apparatus and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the unit is only a logical function division.
  • multiple units or components may be combined or It can be integrated into another device, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.
  • the technical solution of the present invention essentially or part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium , Including a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present invention.
  • the foregoing storage medium / unit includes: universal serial bus flash disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), Various media such as magnetic disks or optical disks that can store program codes.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne un procédé et un dispositif de commande d'affichage d'image à ultra haute définition. Le procédé comprend les étapes suivantes consistant à : diviser une trame/un champ d'une image à ultra haute définition en une pluralité de rangées de données vidéo par rangée ; mettre en cache K rangées de données vidéo de la pluralité de rangées de données vidéo ; envoyer en parallèle les K rangées de données vidéo mises en cache au réseau d'affichage à ultra haute définition, et commander à la rangée correspondant aux K rangées de données vidéo du réseau d'affichage à ultra haute définition de s'afficher simultanément ; mettre en cache K autres rangées de données vidéo de la pluralité de rangées de données vidéo ; envoyer en parallèle les K autres rangées de données vidéo mises en cache au réseau d'affichage à ultra haute définition, et commander à la rangée correspondant aux K autres rangées de données vidéo du réseau d'affichage à ultra haute définition de s'afficher simultanément ; et répéter l'opération pour le reste de la pluralité de rangées de données vidéo jusqu'à ce que les rangées correspondant à la pluralité de rangées de données vidéo de la trame de l'image à ultra haute définition du réseau d'affichage à ultra haute définition soient commandées pour s'afficher. Le procédé réduit un débit de données vidéo, et garantit la précision des niveaux de gris de l'image affichée.
PCT/CN2018/089381 2018-05-31 2018-05-31 Procédé et dispositif de commande d'affichage d'image à ultra haute définition WO2019227440A1 (fr)

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CN101447156A (zh) * 2007-11-29 2009-06-03 三星电子株式会社 显示设备及其驱动方法
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CN104038719A (zh) * 2014-05-29 2014-09-10 清华大学 一种基于视频帧的超高清视频显示系统及方法
CN105719588A (zh) * 2014-12-22 2016-06-29 三星显示有限公司 扫描线驱动器芯片和包括其的显示设备
CN106920499A (zh) * 2015-12-28 2017-07-04 乐金显示有限公司 显示装置及其驱动方法和个人沉浸式装置
CN106993150A (zh) * 2017-04-14 2017-07-28 深圳市唯奥视讯技术有限公司 一种兼容超高清视频输入的视频图像处理系统及方法
US20170287429A1 (en) * 2016-03-29 2017-10-05 Samsung Electronics Co., Ltd. Display driving circuit and display device comprising the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447156A (zh) * 2007-11-29 2009-06-03 三星电子株式会社 显示设备及其驱动方法
CN102759795A (zh) * 2011-04-29 2012-10-31 上海数字电视国家工程研究中心有限公司 光束并行扫描成像的图像显示系统及方法
CN104038719A (zh) * 2014-05-29 2014-09-10 清华大学 一种基于视频帧的超高清视频显示系统及方法
CN105719588A (zh) * 2014-12-22 2016-06-29 三星显示有限公司 扫描线驱动器芯片和包括其的显示设备
CN106920499A (zh) * 2015-12-28 2017-07-04 乐金显示有限公司 显示装置及其驱动方法和个人沉浸式装置
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