WO2019218687A1 - 激光器驱动电路 - Google Patents

激光器驱动电路 Download PDF

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Publication number
WO2019218687A1
WO2019218687A1 PCT/CN2018/125348 CN2018125348W WO2019218687A1 WO 2019218687 A1 WO2019218687 A1 WO 2019218687A1 CN 2018125348 W CN2018125348 W CN 2018125348W WO 2019218687 A1 WO2019218687 A1 WO 2019218687A1
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Prior art keywords
pole
driving circuit
coupled
signal
transistor
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PCT/CN2018/125348
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English (en)
French (fr)
Inventor
臧大军
王翠翠
王临春
陆玉春
刘庆智
莫道春
雷文阳
徐小飞
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华为技术有限公司
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Publication of WO2019218687A1 publication Critical patent/WO2019218687A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor

Definitions

  • the present application relates to the field of circuit technologies, and in particular, to a laser driving circuit.
  • the current optical link system (also referred to as a photoelectric interconnect link system) mainly includes an Application Specific Integrated Circuit (ASIC) chip, a laser driver, a laser, an optical fiber, and a photodetector which are sequentially connected. (Photoelectric Detector; PD) and Trans-Impedance Amplifier (TIA).
  • ASIC Application Specific Integrated Circuit
  • PD Photoelectric Detector
  • TIA Trans-Impedance Amplifier
  • the ASIC chip is coupled to the laser driver via a Serdes interface (a serial communication interface) disposed in the ASIC chip and provides an initial voltage signal to the laser driver; the laser driver converts the initial voltage signal into a current signal and provides the laser with The current signal; the current signal passes through the laser to excite the laser to emit an optical signal; the optical signal emitted by the laser is transmitted to the photodetector through the optical fiber; the photodetector is used to convert the received optical signal into a current signal, and the transimpedance amplifier is used to conduct the current The signal is converted to a voltage signal.
  • the laser may be a Vertical Cavity Surface Emitting Laser (VCSEL) or a Direct Modulation Laser (DML).
  • a laser driver is provided in the related art.
  • the laser driver comprises two parts: an on-chip driving circuit and an off-chip passive network.
  • the on-chip driving circuit is prepared on the driving chip, and the off-chip passive network is composed of a resistor, a capacitor and an inductor.
  • the passive components are composed, and the on-chip driver circuit and the off-chip passive network are interconnected on a Printed Circuit Board (PCB).
  • the laser driver supplies a DC bias current and an AC operating current (the AC operating current is provided by the on-chip driving circuit) to the laser through an off-chip passive network to excite the laser to emit an optical signal.
  • the DC bias current is used to provide the quiescent operating point current required for the laser to operate
  • the AC operating current is used to modulate the optical power of the laser.
  • the off-chip passive network occupies a large area, which is inconvenient to be integrated in the chip, resulting in low integration of the laser driver.
  • the embodiment of the present application provides a laser driving circuit, which can solve the problem that the degree of integration of the laser driver in the related art is low.
  • the technical solution is as follows:
  • the present application provides a laser driving circuit, the laser driving circuit comprising: a driving circuit and an impedance conversion circuit;
  • the driving circuit is configured to receive an initial voltage signal, convert the initial voltage signal into a target voltage signal, and output the target voltage signal to the impedance converting circuit; the impedance converting circuit is configured to use the target voltage signal Converting to a target current signal and providing the target current signal to an electro-optical converter, the target current signal comprising an alternating current operating signal and a direct current biasing signal for providing static operation of the electro-optical converter Point current.
  • the laser driving circuit provided by the present application can provide a DC bias signal and an AC working signal to the electro-optical converter to drive the electro-optical converter to emit light. Compared with the related technology, there is no need to set an off-chip passive network. The area occupied by the laser driver circuit is small, which facilitates the integration of the laser driver and saves costs.
  • the impedance conversion circuit is further configured to perform impedance matching with the electro-optical converter.
  • the output impedance of the impedance conversion circuit may be equal to the impedance of the electro-optic converter, or may not be equal to the impedance of the electro-optical converter, which is not limited thereto.
  • the impedance conversion circuit can be used for impedance matching with the electro-optical converter, reducing signal reflection between the electro-optical converter and the laser driving circuit, and improving signal utilization.
  • the impedance conversion circuit includes a resistor R1, a resistor R2, a resistor R3, a transistor Q1, and a bias current source, and the R1 is coupled to the first pole and the gate of the Q1.
  • the first pole of the Q1 is connected to the output end of the driving circuit, and the sum of the currents of the R1, the Q1 and the electro-optical converter is equal to the bias current The current generated by the source;
  • the R2 is coupled between the first pole of the Q1 and the first signal source, and the R3 is coupled to the second pole of the Q1 and the first signal source.
  • the electro-optical converter is coupled between the third pole of the Q1 and the first signal source, and the bias current source is coupled between the third pole of the Q1 and the second signal source;
  • the R2 is coupled between the first pole of the Q1 and the second signal source, and the R3 is coupled to the second pole of the Q1 and the second signal
  • the electro-optic converter is coupled between the third pole of the Q1 and the second signal source, the bias current source being coupled to the third pole of the Q1 and the first signal source between;
  • first signal source and the second signal source are used to supply a power supply voltage to the laser driving circuit.
  • the impedance conversion circuit further includes a bias current source, and a sum of the R1, the current of the Q1 and the current on the electro-optical converter is equal to a current generated by the bias current source; when the Q1 is In the case of a P-type transistor, the bias current source is coupled between the third pole of the Q1 and the second signal source; when the Q1 is an N-type transistor, the bias current source is coupled in the Between the third pole of Q1 and the first signal source.
  • the ripple (noise) of the first signal source and/or the second signal source can be shielded to prevent the ripple from affecting the current passing through the electro-optical converter, and the electro-optical converter is improved.
  • the signal-to-noise ratio of the output optical signal eliminates the need to separately set the decoupling capacitor to shield the noise of the signal source, facilitating the integration of the laser driving circuit.
  • the bias current source I BIAS can be implemented by using a transistor.
  • the impedance conversion circuit includes a resistor R4, a transistor Q1, and a transistor Q2, wherein the Q1 and the Q2 are both N-type transistors;
  • the R4 is connected in series between the second pole of the Q1 and the third pole of the Q2, the first pole of the Q1 is connected to the output end of the driving circuit, and the third pole of the Q1 is first a signal source is connected, a first pole of the Q2 is coupled to a bias voltage, a second pole of the Q2 is coupled to a second signal source, and the third optical pole is coupled to the third pole of the Q1 Between the third pole of Q2;
  • first signal source and the second signal source are used to supply a power supply voltage to the laser driving circuit.
  • the provision of an all-N transistor in the impedance conversion circuit can improve the bandwidth and signal transmission rate of the impedance conversion circuit, and facilitate high-speed optoelectronic interconnection.
  • the discrete devices of the N-type transistor are relatively mature.
  • the impedance conversion circuit can be prepared not only by an integrated circuit (IC) process, but also by using a wiring connection discrete device on the PCB.
  • the driving circuit when the Q1 is a P-type transistor, the driving circuit includes a differential pair transistor, the resistor R2, a resistor R5, a resistor R6, and two DC current sources, a differential pair transistor for amplifying an initial voltage signal input to the driving circuit;
  • the differential pair transistor includes a transistor Q3 and a transistor Q4, the initial voltage signal being respectively applied to a first pole of the Q3 and a first pole of the Q4, the R2 being coupled to a third pole of the Q4
  • the R5 is coupled between the third pole of the Q3 and the first signal source
  • the R6 is coupled to the second pole of the Q3 and the second pole of the Q4.
  • the two direct current sources are respectively coupled between the second pole of the Q3 and the second signal source and between the second pole of the Q4 and the second signal source, Two DC current sources are used to provide a DC bias current to the drive circuit;
  • R5 is a degraded resistor that is used to receive signals and increase the bandwidth of the driver circuit.
  • the driving circuit when the Q1 is an N-type transistor, the driving circuit includes a differential pair transistor, a resistor R5, a resistor R6, a resistor R7, and two DC current sources, the difference a pair of transistors for amplifying an initial voltage signal input to the driving circuit;
  • the differential pair transistor includes a transistor Q3 and a transistor Q4, the initial voltage signal being respectively applied to a first pole of the Q3 and a first pole of the Q4, the R7 being coupled to a third pole of the Q4
  • the R5 is coupled between the third pole of the Q3 and the first signal source
  • the R6 is coupled to the second pole of the Q3 and the second pole of the Q4.
  • the two direct current sources are respectively coupled between the second pole of the Q3 and the second signal source and between the second pole of the Q4 and the second signal source, Two DC current sources are used to provide a DC bias current to the drive circuit;
  • R5 is a degraded resistor that is used to receive signals and increase the bandwidth of the driver circuit.
  • the driving circuit includes a differential pair transistor, a resistor R5, a resistor R6, a resistor R7, and two DC current sources, and the differential pair transistor is used to amplify an input to the driving circuit.
  • the differential pair transistor includes a transistor Q3 and a transistor Q4, the initial voltage signal being respectively applied to a first pole of the Q3 and a first pole of the Q4, the R7 being coupled to a third pole of the Q4
  • the R5 is coupled between the third pole of the Q3 and the first signal source
  • the R6 is coupled to the second pole of the Q3 and the second pole of the Q4.
  • the two direct current sources are respectively coupled between the second pole of the Q3 and the second signal source and between the second pole of the Q4 and the second signal source, Two DC current sources are used to provide a DC bias current to the drive circuit;
  • the third end of the Q4 is the output end of the driving circuit.
  • the driving circuit further includes a cascode tube, the cascode tube includes a transistor Q5 and a transistor Q6; the first poles of the Q5 and the Q6 are coupled to the same bias voltage, The second pole of the Q5 is coupled to the third pole of the Q3, the third pole of the Q5 is connected to the R5, and the second pole of the Q6 is coupled to the third pole of the Q4;
  • the third pole of the Q6 is connected to the R2;
  • the third pole of the Q6 is connected to the R7;
  • the third end of the Q6 is the output end of the driving circuit.
  • the sizes of Q3 and Q4 used in the above driving circuit are relatively large, so that for Q3 and Q4, the parasitic capacitance between the first pole and the third pole is relatively large, and the circuit works.
  • the parasitic capacitance generates a Miller effect, which affects the bandwidth and speed of the circuit.
  • Increasing the cascode tube can reduce the influence of parasitic capacitance on the circuit bandwidth, thereby increasing the driving speed of the circuit.
  • the impedance conversion circuit further includes a buffer stage coupled between the third pole of the Q6 and the first pole of the Q1.
  • the buffer stage can be used to match the voltage and resistance in the circuit.
  • the buffer stage includes a transistor Q7 and a resistor R8, a first pole of the Q7 is coupled to the third pole of the Q6, and a third pole of the Q7 is coupled to the first signal source.
  • the R8 is connected in series between the second pole of the Q7 and the first pole of the Q1.
  • the bias voltage Vb satisfies: V1+VBE5 ⁇ Vb ⁇ VDD ⁇ Ib1*R5, where V1 represents a voltage value of the initial voltage signal, and VBE5 represents a first pole and a second pole of the Q5.
  • the voltage difference between Ib1 represents a DC bias current value generated by a DC current source coupled to the second pole of the Q3, and the VDD represents a voltage value of the first signal source.
  • the impedance conversion circuit may further include a resistor R9 connected in series between the output terminal of the driving circuit and the first pole of the Q1.
  • R9 is the base equalization resistor.
  • the driving circuit further includes a capacitor C1, and the C1 is connected in parallel with the R5.
  • the branch of Q3 is not exactly the same as the branch of Q4.
  • the third pole of Q3 is broken. Risk, parallel to C1 on R5, can effectively prevent the third pole of Q3 from being broken down, improving the reliability of the circuit.
  • the present application further provides another driving phone, the driving circuit includes a differential pair transistor, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a transistor Q8, wherein the differential pair transistor is used to amplify the input to the The initial voltage signal of the drive circuit;
  • the differential pair transistor includes a transistor Q3 and a transistor Q4, the initial voltage signal being respectively applied to a first pole of the Q3 and a first pole of the Q4, the R10 being coupled to a third pole of the Q3
  • the R11 is coupled between the third pole of the Q4 and the first signal source
  • the R12 is coupled between the second pole of the Q3 and the third pole of the Q8.
  • the R13 is coupled between the second pole of the Q4 and the third pole of the Q8, the first pole of the Q8 is coupled to a bias voltage, and the second pole of the Q8 is Two signal sources are connected;
  • the third end of the Q4 is the output end of the driving circuit.
  • the driving circuit further includes a capacitor C1, and the C1 is connected in parallel with the R10.
  • the branch of Q3 is not exactly the same as the branch of Q4.
  • the third pole of Q3 is broken. Risk, parallel to C1 on R10, can effectively prevent the third pole of Q3 from being broken down, improving the reliability of the circuit.
  • the driving circuit further includes a capacitor C2 coupled between the second pole of the Q3 and the second pole of the Q4.
  • C2 is coupled between the second pole of Q3 and the second pole of Q4, that is, C2 is connected in parallel with R6, which can increase the bandwidth of the driving circuit.
  • the driving circuit further includes a capacitor C3 and a capacitor C4, and the C3 is coupled between the first pole of the Q3 and the third pole of the Q4, the C4 Coupling between the first pole of the Q4 and the third pole of the Q3.
  • the parasitic capacitance between the first pole and the third pole is relatively large for Q3 and Q4, respectively.
  • the parasitic capacitance will produce the Miller effect, affecting the bandwidth and speed of the circuit.
  • the laser driving circuit further includes a level converting circuit, configured to convert an input voltage signal input to the laser driving circuit into the initial voltage signal, and the initial voltage signal The drive circuit is input.
  • a level converting circuit configured to convert an input voltage signal input to the laser driving circuit into the initial voltage signal, and the initial voltage signal The drive circuit is input.
  • the input voltage signal may be output by the Serdes interface.
  • a front end circuit needs to be disposed between the laser driving circuit and the Serdes interface to equalize the input voltage signal to obtain an initial voltage signal, for example, The input voltage signal is superimposed on a certain DC level to obtain an initial voltage signal; and in the present application, by directly setting a level conversion circuit in the laser driving circuit, direct coupling between the input end of the laser driving circuit and the Serdes interface can be achieved.
  • the chip needs for light.
  • the level conversion circuit includes a first signal input end and a second signal input end, and the input voltage signal includes a first input voltage signal and a second input voltage signal, where the first input voltage signal passes through The first signal input terminal is input to the level conversion circuit, and the second input voltage signal is input to the level conversion circuit through the second signal input terminal, and the level conversion circuit includes a transistor Q9, a transistor Q10, Resistor R14 and resistor R15;
  • the first end of the Q9 is the first signal input end
  • the first end of the Q10 is the second signal input end
  • the third pole of the Q9 and the third pole of the Q10 are both coupled to the second a signal source
  • the second pole of the Q9 is connected to the first signal source through the R14
  • the second pole of the Q10 is connected to the first signal source through the R15
  • the second pole of the Q9 is
  • the second pole of the Q10 is configured to input the initial voltage signal into the driving circuit
  • first signal source and the second signal source are used to supply a power supply voltage to the laser driving circuit.
  • the level conversion circuit further includes a transistor Q11 coupled between the R14 and the first signal source, and a transistor Q12 coupled to the R15 and the first signal. Between sources;
  • first pole of the Q11 is coupled to the third pole of the Q11
  • the second pole of the Q11 is coupled to the first signal source
  • the third pole of the Q11 passes the R14 and the a second pole of Q9 is coupled
  • a first pole of the Q12 is coupled to the third pole of the Q12
  • a second pole of the Q12 is coupled to the first signal source
  • a third pole of the Q12 is passed through R15 is connected to the second pole of the Q10.
  • the present application provides an optoelectronic link system, the optoelectronic link system comprising a laser driving circuit and a laser, wherein the laser driving circuit is the laser driving circuit according to any one of the first aspects;
  • the laser driving circuit is configured to provide a DC bias signal and an AC working signal to the laser, the DC bias signal being a static operating point current of the laser;
  • the laser is used to convert the alternating current operating signal into an optical signal.
  • the laser driving circuit provided by the present application can provide a DC bias signal and an AC working signal to the electro-optical converter to drive the electro-optical converter to emit light. Compared with the related art, there is no need to provide an off-chip passive network, and the laser driving is reduced.
  • the area occupied by the circuit, and the bias current source is provided with a bias current source, which can shield the noise of the signal source, so there is no need to separately set the decoupling capacitor, which facilitates the integration of the laser driver and saves cost;
  • the impedance conversion circuit It can be used for impedance matching with an electro-optical converter, reducing signal reflection between the electro-optical converter and the laser driving circuit, and improving signal utilization; further, setting a level conversion circuit in the laser driving circuit can realize laser driving The direct coupling of the input of the circuit to the Serdes interface satisfies the requirements of the chip.
  • FIG. 1 is a schematic structural diagram of an optical link system according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a laser driving circuit provided by an embodiment of the present application.
  • Figure 3 shows the circuit symbol of the N-type transistor
  • Figure 4 shows the circuit symbol of the P-type transistor
  • Figure 5 shows the circuit symbol of the NMOS transistor
  • Figure 6 shows the circuit symbol of the PMOS tube
  • FIG. 7 is a schematic diagram of another laser driving circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of still another laser driving circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of still another laser driving circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of still another laser driving circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a laser driving circuit according to another embodiment of the present application.
  • FIG. 12 is a schematic diagram of another laser driving circuit according to another embodiment of the present application.
  • FIG. 13 is a schematic diagram of still another laser driving circuit according to another embodiment of the present application.
  • FIG. 14 is a schematic diagram of a laser driving circuit according to another embodiment of the present application.
  • 15 is a schematic diagram of another laser driving circuit according to another embodiment of the present application.
  • 16 is a schematic diagram of still another laser driving circuit according to another embodiment of the present application.
  • 17 is a schematic diagram of still another laser driving circuit according to another embodiment of the present application.
  • FIG. 18 is a schematic diagram of still another laser driving circuit according to another embodiment of the present application.
  • FIG. 19 is a schematic diagram of a laser driving circuit according to still another embodiment of the present application.
  • 20 is a schematic diagram of another laser driving circuit according to still another embodiment of the present application.
  • 21 is a schematic diagram of still another laser driving circuit according to still another embodiment of the present application.
  • FIG. 22 is a schematic diagram of still another laser driving circuit according to still another embodiment of the present application.
  • FIG. 23 is a schematic diagram of a laser driving circuit according to another embodiment of the present application.
  • FIG. 24 is a schematic diagram of another laser driving circuit according to another embodiment of the present application.
  • FIG. 25 is a schematic diagram of still another laser driving circuit according to another embodiment of the present application.
  • FIG. 26 is a schematic diagram of still another laser driving circuit according to another embodiment of the present application.
  • FIG. 27 is a schematic diagram of still another laser driving circuit according to an embodiment of the present application.
  • the system may include a transmitter (Transmitter, Tx) 01, a laser driver 02, an electro-optical converter 03, and an optical fiber 04.
  • the laser driver may include the laser driving circuit provided by the embodiment of the present application.
  • the laser driving circuit may be integrated on the driving chip or integrated on a printed circuit board (PCB) or a motherboard. limited.
  • the electro-optic converter can be a VCSEL or DML, etc., and the laser driving circuit can be connected to the electro-optical converter by wire or flip-chip bonding.
  • the laser driving circuit can be disposed in a Transmitter Optical Subassembly (TOSA) product or a router.
  • TOSA Transmitter Optical Subassembly
  • the optical link system provided by the embodiment of the present application may be applied to an Ethernet or data center switch, and the optical fiber may be a multimode fiber (MMF) with a length of 100 meters or a length of 2 kilometers.
  • MMF multimode fiber
  • SMF Single mode fiber
  • the laser driving circuit may include a driving circuit 021 and an impedance converting circuit 022.
  • the driving circuit 021 is configured to receive an initial voltage signal, convert the initial voltage signal into a target voltage signal, and output a target voltage signal to the impedance converting circuit 022.
  • the driving circuit can amplify Vin1 and Vin2 to obtain a target voltage signal.
  • the target voltage signal is a voltage signal required for the operation of the electro-optical converter.
  • the initial voltage signal can be provided by an external circuit, such as a front end circuit or an AC signal source.
  • the impedance conversion circuit 022 is configured to convert the target voltage signal into a target current signal, and provide a target current signal to the electro-optical converter 03.
  • the target current signal includes an alternating current working signal and a direct current bias signal, and the DC bias signal is used to provide electro-optical conversion.
  • the static working point of the electro-optical converter refers to the working state of the electro-optical converter when the electro-optical converter is in a static state.
  • the quiescent operating point is high and the AC signal is input to the electro-optical converter, the electro-optical converter will exhibit saturation distortion.
  • the quiescent operating point is low and the AC signal is input to the electro-optical converter, the electro-optical converter will have a cut-off distortion.
  • an appropriate DC bias signal can be supplied to the electro-optic converter. Further, the electro-optical converter can convert the target current signal into an optical signal.
  • the impedance conversion circuit 022 can also be used for impedance matching with the electro-optical converter 03.
  • the output impedance of the impedance conversion circuit can be approximately equal to the impedance of the electro-optic converter.
  • the output impedance of the impedance conversion circuit can also be designed to be about 50 ohms to achieve impedance matching between the impedance conversion circuit and the electro-optical converter.
  • the laser driving circuit provided by the embodiment of the present application can provide a DC bias signal and an AC working signal to the electro-optical converter to drive the electro-optical converter to emit light.
  • the impedance conversion circuit can be used for impedance matching with the electro-optical converter, and the electro-optical converter and the laser driving circuit are reduced. Signal reflection between them improves signal utilization.
  • the transistor according to the following embodiments of the present application may be a Bipolar Transistor (also referred to as a bipolar junction transistor) or a FET transistor (such as a Metal-Oxide-Semiconductor Field-Effect Transistor; MOSFET). )), etc., the type of transistor is not limited in this application. Among them, the transistor can be divided into an N-type transistor and a P-type transistor.
  • FIG. 3 and FIG. 4 are circuit symbols of an N-type transistor (NPN) and a P-type transistor (PNP), respectively; FIGS. 5 and 6 are respectively N-type.
  • N-type transistor corresponds to N-type MOSFET
  • P-type transistor corresponds to P-type MOSFET
  • the three electrodes of the triode are base (B1) and emitter (Emitter) ; E) and the collector (Collector; C), corresponding to the gate (Gate; G), source (S; S) and drain (Drain; D) of the MOSFET.
  • the transistor when the transistor is a triode, the first pole represents the base, the second pole represents the emitter, and the third pole represents the collector; when the transistor is a FET transistor, The first pole is used to indicate the gate, and the second pole and the third pole are used to represent one of the source and the drain, respectively.
  • the drawings in the following embodiments of the present application exemplarily explain the respective circuits by taking a triode as a transistor as an example.
  • FIG. 7 and FIG. 8 are schematic diagrams of an impedance conversion circuit provided by an embodiment of the present application.
  • the impedance conversion circuit 022 includes a resistor R1, a resistor R2, a resistor R3, and a transistor Q1, R1. Coupled between the first pole of Q1 and the third pole of Q1, the first pole of Q1 is coupled to the output of the driver circuit.
  • R2 is coupled between the first pole of Q1 and the first signal source VDD
  • R3 is coupled between the second pole of Q1 and the first signal source VDD
  • the electro-optic converter 03 Coupling between the third pole of Q1 and the first signal source VDD.
  • R2 is coupled between the first pole of Q1 and the second signal source VSS
  • R3 is coupled between the second pole of Q1 and the second signal source VSS
  • the electro-optic converter 03 Coupling between the third pole of Q1 and the second signal source VSS.
  • the first signal source and the second signal source are used to supply a power supply voltage to the laser driving circuit, and the power supply voltage is used to ensure that the laser driving circuit is in a normal working state.
  • the first signal source and the second signal source may be peripheral power circuits or DC power sources, which are not limited thereto.
  • the driving circuit provides the target voltage signal required for Q1 operation to point A, so that the current flowing through Q1 is equal to the sum of the required direct current and the alternating current, and the impedance converting circuit supplies the alternating current working signal and the direct current to the electro-optical converter.
  • the target current signal of the bias signal is used to drive the electro-optic converter to emit an optical signal.
  • R1 can be equal to R2, and R1, R2, R3, and Q1 can form a deep negative feedback network, and the impedance of the four electronic components is approximately (1+R1/R2)*R3, which needs to be explained Adjusting the resistance values of R1, R2 and/or R3 can achieve impedance matching between the impedance conversion circuit and the electro-optical converter, reduce signal reflection between the electro-optical converter and the laser driving circuit, and improve signal utilization.
  • the impedance conversion circuit 022 further includes a bias current source I BIAS , and the sum of the currents on R1, Q1 and the electro-optical converter 03 is equal to the current generated by the bias current source I BIAS .
  • the bias current source By setting the bias current source, the ripple (noise) of the first signal source and/or the second signal source can be shielded, the ripple is prevented from affecting the current passing through the electro-optical converter, and the optical signal output by the electro-optical converter is improved.
  • Signal-to-noise ratio eliminates the need to separately set the decoupling capacitor to shield the noise of the signal source, facilitating the integration of the laser driver circuit.
  • the bias current source I BIAS can be implemented by using a transistor.
  • the bias current source I BIAS is coupled between the third pole of Q1 and the second signal source VSS; see FIG. 8, when Q1 is an N-type transistor, the bias current source The I BIAS is coupled between the third pole of Q1 and the first signal source VDD.
  • the bias current source I BIAS may be formed by an N-type transistor; when Q1 is an N-type transistor, the bias current source I BIAS may be composed of a P-type transistor, using different types.
  • the transistor acts as a Q1 and bias current source, respectively, to complement Q1 and the bias current source to improve circuit performance.
  • FIG. 9 is a schematic diagram of another impedance conversion circuit according to an embodiment of the present application.
  • the impedance conversion circuit 022 includes a resistor R4, a transistor Q1, and a transistor Q2. Both Q1 and Q2 are N-type transistors. R4 is connected in series between the second pole of Q1 and the third pole of Q2, the first pole of Q1 is connected to the output end of the driving circuit, the third pole of Q1 is connected to the first signal source VDD, and the first pole of Q2 is coupled.
  • the second pole of Q2 is coupled to a second signal source VSS, and the electro-optic converter 03 is coupled between the third pole of Q1 and the third pole of Q2.
  • the bias voltage Va can be provided by a bias circuit (Bias Circuit; BC) or a DC power source.
  • the first signal source and the second signal source are used to supply a power supply voltage to the laser driving circuit, and the output impedance of the impedance converting circuit is approximately equal to the sum of the resistances of the second poles of R4 and Q1.
  • the power supply voltage is used to ensure that the laser driving circuit is in a normal working state, and the first signal source and the second signal source may be peripheral power circuits or DC power sources, which are not limited.
  • the driving circuit supplies the target voltage signal required for Q1 operation to point A, so that the current flowing through Q1 is equal to the sum of a required direct current and the alternating current, and the impedance conversion circuit converts to the electro-optical conversion.
  • a target current signal including an alternating current working signal and a direct current biasing signal is provided to drive the electro-optic converter to emit an optical signal.
  • the voltage difference between point A and VDD determines the current flowing through the electro-optical converter.
  • the impedance conversion circuit shown in FIG. 9 it is possible to realize that all the transistors provided in the laser driving circuit are N-type transistors, compared with the impedance conversion circuit shown in FIG. 7 or FIG.
  • the bandwidth and signal transmission rate of the impedance conversion circuit can be improved, and high-speed optoelectronic interconnection can be realized.
  • the impedance conversion circuit can be prepared not only by using an integrated circuit (IC) process.
  • an impedance conversion circuit can be prepared by connecting discrete devices on the PCB by wiring.
  • the impedance conversion circuit 022 may further include a resistor R9.
  • R9 is connected in series at the output end of the driving circuit 021 and the first of the Q1. Between the poles. Among them, R9 is the base equalization resistor. By setting the base equalization resistor, the oscillation of the circuit can be reduced and the circuit stability can be improved.
  • the embodiment of the present application provides a driving circuit.
  • the following describes the structure of the driving circuit through FIG. 11 to FIG. 13, including:
  • FIG. 11 is a schematic diagram of a laser driving circuit according to an embodiment of the present application.
  • the impedance conversion circuit is as shown in FIG. 7, that is, Q1 is a P-type transistor.
  • the driving circuit 021 includes a differential pair transistor.
  • the differential pair transistor is used to amplify the initial voltage signal input to the driving circuit;
  • the differential pair transistor includes transistor Q3 and transistor Q4, initial voltage signal Vin1 and Vin2 is respectively loaded on the first pole of Q3 and the first pole of Q4, R2 is coupled between the third pole of Q4 and the first signal source VDD, and R5 is coupled between the third pole of Q3 and the first signal source VDD.
  • R6 is coupled between the second pole of Q3 and the second pole of Q4, and two DC current sources are respectively coupled between the second pole of Q3 and the second signal source VSS and the second pole and the second signal source of Q4 Between VSS, two DC current sources are used to provide a DC bias current to the drive circuit.
  • the output end of the third extreme drive circuit of Q4 the output impedance of the impedance conversion circuit (from the point A to the impedance conversion circuit) is approximately (1+R1/R2)*R3.
  • the coupling point B is substantially the first pole of Q1, and the voltage of the coupling point B determines the magnitude of the current flowing through Q1.
  • the impedance converting circuit is as shown in FIG. 8, that is, Q1 is an N-type transistor.
  • the driving circuit 021 includes a differential pair transistor.
  • the differential pair transistor is used to amplify the initial voltage signal input to the driving circuit;
  • the differential pair transistor includes the transistor Q3 and the transistor Q4, and the initial voltage signal is respectively Loaded on the first pole of Q3 and the first pole of Q4,
  • R7 is coupled between the third pole of Q4 and the first signal source VDD, and
  • R5 is coupled between the third pole of Q3 and the first signal source VDD,
  • R6 Coupling between the second pole of Q3 and the second pole of Q4, two DC current sources are respectively coupled between the second pole of Q3 and the second signal source VSS and the second pole of Q4 and the second signal source VSS In between, two DC current sources are used to provide a DC bias current to the drive circuit.
  • the output end of the third extreme drive circuit of Q4 the output impedance of the impedance conversion circuit is approximately (1+R1/(R2
  • FIG. 13 is a schematic diagram of still another laser driving circuit according to an embodiment of the present application.
  • the impedance converting circuit is as shown in FIG. 9, that is, the transistors in the impedance converting circuit are all N-type transistors, see FIG.
  • driving The circuit comprises a differential pair transistor, a resistor R5, a resistor R6, a resistor R7 and two direct current sources (Ib1 and Ib2), the differential pair transistor is for amplifying an initial voltage signal input to the driving circuit; the differential pair transistor comprises a transistor Q3 and a transistor Q4 The initial voltage signals are respectively loaded on the first pole of Q3 and the first pole of Q4, R7 is coupled between the third pole of Q4 and the first signal source VDD, and R5 is coupled to the third pole of Q3 and the first signal source.
  • R6 is coupled between the second pole of Q3 and the second pole of Q4, and two DC current sources are respectively coupled between the second pole of Q3 and the second signal source VSS and the second pole of Q4 and Between the two signal sources VSS, two DC current sources are used to supply a DC bias current to the drive circuit.
  • the output end of the third extreme drive circuit of Q4, that is, the third pole of Q4 is connected to the first pole of Q1.
  • the working process of the laser driving circuit shown in FIG. 13 can refer to the working process of the laser driving circuit shown in FIG. 11, and details are not described herein.
  • the driving circuit 021 may further include a capacitor C2 coupled between the second pole of Q3 and the second pole of Q4, that is, C2 and R6 are connected in parallel to increase the driving circuit.
  • C2 and R6 are connected in parallel to increase the driving circuit.
  • R6 is a degenerative resistor for receiving signals and increasing the bandwidth of the driving circuit.
  • the driving circuit 021 may further include a capacitor C1.
  • the capacitors C1 and R5 are connected in parallel, wherein FIG. 14 Corresponding to Fig. 11, Fig. 15 corresponds to Fig. 12, and Fig. 16 corresponds to Fig. 13.
  • the branch of Q3 is not exactly the same as the branch of Q4.
  • the third pole of Q3 is The risk of breakdown, parallel to C1 on R5, can effectively prevent the third pole of Q3 from being broken down, improving the reliability of the circuit.
  • the embodiment of the present application further provides another driving circuit.
  • the driving circuit 021 includes a differential pair transistor, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a transistor Q8.
  • the differential pair transistor is used to amplify the input to The initial voltage signal of the driving circuit; the differential pair transistor includes a transistor Q3 and a transistor Q4, and the initial voltage signals Vin1 and Vin2 are respectively applied to the first pole of Q3 and the first pole of Q4, and R10 is coupled to the third pole of Q3 and the first Between the signal source VDD, R11 is coupled between the third pole of Q4 and the first signal source VDD, R12 is coupled between the second pole of Q3 and the third pole of Q8, and R13 is coupled to the second pole of Q4 and Q8. Between the third poles, the first pole of Q8 is coupled to a bias voltage Va, and the second pole of Q8 is coupled to the second signal source VSS.
  • the driving circuit 021 may further include a capacitor C1, and C1 and R10 are connected in parallel.
  • the branch of Q3 is not exactly the same as the branch of Q4.
  • the third pole of Q3 is The risk of breakdown, parallel to C1 on R10, can effectively prevent the third pole of Q3 from being broken down, improving the reliability of the circuit.
  • the impedance conversion circuit is taken as an example of the impedance conversion circuit shown in FIG. 9.
  • the driving circuit shown in FIG. 17 or FIG. 18 can also be matched as shown in FIG. 7 or The impedance conversion circuit shown in FIG. 8 will not be described here.
  • the embodiment of the present application further improves the circuit structure: as shown in FIG. 11 to FIG. 13 and The neutralization capacitors C3 and C4 are added to the drive circuit shown in any of FIG.
  • the driving circuit 021 may further include a capacitor C3 and a capacitor C4.
  • the C3 is coupled between the first pole of Q3 and the third pole of Q4, and C4 is coupled to the first pole of Q4.
  • FIG. 19 corresponds to FIG. 11
  • FIG. 20 corresponds to FIG. 12
  • FIG. 21 corresponds to FIG. 13
  • FIG. 22 corresponds to FIG.
  • the size of C3 is equal to the size of the parasitic capacitance between the base and the collector of Q3
  • the size of C4 is equal to the size of the parasitic capacitance between the base and the collector of Q4.
  • neutralization capacitors C3 and C4 are provided in the driving circuit to neutralize the capacitance between the base and the collector of Q3 and Q4, increase the bandwidth of the circuit, and thereby increase the driving speed of the circuit.
  • the problem of parasitic capacitance of Q3 and Q4 can also be solved by adding a cascode tube in the driving circuit.
  • the driving circuit 021 may further include a cascode tube including a transistor Q5 and a transistor Q6; the first poles of Q5 and Q6 are coupled at the same bias voltage Vb.
  • the second pole of Q5 is coupled to the third pole of Q3, the third pole of Q5 is coupled to R5, and the second pole of Q6 is coupled to the third pole of Q4.
  • FIG. 24 when Q1 is an N-type transistor, the third pole of Q6 is connected to R7, FIG. 24 corresponds to FIG. 12, and FIG. 25 corresponds to FIG.
  • the impedance conversion circuit 022 may further include a buffer stage coupled between the third pole of Q6 and the first pole of Q1.
  • the buffer stage includes The first pole of transistor Q7 and resistors R8, Q7 are coupled to the third pole of Q6, the third pole of Q7 is coupled to the first signal source VDD, and R8 is connected in series between the second pole of Q7 and the first pole of Q1. .
  • the bias voltage Vb satisfies: V1+VBE5 ⁇ Vb ⁇ VDD-Ib1*R5, wherein V1 represents a voltage value (Vin1) of the initial voltage signal, and VBE5 represents a voltage between the first pole and the second pole of Q5. The difference is about 0.8 volts, Ib1 represents the value of the DC bias current generated by the DC current source coupled to the second pole of Q3, and VDD represents the voltage value of the first signal source.
  • a resistor R8 can be connected in series between the point A and the second pole of Q7, and the output of the impedance conversion circuit at this time
  • the impedance is approximately (1+R1/(R2
  • the laser driving circuit provided by the embodiment of the present application may further include a level converting circuit 023 for converting an input voltage signal input to the laser driving circuit into The initial voltage signal is input to the drive circuit 021.
  • the input voltage signal may be output by the Serdes interface.
  • the front end circuit pair input voltage signal needs to be set between the laser driving circuit and the Serdes interface.
  • the input voltage signal may be superimposed on a certain DC level to obtain an initial voltage signal; and in the embodiment of the present application, the laser may be implemented by setting a level conversion circuit in the laser driving circuit.
  • the direct coupling of the input of the drive circuit to the Serdes interface satisfies the requirements of the chip.
  • the input voltage signal can be a 4-level Pulse Amplitude Modulation-4 level (PAM4) signal.
  • PAM4 4-level Pulse Amplitude Modulation-4 level
  • the level conversion circuit 023 includes a first signal input terminal Int1 and a second signal input terminal int2.
  • the input voltage signal includes a first input voltage signal Vin+ and a second input voltage signal Vin-, and the first input voltage signal Vin+ passes
  • the first signal input terminal int1 is input to the level conversion circuit 023, and the second input voltage signal Vin- is input to the level conversion circuit 023 through the second signal input terminal int2.
  • the level conversion circuit 023 includes a transistor Q9, a transistor Q10, a resistor R14 and a resistor.
  • the first extreme first signal input terminal int1 of Q9, the first extreme second signal input terminal int2 of Q10, the third pole of Q9 and the third pole of Q10 are coupled to the second signal source VSS, the first of Q9
  • the second pole is connected to the first signal source VDD through R14
  • the second pole of Q10 is connected to the first signal source VDD through R15
  • the second pole of Q9 and the second pole of Q10 are used to input the initial voltage signals (Vin1 and Vin2) Drive circuit 021.
  • the first signal source and the second signal source are used to supply a power supply voltage to the laser driving circuit, and the power supply voltage is used to ensure that the laser driving circuit is in a normal working state.
  • a resistance of 100 ohms ( ⁇ ) may be coupled between the first signal input terminal int1 and the second signal input terminal int2.
  • the level conversion circuit can increase the input voltage signal (for example, 0.2 to 0.6 volts) to the initial voltage signal required by the driving circuit (for example, 0.9 to 1.3 volts). ), the input voltage signal outputted by the Serdes interface can directly drive the function of the electro-optical converter after passing through the laser driving circuit.
  • the level shifting circuit 023 may further include a transistor Q11 and a transistor Q12, Q11 is coupled between R14 and the first signal source VDD, and Q12 is coupled between R15 and the first signal source VDD; wherein, Q11 The first pole is coupled to the third pole of Q11, the second pole of Q11 is coupled to the first signal source VDD, the third pole of Q11 is coupled to the second pole of Q9 via R14, and the first pole of Q12 is coupled to Q12 On the third pole, the second pole of Q12 is coupled to the first signal source VDD, and the third pole of Q12 is coupled to the second pole of Q10 via R15.
  • Q11 and Q12 can share a part of the voltage drop, and the voltage of VDD after Q11 and Q12 is reduced by about 0.7 volt, so that the resistance of R14 and R15 can be reduced. The value, in turn, reduces the area of the laser drive circuit.
  • the driving circuit involved in FIGS. 26 and 27 may be a driving circuit as shown in any of FIGS. 11 to 16, 19 to 21, and 23 to 25; in FIGS. 26 and 27
  • the impedance conversion circuit shown in FIG. 7 is used as an example.
  • the actual impedance conversion circuit can also be an impedance conversion circuit as shown in any of FIG. 8 to FIG. 10, which is not limited in this embodiment of the present application.
  • the driving circuit is described by taking an N-type transistor as an example.
  • a P-type transistor can also be used in the driving circuit, and the circuit structure can refer to an N-type transistor.
  • the circuit structure is not described here.
  • an N-type transistor is used in the laser driving circuit, not only the laser driving circuit can be prepared by using an IC process, but also the laser driving circuit can be prepared by using a wiring connection discrete device on the PCB.
  • the laser driving circuit provided by the embodiment of the present application can provide a DC bias signal and an AC working signal to the electro-optical converter to drive the electro-optical converter to emit light, and does not need to be provided with off-chip passiveness compared with the related art.
  • the network reduces the area occupied by the laser driving circuit, and the bias current source is provided with a bias current source, which can shield the noise of the signal source, so there is no need to separately set the decoupling capacitor, which facilitates the integration of the laser driver and saves Cost;
  • the impedance conversion circuit can be used for impedance matching with the electro-optic converter, reducing signal reflection between the electro-optical converter and the laser driving circuit, and improving signal utilization; further, setting the level in the laser driving circuit
  • the conversion circuit can realize direct coupling between the input end of the laser driving circuit and the Serdes interface, and meets the requirement of the chip light emission.
  • R represents a resistor
  • Q represents a transistor
  • C represents a capacitor

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Abstract

本申请公开了一种激光器驱动电路，属于电路技术领域。所述激光器驱动电路包括：驱动电路和阻抗转换电路；所述驱动电路用于接收初始电压信号，并将所述初始电压信号转换为目标电压信号，向所述阻抗转换电路输出所述目标电压信号；所述阻抗转换电路用于将所述目标电压信号转换为目标电流信号，并向电光转换器提供所述目标电流信号，所述目标电流信号包括交流工作信号和直流偏置信号，所述直流偏置信号用于提供所述电光转换器的静态工作点电流。本申请解决了相关技术中激光器驱动器的集成度较低的问题。

Description

激光器驱动电路
本申请要求于2018年05月16日提交的申请号为201810468501.0、发明名称为“激光器驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，特别涉及一种激光器驱动电路。
背景技术
随着互联网技术的快速发展，光电互连需求不断增长。目前的光电链路系统(也可称为光电互连链路系统)主要包括依次连接的专用集成电路(Application Specific Integrated Circuit；ASIC)芯片、激光器驱动器(Laser Driver)、激光器、光纤、光电探测器(Photoelectric Detector；PD)和跨阻放大器(Trans-Impedance Amplifier；TIA)。ASIC芯片通过设置在ASIC芯片中的Serdes接口(一种串行通信接口)与激光器驱动器耦合，并向激光器驱动器提供初始电压信号；激光器驱动器用于将初始电压信号转换为电流信号，并向激光器提供该电流信号；电流信号经过激光器时激发激光器发射光信号；激光器发射的光信号通过光纤向光电探测器传输；光电探测器用于将接收到的光信号转换为电流信号，跨阻放大器用于将电流信号转换为电压信号。其中，激光器可以为垂直腔面发射激光器(Vertical Cavity Surface Emitting Laser；VCSEL)或直接调制激光器(Direct Modulation Laser；DML)等。
相关技术中提供了一种激光器驱动器，该激光器驱动器包括两部分：片内驱动电路和片外无源网络，片内驱动电路在驱动芯片上制备，片外无源网络由电阻、电容和电感等无源器件组成，片内驱动电路和片外无源网络在印制电路板(Printed Circuit Board；PCB)上完成互连。该激光器驱动器通过片外无源网络分别向激光器提供直流偏置电流和交流工作电流(交流工作电流由片内驱动电路提供)，以激发激光器发出光信号。其中，直流偏置电流用于提供激光器工作所需的静态工作点电流，交流工作电流用于调制激光器的光功率。
但是，相关技术提供的激光器驱动器中，片外无源网络占用的面积较大，不便于集成在芯片中，导致激光器驱动器的集成度较低。
发明内容
本申请实施例提供了一种激光器驱动电路，可以解决相关技术中激光器驱动器的集成度较低的问题。所述技术方案如下：
第一方面，本申请提供了一种激光器驱动电路，所述激光器驱动电路包括：驱动电路和阻抗转换电路；
所述驱动电路用于接收初始电压信号，并将所述初始电压信号转换为目标电压信号，向所述阻抗转换电路输出所述目标电压信号；所述阻抗转换电路用于将所述目标电压信号转换为目标电流信号，并向电光转换器提供所述目标电流信号，所述目标电流信号包括交流工作信号和直流偏置信号，所述直流偏置信号用于提供所述电光转换器的静态工作点电 流。
需要说明的是，本申请提供的激光器驱动电路能够实现向电光转换器提供直流偏置信号和交流工作信号，以驱动电光转换器发光，与相关技术相比，无需设置片外无源网络，减小了激光器驱动电路所占用的面积，便于实现激光器驱动器的集成，且节约了成本。
可选的，所述阻抗转换电路还用于与所述电光转换器进行阻抗匹配。其中，阻抗转换电路的输出阻抗可以等电光转换器的阻抗，也可以不等于电光转换器的阻抗，对此不做限定。
需要说明的是，阻抗转换电路能够用于与电光转换器进行阻抗匹配，减少了电光转换器与激光器驱动电路之间的信号反射，提高了信号利用率。
可选的，在第一种阻抗转换电路中，所述阻抗转换电路包括电阻R1、电阻R2、电阻R3、晶体管Q1和偏置电流源，所述R1耦合在所述Q1的第一极和所述Q1的第三极之间，所述Q1的第一极与所述驱动电路的输出端连接，所述R1、所述Q1与所述电光转换器上的电流之和等于所述偏置电流源所产生的电流；
当所述Q1为P型晶体管时，所述R2耦合在所述Q1的第一极与第一信号源之间，所述R3耦合在所述Q1的第二极与所述第一信号源之间，所述电光转换器耦合在所述Q1的第三极与所述第一信号源之间，所述偏置电流源耦合在所述Q1的第三极与第二信号源之间；
当所述Q1为N型晶体管时，所述R2耦合在所述Q1的第一极与所述第二信号源之间，所述R3耦合在所述Q1的第二极与所述第二信号源之间，所述电光转换器耦合在所述Q1的第三极与所述第二信号源之间，所述偏置电流源耦合在所述Q1的第三极与所述第一信号源之间；
其中，所述第一信号源和所述第二信号源用于向所述激光器驱动电路提供电源电压。
可选的，所述阻抗转换电路还包括偏置电流源，所述R1、所述Q1与所述电光转换器上的电流之和等于所述偏置电流源所产生的电流；当所述Q1为P型晶体管时，所述偏置电流源耦合在所述Q1的第三极与所述第二信号源之间；当所述Q1为N型晶体管时，所述偏置电流源耦合在所述Q1的第三极与所述第一信号源之间。
需要说明的是，通过设置偏置电流源，可以屏蔽第一信号源和/或第二信号源的纹波(噪声)，避免纹波对电光转换器上经过的电流造成影响，提高电光转换器输出的光信号的信噪比，无需单独设置退耦电容以屏蔽信号源的噪声，便于实现激光器驱动电路的集成。其中，偏置电流源I BIAS可以是利用晶体管实现的。
可选的，在第二种阻抗转换电路中，所述阻抗转换电路包括电阻R4、晶体管Q1和晶体管Q2，所述Q1与所述Q2均为N型晶体管；
所述R4串联在所述Q1的第二极与所述Q2的第三极之间，所述Q1的第一极与所述驱动电路的输出端连接，所述Q1的第三极与第一信号源连接，所述Q2的第一极耦合在某一偏置电压上，所述Q2的第二极与第二信号源连接，所述电光转换器耦合在所述Q1的第三极与所述Q2的第三极之间；
其中，所述第一信号源和所述第二信号源用于向所述激光器驱动电路提供电源电压。
需要说明的是，在阻抗转换电路中设置全N型晶体管，一方面可以提高阻抗转换电路的带宽和信号传输速率，便于实现高速的光电互连，另一方面由于N型晶体管的分立器件 较为成熟，不仅可以采用集成电路(Integrated Circuit；IC)工艺制备阻抗转换电路，而且可以通过在PCB上采用布线连接分立器件制备阻抗转换电路。
可选的，针对第一种阻抗转换电路，当所述Q1为P型晶体管时，所述驱动电路包括差分对晶体管、所述电阻R2、电阻R5、电阻R6和两个直流电流源，所述差分对晶体管用于放大输入至所述驱动电路的初始电压信号；
所述差分对晶体管包括晶体管Q3和晶体管Q4，所述初始电压信号分别加载在所述Q3的第一极和所述Q4的第一极上，所述R2耦合在所述Q4的第三极与所述第一信号源之间，所述R5耦合在所述Q3的第三极与所述第一信号源之间，所述R6耦合在所述Q3的第二极与所述Q4的第二极之间，所述两个直流电流源分别耦合在所述Q3的第二极与所述第二信号源之间以及所述Q4的第二极与所述第二信号源之间，所述两个直流电流源用于向所述驱动电路提供直流偏置电流；
其中，所述Q4的第三极为所述驱动电路的输出端。R5为退化电阻，用于承接信号以及增加驱动电路的带宽。
可选的，针对第一种阻抗转换电路，，当所述Q1为N型晶体管时，所述驱动电路包括差分对晶体管、电阻R5、电阻R6、电阻R7和两个直流电流源，所述差分对晶体管用于放大输入至所述驱动电路的初始电压信号；
所述差分对晶体管包括晶体管Q3和晶体管Q4，所述初始电压信号分别加载在所述Q3的第一极和所述Q4的第一极上，所述R7耦合在所述Q4的第三极与所述第一信号源之间，所述R5耦合在所述Q3的第三极与所述第一信号源之间，所述R6耦合在所述Q3的第二极与所述Q4的第二极之间，所述两个直流电流源分别耦合在所述Q3的第二极与所述第二信号源之间以及所述Q4的第二极与所述第二信号源之间，所述两个直流电流源用于向所述驱动电路提供直流偏置电流；
其中，所述Q4的第三极为所述驱动电路的输出端。R5为退化电阻，用于承接信号以及增加驱动电路的带宽。
可选的，针对第二种阻抗转换电路，所述驱动电路包括差分对晶体管、电阻R5、电阻R6、电阻R7和两个直流电流源，所述差分对晶体管用于放大输入至所述驱动电路的初始电压信号；
所述差分对晶体管包括晶体管Q3和晶体管Q4，所述初始电压信号分别加载在所述Q3的第一极和所述Q4的第一极上，所述R7耦合在所述Q4的第三极与所述第一信号源之间，所述R5耦合在所述Q3的第三极与所述第一信号源之间，所述R6耦合在所述Q3的第二极与所述Q4的第二极之间，所述两个直流电流源分别耦合在所述Q3的第二极与所述第二信号源之间以及所述Q4的第二极与所述第二信号源之间，所述两个直流电流源用于向所述驱动电路提供直流偏置电流；
其中，所述Q4的第三极为所述驱动电路的输出端。
可选的，所述驱动电路还包括共源共栅管，所述共源共栅管包括晶体管Q5和晶体管Q6；所述Q5和所述Q6的第一极耦合在同一偏置电压上，所述Q5的第二极耦合在所述Q3的第三极上，所述Q5的第三极与所述R5连接，所述Q6的第二极耦合在所述Q4的第三极上；
当所述Q1为P型晶体管时，所述Q6的第三极与所述R2连接；
当所述Q1为N型晶体管时，所述Q6的第三极与所述R7连接；
其中，所述Q6的第三极为所述驱动电路的输出端。
需要说明的是，上述驱动电路中所采用的Q3和Q4的尺寸相对较大，因此分别对于Q3和Q4而言，第一极和第三极之间的寄生电容比较大，在电路的工作过程中，该寄生电容会产生米勒效应，影响电路的带宽和速度，增加共源共栅管可以减小寄生电容对电路带宽的影响，进而提高电路的驱动速度。
可选的，当所述Q1为N型晶体管时，所述阻抗转换电路还包括缓冲级，所述缓冲级耦合在所述Q6的第三极与所述Q1的第一极之间。
其中，缓冲级可以用于匹配电路中的电压和电阻。
可选的，所述缓冲级包括晶体管Q7和电阻R8，所述Q7的第一极耦合在所述Q6的第三极上，所述Q7的第三极耦合在所述第一信号源上，所述R8串联在所述Q7的第二极与所述Q1的第一极之间。
可选的，所述偏置电压Vb满足：V1+VBE5＜Vb＜VDD-Ib1*R5，其中，V1表示所述初始电压信号的电压值，VBE5表示所述Q5的第一极与第二极之间的电压差值，Ib1表示与所述Q3的第二极耦合的直流电流源所产生的直流偏置电流值，所述VDD表示所述第一信号源的电压值。
需要说明的是，将Q5和Q6的第一极耦合在偏置电压Vb上，且使偏置电压Vb满足上述公式，可以使得驱动电路中的所有晶体管均处于放大状态。
在第二种阻抗转换电路中，阻抗转换电路还可以包括电阻R9，所述R9串联在所述驱动电路的输出端与所述Q1的第一极之间。其中，R9为基极均衡电阻，通过设置基极均衡电阻可以减小电路的振荡，提高电路稳定性。
可选的，所述驱动电路还包括电容C1，所述C1与所述R5并联。
需要说明的是，由于在驱动电路工作过程中，Q3所在支路与Q4所在支路不完全相同，当输入的初始电压信号的电压摆幅较大时，Q3的第三极有被击穿的风险，在R5上并联上C1，可以有效防止Q3的第三极被击穿，提高了电路的可靠性。
可选的，本申请还提供了另一种驱动电话，该驱动电路包括差分对晶体管、电阻R10、电阻R11、电阻R12、电阻R13和晶体管Q8，所述差分对晶体管用于放大输入至所述驱动电路的初始电压信号；
所述差分对晶体管包括晶体管Q3和晶体管Q4，所述初始电压信号分别加载在所述Q3的第一极和所述Q4的第一极上，所述R10耦合在所述Q3的第三极与第一信号源之间，所述R11耦合在所述Q4的第三极与所述第一信号源之间，所述R12耦合在所述Q3的第二极与所述Q8的第三极之间，所述R13耦合在所述Q4的第二极与所述Q8的第三极之间，所述Q8的第一极耦合在某一偏置电压上，所述Q8的第二极与第二信号源连接；
其中，所述Q4的第三极为所述驱动电路的输出端。
可选的，所述驱动电路还包括电容C1，所述C1与所述R10并联。
需要说明的是，由于在驱动电路工作过程中，Q3所在支路与Q4所在支路不完全相同，当输入的初始电压信号的电压摆幅较大时，Q3的第三极有被击穿的风险，在R10上并联上C1，可以有效防止Q3的第三极被击穿，提高了电路的可靠性。
可选的，在第一种驱动电路中，所述驱动电路还包括电容C2，所述C2耦合在所述Q3 的第二极与所述Q4的第二极之间。
其中，C2耦合在Q3的第二极与Q4的第二极之间，也即是，C2与R6并联，可以增加驱动电路的带宽。
可选的，在上述两种驱动电路中，所述驱动电路还包括电容C3和电容C4，所述C3耦合在所述Q3的第一极与所述Q4的第三极之间，所述C4耦合在所述Q4的第一极与所述Q3的第三极之间。
需要说明的是，由于上述两种驱动电路中，所采用的Q3和Q4的尺寸相对较大，因此分别对于Q3和Q4而言，第一极和第三极之间的寄生电容比较大，在电路的工作过程中，该寄生电容会产生米勒效应，影响电路的带宽和速度，通过在驱动电路中设置中和电容C3和C4，可以中和Q3和Q4的基极和集电极之间的电容，增大电路的带宽，进而提升电路的驱动速度。
可选的，所述激光器驱动电路还包括电平转换电路，所述电平转换电路用于将输入所述激光器驱动电路的输入电压信号转换为所述初始电压信号，并将所述初始电压信号输入所述驱动电路。
需要说明的是，输入电压信号可以是Serdes接口输出的，在前述激光器驱动电路中，需要在激光器驱动电路与Serdes接口之间设置前端电路对输入电压信号进行均衡以得到初始电压信号，例如可以将输入电压信号叠加在某一直流电平上以得到初始电压信号；而在本申请中，通过在激光器驱动电路中设置电平转换电路，可以实现激光器驱动电路的输入端与Serdes接口的直接耦合，满足了芯片出光需求。
可选的，所述电平转换电路包括第一信号输入端和第二信号输入端，所述输入电压信号包括第一输入电压信号和第二输入电压信号，所述第一输入电压信号通过所述第一信号输入端输入所述电平转换电路，所述第二输入电压信号通过所述第二信号输入端输入所述电平转换电路，所述电平转换电路包括晶体管Q9、晶体管Q10、电阻R14和电阻R15；
所述Q9的第一极为所述第一信号输入端，所述Q10的第一极为所述第二信号输入端，所述Q9的第三极与所述Q10的第三极均耦合在第二信号源上，所述Q9的第二极通过所述R14与第一信号源连接，所述Q10的第二极通过所述R15与所述第一信号源连接，所述Q9的第二极与所述Q10的第二极用于将所述初始电压信号输入所述驱动电路；
其中，所述第一信号源和所述第二信号源用于向所述激光器驱动电路提供电源电压。
可选的，所述电平转换电路还包括晶体管Q11和晶体管Q12，所述Q11耦合在所述R14与所述第一信号源之间，所述Q12耦合在所述R15与所述第一信号源之间；
其中，所述Q11的第一极耦合在所述Q11的第三极上，所述Q11的第二极与所述第一信号源连接，所述Q11的第三极通过所述R14与所述Q9的第二极连接，所述Q12的第一极耦合在所述Q12的第三极上，所述Q12的第二极与所述第一信号源连接，所述Q12的第三极通过所述R15与所述Q10的第二极连接。
第二方面，本申请提供了一种光电链路系统，所述光电链路系统包括激光器驱动电路及激光器，所述激光器驱动电路为第一方面任一所述的激光器驱动电路；
所述激光器驱动电路用于向所述激光器提供直流偏置信号和交流工作信号，所述直流偏置信号为所述激光器的静态工作点电流；
所述激光器用于将所述交流工作信号转换为光信号。
本申请实施例提供的技术方案带来的有益效果包括：
本申请提供的激光器驱动电路，能够实现向电光转换器提供直流偏置信号和交流工作信号，以驱动电光转换器发光，与相关技术相比，无需设置片外无源网络，减小了激光器驱动电路所占用的面积，且阻抗转换电路中设置有偏置电流源，可以屏蔽信号源的噪声，因此无需单独设置退耦电容，便于实现激光器驱动器的集成，且节约了成本；另外，阻抗转换电路能够用于与电光转换器进行阻抗匹配，减少了电光转换器与激光器驱动电路之间的信号反射，提高了信号利用率；进一步的，在激光器驱动电路中设置电平转换电路，可以实现激光器驱动电路的输入端与Serdes接口的直接耦合，满足了芯片出光需求。
附图说明
图1是本申请实施例提供的一种光电链路系统的结构示意图；
图2是本申请实施例提供的一种激光器驱动电路的示意图；
图3表示N型三极管的电路符号；
图4表示P型三极管的电路符号；
图5表示NMOS管的电路符号；
图6表示PMOS管的电路符号；
图7是本申请实施例提供的另一种激光器驱动电路的示意图；
图8是本申请实施例提供的又一种激光器驱动电路的示意图；
图9是本申请实施例提供的再一种激光器驱动电路的示意图；
图10是本申请实施例提供的还一种激光器驱动电路的示意图；
图11是本申请另一实施例提供的一种激光器驱动电路的示意图；
图12是本申请另一实施例提供的另一种激光器驱动电路的示意图；
图13是本申请另一实施例提供的又一种激光器驱动电路的示意图；
图14是本申请又一实施例提供的一种激光器驱动电路的示意图；
图15是本申请又一实施例提供的另一种激光器驱动电路的示意图；
图16是本申请又一实施例提供的又一种激光器驱动电路的示意图；
图17是本申请又一实施例提供的再一种激光器驱动电路的示意图；
图18是本申请又一实施例提供的还一种激光器驱动电路的示意图；
图19是本申请再一实施例提供的一种激光器驱动电路的示意图；
图20是本申请再一实施例提供的另一种激光器驱动电路的示意图；
图21是本申请再一实施例提供的又一种激光器驱动电路的示意图；
图22是本申请再一实施例提供的再一种激光器驱动电路的示意图；
图23是本申请还一实施例提供的一种激光器驱动电路的示意图；
图24是本申请还一实施例提供的另一种激光器驱动电路的示意图；
图25是本申请还一实施例提供的又一种激光器驱动电路的示意图；
图26是本申请还一实施例提供的再一种激光器驱动电路的示意图；
图27是本申请还一实施例提供的还一种激光器驱动电路的示意图。
具体实施方式
下面将结合附图对本申请实施方式作进一步地详细描述。
图1是本申请实施例提供的一种光电链路系统的结构示意图，如图1所示，该系统可以包括发送机(Transmitter，Tx)01、激光器驱动器02、电光转换器03、光纤04、光电探测器05、跨阻放大器06和接收机(Receiver；Rx)07。其中，激光器驱动器可以包括本申请实施例提供的激光器驱动电路，该激光器驱动电路可以集成在驱动芯片上，也可以集成在印制电路板(Printed Circuit Board；PCB)或主板上，对此不做限定。电光转换器可以为VCSEL或DML等，激光器驱动电路可以通过金属线或倒装焊的形式与电光转换器连接。可选的，该激光器驱动电路可以设置在光发射次模块(Transmitter Optical Subassembly；TOSA)产品或路由器中。
可选的，本申请实施例提供的光电链路系统可以应用于以太网或数据中心交换机，上述光纤可以为长度为100米的多模光纤(Multi Mode Fiber；MMF)或长度为2千米的单模光纤(Single Mode Fiber；SMF)等。
图2是本申请实施例提供的一种激光器驱动电路的示意图，如图2所示，该激光器驱动电路可以包括：驱动电路021和阻抗转换电路022。
驱动电路021用于接收初始电压信号，并将初始电压信号转换为目标电压信号，向阻抗转换电路022输出目标电压信号。
参见图2，初始电压信号包括Vin1和Vin2，Vin1和Vin2输入驱动电路后，驱动电路可以对Vin1和Vin2进行放大，以得到目标电压信号。其中，目标电压信号为电光转换器工作所需的电压信号。
可选的，初始电压信号可以由外部电路(例如前端电路或交流信号源)提供。
阻抗转换电路022用于将目标电压信号转换为目标电流信号，并向电光转换器03提供目标电流信号，目标电流信号包括交流工作信号和直流偏置信号，该直流偏置信号用于提供电光转换器03的静态工作点电流。
其中，电光转换器的静态工作点是指当电光转换器处于静态时，电光转换器所处的工作状态。当静态工作点偏高，向电光转换器输入交流信号时，电光转换器会出现饱和失真的现象；当静态工作点偏低，向电光转换器输入交流信号时，电光转换器会出现截止失真的现象，可通过阻抗转换电路向电光转换器提供合适的直流偏置信号。进一步的，电光转换器可以将目标电流信号转换为光信号。
可选的，阻抗转换电路022还可以用于与电光转换器03进行阻抗匹配。
其中，阻抗转换电路的输出阻抗可以近似等于电光转换器的阻抗。示例的，当电光转换器的阻抗为50欧姆时，可以设计阻抗转换电路的输出阻抗也约为50欧姆，以实现阻抗转换电路与电光转换器的阻抗匹配。
需要说明的是，本申请实施例提供的激光器驱动电路能够实现向电光转换器提供直流偏置信号和交流工作信号，以驱动电光转换器发光，与相关技术相比，无需设置片外无源网络，减小了激光器驱动电路所占用的面积，便于实现激光器驱动器的集成，且节约了成本；另外，阻抗转换电路能够用于与电光转换器进行阻抗匹配，减少了电光转换器与激光器驱动电路之间的信号反射，提高了信号利用率。
本申请以下实施例涉及的晶体管可以为三极管(Bipolar Transistor)(也可称为双极结型晶体管)或场效应管晶体管(例如金属氧化物半导体管(Metal-Oxide-Semiconductor Field-Effect Transistor；MOSFET))等，本申请对晶体管的类型不做限定。其中，晶体管可以分为N型晶体管和P型晶体管，示例的，图3和图4分别为N型三极管(NPN)和P型三极管(PNP)的电路符号；图5和图6分别为N型MOSFET(NMOS)和P型MOSFET(PMOS)的电路符号；N型三极管对应N型MOSFET，P型三极管对应P型MOSFET，三极管的三个电极分别是基极(Base；B)、发射极(Emitter；E)和集电极(Collector；C)，分别对应MOSFET管的栅极(Gate；G)、源极(Source；S)和漏极(Drain；D)。
为了便于描述，在本申请实施例中，当晶体管为三极管时，采用第一极表示基极，采用第二极表示发射极，采用第三极表示集电极；当晶体管为场效应管晶体管时，采用第一极表示栅极，采用第二极和第三极分别表示源极和漏极中的一个。本申请以下实施例中的附图以采用三极管作为晶体管为例对各个电路进行示例性解释。
可选的，图7和图8分别是本申请实施例提供的阻抗转换电路的示意图，如图7和图8所示，阻抗转换电路022包括电阻R1、电阻R2、电阻R3和晶体管Q1，R1耦合在Q1的第一极和Q1的第三极之间，Q1的第一极与驱动电路的输出端连接。
参见图7，当Q1为P型晶体管时，R2耦合在Q1的第一极与第一信号源VDD之间，R3耦合在Q1的第二极与第一信号源VDD之间，电光转换器03耦合在Q1的第三极与第一信号源VDD之间。
参见图8，当Q1为N型晶体管时，R2耦合在Q1的第一极与第二信号源VSS之间，R3耦合在Q1的第二极与第二信号源VSS之间，电光转换器03耦合在Q1的第三极与第二信号源VSS之间。
其中，第一信号源和第二信号源用于向激光器驱动电路提供电源电压，该电源电压用于保证激光器驱动电路处于正常工作状态。第一信号源和第二信号源可以为外围电源电路或直流电源，对此不做限定。驱动电路通过向A点提供Q1工作所需的目标电压信号，使得流过Q1的电流等于某一需要的直流电流与交流电流之和，阻抗转换电路再向电光转换器提供包括交流工作信号和直流偏置信号的目标电流信号，以驱动电光转换器发出光信号。
可选的，R1可以等于R2，R1、R2、R3和Q1能够组成一个深度负反馈网络，该四个电子元件组成的阻抗近似为(1+R1/R2)*R3，需要说明的是，通过调整R1、R2和/或R3的电阻值，可以实现阻抗转换电路与电光转换器的阻抗匹配，减少了电光转换器与激光器驱动电路之间的信号反射，提高了信号利用率。
参见图7或图8，阻抗转换电路022还包括偏置电流源I BIAS，R1、Q1与电光转换器03上的电流之和等于偏置电流源I BIAS所产生的电流。通过设置偏置电流源，可以屏蔽第一信号源和/或第二信号源的纹波(噪声)，避免纹波对电光转换器上经过的电流造成影响，提高电光转换器输出的光信号的信噪比，无需单独设置退耦电容以屏蔽信号源的噪声，便于实现激光器驱动电路的集成。其中，偏置电流源I BIAS可以是利用晶体管实现的。
参见图7，当Q1为P型晶体管时，偏置电流源I BIAS耦合在Q1的第三极与第二信号源VSS之间；参见图8，当Q1为N型晶体管时，偏置电流源I BIAS耦合在Q1的第三极与第一信号源VDD之间。
可选的，当Q1为P型晶体管时，偏置电流源I BIAS可以由N型晶体管构成；当Q1为N型晶体管时，偏置电流源I BIAS可以由P型晶体管构成，采用不同类型的晶体管分别作为Q1和偏置电流源，可以实现Q1和偏置电流源的互补，以提高电路的性能。
可选的，图9是本申请实施例提供的另一种阻抗转换电路的示意图，如图9所示，阻抗转换电路022包括电阻R4、晶体管Q1和晶体管Q2，Q1与Q2均为N型晶体管；R4串联在Q1的第二极与Q2的第三极之间，Q1的第一极与驱动电路的输出端连接，Q1的第三极与第一信号源VDD连接，Q2的第一极耦合在某一偏置电压Va上，Q2的第二极与第二信号源VSS连接，电光转换器03耦合在Q1的第三极与Q2的第三极之间。示例的，该偏置电压Va可以由偏置电路(Bias Circuit；BC)或直流电源提供。
其中，第一信号源和第二信号源用于向激光器驱动电路提供电源电压，阻抗转换电路的输出阻抗近似等于R4与Q1的第二极的电阻之和。电源电压用于保证激光器驱动电路处于正常工作状态，第一信号源和第二信号源可以为外围电源电路或直流电源，对此不做限定。在图7至图9中，驱动电路通过向A点提供Q1工作所需的目标电压信号，使得流过Q1的电流等于某一需要的直流电流与交流电流之和，阻抗转换电路再向电光转换器提供包括交流工作信号和直流偏置信号的目标电流信号，以驱动电光转换器发出光信号。
在如图9所示的阻抗转换电路中，A点与VDD之间的电压差决定了流过电光转换器的电流。
需要说明的是，采用如图9所示的阻抗转换电路，可以实现在激光器驱动电路中设置的晶体管全部均为N型晶体管，与图7或图8所示的阻抗转换电路相比，一方面可以提高阻抗转换电路的带宽和信号传输速率，便于实现高速的光电互连，另一方面由于N型晶体管的分立器件较为成熟，不仅可以采用集成电路(Integrated Circuit；IC)工艺制备阻抗转换电路，而且可以通过在PCB上采用布线连接分立器件制备阻抗转换电路。
在本申请实施例中，在如图9所示的阻抗转换电路的基础上，阻抗转换电路022还可以包括电阻R9，如图10所示，R9串联在驱动电路021的输出端与Q1的第一极之间。其中，R9为基极均衡电阻，通过设置基极均衡电阻可以减小电路的振荡，提高电路稳定性。
本申请实施例提供了一种驱动电路，以下通过图11至图13对该驱动电路的结构进行说明，包括：
图11是本申请实施例提供的一种激光器驱动电路的示意图，在图11中，阻抗转换电路如图7所示，即Q1为P型晶体管，参见图11，驱动电路021包括差分对晶体管、电阻R2、电阻R5、电阻R6和两个直流电流源(Ib1和Ib2)，差分对晶体管用于放大输入至驱动电路的初始电压信号；差分对晶体管包括晶体管Q3和晶体管Q4，初始电压信号Vin1和Vin2分别加载在Q3的第一极和Q4的第一极上，R2耦合在Q4的第三极与第一信号源VDD之间，R5耦合在Q3的第三极与第一信号源VDD之间，R6耦合在Q3的第二极与Q4的第二极之间，两个直流电流源分别耦合在Q3的第二极与第二信号源VSS之间以及Q4的第二极与第二信号源VSS之间，两个直流电流源用于向驱动电路提供直流偏置电流。
其中，Q4的第三极为驱动电路的输出端，阻抗转换电路的输出阻抗(从A点向阻抗转换电路看进去)近似为(1+R1/R2)*R3。
可选的，R2和R5为驱动电路中的负载电阻，可选R2＝R5；两个直流电流源可以是利 用晶体管实现的，可选Ib1＝Ib2。则如图11所示的激光器驱动电路的工作过程如下：
通过外围电源电路或直流电源向激光器驱动电路提供电源电压(包括VDD和VSS)和直流偏置电流(包括Ib1、Ib2和I BIAS)，使激光器驱动电路工作在合适的直流静态工作点；前端电路或交流信号源产生初始电压信号Vin1和Vin2，将Vin1和Vin2分别加载在Q3的第一极和Q4的第一极上，Q3和Q4对初始电压信号进行放大，得到目标电压信号，电压放大倍数近似等于2R2/R6，则驱动电路021与阻抗转换电路022的耦合点B的电压近似等于2R2/R6*((Vin1)-(Vin2))+VDD-Ib2*R2；阻抗转换电路022将目标电压信号转换为目标电流信号，向电光转换器03提供目标电流信号，并完成与电光转换器03的阻抗匹配。其中，耦合点B实质为Q1的第一极，耦合点B的电压决定了流过Q1的电流大小，相应的，流过Q1的第三极的电流大小约等于(2R2/R6*((Vin2)-(Vin1))+Ib2*R2-V 截止)/R3，则流过电光转换器的电流大小约等于I BIAS-(2R2/R6*((Vin2)-(Vin1))+Ib2*R2-V 截止)/R3，V 截止表示Q1的截止电压，例如V 截止＝0.7。
图12是本申请实施例提供的另一种激光器驱动电路的示意图，在图12中，阻抗转换电路如图8所示，即Q1为N型晶体管，参见图12，驱动电路021包括差分对晶体管、电阻R5、电阻R6、电阻R7和两个直流电流源(Ib1和Ib2)，差分对晶体管用于放大输入至驱动电路的初始电压信号；差分对晶体管包括晶体管Q3和晶体管Q4，初始电压信号分别加载在Q3的第一极和Q4的第一极上，R7耦合在Q4的第三极与第一信号源VDD之间，R5耦合在Q3的第三极与第一信号源VDD之间，R6耦合在Q3的第二极与Q4的第二极之间，两个直流电流源分别耦合在Q3的第二极与第二信号源VSS之间以及Q4的第二极与第二信号源VSS之间，两个直流电流源用于向驱动电路提供直流偏置电流。
其中，Q4的第三极为驱动电路的输出端，阻抗转换电路的输出阻抗近似为(1+R1/(R2||R7))*R3，R2||R7表示R2和R7的并联电阻。
可选的，R5和R7为驱动电路中的负载电阻，可选R5＝R7。需要说明的是，如图12所示的激光器驱动电路的工作过程可以参考如图11所示的激光器驱动电路的工作过程，在此不做赘述。
图13是本申请实施例提供的又一种激光器驱动电路的示意图，在图13中，阻抗转换电路如图9所示，即阻抗转换电路中的晶体管均为N型晶体管，参见图13，驱动电路包括差分对晶体管、电阻R5、电阻R6、电阻R7和两个直流电流源(Ib1和Ib2)，差分对晶体管用于放大输入至驱动电路的初始电压信号；差分对晶体管包括晶体管Q3和晶体管Q4，初始电压信号分别加载在Q3的第一极和Q4的第一极上，R7耦合在Q4的第三极与第一信号源VDD之间，R5耦合在Q3的第三极与第一信号源VDD之间，R6耦合在Q3的第二极与Q4的第二极之间，两个直流电流源分别耦合在Q3的第二极与第二信号源VSS之间以及Q4的第二极与第二信号源VSS之间，两个直流电流源用于向驱动电路提供直流偏置电流。
其中，Q4的第三极为驱动电路的输出端，即Q4的第三极与Q1的第一极连接。
需要说明的是，如图13所示的激光器驱动电路的工作过程可以参考如图11所示的激光器驱动电路的工作过程，在此不做赘述。
可选的，参见图11至图13，驱动电路021还可以包括电容C2，C2耦合在Q3的第二极与Q4的第二极之间，也即是，C2与R6并联，可以增加驱动电路的带宽。其中，R6为退化电阻，用于承接信号以及增加驱动电路的带宽。
进一步的，在如图11至图13任一所示的激光器驱动电路的基础上，驱动电路021还可以包括电容C1，如图14至图16所示，电容C1与R5并联，其中，图14对应图11，图15对应图12，图16对应图13。
需要说明的是，由于在驱动电路工作过程中，Q3所在支路与Q4所在支路不完全相同，当输入的初始电压信号Vin1和Vin2的电压摆幅较大时，Q3的第三极有被击穿的风险，在R5上并联上C1，可以有效防止Q3的第三极被击穿，提高了电路的可靠性。
本申请实施例还提供了另一种驱动电路，如图17所示，驱动电路021包括差分对晶体管、电阻R10、电阻R11、电阻R12、电阻R13和晶体管Q8，差分对晶体管用于放大输入至驱动电路的初始电压信号；差分对晶体管包括晶体管Q3和晶体管Q4，初始电压信号Vin1和Vin2分别加载在Q3的第一极和Q4的第一极上，R10耦合在Q3的第三极与第一信号源VDD之间，R11耦合在Q4的第三极与第一信号源VDD之间，R12耦合在Q3的第二极与Q8的第三极之间，R13耦合在Q4的第二极与Q8的第三极之间，Q8的第一极耦合在某一偏置电压Va上，Q8的第二极与第二信号源VSS连接。
其中，Q4的第三极为驱动电路的输出端。可选的，R10＝R11，R12＝R13。
可选的，如图18所示，驱动电路021还可以包括电容C1，C1与R10并联。需要说明的是，由于在驱动电路工作过程中，Q3所在支路与Q4所在支路不完全相同，当输入的初始电压信号Vin1和Vin2的电压摆幅较大时，Q3的第三极有被击穿的风险，在R10上并联上C1，可以有效防止Q3的第三极被击穿，提高了电路的可靠性。
在上述图17和图18中，以阻抗转换电路为如图9所示的阻抗转换电路为例进行说明，可选的，如图17或图18所示的驱动电路也可匹配如图7或图8所示的阻抗转换电路，在此不做赘述。
需要说明的是，由于本申请实施例提供的上述驱动电路中，所采用的Q3和Q4的尺寸相对较大，因此分别对于Q3和Q4而言，第一极和第三极之间的寄生电容比较大，在电路的工作过程中，该寄生电容会产生米勒效应，影响电路的带宽和速度，对此，本申请实施例对电路结构进行了进一步的改进：在如图11至图13以及图17任一所示的驱动电路的基础上增加中和电容C3和C4。
示例的，如图19至图22所示，驱动电路021还可以包括电容C3和电容C4，C3耦合在Q3的第一极与Q4的第三极之间，C4耦合在Q4的第一极与Q3的第三极之间。其中，图19对应图11，图20对应图12，图21对应图13，图22对应图17。
其中，C3的大小等于Q3的基极与集电极之间的寄生电容的大小，C4的大小等于Q4的基极与集电极之间的寄生电容的大小，实际应用中，Q3和Q4的尺寸相等，则C3＝C4。
需要说明的是，在驱动电路中设置中和电容C3和C4，可以中和Q3和Q4的基极和集电极之间的电容，增大电路的带宽，进而提升电路的驱动速度。
可选的，针对上述第一种驱动电路，还可以通过在驱动电路中增加共源共栅管以解决Q3和Q4的寄生电容的问题。
示例的，如图23至图25所示，驱动电路021还可以包括共源共栅管，共源共栅管包括晶体管Q5和晶体管Q6；Q5和Q6的第一极耦合在同一偏置电压Vb上，Q5的第二极耦 合在Q3的第三极上，Q5的第三极与R5连接，Q6的第二极耦合在Q4的第三极上。
参见图23，当Q1为P型晶体管时，Q6的第三极与R2连接。
参见图24或图25，当Q1为N型晶体管时，Q6的第三极与R7连接，图24对应图12，图25对应图13。
其中，Q6的第三极为驱动电路的输出端。
可选的，当Q1为N型晶体管时，阻抗转换电路022还可以包括缓冲级，缓冲级耦合在Q6的第三极与Q1的第一极之间，参见图24或图25，缓冲级包括晶体管Q7和电阻R8，Q7的第一极耦合在Q6的第三极上，Q7的第三极耦合在第一信号源VDD上，R8串联在Q7的第二极与Q1的第一极之间。
其中，上述偏置电压Vb满足：V1+VBE5＜Vb＜VDD-Ib1*R5，其中，V1表示初始电压信号的电压值(Vin1)，VBE5表示Q5的第一极与第二极之间的电压差值，约为0.8伏，Ib1表示与Q3的第二极耦合的直流电流源所产生的直流偏置电流值，VDD表示第一信号源的电压值。
需要说明的是，将Q5和Q6的第一极耦合在偏置电压Vb上，且使偏置电压Vb满足上述公式，可以使得驱动电路中的所有晶体管均处于放大状态。进一步的，在如图24或图25所示的激光器驱动电路中，由于在驱动电路中增加了Q5和Q6，当电路工作时，驱动电路输出的电压会高于Q1的第一极所需的电压，因此可以通过在阻抗转换电路中设置缓冲级，降低到达Q1的第一极的电压。在阻抗转换电路中增加Q7后，C点的电压较于B点的电压降低了0.7伏(Q7的截止电压)，由于Q7的发射极到VSS之间的阻抗很小，因此增加Q7后，会使得A点到VSS的电阻减小，为了保证阻抗转换电路的输出阻抗仍与电光转化器的阻抗匹配，可以在A点与Q7的第二极之间串联电阻R8，此时阻抗转换电路的输出阻抗近似为(1+R1/(R2||R8))*R3，R2||R8表示R2和R8的并联电阻。
可选的，如图26和图27所示，本申请实施例提供的激光器驱动电路还可以包括电平转换电路023，该电平转换电路023用于将输入激光器驱动电路的输入电压信号转换为初始电压信号，并将初始电压信号输入驱动电路021。
需要说明的是，输入电压信号可以是Serdes接口输出的，在前述如图7至图25任一所述的激光器驱动电路中，需要在激光器驱动电路与Serdes接口之间设置前端电路对输入电压信号进行均衡以得到初始电压信号，例如可以将输入电压信号叠加在某一直流电平上以得到初始电压信号；而在本申请实施例中，通过在激光器驱动电路中设置电平转换电路，可以实现激光器驱动电路的输入端与Serdes接口的直接耦合，满足了芯片出光需求。示例的，输入电压信号可以为4电平脉冲幅度调制(Pulse Amplitude Modulation-4level；PAM4)信号。
参见图26，电平转换电路023包括第一信号输入端int1和第二信号输入端int2，输入电压信号包括第一输入电压信号Vin+和第二输入电压信号Vin-，第一输入电压信号Vin+通过第一信号输入端int1输入电平转换电路023，第二输入电压信号Vin-通过第二信号输入端int2输入电平转换电路023，电平转换电路023包括晶体管Q9、晶体管Q10、电阻R14和电阻R15；Q9的第一极为第一信号输入端int1，Q10的第一极为第二信号输入端int2，Q9的第三极与Q10的第三极均耦合在第二信号源VSS上，Q9的第二极通过R14与第一信号 源VDD连接，Q10的第二极通过R15与第一信号源VDD连接，Q9的第二极与Q10的第二极用于将初始电压信号(Vin1和Vin2)输入驱动电路021。
其中，第一信号源和第二信号源用于向激光器驱动电路提供电源电压，该电源电压用于保证激光器驱动电路处于正常工作状态。
可选的，参见图26，第一信号输入端int1与第二信号输入端int2之间可以耦合有阻值为100欧姆(Ω)的电阻。
需要说明的是，在如图26所示的电平转换电路中，电平转换电路可以将输入电压信号(例如0.2～0.6伏)提高至驱动电路所需的初始电压信号(例如0.9～1.3伏)，实现Serdes接口输出的输入电压信号经过激光器驱动电路后能够直驱电光转换器的功能。
进一步的，参见图27，电平转换电路023还可以包括晶体管Q11和晶体管Q12，Q11耦合在R14与第一信号源VDD之间，Q12耦合在R15与第一信号源VDD之间；其中，Q11的第一极耦合在Q11的第三极上，Q11的第二极与第一信号源VDD连接，Q11的第三极通过R14与Q9的第二极连接，Q12的第一极耦合在Q12的第三极上，Q12的第二极与第一信号源VDD连接，Q12的第三极通过R15与Q10的第二极连接。
需要说明的是，与如图26所示的电平转换电路相比，Q11和Q12能够分担一部分压降，VDD经过Q11和Q12后电压会降低0.7伏左右，因此可以减小R14和R15的阻值，进而减小激光器驱动电路的面积。
可选的，图26和图27中的涉及的驱动电路可以为如图11至图16、图19至图21和图23至图25任一所示的驱动电路；在图26和图27中，采用如图7所示的阻抗转换电路为例，实际阻抗转换电路还可以为如图8至图10任一所示的阻抗转换电路，本申请实施例对此不做限定。
需要说明的是，在本申请实施例中，驱动电路均以采用N型晶体管为例进行说明，实际实现过程中，驱动电路中也可以采用P型晶体管，其电路结构可参考采用N型晶体管时的电路结构，在此不做赘述。可选的，当激光器驱动电路中均采用N型晶体管时，不仅可以采用IC工艺制备激光器驱动电路，还可以实现通过在PCB上采用布线连接分立器件制备激光器驱动电路。
综上所述，本申请实施例提供的激光器驱动电路，能够实现向电光转换器提供直流偏置信号和交流工作信号，以驱动电光转换器发光，与相关技术相比，无需设置片外无源网络，减小了激光器驱动电路所占用的面积，且阻抗转换电路中设置有偏置电流源，可以屏蔽信号源的噪声，因此无需单独设置退耦电容，便于实现激光器驱动器的集成，且节约了成本；另外，阻抗转换电路能够用于与电光转换器进行阻抗匹配，减少了电光转换器与激光器驱动电路之间的信号反射，提高了信号利用率；进一步的，在激光器驱动电路中设置电平转换电路，可以实现激光器驱动电路的输入端与Serdes接口的直接耦合，满足了芯片出光需求。
需要说明的是，在本申请实施例中，“R”表示电阻，“Q”表示晶体管，“C”表示电容。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种激光器驱动电路，其特征在于，所述激光器驱动电路包括：驱动电路和阻抗转换电路；
    所述驱动电路用于接收初始电压信号，并将所述初始电压信号转换为目标电压信号，向所述阻抗转换电路输出所述目标电压信号；
    所述阻抗转换电路用于将所述目标电压信号转换为目标电流信号，并向电光转换器提供所述目标电流信号，所述目标电流信号包括交流工作信号和直流偏置信号，所述直流偏置信号用于提供所述电光转换器的静态工作点电流。
  2. 根据权利要求1所述的激光器驱动电路，其特征在于，
    所述阻抗转换电路还用于与所述电光转换器进行阻抗匹配。
  3. 根据权利要求1或2所述的激光器驱动电路，其特征在于，所述阻抗转换电路包括电阻R1、电阻R2、电阻R3、晶体管Q1和偏置电流源，所述R1耦合在所述Q1的第一极和所述Q1的第三极之间，所述Q1的第一极与所述驱动电路的输出端连接，所述R1、所述Q1与所述电光转换器上的电流之和等于所述偏置电流源所产生的电流；
    当所述Q1为P型晶体管时，所述R2耦合在所述Q1的第一极与第一信号源之间，所述R3耦合在所述Q1的第二极与所述第一信号源之间，所述电光转换器耦合在所述Q1的第三极与所述第一信号源之间，所述偏置电流源耦合在所述Q1的第三极与第二信号源之间；
    当所述Q1为N型晶体管时，所述R2耦合在所述Q1的第一极与所述第二信号源之间，所述R3耦合在所述Q1的第二极与所述第二信号源之间，所述电光转换器耦合在所述Q1的第三极与所述第二信号源之间，所述偏置电流源耦合在所述Q1的第三极与所述第一信号源之间；
    其中，所述第一信号源和所述第二信号源用于向所述激光器驱动电路提供电源电压。
  4. 根据权利要求1或2所述的激光驱动电路，其特征在于，所述阻抗转换电路包括电阻R4、晶体管Q1和晶体管Q2，所述Q1与所述Q2均为N型晶体管；
    所述R4串联在所述Q1的第二极与所述Q2的第三极之间，所述Q1的第一极与所述驱动电路的输出端连接，所述Q1的第三极与第一信号源连接，所述Q2的第一极耦合在某一偏置电压上，所述Q2的第二极与第二信号源连接，所述电光转换器耦合在所述Q1的第三极与所述Q2的第三极之间；
    其中，所述第一信号源和所述第二信号源用于向所述激光器驱动电路提供电源电压。
  5. 根据权利要求3所述的激光器驱动电路，其特征在于，当所述Q1为P型晶体管时，所述驱动电路包括差分对晶体管、所述R2、电阻R5、电阻R6和两个直流电流源，所述差分对晶体管用于放大输入至所述驱动电路的初始电压信号；
    所述差分对晶体管包括晶体管Q3和晶体管Q4，所述初始电压信号分别加载在所述Q3的第一极和所述Q4的第一极上，所述R2耦合在所述Q4的第三极与所述第一信号源之间， 所述R5耦合在所述Q3的第三极与所述第一信号源之间，所述R6耦合在所述Q3的第二极与所述Q4的第二极之间，所述两个直流电流源分别耦合在所述Q3的第二极与所述第二信号源之间以及所述Q4的第二极与所述第二信号源之间，所述两个直流电流源用于向所述驱动电路提供直流偏置电流；
    其中，所述Q4的第三极为所述驱动电路的输出端。
  6. 根据权利要求3所述的激光器驱动电路，其特征在于，当所述Q1为N型晶体管时，所述驱动电路包括差分对晶体管、电阻R5、电阻R6、电阻R7和两个直流电流源，所述差分对晶体管用于放大输入至所述驱动电路的初始电压信号；
    所述差分对晶体管包括晶体管Q3和晶体管Q4，所述初始电压信号分别加载在所述Q3的第一极和所述Q4的第一极上，所述R7耦合在所述Q4的第三极与所述第一信号源之间，所述R5耦合在所述Q3的第三极与所述第一信号源之间，所述R6耦合在所述Q3的第二极与所述Q4的第二极之间，所述两个直流电流源分别耦合在所述Q3的第二极与所述第二信号源之间以及所述Q4的第二极与所述第二信号源之间，所述两个直流电流源用于向所述驱动电路提供直流偏置电流；
    其中，所述Q4的第三极为所述驱动电路的输出端。
  7. 根据权利要求4所述的激光器驱动电路，其特征在于，所述驱动电路包括差分对晶体管、电阻R5、电阻R6、电阻R7和两个直流电流源，所述差分对晶体管用于放大输入至所述驱动电路的初始电压信号；
    所述差分对晶体管包括晶体管Q3和晶体管Q4，所述初始电压信号分别加载在所述Q3的第一极和所述Q4的第一极上，所述R7耦合在所述Q4的第三极与所述第一信号源之间，所述R5耦合在所述Q3的第三极与所述第一信号源之间，所述R6耦合在所述Q3的第二极与所述Q4的第二极之间，所述两个直流电流源分别耦合在所述Q3的第二极与所述第二信号源之间以及所述Q4的第二极与所述第二信号源之间，所述两个直流电流源用于向所述驱动电路提供直流偏置电流；
    其中，所述Q4的第三极为所述驱动电路的输出端。
  8. 根据权利要求5至7任一所述的激光器驱动电路，其特征在于，所述驱动电路还包括共源共栅管，所述共源共栅管包括晶体管Q5和晶体管Q6；
    所述Q5和所述Q6的第一极耦合在同一偏置电压上，所述Q5的第二极耦合在所述Q3的第三极上，所述Q5的第三极与所述R5连接，所述Q6的第二极耦合在所述Q4的第三极上；
    当所述Q1为P型晶体管时，所述Q6的第三极与所述R2连接；
    当所述Q1为N型晶体管时，所述Q6的第三极与所述R7连接；
    其中，所述Q6的第三极为所述驱动电路的输出端。
  9. 根据权利要求8所述的激光器驱动电路，其特征在于，当所述Q1为N型晶体管时，所述阻抗转换电路还包括缓冲级，所述缓冲级耦合在所述Q6的第三极与所述Q1的第一极之 间。
  10. 根据权利要求9所述的激光器驱动电路，其特征在于，所述缓冲级包括晶体管Q7和电阻R8，所述Q7的第一极耦合在所述Q6的第三极上，所述Q7的第三极耦合在所述第一信号源上，所述R8串联在所述Q7的第二极与所述Q1的第一极之间。
  11. 根据权利要求8所述的激光器驱动电路，其特征在于，
    所述偏置电压Vb满足：V1+VBE5＜Vb＜VDD-Ib1*R5，
    其中，V1表示所述初始电压信号的电压值，VBE5表示所述Q5的第一极与第二极之间的电压差值，Ib1表示与所述Q3的第二极耦合的直流电流源所产生的直流偏置电流值，所述VDD表示所述第一信号源的电压值。
  12. 根据权利要求4所述的激光器驱动电路，其特征在于，所述阻抗转换电路还包括电阻R9，所述R9串联在所述驱动电路的输出端与所述Q1的第一极之间。
  13. 根据权利要求5至7任一所述的激光器驱动电路，其特征在于，所述驱动电路还包括电容C1，所述C1与所述R5并联。
  14. 根据权利要求1所述的激光器驱动电路，其特征在于，所述驱动电路包括差分对晶体管、电阻R10、电阻R11、电阻R12、电阻R13和晶体管Q8，所述差分对晶体管用于放大输入至所述驱动电路的初始电压信号；
    所述差分对晶体管包括晶体管Q3和晶体管Q4，所述初始电压信号分别加载在所述Q3的第一极和所述Q4的第一极上，所述R10耦合在所述Q3的第三极与第一信号源之间，所述R11耦合在所述Q4的第三极与所述第一信号源之间，所述R12耦合在所述Q3的第二极与所述Q8的第三极之间，所述R13耦合在所述Q4的第二极与所述Q8的第三极之间，所述Q8的第一极耦合在某一偏置电压上，所述Q8的第二极与第二信号源连接；
    其中，所述Q4的第三极为所述驱动电路的输出端。
  15. 根据权利要求14所述的激光器驱动电路，其特征在于，所述驱动电路还包括电容C1，所述C1与所述R10并联。
  16. 根据权利要求5至7任一所述的激光器驱动电路，其特征在于，所述驱动电路还包括电容C2，所述C2耦合在所述Q3的第二极与所述Q4的第二极之间。
  17. 根据权利要求5至7、14任一所述的激光器驱动电路，其特征在于，所述驱动电路还包括电容C3和电容C4，所述C3耦合在所述Q3的第一极与所述Q4的第三极之间，所述C4耦合在所述Q4的第一极与所述Q3的第三极之间。
  18. 根据权利要求1或2所述的激光器驱动电路，其特征在于，所述激光器驱动电路还 包括电平转换电路，所述电平转换电路用于将输入所述激光器驱动电路的输入电压信号转换为所述初始电压信号，并将所述初始电压信号输入所述驱动电路。
  19. 根据权利要求18所述的激光器驱动电路，其特征在于，所述电平转换电路包括第一信号输入端和第二信号输入端，所述输入电压信号包括第一输入电压信号和第二输入电压信号，所述第一输入电压信号通过所述第一信号输入端输入所述电平转换电路，所述第二输入电压信号通过所述第二信号输入端输入所述电平转换电路，所述电平转换电路包括晶体管Q9、晶体管Q10、电阻R14和电阻R15；
    所述Q9的第一极为所述第一信号输入端，所述Q10的第一极为所述第二信号输入端，所述Q9的第三极与所述Q10的第三极均耦合在第二信号源上，所述Q9的第二极通过所述R14与第一信号源连接，所述Q10的第二极通过所述R15与所述第一信号源连接，所述Q9的第二极与所述Q10的第二极用于将所述初始电压信号输入所述驱动电路；
    其中，所述第一信号源和所述第二信号源用于向所述激光器驱动电路提供电源电压。
  20. 根据权利要求19所述的激光器驱动电路，其特征在于，所述电平转换电路还包括晶体管Q11和晶体管Q12，所述Q11耦合在所述R14与所述第一信号源之间，所述Q12耦合在所述R15与所述第一信号源之间；
    其中，所述Q11的第一极耦合在所述Q11的第三极上，所述Q11的第二极与所述第一信号源连接，所述Q11的第三极通过所述R14与所述Q9的第二极连接，所述Q12的第一极耦合在所述Q12的第三极上，所述Q12的第二极与所述第一信号源连接，所述Q12的第三极通过所述R15与所述Q10的第二极连接。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646560A (en) * 1994-09-30 1997-07-08 National Semiconductor Corporation Integrated low-power driver for a high-current laser diode
CN101692521A (zh) * 2009-10-16 2010-04-07 上海博为光电科技有限公司 用于光通信发送机的激光二极管驱动器
CN104617483A (zh) * 2015-01-27 2015-05-13 东南大学 一种带宽补偿的超高速激光驱动器电路和驱动器芯片

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3000757B2 (ja) * 1991-11-06 2000-01-17 住友電気工業株式会社 半導体レーザ駆動回路
JP3751955B2 (ja) * 2003-05-28 2006-03-08 株式会社東芝 半導体レーザ駆動回路及び光通信器
US20050105574A1 (en) * 2003-11-14 2005-05-19 Wu Xin M. Laser driver for optical communication network
JP4899318B2 (ja) * 2005-02-21 2012-03-21 富士ゼロックス株式会社 半導体レーザ駆動回路、およびそれを用いた光伝送装置、レーザプリンタおよびレーザ書込み装置
US8358080B2 (en) * 2010-01-29 2013-01-22 Canon Kabushiki Kaisha Light emitting element driving circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646560A (en) * 1994-09-30 1997-07-08 National Semiconductor Corporation Integrated low-power driver for a high-current laser diode
CN101692521A (zh) * 2009-10-16 2010-04-07 上海博为光电科技有限公司 用于光通信发送机的激光二极管驱动器
CN104617483A (zh) * 2015-01-27 2015-05-13 东南大学 一种带宽补偿的超高速激光驱动器电路和驱动器芯片

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