WO2019214323A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2019214323A1
WO2019214323A1 PCT/CN2019/076250 CN2019076250W WO2019214323A1 WO 2019214323 A1 WO2019214323 A1 WO 2019214323A1 CN 2019076250 W CN2019076250 W CN 2019076250W WO 2019214323 A1 WO2019214323 A1 WO 2019214323A1
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WIPO (PCT)
Prior art keywords
pixel
lines
pixel electrode
array
array substrate
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PCT/CN2019/076250
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English (en)
French (fr)
Inventor
杨明
玄明花
张粲
王灿
岳晗
丛宁
刘佳尧
赵文卿
肖丽
刘冬妮
王磊
陈亮
陈小川
杨盛际
卢鹏程
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京东方科技集团股份有限公司
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Priority to US16/642,584 priority Critical patent/US11374032B2/en
Publication of WO2019214323A1 publication Critical patent/WO2019214323A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • Integral imaging is an autostereoscopic and multi-view three-dimensional imaging technique that captures and reproduces a light field by using a two-dimensional microlens array.
  • the object space scene is imaged using a capture microlens array and the resulting image is captured using an image sensor located at the focal plane of the microlens array. Since each microlens in the microlens array provides information of the scene from different directions, an array of elemental images of different viewing angles is obtained, each meta image corresponding to one of the respective microlenses.
  • an array of meta images is displayed on a two dimensional display and the light emitted from the display is transmitted using a reproducing microlens array having the same parameters as the parameters of the captured microlens array.
  • the reproducing microlens array concentrates the light rays from the respective element images, thereby reproducing the object space scene.
  • an array substrate comprising: a plurality of pixel regions arranged in rows and columns.
  • the plurality of pixel regions includes respective pixel electrode arrays and respective pixel circuits associated with the respective pixel electrode arrays.
  • Each of the pixel electrode arrays is arranged in rows and columns, and each of the pixel electrode arrays includes a plurality of pixel electrodes arranged in an array.
  • the array substrate further includes a plurality of sets of gate lines extending in the row direction.
  • the plurality of sets of gate lines and each row of pixel electrode arrays are alternately arranged with each other in a column direction crossing the row direction.
  • the array substrate further includes a plurality of sets of data lines extending in the column direction.
  • Each pixel circuit is connected to a plurality of pixel electrodes of a corresponding one of the pixel electrode arrays, a corresponding one of the plurality of sets of gate lines, and a corresponding one of the plurality of sets of data lines Group data line.
  • each of the pixel circuits includes a respective plurality of first transistors, and each of the first transistors includes a gate connected to a corresponding one of the corresponding ones of the gate lines, connected to the corresponding a first pole of a corresponding one of the plurality of data lines and a second pole connected to a corresponding one of the plurality of pixel electrodes of the corresponding one of the pixel electrode arrays.
  • the gates of different first transistors connected to pixel electrodes of different rows are connected to respective ones of the corresponding set of gate lines, and are connected to different first rows of pixel electrodes.
  • a first pole of the transistor is coupled to a respective one of the respective one of the data lines.
  • the plurality of pixel electrodes of each pixel electrode array are arranged in an array of M ⁇ N, each set of gate lines includes M gate lines, and each set of data lines includes N data lines, and M is An integer greater than 1, and N is an integer greater than or equal to one.
  • the plurality of pixel electrodes of each pixel electrode array are arranged in an array of M ⁇ N, wherein each set of gate lines includes M gate lines, and each set of data lines includes N data lines, M Is an integer greater than or equal to 1, and N is an integer greater than one.
  • the array substrate further includes a set of multiplexed lines extending in the column direction.
  • Each set of data lines includes a respective single data line
  • each pixel circuit includes a plurality of pairs of transistors
  • each pair of transistors includes: a first transistor including a gate connected to a corresponding one of the corresponding one of the gate lines a first pole, and a second pole connected to a corresponding one of the plurality of pixel electrodes of the corresponding one of the pixel electrode arrays; and a second transistor including a connection to the set of multiplexed lines a gate corresponding to a multiplex line, a first pole connected to a single data line of the corresponding set of data lines, and a second pole connected to the first pole of the first transistor.
  • the gates of respective ones of the different pairs of transistors connected to the pixel electrodes of the different rows are connected to respective ones of the corresponding ones of the gate lines, and are connected to pixels of different columns
  • the gates of the respective second transistors of the different pairs of electrodes are connected to respective ones of the plurality of sets of multiplexed lines.
  • the plurality of pixel electrodes of each pixel electrode array are arranged in an array of M ⁇ N, each set of gate lines includes M gate lines, and the set of multiplex lines includes N strips Multiplex line.
  • each of the pixel regions further includes a corresponding plurality of electrode leads, and each of the pixel circuits is connected to a corresponding one of the plurality of pixel electrodes of the corresponding one of the pixel electrode arrays via the respective plurality of electrode leads Pixel electrode.
  • the plurality of electrode leads are made of a transparent conductive material.
  • the transparent conductive material comprises indium tin oxide or indium zinc oxide.
  • a display panel comprising the array substrate as described above.
  • a display device comprising the display panel as described above.
  • the display device further includes a lens array on a light exit side of the display panel.
  • the lens array includes a plurality of lenses that are disposed opposite respective pixel electrode arrays in each of the pixel electrode arrays.
  • 1 is a schematic structural view of an array substrate in the related art
  • FIG. 2 is a schematic structural view of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a partial schematic view showing a pixel region in the array substrate of FIG. 2;
  • FIG. 4 is a schematic structural view of an array substrate according to another embodiment of the present disclosure.
  • FIG. 5 is a partial schematic view showing a pixel region in the array substrate of FIG. 4;
  • FIG. 6 shows a timing chart for driving pixel electrodes in the pixel region of FIG. 5;
  • FIG. 7 is a block diagram showing a structure of a display device according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic block diagram of the display device of FIG.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/ Some should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section without departing from the teachings of the invention.
  • any arrangement of devices to achieve the same function is effectively “associated” such that the desired functionality is implemented. Accordingly, any two devices that are combined herein to implement a particular function can be seen as “associated” with each other such that the desired functionality is implemented.
  • FIG. 1 is a schematic view showing the structure of an array substrate in the related art.
  • gate lines such as Gm-1, Gm, and Gm+1, are crossed with data lines such as Sn-1, Sn, and Sn+1 to define a plurality of pixel electrodes PE.
  • Each of the pixel electrodes PE is connected to a corresponding one of the gate lines and a corresponding one of the respective data lines via a corresponding thin film transistor T.
  • the individual pixel electrodes PE are separated by gate lines and data lines, resulting in a large gap between the pixel electrodes PE, and thus a lower PPI.
  • FIG. 2 shows a schematic structural view of an array substrate 100 according to an embodiment of the present disclosure
  • FIG. 3 shows a partial schematic view of the upper left pixel region 110 in the array substrate 100 of FIG. 2.
  • the array substrate 100 includes a plurality of pixel regions 110 arranged in rows and columns, and a plurality of sets of gate lines extending in the row direction x (in this example, Gm-1, Gm, and Gm+ are shown). a first set of gate lines of 1 and a second set of gate lines including Gm+2, Gm+3, and Gm+4), and a plurality of sets of data lines extending in a column direction y crossing the row direction x (in this example) A first set of data lines including Dn-1, Dn, and Dn+1 and a second set of data lines including Dn+2, Dn+3, and Dn+4 are shown.
  • each of the pixel regions 110 includes a corresponding pixel electrode array 111 and a corresponding pixel circuit 112 associated with the pixel electrode array 111.
  • Each of the pixel electrode arrays 111 includes a plurality of pixel electrodes PE arranged in an array.
  • Each pixel circuit 112 is connected to a plurality of pixel electrodes PE of a corresponding pixel electrode array 111, a corresponding set of gate lines (in this example, Gm-1, Gm, and Gm+1), and a corresponding set of data lines (In this example, Dn-1, Dn, and Dn+1).
  • each pixel circuit 112 includes a corresponding plurality of first transistors T1.
  • Each of the first transistors T1 includes a gate connected to a corresponding one of the corresponding one of the gate lines Gm-1, Gm, and Gm+1, connected to the corresponding set of data lines Dn-1, Dn, and a first pole of a corresponding one of the data lines of Dn+1, and a second pole of a corresponding one of the plurality of pixel electrodes PE connected to the corresponding one of the pixel electrode arrays 111.
  • the first transistor labeled with the reference symbol "T1" includes a gate connected to the gate line Gm, a first pole connected to the data line Dn-1, and a second connected to the pixel electrode array 111.
  • the first electrode of the first transistor T1 is connected to the data line Dn-1 via the data line lead DLL
  • the second electrode of the first transistor T1 is connected to the pixel electrode PE via the electrode lead PEL.
  • the data line lead DLL may be made of a metal material such as aluminum, molybdenum, copper or a combination thereof.
  • the material of the electrode lead PEL can also be made of such a metal material.
  • the electrode lead PEL may be made of a transparent conductive material such as indium tin oxide or indium zinc oxide to improve the visual effect.
  • the gates of different first transistors T1 connected to the pixel electrodes PE of different rows are connected to respective different gate lines of the corresponding set of gate lines Gm-1, Gm and Gm+1, and are connected to
  • the first poles of the different first transistors T1 of the different columns of pixel electrodes PE are connected to respective ones of the corresponding set of data lines Dn-1, Dn and Dn+1.
  • the gates of the upper right first transistor T1 and the lower right first transistor T1 are connected to the gate lines Gm-1 and Gm+1, respectively, and the first lower transistor T1 and the lower right first transistor T1 are respectively connected.
  • One pole is connected to the data lines Dn-1 and Dn+1, respectively.
  • the pixel circuit 112 shown in Figure 3 is exemplary. Depending on the type of display substrate 100, pixel circuit 112 can be in any suitable form. For example, in the case of a liquid crystal display, the pixel circuit 112 may simply include a transistor array as shown in FIG. 3, and in this case, each pixel electrode PE constitutes one plate of a corresponding liquid crystal capacitor. In the case of an organic light emitting diode display, the pixel circuit 112 may include a plurality of driving circuits each for driving a corresponding organic light emitting diode to emit light, and in this case, each pixel electrode PE constitutes, for example, a corresponding The anode of the organic light emitting diode.
  • each of the pixel electrode arrays 111 is arranged in rows and columns, and the plurality of sets of gate lines and the respective rows of pixel electrode arrays 111 are alternately arranged in the column direction y.
  • the plurality of sets of data lines and the columns of pixel regions 110 are alternately arranged in the row direction x.
  • the gate lines and the data lines are not disposed between the pixel electrodes PE in each of the pixel electrode arrays 111, the arrangement of the pixel electrodes PE is more compact. This results in a significantly improved PPI within each pixel electrode array 111.
  • each pixel electrode array 111 includes 3 ⁇ 3 pixel electrodes PE, each set of gate lines includes 3 gate lines, and each set of data lines also includes 3 data lines.
  • each of the pixel electrode arrays 111 may include, for example, 2 ⁇ 2 pixel electrodes PE, 2 ⁇ 4 pixel electrodes PE, or 2 ⁇ 1 pixel electrodes PE.
  • the plurality of pixel electrodes PE of each pixel electrode array 111 are arranged in an array of M ⁇ N, each set of gate lines includes M gate lines, and each set of data lines includes N data lines.
  • M is an integer greater than 1
  • N is an integer greater than or equal to 1.
  • M is an integer greater than or equal to 1
  • N is an integer greater than one.
  • FIG. 4 shows a schematic structural view of an array substrate 200 according to another embodiment of the present disclosure
  • FIG. 5 shows a partial schematic view of the upper left pixel region 210 in the array substrate 200 of FIG.
  • the array substrate 200 includes a plurality of pixel regions 210 arranged in rows and columns, and a plurality of sets of gate lines extending in the row direction x (in this example, G1, G2, and G3 are shown). a first set of gate lines and a second set of gate lines including G4, G5, and G6), and a plurality of sets of data lines extending in a column direction y crossing the row direction x (in this example, a portion including D1 is shown) A set of data lines and a second set of data lines including D2).
  • each of the pixel regions 210 includes a corresponding pixel electrode array 211 and a corresponding pixel circuit 212 associated with the pixel electrode array 211.
  • Each of the pixel electrode arrays 211 includes a plurality of pixel electrodes PE arranged in an array.
  • Each pixel circuit 212 is connected to a plurality of pixel electrodes PE of a corresponding pixel electrode array 211, a corresponding set of gate lines (in this example, G1, G2, and G3), and a corresponding set of data lines (in this example) Medium, D1).
  • the array substrate 200 further includes a set of multiplexed lines (MUX1, MUX2, and MUX3 in the examples of FIGS. 4 and 5) extending in the column direction y, and each set of data lines includes a corresponding single strip Data line (in the example of Figures 4 and 5, D1 or D2).
  • each pixel circuit 212 includes a plurality of pairs of transistors, each pair of transistors including: a first transistor T1 including a corresponding one of the corresponding one of the gate lines G1, G2, and G3.
  • MUX1, MUX2, and MUX3 including a connection to the one a gate of a corresponding one of the group multiplex lines MUX1, MUX2, and MUX3, a first pole of a single data line connected to the corresponding one of the data lines D1, and a first pole connected to the first The second pole of the first pole of transistor T1.
  • the first transistor labeled with the reference symbol “T1” includes a gate connected to the gate line G2, a first pole of the second pole of the second transistor labeled with the reference symbol “T2", And a second pole connected to the second row and the pixel electrode PE of the first column in the pixel electrode array 211, and the second transistor labeled with the reference symbol “T2” includes a gate connected to the multiplex line MUX1
  • the pole is connected to the first pole of the data line D1 and to the second pole of the first pole of the first transistor labeled with the reference symbol "T1".
  • the gate of the second transistor T2 is connected to the multiplex line MUX1 via the multiplex line lead L21. Also shown in FIG.
  • the multiplex lines MUX1, MUX2, and MUX3 and the multiplexed line leads L11, L12, L13, L21, L22, L23, L31, L32, and L33 may be made of a metal material (for example, aluminum, molybdenum, copper, or a combination thereof) production.
  • the gates of the respective first transistors T1 of the different pairs of transistors connected to the pixel electrodes PE of different rows are connected to respective ones of the corresponding ones of the gate lines G1, G2 and G3, and wherein The gates of the respective second transistors T2 of the different pairs of transistors connected to the pixel electrodes PE of the different columns are connected to respective different multiplexed lines of the set of multiplexed lines MUX1, MUX2, and MUX3.
  • the gates of the upper right first transistor T1 and the lower right first transistor T1 are respectively connected to the gate lines G1 and G3, and the first lower left second transistor T2 and the lower right second transistor T2 have the first poles respectively Connected to the multiplex lines MUX1 and MUX3.
  • the multiplex lines MUX1, MUX2, and MUX3 transmit respective scan pulse signals in a time division manner during gate scanning. This makes it possible in each pixel electrode array 211 that the respective pixel electrodes PE in the same row can be supplied with different data voltages from the same data line. Thus, in each of the pixel electrode arrays 211, each of the pixel electrodes PE in the same row can be driven by the signals of the same gate line and the same data line, thereby realizing a normal display function.
  • the data lines in the array substrate 200 are reduced, and thus the PPI of the array substrate 200 is further improved.
  • the arrangement of the multiplex lines MUX1, MUX2, and MUX3 is exemplary, and in other embodiments, the multiplex lines MUX1, MUX2, and MUX3 may be arranged in other locations. .
  • the multiplex lines MUX1, MUX2, and MUX3 may also be disposed on the right side of the array substrate 200.
  • each pixel electrode array 211 includes 3 ⁇ 3 pixel electrodes PE, each set of gate lines includes 3 gate lines, and the set of multiplex lines also includes 3 multiplex lines line.
  • each of the pixel electrode arrays 211 may include, for example, 2 ⁇ 2 pixel electrodes PE, 2 ⁇ 4 pixel electrodes PE, or 2 ⁇ 1 pixel electrodes PE.
  • the plurality of pixel electrodes PE of each pixel electrode array 211 are arranged in an array of M ⁇ N, each set of gate lines includes M gate lines, and the set of multiplex lines includes N strips Multiplex line.
  • M is an integer greater than 1
  • N is an integer greater than or equal to 1.
  • M is an integer greater than or equal to 1
  • N is an integer greater than one.
  • FIG. 6 shows a timing diagram for driving the pixel electrode PE in the pixel region 210 of FIG.
  • the gate scan signal is valid for a period of time t (high level in this example).
  • the time period t includes a first time period t1, a second time period t2, and a third time period t3.
  • the multiplex lines MUX1, MUX2, and MUX3 transmit respective scan pulse signals in a time division manner during the time period t, wherein the respective scan pulse signals are in the first, second, and third time periods t1, t2, and Valid within t3.
  • the scan pulse signal on the multiplex line MUX1 is active, and the first data voltage is present on the data line D1.
  • the first data voltage is delivered to the pixel electrode PE of the first column of the first row.
  • the scan pulse signal on the multiplex line MUX2 is active, and the second data voltage is present on the data line D1.
  • the second data voltage is transmitted to the pixel electrode PE of the first row and the second column.
  • the scan pulse signal on the multiplex line MUX3 is active, and the third data voltage is present on the data line D1.
  • the third data voltage is transmitted to the pixel electrode PE of the first row and the third column.
  • an effective gate scan signal is supplied to the gate line G2, and respective scan pulse signals are sequentially supplied to the multiplex lines MUX1, MUX2, and MUX3, and scan pulse signals on the multiplex lines MUX1, MUX2, and MUX3 are sequentially supplied.
  • Each data voltage is supplied to the data line D1 in synchronization. These data voltages are respectively transferred to the pixel electrode PE of the first row of the second row, the pixel electrode PE of the second row and the second column, and the pixel electrode PE of the second row and the third column.
  • an effective gate scan signal is supplied to the gate line G3, and respective scan pulse signals are sequentially supplied to the multiplex lines MUX1, MUX2, and MUX3, and scan pulse signals on the multiplex lines MUX1, MUX2, and MUX3 are sequentially supplied.
  • Each data voltage is supplied to the data line D1 in synchronization. These data voltages are respectively transferred to the pixel electrode PE of the first row of the third row, the pixel electrode PE of the third row and the second column, and the pixel electrode PE of the third row and the third column.
  • FIG. 7 shows a schematic structural diagram of a display device 300 according to an embodiment of the present disclosure.
  • the display device 300 includes a display panel 310 that includes an array substrate 312.
  • the array substrate 312 may take the form of the array substrate 100 or 200 described in connection with the above embodiments.
  • FIG. 7 illustrates a plurality of pixel electrode arrays 311 in the array substrate 312, each of which may take the form of a pixel electrode array 111 or 211 depending on the implementation of the array substrate 312.
  • the display panel 310 may further include an opposite substrate (not shown) opposite to the array substrate 312.
  • the display panel 310 may further include a cover (not shown) opposite to the array substrate 312.
  • the display device 300 further includes a lens array 320 that is located on the light exit side of the display panel 310 .
  • the lens array 320 includes a plurality of lenses 322 that are disposed opposite respective pixel electrode arrays in each of the pixel electrode arrays 311.
  • the pixels corresponding to the respective pixel electrode arrays 311 are used to display corresponding meta images, which are then projected by the plurality of lenses 322 to the viewing zone. This makes the display device 300 a three-dimensional display based on integrated imaging.
  • FIG. 8 shows a schematic block diagram of a display device 300.
  • the display device 300 includes a display panel 310, a lens array 320, a gate driver 330, a data driver 340, and a timing controller 350.
  • the display panel 310 includes an array substrate 312 (not shown in FIG. 8) as described above, such as the array substrate 100 or 200.
  • the display panel 310 may further include an opposite substrate (not shown) opposite to the array substrate and a liquid crystal layer (not shown) sandwiched between the array substrate and the opposite substrate.
  • the display panel 310 may further include a cover (not shown) opposite to the array substrate.
  • the display panel 310 includes a plurality of sets of gate lines GL, a plurality of sets of data lines DL, and a plurality of pixel areas PX, such as a plurality of pixel areas 110 or 210.
  • Each of the pixel regions PX is located at a corresponding intersection of the plurality of sets of gate lines GL and the plurality of sets of data lines DL.
  • the display panel 310 further includes a set of multiplexed lines (not shown).
  • the gate driver 330 is electrically connected to each group of gate lines GL and sequentially supplies gate scan signals to the respective gate lines.
  • the gate driver 330 may be integrated in the display panel 310.
  • the gate driver 330 may be connected to the display panel 310 by a Tape Carrier Package (TCP).
  • TCP Tape Carrier Package
  • the gate driver 330 can be implemented by typical techniques in the art and will not be described in detail herein.
  • the data driver 340 is electrically connected to each group of data lines DL and applies data voltages to the respective data lines.
  • data driver 340 can include a plurality of data driven chips operating in parallel.
  • Data driver 340 can be implemented by typical techniques in the art and will not be described in detail herein.
  • the timing controller 350 controls the operation of each of the gate driver 330 and the data driver 340. Specifically, the timing controller 350 outputs a data control signal and image data to control a driving operation of the data driver 340, and outputs a gate control signal to control a driving operation of the gate driver 330. In the case of the array substrate 200, the timing controller 350 may also include or control circuitry for generating scan pulse signals (as shown in FIG. 6) to be sequentially applied to the set of multiplex lines (not shown) show). The timing controller 350 can be implemented by typical techniques in the art. Typically, timing controller 350 can be a conventional processor, controller, microcontroller, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or state machine.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the timing controller 350 can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • the display device 300 can be any product or component having a display function, such as a cell phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板（100），包括：多个像素区域（110），按行和列排布；多个像素区域（110）包括相应的像素电极阵列（111）和与相应的像素电极阵列（111）相关联的相应的像素电路（112）；各像素电极阵列（111）按行和列布置，并且每个像素电极阵列（111）包括呈阵列排布的多个像素电极（PE）；阵列基板(110)还包括在行方向上延伸的多组栅线（Gm）和在列方向上延伸的多组数据线（Dm）。多组栅线（Gm）与各行像素电极阵列(111)在列方向上彼此交替排布。多组数据线（Dm）与各列像素区域(110)在行方向上彼此交替排布。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求2018年5月10日提交的中国专利申请No.201810443168.8的优先权，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板、显示面板及显示装置。
背景技术
集成成像(integral imaging)是一种自动立体和多视三维成像技术，其通过使用二维微透镜阵列捕获和再现光场。在捕获过程中，利用一个捕获微透镜阵列对物体空间场景进行成像，并利用位于该微透镜阵列的焦平面处的图像传感器捕获所成的像。由于微透镜阵列中的各微透镜从不同方向提供场景的信息，因此得到不同视角的元图像(elemental image)的阵列，每个元图像对应于各微透镜中的一个相应微透镜。在再现过程中，在二维显示器上显示元图像的阵列，并且利用具有与捕获微透镜阵列的参数相同的参数的再现微透镜阵列来透射从显示器发射的光线。根据光路可逆的原理，再现微透镜阵列把来自各元图像的光线聚集，从而再现物体空间场景。
集成成像要求高解析度的图像捕获设备和高解析度的显示器。虽然已经提出了提高PPI(pixel per inch)的各种解决方案，但是仍然存在对于替换方案的需要。
发明内容
根据本公开的一个方面，提供了一种阵列基板，包括：多个像素区域，按行和列排布。所述多个像素区域包括相应的像素电极阵列和与所述相应的像素电极阵列相关联的相应的像素电路。各所述像素电极阵列按行和列布置，并且每个像素电极阵列包括呈阵列排布的多个像素电极。该阵列基板还包括多组栅线，在行方向上延伸。所述多组栅线与各行像素电极阵列在与所述行方向交叉的列方向上彼此交替排布。该阵列基板还包括多组数据线，在所述列方向上延伸。所述多组数据线与各列像素区域在所述行方向上彼此交替排布。每个像素电路连接到各所述像素电极阵列中的相应一个像素电极阵列的多个像素电 极、所述多组栅线中的对应一组栅线、以及所述多组数据线中的对应一组数据线。
在一些实施例中，每个像素电路包括相应的多个第一晶体管，并且每个第一晶体管包括连接到所述对应一组栅线中的对应一条栅线的栅极、连接到所述对应一组数据线中的对应一条数据线的第一极、以及连接到所述相应一个像素电极阵列的所述多个像素电极中的相应一个像素电极的第二极。
在一些实施例中，连接到不同行的像素电极的不同第一晶体管的栅极连接到所述对应一组栅线中的各自不同的栅线，并且连接到不同列的像素电极的不同第一晶体管的第一极连接到所述对应一组数据线中的各自不同的数据线。
在一些实施例中，每个像素电极阵列的所述多个像素电极呈M×N的阵列排布，每组栅线包括M条栅线，并且每组数据线包括N条数据线，M为大于1的整数，并且N为大于或等于1的整数。
在一些实施例中，每个像素电极阵列的所述多个像素电极呈M×N的阵列排布，其中每组栅线包括M条栅线，并且每组数据线包括N条数据线，M为大于或等于1的整数，并且N为大于1的整数。
在一些实施例中，所述阵列基板还包括沿所述列方向延伸的一组多路复用线。每组数据线包括相应的单条数据线，每个像素电路包括多对晶体管，并且每一对晶体管包括：第一晶体管，包括连接到所述对应一组栅线中的对应一条栅线的栅极、第一极、以及连接到所述相应一个像素电极阵列的所述多个像素电极中的相应一个像素电极的第二极；以及第二晶体管，包括连接到所述一组多路复用线中的对应一条多路复用线的栅极、连接到所述对应一组数据线的单条数据线的第一极、以及连接到所述第一晶体管的第一极的第二极。
在一些实施例中，连接到不同行的像素电极的不同对晶体管中的各第一晶体管的栅极连接到所述对应一组栅线中的各自不同的栅线，并且连接到不同列的像素电极的不同对晶体管中的各第二晶体管的栅极连接到所述一组多路复用线中的各自不同的多路复用线。
在一些实施例中，每个像素电极阵列的所述多个像素电极呈M×N的阵列排布，每组栅线包括M条栅线，并且所述一组多路复用线包括N条多路复用线。
在一些实施例中，每个像素区域还包括相应的多条电极引线，并且每个像素电路经由所述相应的多条电极引线连接到所述相应一个像素电极阵列的多个像素电极中的相应像素电极。
在一些实施例中，所述多条电极引线由透明导电材料制成。
在一些实施例中，所述透明导电材料包括氧化铟锡或氧化铟锌。
根据本公开的另一方面，提供了一种显示面板，包括如上所述的阵列基板。
根据本公开的另一方面，提供了一种显示装置，包括如上所述的显示面板。
在一些实施例中，所述显示装置还包括位于所述显示面板的出光侧的透镜阵列。所述透镜阵列包括多个透镜，所述多个透镜被布置成与各所述像素电极阵列中的相应像素电极阵列相对。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1示出了相关技术中的一种阵列基板的结构示意图；
图2示出了根据本公开实施例的一种阵列基板的结构示意图；
图3示出了图2的阵列基板中的一个像素区域的局部示意图；
图4示出了根据本公开另一实施例的一种阵列基板的结构示意图；
图5示出了图4的阵列基板中的一个像素区域的局部示意图；
图6示出了用于驱动图5的像素区域中的像素电极的时序图；
图7示出了根据本公开实施例的一种显示装置的结构示意图；并且
图8示出了图7的显示装置的示意性框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本发明的教导。
诸如“行方向”、“列方向”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个 (些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在行方向上延伸”的元件将取向为“在列方向上延伸”。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本发明。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在...上”或“直接在...上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本发明的理想化实施例的示意性图示(以及中间结构)描述本发明的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本发明的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本发明的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术 语)具有与本发明所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
用以实现同一功能的各设备的任何布置是有效地“关联的”以使得期望的功能被实现。因此，在本文中被组合来实现特定功能的任何两个设备可被视为彼此“关联”以使得所期望的功能被实现。
图1示出了相关技术中的一种阵列基板的结构示意图。
如图1所示，栅线，如Gm-1、Gm和Gm+1，与数据线，如Sn-1、Sn和Sn+1交叉以定义多个像素电极PE。每个像素电极PE经由一个相应的薄膜晶体管T连接到各栅线中的对应一条和各数据线中的对应一条。在这样的阵列基板中，各单独的像素电极PE被栅线及数据线分隔，导致像素电极PE之间较大的间隙，以及因此较低的PPI。
图2示出了根据本公开实施例的一种阵列基板100的结构示意图，并且图3示出了图2的阵列基板100中的左上像素区域110的局部示意图。
参照图2，阵列基板100包括：按行和列排布的多个像素区域110、在行方向x上延伸的多组栅线(在该示例中示出了包括Gm-1、Gm和Gm+1的第一组栅线和包括Gm+2、Gm+3和Gm+4的第二组栅线)、以及在与行方向x交叉的列方向y上延伸的多组数据线(在该示例中示出了包括Dn-1、Dn和Dn+1的第一组数据线和包括Dn+2、Dn+3和Dn+4的第二组数据线)。
参考图3，每个像素区域110包括相应的像素电极阵列111和与像素电极阵列111相关联的相应的像素电路112。每个像素电极阵列111包括呈阵列排布的多个像素电极PE。每个像素电路112连接到一个相应像素电极阵列111的多个像素电极PE、对应的一组栅线(在该示例中，Gm-1、Gm和Gm+1)、以及对应的一组数据线(在该示例中，Dn-1、Dn和Dn+1)。
在该实施例中，每个像素电路112包括相应的多个第一晶体管T1。每个第一晶体管T1包括连接到所述对应一组栅线Gm-1、Gm和Gm+1中的对应一条栅线的栅极、连接到所述对应一组数据线Dn-1、Dn和 Dn+1中的对应一条数据线的第一极、以及连接到所述相应一个像素电极阵列111的所述多个像素电极PE中的相应一个像素电极的第二极。在图3中，被标记有参考符号“T1”的第一晶体管包括连接到栅线Gm的栅极、连接到数据线Dn-1的第一极、以及连接到位于像素电极阵列111中的第二行和第一列的像素电极PE的第二极。具体地，该第一晶体管T1的第一极经由数据线引线DLL连接到数据线Dn-1，并且该第一晶体管T1的第二极经由电极引线PEL连接到像素电极PE。数据线引线DLL可以由金属材料(例如，铝、钼、铜或其组合)制成。电极引线PEL的材料也可以由这样的金属材料制成。替换地，电极引线PEL可以由透明导电材料(例如，氧化铟锡或氧化铟锌)制成以改进视觉效果。
更一般地，连接到不同行的像素电极PE的不同第一晶体管T1的栅极连接到所述对应一组栅线Gm-1、Gm和Gm+1中的各自不同的栅线，并且连接到不同列的像素电极PE的不同第一晶体管T1的第一极连接到所述对应一组数据线Dn-1、Dn和Dn+1中的各自不同的数据线。例如，右上的第一晶体管T1和右下的第一晶体管T1的栅极被分别连接到栅线Gm-1和Gm+1，并且左下的第一晶体管T1和右下的第一晶体管T1的第一极被分别连接到数据线Dn-1和Dn+1。这样，在每个像素电极阵列111中，同一行中的各个像素电极PE可以由同一条栅线和各自不同的数据线的信号驱动，实现正常的显示功能。
将理解的是，图3中示出的像素电路112是示例性的。取决于显示基板100的类型，像素电路112可以任何适当的形式。例如，在液晶显示器的情况下，像素电路112可以简单地包括如图3中所示的晶体管阵列，并且在这种情况下，每个像素电极PE构成一个相应的液晶电容器的一个极板。在有机发光二极管显示器的情况下，像素电路112可以包括多个驱动电路，每个驱动电路用于驱动一个相应的有机发光二极管发光，并且在这种情况下，每个像素电极PE构成例如一个相应的有机发光二极管的阳极。
返回参考图2，各像素电极阵列111按行和列布置，并且所述多组栅线与各行像素电极阵列111在列方向y上彼此交替排布。所述多组数据线与各列像素区域110在行方向x上彼此交替排布。如图2所示，由于每个像素电极阵列111内的像素电极PE之间没有设置栅线和数据 线，所以像素电极PE的排布更加紧密。这导致在每个像素电极阵列111内显著提高的PPI。
在图2的示例中，每个像素电极阵列111包括3×3个像素电极PE，每组栅线包括3条栅线，并且每组数据线也包括3条数据线。然而，本公开不限于此。例如，每个像素电极阵列111可以包括例如2×2个像素电极PE、2×4个像素电极PE、或2×1个像素电极PE。更一般地，每个像素电极阵列111的所述多个像素电极PE呈M×N的阵列排布，每组栅线包括M条栅线，并且每组数据线包括N条数据线。M为大于1的整数，并且N为大于或等于1的整数。替换地，M为大于或等于1的整数，并且N为大于1的整数。
图4示出了根据本公开另一实施例的一种阵列基板200的结构示意图，并且图5示出了图4的阵列基板200中的左上像素区域210的局部示意图。
与阵列基板100类似，阵列基板200包括：按行和列排布的多个像素区域210、在行方向x上延伸的多组栅线(在该示例中示出了包括G1、G2和G3的第一组栅线和包括G4、G5和G6的第二组栅线)、以及在与行方向x交叉的列方向y上延伸的多组数据线(在该示例中示出了包括D1的第一组数据线和包括D2的第二组数据线)。参考图5，每个像素区域210包括相应的像素电极阵列211和与像素电极阵列211相关联的相应的像素电路212。每个像素电极阵列211包括呈阵列排布的多个像素电极PE。每个像素电路212连接到一个相应像素电极阵列211的多个像素电极PE、对应的一组栅线(在该示例中，G1、G2和G3)、以及对应的一组数据线(在该示例中，D1)。
不同于阵列基板100，阵列基板200还包括沿列方向y延伸的一组多路复用线(在图4和5的示例中，MUX1、MUX2和MUX3)，并且每组数据线包括相应的单条数据线(在图4和5的示例中，D1或D2)。如图5所示，每个像素电路212包括多对晶体管，每一对晶体管包括：第一晶体管T1，其包括连接到所述对应一组栅线G1、G2和G3中的对应一条栅线的栅极、第一极、以及连接到所述相应一个像素电极阵列211的所述多个像素电极PE中的相应一个像素电极的第二极；和第二晶体管T2，其包括连接到所述一组多路复用线MUX1、MUX2和MUX3中的对应一条多路复用线的栅极、连接到所述对应一组数据线 D1的单条数据线的第一极、以及连接到所述第一晶体管T1的第一极的第二极。在图5的示例中，被标记有参考符号“T1”的第一晶体管包括连接到栅线G2的栅极、被标记有参考符号“T2”的第二晶体管的第二极的第一极、以及连接到位于像素电极阵列211中的第二行和第一列的像素电极PE的第二极，并且被标记有参考符号“T2”的第二晶体管包括连接到多路复用线MUX1的栅极、连接到数据线D1的第一极、以及连接到被标记有参考符号“T1”的第一晶体管的第一极的第二极。具体地，该第二晶体管T2的栅极经由多路复用线引线L21连接到多路复用线MUX1。图5中还示出了用于其余第二晶体管的相应的多路复用线引线L11、L12、L13、L22、L23、L31、L32和L33。多路复用线MUX1、MUX2和MUX3和多路复用线引线L11、L12、L13、L21、L22、L23、L31、L32和L33可以由金属材料(例如，铝、钼、铜或其组合)制成。
更一般地，连接到不同行的像素电极PE的不同对晶体管中的各第一晶体管T1的栅极连接到所述对应一组栅线G1、G2和G3中的各自不同的栅线，并且其中连接到不同列的像素电极PE的不同对晶体管中的各第二晶体管T2的栅极连接到所述一组多路复用线MUX1、MUX2和MUX3中的各自不同的多路复用线。例如，右上的第一晶体管T1和右下的第一晶体管T1的栅极被分别连接到栅线G1和G3，并且左下的第二晶体管T2和右下的第二晶体管T2的第一极被分别连接到多路复用线MUX1和MUX3。如下面将描述的，多路复用线MUX1、MUX2和MUX3在栅极扫描期间以时分方式传送各自的扫描脉冲信号。这使得在每个像素电极阵列211中，同一行中的各个像素电极PE可以从同一条数据线被供应不同的数据电压。这样，在每个像素电极阵列211中，同一行中的各个像素电极PE可以由同一条栅线和同一条数据线的信号驱动，实现正常的显示功能。
通过提供多路复用线MUX1、MUX2和MUX3和第二晶体管T2，减少了阵列基板200中的数据线，并且因此阵列基板200的PPI进一步得到提高。将理解的是，在图4中，多路复用线MUX1、MUX2和MUX3的布置是示例性的，并且在其他实施例中，多路复用线MUX1、MUX2和MUX3可以被布置在其他位置。例如，多路复用线MUX1、MUX2和MUX3也可设置在阵列基板200的右侧。
在图4的示例中，每个像素电极阵列211包括3×3个像素电极PE，每组栅线包括3条栅线，并且所述一组多路复用线也包括3条多路复用线。然而，本公开不限于此。例如，每个像素电极阵列211可以包括例如2×2个像素电极PE、2×4个像素电极PE、或2×1个像素电极PE。更一般地，每个像素电极阵列211的所述多个像素电极PE呈M×N的阵列排布，每组栅线包括M条栅线，并且所述一组多路复用线包括N条多路复用线。M为大于1的整数，并且N为大于或等于1的整数。替换地，M为大于或等于1的整数，并且N为大于1的整数。
图6示出了用于驱动图5的像素区域210中的像素电极PE的时序图。
针对栅线G1，栅极扫描信号在时间段t内有效(在该示例中为高电平)。时间段t包括第一时间段t1、第二时间段t2和第三时间段t3。多路复用线MUX1、MUX2和MUX3在该时间段t内以时分方式传送各自的扫描脉冲信号，其中所述各自的扫描脉冲信号分别在第一、第二和第三时间段t1、t2和t3内有效。
在第一时间段t1内，多路复用线MUX1上的扫描脉冲信号有效，并且数据线D1上存在第一数据电压。该第一数据电压被传送至第一行第一列的像素电极PE。
在第二时间段t2内，多路复用线MUX2上的扫描脉冲信号有效，并且数据线D1上存在第二数据电压。该第二数据电压被传送至第一行第二列的像素电极PE。
在第三时间段t3内，多路复用线MUX3上的扫描脉冲信号有效，并且数据线D1上存在第三数据电压。该第三数据电压被传送至第一行第三列的像素电极PE。
接着，向栅线G2供应有效的栅极扫描信号，向多路复用线MUX1、MUX2和MUX3依次供应各自的扫描脉冲信号，并且与多路复用线MUX1、MUX2和MUX3上的扫描脉冲信号同步地向数据线D1供应各数据电压。这些数据电压被分别传送至第二行第一列的像素电极PE、第二行第二列的像素电极PE和第二行第三列的像素电极PE。最后，向栅线G3供应有效的栅极扫描信号，向多路复用线MUX1、MUX2和MUX3依次供应各自的扫描脉冲信号，并且与多路复用线MUX1、MUX2和MUX3上的扫描脉冲信号同步地向数据线D1供应各数据电 压。这些数据电压被分别传送至第三行第一列的像素电极PE、第三行第二列的像素电极PE和第三行第三列的像素电极PE。
图7示出了根据本公开实施例的一种显示装置300的结构示意图。
参考图7，显示装置300包括显示面板310，该显示面板310包括阵列基板312。阵列基板312可以采取结合上面实施例描述的阵列基板100或200的形式。图7示出了阵列基板312中的多个像素电极阵列311，其每一个取决于阵列基板312的实现方式可以采取像素电极阵列111或211的形式。在液晶显示器的情况下，显示面板310还可以包括与阵列基板312相对的对向基板(未示出)。在有机发光二极管显示器的情况下，显示面板310还可以包括与阵列基板312相对的盖板(未示出)。
在图7的示例中，显示装置300还包括透镜阵列320，透镜阵列320位于显示面板310的出光侧。透镜阵列320包括多个透镜322，所述多个透镜322被布置成与各所述像素电极阵列311中的相应像素电极阵列相对。各个像素电极阵列311所对应的像素用于显示相应的元图像，所述元图像然后被多个透镜322投射至观看区。这使得显示装置300成为基于集成成像的三维显示器。
图8示出了显示装置300的示意性框图。参照图8，显示装置300包括显示面板310、透镜阵列320、栅极驱动器330、数据驱动器340、以及时序控制器350。
显示面板310包括如上所述的阵列基板312(图8中未示出)，例如阵列基板100或200。在液晶显示器的情况下，显示面板310还可以包括与阵列基板相对的对向基板(未示出)和夹在阵列基板与对向基板之间的液晶层(未示出)。在有机发光二极管显示器的情况下，显示面板310还可以包括与阵列基板相对的盖板(未示出)。显示面板310包括多组栅线GL、多组数据线DL、以及多个像素区域PX，例如多个像素区域110或210。各像素区域PX位于多组栅极线GL和多组数据线DL的相应交叉处。在阵列基板200的情况下，显示面板310还包括一组多路复用线(未示出)。
栅极驱动器330电连接到各组栅极线GL并且顺序地向各栅极线供应栅极扫描信号。在一些示例性实施例中，栅极驱动器330可以被集成在显示面板310中。替换地，栅极驱动器330可以通过带式载体封 装(Tape Carrier Package，TCP)连接至显示面板310。栅极驱动器330可以由本领域中的典型技术来实现，并且在此不进行详述。
数据驱动器340电连接至各组数据线DL并且将数据电压施加至各数据线。在一些实施例中，数据驱动器340可以包括多个并行操作的数据驱动芯片。数据驱动器340可以由本领域中的典型技术来实现，并且在此不进行详述。
时序控制器350控制栅极驱动器330和数据驱动器340中的每一个的操作。具体地，时序控制器350输出数据控制信号和图像数据以控制数据驱动器340的驱动操作，以及输出栅极控制信号以控制栅极驱动器330的驱动操作。在阵列基板200的情况下，时序控制器350还可以包括或控制用于生成要顺序地施加到所述一组多路复用线的扫描脉冲信号(如图6所示的)的电路(未示出)。时序控制器350可以由本领域中的典型技术来实现。典型地，时序控制器350可以是常规处理器、控制器、微控制器、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或状态机。时序控制器350也可以被实现为计算设备的组合，例如DSP和微处理器的组合、多个微处理器、结合DSP核的一个或多个微处理器或任何其他这样的配置。
作为示例而非限制，该显示装置300可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
通过研究附图、公开内容和所附的权利要求书，本领域技术人员在实践所要求保护的主题时，能够理解和实现对于所公开的实施例的变型。在权利要求书中，词语“包括”不排除其他元件或步骤，并且不定冠词“一”或“一个”不排除多个。在相互不同的从属权利要求中记载了某些措施的仅有事实并不表明这些措施的组合不能用来获利。

Claims (14)

  1. 一种阵列基板，包括：
    多个像素区域，按行和列排布，其中所述多个像素区域包括相应的像素电极阵列和与所述相应的像素电极阵列相关联的相应的像素电路，其中各所述像素电极阵列按行和列布置，并且其中每个像素电极阵列包括呈阵列排布的多个像素电极；
    多组栅线，在行方向上延伸，其中所述多组栅线与各行像素电极阵列在与所述行方向交叉的列方向上彼此交替排布；以及
    多组数据线，在所述列方向上延伸，其中所述多组数据线与各列像素区域在所述行方向上彼此交替排布，
    其中每个像素电路连接到各所述像素电极阵列中的相应一个像素电极阵列的多个像素电极、所述多组栅线中的对应一组栅线、以及所述多组数据线中的对应一组数据线。
  2. 根据权利要求1所述的阵列基板，其中每个像素电路包括相应的多个第一晶体管，并且其中每个第一晶体管包括连接到所述对应一组栅线中的对应一条栅线的栅极、连接到所述对应一组数据线中的对应一条数据线的第一极、以及连接到所述相应一个像素电极阵列的所述多个像素电极中的相应一个像素电极的第二极。
  3. 根据权利要求2所述的阵列基板，其中连接到不同行的像素电极的不同第一晶体管的栅极连接到所述对应一组栅线中的各自不同的栅线，并且其中连接到不同列的像素电极的不同第一晶体管的第一极连接到所述对应一组数据线中的各自不同的数据线。
  4. 根据权利要求2所述的阵列基板，其中每个像素电极阵列的所述多个像素电极呈M×N的阵列排布，其中每组栅线包括M条栅线，并且其中每组数据线包括N条数据线，M为大于1的整数，并且N为大于或等于1的整数。
  5. 根据权利要求2所述的阵列基板，其中每个像素电极阵列的所述多个像素电极呈M×N的阵列排布，其中每组栅线包括M条栅线，并且其中每组数据线包括N条数据线，M为大于或等于1的整数，并且N为大于1的整数。
  6. 根据权利要求1所述的阵列基板，还包括沿所述列方向延伸的 一组多路复用线，其中每组数据线包括相应的单条数据线，其中每个像素电路包括多对晶体管，并且其中每一对晶体管包括：
    第一晶体管，包括连接到所述对应一组栅线中的对应一条栅线的栅极、第一极、以及连接到所述相应一个像素电极阵列的所述多个像素电极中的相应一个像素电极的第二极；以及
    第二晶体管，包括连接到所述一组多路复用线中的对应一条多路复用线的栅极、连接到所述对应一组数据线的单条数据线的第一极、以及连接到所述第一晶体管的第一极的第二极。
  7. 根据权利要求6所述的阵列基板，其中连接到不同行的像素电极的不同对晶体管中的各第一晶体管的栅极连接到所述对应一组栅线中的各自不同的栅线，并且其中连接到不同列的像素电极的不同对晶体管中的各第二晶体管的栅极连接到所述一组多路复用线中的各自不同的多路复用线。
  8. 根据权利要求6所述的阵列基板，其中每个像素电极阵列的所述多个像素电极呈M×N的阵列排布，其中每组栅线包括M条栅线，并且其中所述一组多路复用线包括N条多路复用线。
  9. 根据权利要求1所述的阵列基板，其中每个像素区域还包括相应的多条电极引线，并且其中每个像素电路经由所述相应的多条电极引线连接到所述相应一个像素电极阵列的多个像素电极中的相应像素电极。
  10. 根据权利要求9所述的阵列基板，其中所述多条电极引线由透明导电材料制成。
  11. 根据权利要求10所述的阵列基板，其中所述透明导电材料包括氧化铟锡或氧化铟锌。
  12. 一种显示面板，包括如权利要求1-11中任一项所述的阵列基板。
  13. 一种显示装置，包括如权利要求12所述的显示面板。
  14. 根据权利要求13所述的显示装置，还包括位于所述显示面板的出光侧的透镜阵列，其中所述透镜阵列包括多个透镜，所述多个透镜被布置成与各所述像素电极阵列中的相应像素电极阵列相对。
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