WO2019210619A1 - 一种阵列基板及制备方法 - Google Patents

一种阵列基板及制备方法 Download PDF

Info

Publication number
WO2019210619A1
WO2019210619A1 PCT/CN2018/101835 CN2018101835W WO2019210619A1 WO 2019210619 A1 WO2019210619 A1 WO 2019210619A1 CN 2018101835 W CN2018101835 W CN 2018101835W WO 2019210619 A1 WO2019210619 A1 WO 2019210619A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
layer
photoresist
stick
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/101835
Other languages
English (en)
French (fr)
Inventor
李朝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/337,530 priority Critical patent/US20210343759A1/en
Publication of WO2019210619A1 publication Critical patent/WO2019210619A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/273—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a delineation of conductive layers, e.g. by RIE

Definitions

  • the present invention relates to the field of display manufacturing technology, and in particular, to an array substrate and a preparation method.
  • a layer of Plastic is first performed on the glass substrate.
  • Film (current process material is polyimide, Polyimide) coating, as the substrate of the array substrate process, then the array substrate fabrication process on the substrate, through 11 mask (mask) process to form the TFT array substrate, Part of the structure is shown in FIG. 1.
  • a first gate insulating layer 102 is first deposited on the basis of the previous layer process (polysilicon layer 101), and the first gate insulating layer is formed.
  • a first gate metal film material mo, molybdenum
  • the first gate metal film yellow light process is performed to form a gate pattern 103 after the gate pattern 103 is formed.
  • a second gate insulating layer 104 is further plated, and then a second gate metal film (material mo, molybdenum) is plated, and then a yellow light process is performed to form a gate capacitor 106, and then at the gate.
  • An interlayer insulating layer 105 is formed on the capacitor 106.
  • the invention provides an array substrate and a preparation method thereof, which can protect the molybdenum metal used for preparing the gate and the gate capacitance from being corroded and oxidized by the environment, and ensure the adhesion of the yellow photoresist, so that the gate does not be in the yellow light process. A disconnection problem has occurred.
  • the invention provides a method for preparing an array substrate, the method comprising the following steps:
  • Step S1 providing a substrate, sequentially preparing a buffer layer, a polysilicon layer, and a first gate insulating layer on the substrate;
  • Step S2 preparing a first gate metal layer on the first gate insulating layer, preparing a first photoresist thin film non-stick metal film on the first gate metal layer, and forming a pattern after exposure and development a gate and a first photoresist layer non-stick metal pattern on the surface of the gate;
  • the first photoresist non-stick metal pattern and the gate are made through the same photomask.
  • the method further comprises the steps of:
  • Step S3 sequentially preparing a second gate insulating layer, a second gate metal layer, and a second photoresist non-stick metal film on the first photoresist non-stick metal pattern, and forming a patterned gate after exposure and development a capacitor and a second photoresist resisting metal pattern on the gate capacitor;
  • the second photoresist non-stick metal pattern and the gate capacitor are made through the same photomask.
  • the method further comprises the steps of:
  • Step S4 preparing an interlayer insulating layer on the second photoresist non-stick metal pattern, patterning to form a source region and a drain region corresponding to the polysilicon layer and penetrating the interlayer insulating layer, a second gate insulating layer and a via of the first gate insulating layer;
  • Step S5 preparing a source/drain metal layer on the interlayer insulating layer, patterning to form a source electrically connected to the source region, and a drain electrically connected to the drain region.
  • the material of the first gate metal layer and the second gate metal layer is molybdenum.
  • the first gate metal layer and the second gate metal layer have a thickness of 2500A.
  • the material of the first photoresist non-stick metal film and the second photoresist non-adhesive metal film is titanium.
  • the first photoresist non-stick metal film and the second photoresist non-stick metal film have a thickness of 500A.
  • the method for preparing the first photoresist non-stick metal film and the second photoresist non-stick metal film comprises coating with a vacuum sputter coater.
  • the invention also provides an array substrate comprising:
  • a first gate insulating layer is prepared on the polysilicon layer
  • a gate electrode corresponding to the polysilicon layer is prepared on the first gate insulating layer
  • the first photoresist layer is not adhered to the metal layer and is prepared on the gate surface;
  • the projection area of the first photoresist-resistant non-stick metal layer on the substrate overlaps with the projection area of the gate on the substrate.
  • the array substrate further includes:
  • a second gate insulating layer is prepared on the first photoresist layer non-stick metal layer
  • a gate capacitance corresponding to the gate is prepared on the second gate insulating layer
  • a second photoresist layer is not adhered to the metal layer and is prepared on the surface of the gate capacitor
  • a projection area of the second photoresist non-stick metal layer on the substrate overlaps with a projection area of the gate capacitance on the substrate.
  • the invention has the beneficial effects that the array substrate and the preparation method of the invention protect the metal molybdenum by coating a metal molybdenum material of the gate and the gate capacitance with a photoresist film (such as Ti).
  • a photoresist film such as Ti
  • the process is simple, the cost is reduced, and the disconnection problem caused by the decrease of the adhesion of the gate photoresist in the yellow light process is reduced without adding a photomask.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a flowchart of a method for preparing an array substrate according to an embodiment of the present invention
  • 3A-3L are schematic diagrams showing a preparation process of an array substrate according to an embodiment of the present invention.
  • the invention is directed to the array substrate of the prior art, in which the molybdenum metal is easily oxidized in the gate yellow light process, and the organic solvent in the environment is liable to adhere to the surface of the molybdenum to reduce the adhesion of the photoresist, resulting in yellow light exposure.
  • This embodiment can solve the drawback because of the technical problem that the photoresist is not sticky and the disconnection is poor.
  • FIG. 2 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention. The method includes the following steps:
  • Step S1 providing a substrate, sequentially preparing a buffer layer, a polysilicon layer, and a first gate insulating layer on the substrate;
  • a base substrate 301 is provided.
  • the base substrate 301 includes a display area and a non-display area.
  • a buffer layer 302 is prepared on the base substrate 301, and the buffer layer 302 is corresponding to the buffer layer 302.
  • the display region prepares a patterned polysilicon layer 303, wherein the polysilicon layer 303 includes source and drain regions at both ends, and the surface of the polysilicon layer 303 is cleaned by a cleaning device 304.
  • a first gate insulating layer 305 is prepared on the surface of the polysilicon layer 303.
  • the material of the first gate insulating layer 305 is a non-metal material such as SiO2, and the thickness of the first gate insulating layer 305. About 1300A.
  • the surface of the first gate insulating layer 305 is cleaned by the cleaning device 304, as shown in FIG. 3C.
  • Step S2 preparing a first gate metal layer on the first gate insulating layer, preparing a first photoresist thin film non-stick metal film on the first gate metal layer, and forming a pattern after exposure and development a gate and a first photoresist layer non-stick metal pattern on the surface of the gate;
  • a first gate metal layer 306 is formed on the surface of the first gate insulating layer 305.
  • the material of the first gate metal layer 306 is metallic molybdenum.
  • the first gate metal layer 306 has a thickness of about 2500A.
  • the metal molybdenum material is easily oxidized with some substances in the air, and is easily contaminated by an organic solvent in the environment, which may cause undesirable phenomena such as wire breakage, but its electrical conductivity is excellent, and it is better to solve the above problems in a display device. The guarantee shows the good performance of the device.
  • a first photoresist layer non-stick metal film 307 is then formed on the first gate metal layer 306.
  • the method for preparing the first photoresist non-stick metal film 307 can be performed by a vacuum sputtering coater.
  • the first photoresist non-stick metal film 307 has good oxidation resistance and corrosion resistance, can protect the metal molybdenum material from being oxidized, and can prevent the metal molybdenum material from being easily trapped in the environment. Contamination, so that the problem of reduced adhesion of the photoresist can be avoided.
  • the first photoresist non-stick metal film 307 has a thickness of about 500A.
  • the material of the first photoresist non-stick metal film 307 is a metal material having the same or similar properties as the above metal titanium.
  • the material of the first photoresist non-stick metal film 307 is metal titanium.
  • a photoresist is applied on the surface of the first photoresist non-stick metal film 307 to perform a first yellow light process.
  • a patterned gate 308 is formed by one exposure and development of the same mask, and a first photoresist-resistant non-stick metal pattern 309 is disposed on the surface of the gate 308.
  • the gate 308 and the first photoresist non-stick metal pattern 309 are located at positions corresponding to the polysilicon layer 303.
  • the cleaning device 304 is used to clean the surface of the first photoresist non-stick metal pattern 309, as shown in FIG. 3G.
  • Step S3 sequentially preparing a second gate insulating layer, a second gate metal layer, and a second photoresist non-stick metal film on the first photoresist non-stick metal pattern, and forming a patterned gate after exposure and development
  • the capacitor and the second photoresist on the gate capacitor do not have a metal pattern.
  • a second gate insulating layer 310 is formed on the surface of the first photoresist non-stick metal pattern 309 and the surface of the first gate insulating layer 305.
  • the material of the second gate insulating layer 310 is a non-metal material such as SiNx.
  • the thickness of the second gate insulating layer 310 is about 1200A. The surface of the second gate insulating layer 310 is then cleaned by the cleaning device 304, as shown in FIG. 3I.
  • a second gate metal layer 311 is formed on the surface of the second gate insulating layer 310.
  • the material of the second gate metal layer 310 is metallic molybdenum.
  • the second gate metal layer 310 has a thickness of about 2500A.
  • a second photoresist non-stick metal film 312 is prepared on the surface of the second gate metal layer 311.
  • the method for preparing the second photoresist-resistant non-stick metal film 312 can be performed by a vacuum sputter coater.
  • the second photoresist non-stick metal film 312 is identical to the material of the second photoresist non-stick metal film 307, and is preferably a metal titanium material.
  • the thickness of the second photoresist non-stick metal film 312 is about 500A.
  • a photoresist is applied on the surface of the second photoresist non-stick metal film 312 to perform a second yellow light process.
  • a patterned gate capacitance 313 is formed after one exposure and development by the same mask, and a second photoresist photoresist non-stick metal pattern 314 is located on the surface of the gate capacitance 313.
  • the gate capacitance 313 and the second photoresist non-stick metal pattern 314 are located at positions corresponding to the polysilicon layer 303.
  • the method for preparing the array substrate further includes the following steps:
  • Step S4 preparing an interlayer insulating layer on the second photoresist non-stick metal pattern, patterning to form a source region and a drain region corresponding to the polysilicon layer and penetrating the interlayer insulating layer, a second gate insulating layer and a via of the first gate insulating layer;
  • Step S5 preparing a source/drain metal layer on the interlayer insulating layer, patterning to form a source electrically connected to the source region, and a drain electrically connected to the drain region.
  • the material of the first photoresist non-stick metal film and the second photoresist non-adhesive metal film of the present invention is not limited to a metal titanium material, and may also be other anti-oxidation, corrosion-resistant and not A metal material that affects the adhesion of photoresist.
  • the invention also provides an array substrate prepared by the above preparation method, which is used for preparing a flexible AMOLED display panel or a liquid crystal display panel.
  • the array substrate includes: a substrate and a buffer layer prepared on the substrate, a polysilicon layer and a first gate insulating layer; a gate corresponding to the polysilicon layer on the first gate insulating layer; a photoresist non-stick metal layer is prepared on the gate surface; a second gate insulating layer is prepared on the first photoresist non-stick metal layer; a gate capacitance corresponding to the gate is prepared in the first The second photoresist layer is formed on the surface of the gate capacitor.
  • a projection area of the first photoresist-resistant non-stick metal layer on the substrate overlaps with a projection area of the gate on the substrate; the second photoresist-resistant non-stick metal layer is in the A projection area on the substrate overlaps a projection area of the gate capacitance on the substrate.
  • the array substrate and the preparation method of the invention have the purpose of protecting the metal molybdenum from being oxidized by plating a layer of anti-resistance non-stick metal film (such as Ti) on the metal molybdenum material of the gate electrode and the gate capacitor.
  • the anti-resistance non-stick metal film has strong corrosion resistance and is not easily contaminated by environmental organic solvents, thereby protecting the yellow light photoresist adhesion, avoiding the problem of lowering the adhesion of the photoresist, simplifying the process, and reducing the cost.
  • the problem of disconnection caused by the decrease in the adhesion of the gate photoresist in the yellow light process is reduced without adding a photomask.

Landscapes

  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

本发明提供一种阵列基板及制备方法，所述方法包括以下步骤：先提供一基板，在所述基板上依次制备缓冲层、多晶硅层以及第一栅绝缘层；然后在所述第一栅绝缘层上制备一层第一栅极金属层，在所述第一栅极金属层上制备一层第一防光阻不黏金属膜，曝光显影后形成图案化的栅极和位于所述栅极表面的第一防光阻不黏金属图案。

Description

一种阵列基板及制备方法 技术领域
本发明涉及显示制造技术领域，尤其涉及一种阵列基板及制备方法。
 背景技术
在AMOLED显示屏生产制程中，首先会在玻璃基板上进行一层Plastic Film（目前工艺材料是聚酰亚胺，Polyimide）的涂布，作为阵列基板制程的基底，之后会在基底上进行阵列基板制作工艺，经过11道mask（光罩）工艺制作形成TFT阵列基板，部分结构如图1所示，其在制备Gate（栅极）工艺时，先在前一层工艺(多晶硅层101)基础上镀一层第一栅绝缘层102，在形成该第一栅绝缘层102的基础上进行镀第一栅极金属膜（材料mo，钼），随后进行所述第一栅极金属膜黄光工艺，刻蚀形成栅极图案103，在所述栅极图案103形成后再镀一层第二栅绝缘层104，之后再镀上一层第二栅极金属膜（材料mo，钼），再进行黄光工艺，刻蚀形成栅极电容106，之后在所述栅极电容106上制备一层间绝缘层105。
在进行上述第一栅极金属膜与第二栅极金属膜黄光工艺中，因为mo金属很容易发生氧化，同时洁净室环境存在有机溶剂，容易附着在mo表面对光阻的粘附性造成下降，导致黄光曝光后有因光阻不粘导致栅极断线不良产生，从而影响显示器件的导电性能。
因此，有必要提供一种阵列基板及制备方法，以解决现有技术所存在的问题。
 技术问题
本发明提供一种阵列基板及制备方法，能够保护用于制备栅极及栅极电容的钼金属不被环境腐蚀和氧化，保证黄光光阻的粘附性，使得栅极在黄光工艺时不会发生断线问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种阵列基板的制备方法，所述方法包括以下步骤：
步骤S1、提供一基板，在所述基板上依次制备缓冲层、多晶硅层以及第一栅绝缘层；
步骤S2、在所述第一栅绝缘层上制备一层第一栅极金属层，在所述第一栅极金属层上制备一层第一防光阻不黏金属膜，曝光显影后形成图案化的栅极和位于所述栅极表面的第一防光阻不黏金属图案；
其中，所述第一防光阻不黏金属图案与所述栅极经由同一道光罩制成。
根据本发明一优选实施例，所述方法还包括以下步骤：
步骤S3、在所述第一防光阻不黏金属图案上依次制备第二栅绝缘层、第二栅极金属层以及第二防光阻不黏金属膜，曝光显影后形成图案化的栅极电容和位于所述栅极电容上的第二防光阻不黏金属图案；
其中，所述第二防光阻不黏金属图案与所述栅极电容经由同一道光罩制成。
根据本发明一优选实施例，所述方法还包括以下步骤：
步骤S4、在所述第二防光阻不黏金属图案上制备一层间绝缘层，图案化后形成对应所述多晶硅层的源极区域与漏极区域且贯穿所述间绝缘层、所述第二栅绝缘层以及所述第一栅绝缘层的过孔；
步骤S5、在所述间绝缘层上制备一层源漏极金属层，图案化后形成与所述源极区域电性连接的源极，以及与所述漏极区域电性连接的漏极。
根据本发明一优选实施例，所述第一栅极金属层与所述第二栅极金属层的材料为钼。
根据本发明一优选实施例，所述第一栅极金属层与所述第二栅极金属层的厚度为2500A。
根据本发明一优选实施例，所述第一防光阻不黏金属膜与所述第二防光阻不黏金属膜的材料为钛。
根据本发明一优选实施例，所述第一防光阻不黏金属膜与所述第二防光阻不黏金属膜的厚度为500A。
根据本发明一优选实施例，所述第一防光阻不黏金属膜与所述第二防光阻不黏金属膜的制备方法包括采用真空溅射镀膜机进行镀膜。
本发明还提供一种阵列基板，包括：
基板；
缓冲层，制备于所述基板上；
多晶硅层，制备于所述缓冲层上；
第一栅绝缘层，制备于所述多晶硅层上；
栅极，对应所述多晶硅层制备于所述第一栅绝缘层上；
第一防光阻不黏金属层，制备于所述栅极表面；
其中，所述第一防光阻不黏金属层在所述基板上的投影区域与所述栅极在所述基板上的投影区域重叠。
根据本发明一优选实施例，所述阵列基板还包括：
第二栅绝缘层，制备于所述第一防光阻不黏金属层上；
栅极电容，对应所述栅极制备于所述第二栅绝缘层上；
第二防光阻不黏金属层，制备于所述栅极电容表面；
其中，所述第二防光阻不黏金属层在所述基板上的投影区域与所述栅极电容在所述基板上的投影区域重叠。
 有益效果
本发明的有益效果为：本发明的阵列基板及制备方法，通过在栅极以及栅极电容的金属钼材料上镀一层防光阻不黏金属膜（比如Ti），起到保护金属钼不被氧化的目的，同时因防光阻不黏金属膜的耐腐蚀性强，不容易被环境有机溶剂污染，从而起到保护黄光光阻粘附性的作用，避免了光阻的粘附性降低问题，制程简单，降低成本，在不增加光罩的情况下减少黄光工艺中栅极光阻粘附性下降引起的断线问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中阵列基板的结构示意图；
图2为本发明实施例提供的阵列基板的制备方法流程图；
图3A~3L为本发明实施例提供的阵列基板的制备流程示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的阵列基板，在栅极黄光工艺中因钼金属容易发生氧化，同时环境中的有机溶剂容易附着在钼表面对光阻的粘附性造成下降，导致黄光曝光后因光阻不粘导致断线不良的技术问题，本实施例能够解决该缺陷。
参阅图2，为本发明实施例提供的阵列基板的制备方法流程图。所述方法包括以下步骤：
步骤S1、提供一基板，在所述基板上依次制备缓冲层、多晶硅层以及第一栅绝缘层；
如图3A所示，提供一衬底基板301，所述衬底基板301包括显示区域与非显示区域，在所述衬底基板301上制备一层缓冲层302，在所述缓冲层302对应所述显示区域制备图案化的多晶硅层303，其中所述多晶硅层303包括位于两端的源极区域与漏极区域，并用清洁装置304清理所述多晶硅层303表面。
如图3B所示，在所述多晶硅层303表面制备一层第一栅绝缘层305，所述第一栅绝缘层305的材料为SiO2等非金属材料，所述第一栅绝缘层305的厚度约1300A。并采用所述清洁装置304清理所述第一栅绝缘层305表面，如图3C所示。
步骤S2、在所述第一栅绝缘层上制备一层第一栅极金属层，在所述第一栅极金属层上制备一层第一防光阻不黏金属膜，曝光显影后形成图案化的栅极和位于所述栅极表面的第一防光阻不黏金属图案；
如图3D所示，在所述第一栅绝缘层305表面制备一层第一栅极金属层306。优选的，所述第一栅极金属层306的材料为金属钼。优选的，所述第一栅极金属层306的厚度约为2500A。该金属钼材料极易与空气中的一些物质发生氧化，容易被环境中的有机溶剂污染易造成断线等不良现象，但其导电性能优良，用于显示器件中则需解决上述问题才能更好的保证显示器件良好的性能。
如图3E所示，接着在所述第一栅极金属层306上制备一层第一防光阻不黏金属膜307。所述第一防光阻不黏金属膜307的制备方法可采用真空溅射镀膜机进行镀膜。该第一防光阻不黏金属膜307具备良好的抗氧化性及耐腐蚀性，可以起到保护金属钼材料不被氧化，以及能够起到使所述金属钼材料不易被环境中的有机溶剂污染，从而可以避免光阻的粘附性降低问题。优选的，所述第一防光阻不黏金属膜307的厚度为500A左右。同时调查发现在相同的洁净室环境下SD层黄光曝光后，未发生光阻粘附性下降导致的断线不良存在，SD层镀膜为(Ti-AL-Ti)，Ti（钛）具有较强耐腐蚀性，不易被氧化，同时有机溶剂对金属钛的影响较小，不会引起黄光光阻粘附性下降的问题而发生断线。因此，所述第一防光阻不黏金属膜307的材料为与上述金属钛性质相同或类似的金属材料。优选的，所述第一防光阻不黏金属膜307的材料为金属钛。
如图3F所示，在所述第一防光阻不黏金属膜307的表面涂布一层光刻胶，进行第一次黄光工艺。经同一道光罩进行一次曝光显影后形成图案化的栅极308，以及位于所述栅极308表面的第一防光阻不黏金属图案309。所述栅极308以及所述第一防光阻不黏金属图案309位于对应所述多晶硅层303的位置。之后采用所述清洁装置304清理所述第一防光阻不黏金属图案309表面，如图3G所示。
步骤S3、在所述第一防光阻不黏金属图案上依次制备第二栅绝缘层、第二栅极金属层以及第二防光阻不黏金属膜，曝光显影后形成图案化的栅极电容和位于所述栅极电容上的第二防光阻不黏金属图案。
如图3H所示，在所述第一防光阻不黏金属图案309表面以及所述第一栅绝缘层305表面制备一层第二栅绝缘层310。优选的，所述第二栅绝缘层310的材料为SiNx等非金属材料。优选的，所述第二栅绝缘层310的厚度为1200A左右。之后采用所述清洁装置304清理所述第二栅绝缘层310表面，如图3I所示。
如图3J所示，在所述第二栅绝缘层310表面制备一层第二栅极金属层311。优选的，所述第二栅极金属层310的材料为金属钼。优选的，所述第二栅极金属层310的厚度约为2500A左右。
如图3K所示，在所述第二栅极金属层311的表面制备一层第二防光阻不黏金属膜312。所述第二防光阻不黏金属膜312的制备方法可采用真空溅射镀膜机进行镀膜。该第二防光阻不黏金属膜312与所述第二防光阻不黏金属膜307的材料一致，优选为金属钛材料。优选的，所述第二防光阻不黏金属膜312的厚度为500A左右。
如图3L所示，在所述第二防光阻不黏金属膜312的表面涂布一层光刻胶，进行第二次黄光工艺。经同一道光罩进行一次曝光显影后形成图案化的栅极电容313，以及位于所述栅极电容313表面的第二防光阻不黏金属图案314。所述栅极电容313以及所述第二防光阻不黏金属图案314位于对应所述多晶硅层303的位置。
此外，所述阵列基板的制备方法还包括以下步骤：
步骤S4、在所述第二防光阻不黏金属图案上制备一层间绝缘层，图案化后形成对应所述多晶硅层的源极区域与漏极区域且贯穿所述间绝缘层、所述第二栅绝缘层以及所述第一栅绝缘层的过孔；
步骤S5、在所述间绝缘层上制备一层源漏极金属层，图案化后形成与所述源极区域电性连接的源极，以及与所述漏极区域电性连接的漏极。
可以理解的是，本发明的所述第一防光阻不黏金属膜与所述第二防光阻不黏金属膜的材料不限于金属钛材料，还可以为其他抗氧化、耐腐蚀且不影响光阻粘附性的金属材料。
本发明还提供一种采用上述制备方法制备的阵列基板，该阵列基板用于制备柔性AMOLED显示面板或液晶显示面板。该阵列基板包括：基板以及依次层叠制备于所述基板上的缓冲层、多晶硅层以及第一栅绝缘层；栅极，对应所述多晶硅层制备于所述第一栅绝缘层上；第一防光阻不黏金属层，制备于所述栅极表面；第二栅绝缘层，制备于所述第一防光阻不黏金属层上；栅极电容，对应所述栅极制备于所述第二栅绝缘层上；第二防光阻不黏金属层，制备于所述栅极电容表面。
其中，所述第一防光阻不黏金属层在所述基板上的投影区域与所述栅极在所述基板上的投影区域重叠；所述第二防光阻不黏金属层在所述基板上的投影区域与所述栅极电容在所述基板上的投影区域重叠。
本发明的阵列基板及制备方法，通过在栅极以及栅极电容的金属钼材料上镀一层防光阻不黏金属膜（比如Ti），起到保护金属钼不被氧化的目的，同时因防光阻不黏金属膜的耐腐蚀性强，不容易被环境有机溶剂污染，从而起到保护黄光光阻粘附性的作用，避免了光阻的粘附性降低问题，制程简单，降低成本，在不增加光罩的情况下减少黄光工艺中栅极光阻粘附性下降引起的断线问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种阵列基板的制备方法，其中，所述方法包括以下步骤：
    步骤S1、提供一基板，在所述基板上依次制备缓冲层、多晶硅层以及第一栅绝缘层；
    步骤S2、在所述第一栅绝缘层上制备一层第一栅极金属层，在所述第一栅极金属层上制备一层第一防光阻不黏金属膜，曝光显影后形成图案化的栅极和位于所述栅极表面的第一防光阻不黏金属图案；
    其中，所述第一防光阻不黏金属图案与所述栅极经由同一道光罩制成。
  2. 根据权利要求1所述的制备方法，其中，所述方法还包括以下步骤：
    步骤S3、在所述第一防光阻不黏金属图案上依次制备第二栅绝缘层、第二栅极金属层以及第二防光阻不黏金属膜，曝光显影后形成图案化的栅极电容和位于所述栅极电容上的第二防光阻不黏金属图案；
    其中，所述第二防光阻不黏金属图案与所述栅极电容经由同一道光罩制成。
  3. 根据权利要求1所述的制备方法，其中，所述方法还包括以下步骤：
    步骤S4、在所述第二防光阻不黏金属图案上制备一层间绝缘层，图案化后形成对应所述多晶硅层的源极区域与漏极区域且贯穿所述间绝缘层、所述第二栅绝缘层以及所述第一栅绝缘层的过孔；
    步骤S5、在所述间绝缘层上制备一层源漏极金属层，图案化后形成与所述源极区域电性连接的源极，以及与所述漏极区域电性连接的漏极。
  4. 根据权利要求2所述的制备方法，其中，所述第一栅极金属层与所述第二栅极金属层的材料为钼。
  5. 根据权利要求2所述的制备方法，其中，所述第一栅极金属层与所述第二栅极金属层的厚度为2500A。
  6. 根据权利要求2所述的制备方法，其中，所述第一防光阻不黏金属膜与所述第二防光阻不黏金属膜的材料为钛。
  7. 根据权利要求2所述的制备方法，其中，所述第一防光阻不黏金属膜与所述第二防光阻不黏金属膜的厚度为500A。
  8. 根据权利要求2所述的制备方法，其中，所述第一防光阻不黏金属膜与所述第二防光阻不黏金属膜的制备方法包括采用真空溅射镀膜机进行镀膜。
  9. 一种阵列基板，其包括：
    基板；
    缓冲层，制备于所述基板上；
    多晶硅层，制备于所述缓冲层上；
    第一栅绝缘层，制备于所述多晶硅层上；
    栅极，对应所述多晶硅层制备于所述第一栅绝缘层上；
    第一防光阻不黏金属层，制备于所述栅极表面；
    其中，所述第一防光阻不黏金属层在所述基板上的投影区域与所述栅极在所述基板上的投影区域重叠。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括：
    第二栅绝缘层，制备于所述第一防光阻不黏金属层上；
    栅极电容，对应所述栅极制备于所述第二栅绝缘层上；
    第二防光阻不黏金属层，制备于所述栅极电容表面；
    其中，所述第二防光阻不黏金属层在所述基板上的投影区域与所述栅极电容在所述基板上的投影区域重叠。
PCT/CN2018/101835 2018-05-03 2018-08-23 一种阵列基板及制备方法 Ceased WO2019210619A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/337,530 US20210343759A1 (en) 2018-05-03 2018-08-23 Array substrate and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810412387.XA CN108598090A (zh) 2018-05-03 2018-05-03 一种阵列基板及制备方法
CN201810412387.X 2018-05-03

Publications (1)

Publication Number Publication Date
WO2019210619A1 true WO2019210619A1 (zh) 2019-11-07

Family

ID=63619639

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/101835 Ceased WO2019210619A1 (zh) 2018-05-03 2018-08-23 一种阵列基板及制备方法

Country Status (3)

Country Link
US (1) US20210343759A1 (zh)
CN (1) CN108598090A (zh)
WO (1) WO2019210619A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110610967A (zh) * 2019-08-28 2019-12-24 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN115440650B (zh) * 2022-09-20 2025-08-01 中国科学院光电技术研究所 柱销式衬底保持器及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094304A (zh) * 2011-11-07 2013-05-08 三星显示有限公司 薄膜晶体管阵列基板及其制造方法和有机发光显示装置
CN103296034A (zh) * 2013-05-28 2013-09-11 京东方科技集团股份有限公司 一种阵列基板、制备方法以及显示装置
CN105093747A (zh) * 2015-08-11 2015-11-25 武汉华星光电技术有限公司 低温多晶硅阵列基板的修补方法
US20160027813A1 (en) * 2013-11-25 2016-01-28 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof and display apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102487041B (zh) * 2010-12-02 2014-07-23 京东方科技集团股份有限公司 阵列基板及其制造方法和电子纸显示器
CN104134674B (zh) * 2014-07-18 2017-02-01 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管阵列基板及其制备方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094304A (zh) * 2011-11-07 2013-05-08 三星显示有限公司 薄膜晶体管阵列基板及其制造方法和有机发光显示装置
CN103296034A (zh) * 2013-05-28 2013-09-11 京东方科技集团股份有限公司 一种阵列基板、制备方法以及显示装置
US20160027813A1 (en) * 2013-11-25 2016-01-28 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof and display apparatus
CN105093747A (zh) * 2015-08-11 2015-11-25 武汉华星光电技术有限公司 低温多晶硅阵列基板的修补方法

Also Published As

Publication number Publication date
US20210343759A1 (en) 2021-11-04
CN108598090A (zh) 2018-09-28

Similar Documents

Publication Publication Date Title
CN107221501B (zh) 垂直型薄膜晶体管及其制备方法
CN102655175B (zh) Tft、阵列基板及显示装置、制备该tft的掩模板
CN101231972A (zh) 柔性显示器件及其制造方法
WO2016029543A1 (zh) 一种薄膜晶体管阵列基板及其制备方法、显示装置
WO2019227668A1 (zh) 触控显示屏的制作方法
CN107731881A (zh) 柔性显示面板及其制造方法、柔性显示装置
WO2020006858A1 (zh) 一种薄膜晶体管及其制作方法
CN106057830A (zh) 一种阵列基板、显示面板及阵列基板制备方法
WO2017156885A1 (zh) 薄膜晶体管、阵列基板及其制作和驱动方法、显示装置
CN111599870A (zh) 一种薄膜晶体管开关及其制备方法、阵列基板和显示面板
CN107579006A (zh) 一种薄膜晶体管、阵列基板及其制备方法
WO2019210619A1 (zh) 一种阵列基板及制备方法
WO2015180357A1 (zh) 阵列基板及其制作方法和显示装置
CN107799466A (zh) Tft基板及其制作方法
WO2021035923A1 (zh) Tft器件及其制备方法、tft阵列基板、显示装置
CN104617049B (zh) 一种阵列基板及其制作方法、显示装置
CN106935660A (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
CN106876260A (zh) 一种闸电极结构及其制造方法和显示装置
CN101093325A (zh) 用于液晶显示器件的阵列基板及其制造方法
CN106531746A (zh) 一种阵列基板、阵列基板的制作方法、显示面板及显示装置
CN106229298A (zh) 一种阵列基板及其制作方法
WO2021114398A1 (zh) 显示面板的制造方法及显示面板
CN105589272A (zh) 阵列基板的制作方法及制得的阵列基板
WO2018176880A1 (zh) 一种阵列基板的制作方法
CN104218151A (zh) 一种有机薄膜晶体管及其制作方法、阵列基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18917279

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18917279

Country of ref document: EP

Kind code of ref document: A1