WO2019206164A1 - 像素电路及其驱动方法、显示面板和显示装置 - Google Patents

像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2019206164A1
WO2019206164A1 PCT/CN2019/084015 CN2019084015W WO2019206164A1 WO 2019206164 A1 WO2019206164 A1 WO 2019206164A1 CN 2019084015 W CN2019084015 W CN 2019084015W WO 2019206164 A1 WO2019206164 A1 WO 2019206164A1
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input end
node
signal input
circuit
voltage
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PCT/CN2019/084015
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English (en)
French (fr)
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殷新社
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京东方科技集团股份有限公司
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Priority to US16/621,137 priority Critical patent/US11087693B2/en
Publication of WO2019206164A1 publication Critical patent/WO2019206164A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • the driving principle of the OLED (Organic Light-Emitting Diode) pixel circuit is to connect the OLED to one electrode of the driving transistor, the other electrode of the driving transistor is connected to the driving voltage, and the gate of the driving transistor is connected to the data line through the switching transistor. .
  • the driving current input to the OLED of the driving transistor has a quadratic relationship with the threshold voltage and the driving voltage of the driving transistor.
  • the input voltage is converted into a current by a driving transistor to drive the OLED to emit light.
  • the magnitude of the drive current is related to its threshold voltage.
  • the present disclosure provides a pixel circuit and a driving method thereof, a display panel, and a display device.
  • An embodiment of the present disclosure provides a pixel circuit including a reset sub-circuit, a charging sub-circuit, a driving sub-circuit, a illuminating sub-circuit, a first capacitor, and a second capacitor;
  • the illuminating sub-circuit is respectively connected to the first node and the first voltage input end;
  • Two ends of the first capacitor are respectively connected to the first node and the first voltage input end;
  • the two ends of the second capacitor are respectively connected to the first node and the second node;
  • the reset sub-circuit is respectively connected to the first node, the reset signal input end and the third control signal input end, and is configured to set a voltage of the first node according to a reset signal;
  • the charging sub-circuit is respectively connected to the second node, the scan signal input end, the data signal input end and the first control signal input end, and is configured to be the first according to the scan signal, the data signal and the first control signal Capacitor and the second capacitor are charged to adjust a voltage of the first node and store display data;
  • the driving sub-circuit is respectively connected to the first node, the second node, the second control signal input end and the second voltage input end, and is configured to input a driving current to the illuminating sub-circuit according to the second control signal To drive the illuminating sub-circuit to emit light.
  • the reset sub-circuit includes a first transistor, and a control electrode of the first transistor is coupled to the reset signal input terminal, and a first pole of the first transistor is coupled to the first node, The second pole of the first transistor is coupled to the third control signal input.
  • the charging subcircuit includes a second transistor and a third transistor
  • a control electrode of the second transistor is connected to the scan signal input end, a first pole of the second transistor is connected to the data signal input end, and a second pole of the second transistor is connected to the second node;
  • a control electrode of the third transistor is connected to the first control signal input end, a first pole of the third transistor is connected to the data signal input end, and a second pole of the third transistor is connected to the second node .
  • the driving subcircuit includes a fourth transistor and a fifth transistor
  • a control electrode of the fourth transistor is connected to the second node, a first pole of the fourth transistor is connected to a second pole of the fifth transistor, and a second pole of the fourth transistor is connected to the first node ;
  • a control electrode of the fifth transistor is connected to the second control signal input end, a first pole of the fifth transistor is connected to a second voltage input end, and a second pole of the fifth transistor is connected to the fourth transistor T4 The first pole.
  • the transistors are all NMOS transistors.
  • Embodiments of the present disclosure provide a display panel including the pixel circuit as described above.
  • An embodiment of the present disclosure provides a display device including a driving chip and a display panel as described above, wherein the driving chip is connected to a pixel circuit in the display panel; and the pixel circuit is based on an input signal of the driving chip Driving the display panel to display an image.
  • An embodiment of the present disclosure provides a driving method for driving a pixel circuit as described above, the driving method comprising:
  • a high level signal is input to the reset signal input end, and a low level signal is input to the first control signal input end, the second control signal input end, and the scan signal input end,
  • the reset sub-circuit sets the voltage of the first node to a first voltage according to the high level signal
  • the charging subcircuit sets a voltage of the second node, and adjusts a voltage of the first node to a second voltage
  • a high level signal is input to the scan signal input end, and a low level signal is input to the first control signal input end, the second control signal input end, and the reset signal input end.
  • the charging subcircuit charges the first capacitor and the second capacitor to store display data input by the data signal input terminal;
  • a high level signal is input to the second control signal input end, and a low level signal is input to the first control signal input end, the scan signal input end and the reset signal input end,
  • the driving sub-circuit inputs a driving current to the illuminating sub-circuit to drive the illuminating sub-circuit to emit light.
  • the voltage of the first node is set and adjusted during the displayed field blanking phase.
  • a voltage of the third control signal input terminal is less than a sum of a voltage of the first voltage input terminal and a turn-on voltage of the illuminating sub-circuit
  • the reference voltage input by the data signal input terminal is greater than the sum of the voltage of the third control signal input terminal and the threshold voltage of the fourth transistor.
  • the pixel circuit includes a reset sub-circuit, a charge sub-circuit and a drive sub-circuit, a light-emitting sub-circuit, a first capacitor, and a second capacitor. Since the illuminating sub-circuit in the pixel circuit emits light, the driving current is only related to the reference voltage and the display data input from the data signal input terminal, thereby avoiding the phenomenon that the pixel brightness is uneven, and eliminating the influence of the power line voltage drop on the display brightness.
  • FIG. 1 is a block diagram showing the structure of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a pixel circuit in accordance with one embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of signal waveforms in accordance with one embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of signal waveforms in accordance with one embodiment of the present disclosure
  • FIG. 5 illustrates an equivalent diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 6 shows an equivalent diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 7 shows an equivalent diagram of a pixel circuit in accordance with one embodiment of the present disclosure
  • FIG. 8 shows an equivalent diagram of a pixel circuit in accordance with one embodiment of the present disclosure.
  • the pixel circuit includes a reset sub-circuit 101, a charging sub-circuit 102, a driving sub-circuit 103, a illuminating sub-circuit 104, a first capacitor C1, and a second capacitor C2.
  • the illuminating sub-circuit 104 is connected to the first node J1 and the first voltage input terminal VSS, respectively. Both ends of the first capacitor C1 are respectively connected to the first node J1 and the first voltage input terminal VSS. Both ends of the second capacitor C2 are connected to the first node J1 and the second node J2, respectively.
  • the reset sub-circuit 101 is connected to the first node J1, the reset signal input terminal Reset and the third control signal input terminal Vini, respectively, and is configured to set the voltage of the first node J1 according to the reset signal.
  • the charging sub-circuit 102 is respectively connected to the second node J2, the scan signal input terminal Gn, the data signal input terminal Vdata and the first control signal input terminal Wth, and is configured to be the first capacitor according to the scan signal, the data signal and the first control signal. C1 and the second capacitor C2 are charged to adjust the voltage of the first node J1 and store the display data.
  • the driving sub-circuit 103 is connected to the first node J1, the second node J2, the second control signal input terminal EM and the second voltage input terminal VDD, respectively, and is configured to input a driving current to the illuminating sub-circuit 104 according to the second control signal, to The driving sub-circuit 104 is illuminated.
  • the illuminating sub-circuit 104 can be an OLED tube.
  • FIG. 2 shows a schematic structural diagram of a pixel circuit in accordance with one embodiment of the present disclosure.
  • the reset sub-circuit 101 includes a first transistor T1, and the control electrode of the first transistor T1 is connected to the reset signal input terminal Reset, the first electrode of the first transistor T1 is connected to the first node J1, and the second electrode of the first transistor T1 is connected to the third electrode. Control signal input terminal Vini.
  • the charging sub-circuit 102 includes a second transistor T2 and a third transistor T3.
  • the control electrode of the second transistor T2 is connected to the scan signal input terminal Gn, the first electrode of the second transistor T2 is connected to the data signal input terminal Vdata, and the second electrode of the second transistor T2 is connected to the second node J2.
  • the control electrode of the third transistor T3 is connected to the first control signal input terminal Wth, the first electrode of the third transistor T3 is connected to the data signal input terminal Vdata, and the second electrode of the third transistor T3 is connected to the second node J2.
  • the driving sub-circuit 103 includes a fourth transistor T4 and a fifth transistor T5.
  • the control electrode of the fourth transistor T4 is connected to the second node J2, the first electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5, and the second electrode of the fourth transistor T4 is connected to the first node J1.
  • the control electrode of the fifth transistor T5 is connected to the second control signal input terminal EM, the first electrode of the fifth transistor T5 is connected to the second voltage input terminal VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the fourth transistor T4.
  • the transistors are all NMOS transistors.
  • a PMOS transistor is used to form a pixel circuit.
  • a negative voltage needs to be applied to the PMOS transistor, so that a large number of holes are accumulated at the interface between the semiconductor and the oxide layer, and holes are tunneled into the trap at the interface of the oxide layer.
  • the threshold voltage of the drive transistor drifts. Since the mobility of holes is low, holes falling in traps are difficult to pull out traps even when a positive voltage is applied.
  • an NMOS transistor is employed. Since the carriers are electrons, the electrons falling in the trap are relatively easily pulled out of the trap, which is advantageous for recovery of the threshold voltage.
  • Embodiments of the present disclosure also provide a display panel including the pixel circuit as described above.
  • the pixel circuit array is arranged to form a display panel.
  • Embodiments of the present disclosure also provide a display device including a driving chip and a display panel as described above.
  • the driving chip is connected to a pixel circuit in the display panel, and the pixel circuit drives the display panel to display an image according to an input signal of the driving chip.
  • Embodiments of the present disclosure provide a driving method for driving a pixel circuit as described above.
  • the illuminating sub-circuit in the pixel circuit emits light in a period of a display frame, and includes a non-emission phase and an illuminating phase in a period of one frame.
  • FIG. 3 shows a schematic diagram of signal waveforms in accordance with an embodiment of the present disclosure.
  • t0 phase of the non-lighting phase ie, the reset phase
  • a high level signal is input to the reset signal input terminal Reset
  • low voltage is input to the first control signal input terminal Wth, the second control signal input terminal EM, and the scan signal input terminal Gn.
  • Flat signal In the t0 phase of the non-lighting phase (ie, the reset phase), a high level signal is input to the reset signal input terminal Reset, and low voltage is input to the first control signal input terminal Wth, the second control signal input terminal EM, and the scan signal input terminal Gn.
  • the reset sub-circuit 101 sets the voltage of the first node J1 to the first voltage V1 in accordance with the high level
  • a high level signal is input to the reset signal input terminal Reset, and a low level signal is input to the first control signal input terminal Wth, the second control signal input terminal EM, and the scan signal input terminal Gn, and the first transistor T1 is turned on.
  • the second transistor T2, the third transistor T3, and the fifth transistor T5 are all turned off.
  • the voltage of the third control signal input terminal Vini is used to charge the first capacitor C1, and the voltage of the first node J1 is set to the first voltage, and the first voltage is the third control. The voltage at the signal input terminal Vini.
  • the voltage of the third control signal input terminal Vini is smaller than the sum of the voltage of the first voltage input terminal VSS and the conduction voltage of the illuminating sub-circuit 104, thereby ensuring that the voltage of the third control signal input terminal Vini is the first capacitor C1.
  • the OLED is not illuminated in the non-lighting phase, thereby improving the contrast of the display panel.
  • a high level signal is input to the first control signal input terminal Wth and the second control input signal terminal EM, and is input to the scan signal input terminal Gn and the reset signal.
  • the terminal Reset inputs a low level signal, the charging subcircuit 102 sets the voltage of the second node J2, and adjusts the voltage of the first node J1 to the second voltage V2.
  • a high level signal is input to the first control signal input terminal Wth and the second control signal input terminal EM, and a low level signal is input to the scan signal input terminal Gn and the reset signal input terminal Reset, and the third transistor T3 and the The five transistors T5 are both turned on, and the first transistor T1 and the second transistor T2 are turned off.
  • the data signal input terminal Vdata is input with a reference voltage Vref, and the voltage of the second node J2 is set.
  • the reference voltage Vref is greater than the voltage of the third control signal input terminal Vini and the fourth transistor T4.
  • the fourth transistor T4 is turned on to charge the first capacitor C1, and the voltage of the first node J1 is adjusted to the second voltage V2.
  • the above setting and adjusting the voltage of the first node J1 is completed in the field blanking phase of the display. Specifically, after scanning one frame of image, the scanning point returns from the lower right corner of the image to the upper left corner of the image to start scanning of a new frame, and the return time interval is the field blanking (V-Blank) phase.
  • DE and ref are signals of an input driving chip
  • DE-ref is an internal signal of a driving chip
  • Vdata, EM, Reset, Wth, G1, etc. is a signal for inputting a display panel to the driving chip, and the display panel is formed by a pixel circuit array arrangement.
  • V-Blank is the field blanking phase of the display
  • H-Blank is the line blanking phase of the display.
  • the OLEDs on the display panel are reset and Vth established in the field blanking phase. Before the OLED emits light, the voltage of the first node in each pixel circuit is set and adjusted.
  • the OLED After entering the illumination stage, the OLED can simultaneously emit light according to the driving signal to realize image display. Compared with the voltage of the next row in the prior art, the embodiment of the present disclosure first completes the voltage setting of all the OLEDs in the field blanking phase, which can save the scanning time.
  • a high level signal is input to the scan signal input terminal Gn to the first control signal input terminal Wth, the second control signal input terminal EM, and the reset signal.
  • the input terminal Reset inputs a low level signal, and the charging sub-circuit 102 charges the first capacitor C1 and the second capacitor C2 to store display data input by the data signal input terminal Vdata.
  • a high level signal is input to the scan signal input terminal Gn, and a low level signal is input to the first control signal input terminal Wth, the second control signal input terminal EM, and the reset signal input terminal Reset, and the second transistor T2 is turned on.
  • the first transistor T1, the third transistor T3, and the fifth transistor T5 are all turned off.
  • the data signal input terminal Vdata inputs display data to charge the first capacitor C1 and the second capacitor C2. Since the first node J1 has no inflow and outflow of electric charge when the display data is input, the electric charge Q2 of the first node J1 is Q1. Let the voltage of the first node J1 be V3 at this time, then
  • V3 (C2 ⁇ Vdata + C1 ⁇ Vref) / (C1 + C2) - Vth.
  • a high level signal is input to the second control signal input terminal EM, and a low level signal is input to the first control signal input terminal Wth, the scan signal input terminal Gn, and the reset signal input terminal Reset.
  • the circuit 103 inputs a drive current to the illuminating sub-circuit 104 to drive the illuminating sub-circuit 104 to emit light.
  • a high level signal is input to the second control signal input terminal EM, and a low level signal is input to the first control signal input terminal Wth, the scan signal input terminal Gn and the reset signal input terminal Reset, and the fifth transistor T5 is turned on.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all turned off.
  • the first node J1 outputs a driving current to drive the illuminating sub-circuit 104 to emit light.
  • the turn-on voltage of the fourth transistor T4 is V G , then
  • the driving current output by the fourth transistor T4 is I, then
  • the driving current I is only related to the display data Vdata and the reference voltage Vref input by the data signal input terminal, and is independent of the driving voltage VDD of the second voltage input terminal and the threshold voltage Vth of the fourth transistor, thereby realizing the driving voltage and
  • the effect of threshold voltage compensation eliminates the effects of hourglass and power supply voltage drop.
  • the pixel circuit includes a reset sub-circuit, a charge sub-circuit, a drive sub-circuit, a light-emitting sub-circuit, a first capacitor, and a second capacitor. Since the illuminating sub-circuit in the pixel circuit emits light, the driving current is only related to the reference voltage and the display data input at the input end of the data signal, thereby avoiding the unevenness of the pixel brightness and eliminating the influence of the power line voltage drop on the display brightness.

Abstract

本公开提供了一种像素电路及其驱动方法、显示面板和显示装置。所述像素电路包括：复位子电路、充电子电路、驱动子电路、发光子电路以及第一电容和第二电容。所述发光子电路分别连接第一节点和第一电压输入端；所述第一电容的两端分别连接所述第一节点和所述第一电压输入端；所述第二电容的两端分别连接所述第一节点和第二节点；所述复位子电路分别连接所述第一节点、复位信号输入端和第三控制信号输入端；所述充电子电路分别连接所述第二节点、扫描信号输入端、数据信号输入端和第一控制信号输入端；所述驱动子电路分别连接所述第一节点、所述第二节点、第二控制信号输入端和第二电压输入端。

Description

像素电路及其驱动方法、显示面板和显示装置
相关申请
本申请要求享有2018年4月28日提交的中国发明专利申请No.201810404476.X的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，特别是涉及一种像素电路及其驱动方法、显示面板和显示装置。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管)像素电路的驱动原理是将OLED连接到驱动晶体管的一个电极上，驱动晶体管的另一个电极连接驱动电压，驱动晶体管的栅极通过开关晶体管连接数据线。驱动晶体管输入到OLED的驱动电流，与驱动晶体管的阈值电压和驱动电压存在二次方的关系。通过驱动晶体管将输入电压转换成电流，驱动OLED发光。根据驱动晶体管的转移曲线，驱动电流的大小和它的阈值电压相关。当相邻两个像素的驱动晶体管的阈值电压出现较大差异时，比如超过0.1V的差异，引起驱动电流产生偏差而导致这两个像素之间出现亮度差异。当观察者的眼睛能感觉到这种亮度差异时，显示画面就出现沙漏现象。同时，由于OLED像素的驱动电路是电流器件，并且电源引线上存在电阻，因此像素的亮度会沿着电源引线的长度出现变化，也就是出现电源压降的现象。
发明内容
本公开提供一种像素电路及其驱动方法、显示面板和显示装置。
本公开实施例提供了一种像素电路，包括复位子电路、充电子电路、驱动子电路、发光子电路、第一电容和第二电容；
所述发光子电路分别连接第一节点和第一电压输入端；
所述第一电容的两端分别连接所述第一节点和所述第一电压输入端；
所述第二电容的两端分别连接所述第一节点和第二节点；
所述复位子电路分别连接所述第一节点、复位信号输入端和第三控制信号输入端，并且被配置为根据复位信号设置所述第一节点的电压；
所述充电子电路分别连接所述第二节点、扫描信号输入端、数据信号输入端和第一控制信号输入端，并且被配置为根据扫描信号、数据信号和第一控制信号为所述第一电容和所述第二电容充电，以调整所述第一节点的电压并存储显示数据；并且
所述驱动子电路分别连接所述第一节点、所述第二节点、第二控制信号输入端和第二电压输入端，并且被配置为根据第二控制信号向所述发光子电路输入驱动电流，以驱动所述发光子电路发光。
在一个实施例中，所述复位子电路包括第一晶体管，并且所述第一晶体管的控制极连接所述复位信号输入端，所述第一晶体管的第一极连接所述第一节点，所述第一晶体管的第二极连接所述第三控制信号输入端。
在一个实施例中，所述充电子电路包括第二晶体管和第三晶体管；
所述第二晶体管的控制极连接所述扫描信号输入端，所述第二晶体管的第一极连接所述数据信号输入端，所述第二晶体管的第二极连接所述第二节点；并且
所述第三晶体管的控制极连接所述第一控制信号输入端，所述第三晶体管的第一极连接所述数据信号输入端，所述第三晶体管的第二极连接所述第二节点。
在一个实施例中，所述驱动子电路包括第四晶体管和第五晶体管；
所述第四晶体管的控制极连接所述第二节点，所述第四晶体管的第一极连接所述第五晶体管的第二极，所述第四晶体管的第二极连接所述第一节点；并且
所述第五晶体管的控制极连接所述第二控制信号输入端，所述第五晶体管的第一极连接第二电压输入端，所述第五晶体管的第二极连接所述第四晶体管T4的第一极。
在一个实施例中，所述晶体管均为NMOS管。
本公开实施例提供了一种显示面板，包括如上所述的像素电路。
本公开实施例提供了一种显示装置，包括驱动芯片和如上所述的显示面板，其中所述驱动芯片连接所述显示面板中的像素电路；并且 所述像素电路根据所述驱动芯片的输入信号驱动所述显示面板显示图像。
本公开实施例提供了一种驱动方法，用于驱动如上所述的像素电路，所述驱动方法包括：
在复位阶段，向所述复位信号输入端输入高电平信号，向所述第一控制信号输入端、所述第二控制信号输入端和所述扫描信号输入端输入低电平信号，所述复位子电路根据所述高电平信号将所述第一节点的电压设置为第一电压；
在阈值电压建立阶段，向所述第一控制信号输入端和所述第二控制信号输入端输入高电平信号，向所述扫描信号输入端和所述复位信号输入端输入低电平信号，所述充电子电路设置第二节点的电压，并将所述第一节点的电压调整为第二电压；
在数据扫描输入阶段，向所述扫描信号输入端输入高电平信号，向所述第一控制信号输入端、所述第二控制信号输入端和所述复位信号输入端输入低电平信号，所述充电子电路向所述第一电容和所述第二电容充电，以存储所述数据信号输入端输入的显示数据；以及
在发光阶段，向所述第二控制信号输入端输入高电平信号，向所述第一控制信号输入端、所述扫描信号输入端和所述复位信号输入端输入低电平信号，所述驱动子电路向所述发光子电路输入驱动电流，以驱动所述发光子电路发光。
在一个实施例中，在显示的场消隐阶段设置并调整所述第一节点的电压。
在一个实施例中，设置所述第一节点的电压时，所述第三控制信号输入端的电压小于所述第一电压输入端的电压与所述发光子电路的导通电压之和；并且
设置所述第二节点的电压时，所述数据信号输入端输入的参考电压大于所述第三控制信号输入端的电压与所述第四晶体管的阈值电压之和。
在本公开的实施例中，像素电路包括复位子电路、充电子电路和驱动子电路、发光子电路、第一电容和第二电容。由于像素电路中发光子电路发光时，驱动电流只与数据信号输入端输入的参考电压和显示数据相关，因此可以避免像素亮度不均匀的现象，并消除电源线压 降对显示亮度的影响。
附图说明
图1示出了根据本公开的一个实施例的像素电路的结构示意图；
图2示出了根据本公开的一个实施例的像素电路的结构示意图；
图3示出了根据本公开的一个实施例的信号波形的示意图；
图4示出了根据本公开的一个实施例的信号波形的示意图；
图5示出了根据本公开的一个实施例的像素电路的等效图；
图6示出了根据本公开的一个实施例的像素电路的等效图；
图7示出了根据本公开的一个实施例的像素电路的等效图；
图8示出了根据本公开的一个实施例的像素电路的等效图。
具体实施方式
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本公开的实施例作进一步详细的说明。
参照图1，示出了根据本公开的一个实施例的像素电路的结构示意图。所述像素电路包括：复位子电路101、充电子电路102、驱动子电路103、发光子电路104、第一电容C1和第二电容C2。
发光子电路104分别连接第一节点J1和第一电压输入端VSS。第一电容C1的两端分别连接第一节点J1和第一电压输入端VSS。第二电容C2的两端分别连接第一节点J1和第二节点J2。复位子电路101分别连接第一节点J1、复位信号输入端Reset和第三控制信号输入端Vini，并且被配置为根据复位信号设置所述第一节点J1的电压。充电子电路102分别连接第二节点J2、扫描信号输入端Gn、数据信号输入端Vdata和第一控制信号输入端Wth，并且被配置为根据扫描信号、数据信号和第一控制信号为第一电容C1和第二电容C2充电，以调整第一节点J1的电压并存储显示数据。驱动子电路103分别连接第一节点J1、第二节点J2、第二控制信号输入端EM和第二电压输入端VDD，并且被配置为根据第二控制信号向发光子电路104输入驱动电流，以驱动发光子电路104发光。
在本实施例中，发光子电路104可以是OLED管。
图2示出了根据本公开的一个实施例的像素电路的结构示意图。
复位子电路101包括第一晶体管T1，并且第一晶体管T1的控制极连接复位信号输入端Reset，第一晶体管T1的第一极连接第一节点J1，第一晶体管T1的第二极连接第三控制信号输入端Vini。
充电子电路102包括第二晶体管T2和第三晶体管T3。第二晶体管T2的控制极连接扫描信号输入端Gn，第二晶体管T2的第一极连接数据信号输入端Vdata，第二晶体管T2的第二极连接第二节点J2。第三晶体管T3的控制极连接第一控制信号输入端Wth，第三晶体管T3的第一极连接数据信号输入端Vdata，第三晶体管T3的第二极连接第二节点J2。
驱动子电路103包括第四晶体管T4和第五晶体管T5。第四晶体管T4的控制极连接第二节点J2，第四晶体管T4的第一极连接第五晶体管T5的第二极，第四晶体管T4的第二极连接第一节点J1。第五晶体管T5的控制极连接第二控制信号输入端EM，第五晶体管T5的第一极连接第二电压输入端VDD，第五晶体管T5的第二极连接第四晶体管T4的第一极。
在本公开的一种优选实施例中，晶体管均为NMOS管。
采用PMOS管组成像素电路，为让驱动晶体管长期导通，需要对PMOS管施加负电压，使得半导体和氧化层的界面堆积大量空穴，空穴会隧穿到氧化层界面的陷阱中。随着越来越多的空穴隧穿到氧化层中陷阱里，驱动晶体管的阈值电压就会发生漂移。由于空穴的迁移率低，掉在陷阱中的空穴即使在施加正电压下也很难拉出陷阱。在本公开的一种优选实施例中采用NMOS管，由于载流子是电子，掉在陷阱中的电子相比较容易被拉出陷阱，有利于阈值电压的恢复。
本公开实施例还提供了一种显示面板，包括如上所述的像素电路。
本实施例中，像素电路阵列排布形成显示面板。
本公开实施例还提供了一种显示装置，包括驱动芯片和如上所述的显示面板。所述驱动芯片连接所述显示面板中的像素电路，并且所述像素电路根据所述驱动芯片的输入信号驱动显示面板显示图像。
本公开实施例提供了一种驱动方法，用于驱动如上所述的像素电路。
像素电路中的发光子电路是以显示帧为周期发光的，在一帧的周期内包括非发光阶段和发光阶段。图3示出了根据本公开的一个实施 例的信号波形的示意图。在非发光阶段的t0阶段(即复位阶段)，向复位信号输入端Reset输入高电平信号，向第一控制信号输入端Wth、第二控制信号输入端EM和扫描信号输入端Gn输入低电平信号。复位子电路101根据所述高电平信号将第一节点J1的电压设置为第一电压V1。
在t0阶段，向复位信号输入端Reset输入高电平信号，向第一控制信号输入端Wth、第二控制信号输入端EM和扫描信号输入端Gn输入低电平信号，第一晶体管T1导通，第二晶体管T2、第三晶体管T3、第五晶体管T5均截止。参见图5所示的像素电路的等效图，利用第三控制信号输入端Vini的电压为第一电容C1充电，将第一节点J1的电压设置为第一电压，第一电压为第三控制信号输入端Vini的电压。此时，第三控制信号输入端Vini的电压小于第一电压输入端VSS的电压与发光子电路104的导通电压之和，从而可以确保第三控制信号输入端Vini的电压为第一电容C1充电后，不会使OLED在非发光阶段发光，进而提高显示面板的对比度。
参照图3，在非发光阶段的t1阶段(即Vth建立阶段)，向第一控制信号输入端Wth和第二控制输入信号端EM输入高电平信号，向扫描信号输入端Gn和复位信号输入端Reset输入低电平信号，充电子电路102设置第二节点J2的电压，并将第一节点J1的电压调整为第二电压V2。
在t1阶段，向第一控制信号输入端Wth和第二控制信号输入端EM输入高电平信号，向扫描信号输入端Gn和复位信号输入端Reset输入低电平信号，第三晶体管T3和第五晶体管T5均导通，第一晶体管T1和第二晶体管T2截止。参见图6所示的像素电路的等效图，数据信号输入端Vdata输入参考电压Vref，设置第二节点J2的电压，参考电压Vref大于第三控制信号输入端Vini的电压与第四晶体管T4的阈值电压Vth之和，第四晶体管T4导通向第一电容C1充电，将第一节点J1的电压调整为第二电压V2。当第一节点J1的电压上升到Vref-Vth时，第四晶体管T4截止，第二节点J2的电压与Vref相等，第一节点J1的电荷为Q1＝C1×(V2-VSS)-C2×Vth＝C1×(Vref-Vth-VSS)-C2×Vth。
上述设置并调整第一节点J1的电压是在显示的场消隐阶段完成的。具体地，在扫描完一帧图像后，扫描点从图像的右下角返回到图 像的左上角，开始新一帧的扫描，返回的时间间隔就是场消隐(V-Blank)阶段。
图4示出了根据本公开的一个实施例的信号波形的示意图，其中DE和Data为输入驱动芯片的信号，DE-ref为驱动芯片的内部信号，Vdata、EM、Reset、Wth、G1......Gn为驱动芯片输入显示面板的信号，显示面板由像素电路阵列排布形成。V-Blank为显示的场消隐阶段，H-Blank为显示的行消隐阶段。显示面板上的OLED均在场消隐阶段进行复位和Vth建立。在OLED发光前，各像素电路中第一节点的电压均已设置并调整完毕。在进入发光阶段后，OLED可以根据驱动信号同时发光，实现图像显示。与现有技术中上一行OLED发光后设置下一行的电压相比，本公开实施例首先在场消隐阶段完成全部OLED的电压设置，这样可以节省扫描时间。
参照图3，在非发光阶段的tn阶段(即数据扫描输入阶段)，向扫描信号输入端Gn输入高电平信号，向第一控制信号输入端Wth、第二控制信号输入端EM和复位信号输入端Reset输入低电平信号，充电子电路102向第一电容C1和第二电容C2充电，以存储所述数据信号输入端Vdata输入的显示数据。
在tn阶段，向扫描信号输入端Gn输入高电平信号，向第一控制信号输入端Wth、第二控制信号输入端EM和复位信号输入端Reset输入低电平信号，第二晶体管T2导通，第一晶体管T1、第三晶体管T3、第五晶体T5均截止。参见图7所示的像素电路的等效图，数据信号输入端Vdata输入显示数据，向第一电容C1和第二电容C2充电。由于输入显示数据时，第一节点J1没有电荷的流入流出，所以第一节点J1的电荷Q2＝Q1。设此时第一节点J1的电压为V3，则
C1×(V3-VSS)-C2×(Vdata-V3)＝C1×(Vref-Vth-VSS)-C2×Vth，
(C1+C2)×V3＝C2×Vdata+C1×Vref-(C1+C2)×Vth，
则V3＝(C2×Vdata+C1×Vref)/(C1+C2)-Vth。
参照图3，在发光阶段，向第二控制信号输入端EM输入高电平信号，向第一控制信号输入端Wth、扫描信号输入端Gn和复位信号输入端Reset输入低电平信号，驱动子电路103向发光子电路104输入驱动电流驱动所述发光子电路104发光。
在发光阶段，向第二控制信号输入端EM输入高电平信号，向第 一控制信号输入端Wth、扫描信号输入端Gn和复位信号输入端Reset输入低电平信号，第五晶体管T5导通，第一晶体管T1、第二晶体管T2和第三晶体管T3均截止。参见图8所示的像素电路的等效图，第一节点J1输出驱动电流，以驱动发光子电路104发光。第四晶体管T4的导通电压为V G，则
V G＝V J2-V J1＝V J2-V3＝Vdata-(C2×Vdata+C1×Vref)/(C1+C2)+Vth
＝C1/(C1+C2)×(Vdata-Vref)+Vth
第四晶体管T4输出的驱动电流为I，则
I＝(1/2)×μ×C OX×(W/L)×(V G-Vth) 2
＝μC OXW[C1(Vdata-Vref)/(C1+C2)] 2/(2L)
由此可见，驱动电流I只与数据信号输入端输入的显示数据Vdata和参考电压Vref相关，而与第二电压输入端的驱动电压VDD和第四晶体管的阈值电压Vth无关，实现了对驱动电压和阈值电压补偿的效果，从而消除了沙漏现象和电源压降效应。
综上所述，在根据本公开的实施例中，像素电路包括复位子电路、充电子电路、驱动子电路、发光子电路、第一电容和第二电容。由于像素电路中发光子电路发光时，驱动电流只与数据信号输入端输入的参考电压和显示数据相关，因此可以避免像素亮度的不均匀现象，并消除电源线压降对显示亮度的影响。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参照即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本公开所提供的像素电路及其驱动方法、显示面板和显示装置，进行了详细介绍，本文中采用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的技术方案及其核心思想；同时，对于本领域的一般技术人员而言，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。

Claims (10)

  1. 一种像素电路，包括复位子电路、充电子电路、驱动子电路、发光子电路、第一电容和第二电容；
    所述发光子电路分别连接第一节点和第一电压输入端；
    所述第一电容的两端分别连接所述第一节点和所述第一电压输入端；
    所述第二电容的两端分别连接所述第一节点和第二节点；
    所述复位子电路分别连接所述第一节点、复位信号输入端和第三控制信号输入端，并且被配置为根据复位信号设置所述第一节点的电压；
    所述充电子电路分别连接所述第二节点、扫描信号输入端、数据信号输入端和第一控制信号输入端，并且被配置为根据扫描信号、数据信号和第一控制信号为所述第一电容和所述第二电容充电，以调整所述第一节点的电压并存储显示数据；并且
    所述驱动子电路分别连接所述第一节点、所述第二节点、第二控制信号输入端和第二电压输入端，并且被配置为根据第二控制信号向所述发光子电路输入驱动电流，以驱动所述发光子电路发光。
  2. 根据权利要求1所述的像素电路，其中，所述复位子电路包括第一晶体管，并且所述第一晶体管的控制极连接所述复位信号输入端，所述第一晶体管的第一极连接所述第一节点，所述第一晶体管的第二极连接所述第三控制信号输入端。
  3. 根据权利要求1所述的像素电路，其中，所述充电子电路包括第二晶体管和第三晶体管；
    所述第二晶体管的控制极连接所述扫描信号输入端，所述第二晶体管的第一极连接所述数据信号输入端，所述第二晶体管的第二极连接所述第二节点；并且
    所述第三晶体管的控制极连接所述第一控制信号输入端，所述第三晶体管的第一极连接所述数据信号输入端，所述第三晶体管的第二极连接所述第二节点。
  4. 根据权利要求1所述的像素电路，其中，所述驱动子电路包括第四晶体管和第五晶体管；
    所述第四晶体管的控制极连接所述第二节点，所述第四晶体管的第一极连接所述第五晶体管的第二极，所述第四晶体管的第二极连接所述第一节点；并且
    所述第五晶体管的控制极连接所述第二控制信号输入端，所述第五晶体管的第一极连接第二电压输入端，所述第五晶体管的第二极连接所述第四晶体管T4的第一极。
  5. 根据权利要求1-4中任一项所述的像素电路，其中，所述晶体管均为NMOS管。
  6. 一种显示面板，包括根据权利要求1-4中任一项所述的像素电路。
  7. 一种显示装置，包括驱动芯片和根据权利要求6所述的显示面板，其中
    所述驱动芯片连接所述显示面板中的像素电路；并且
    所述像素电路根据所述驱动芯片的输入信号驱动所述显示面板显示图像。
  8. 一种像素电路的驱动方法，所述像素电路包括复位子电路、充电子电路、驱动子电路、发光子电路、第一电容和第二电容；
    所述发光子电路分别连接第一节点和第一电压输入端；
    所述第一电容的两端分别连接所述第一节点和所述第一电压输入端；
    所述第二电容的两端分别连接所述第一节点和第二节点；
    所述复位子电路分别连接所述第一节点、复位信号输入端和第三控制信号输入端，并且被配置为根据复位信号设置所述第一节点的电压；
    所述充电子电路分别连接所述第二节点、扫描信号输入端、数据信号输入端和第一控制信号输入端，并且被配置为根据扫描信号、数据信号和第一控制信号为所述第一电容和所述第二电容充电，以调整所述第一节点的电压并存储显示数据；并且
    所述驱动子电路分别连接所述第一节点、所述第二节点、第二控制信号输入端和第二电压输入端，并且被配置为根据第二控制信号向所述发光子电路输入驱动电流，以驱动所述发光子电路发光，
    所述驱动方法包括：
    在复位阶段，向所述复位信号输入端输入高电平信号，向所述第一控制信号输入端、所述第二控制信号输入端和所述扫描信号输入端输入低电平信号，所述复位子电路根据所述高电平信号将所述第一节点的电压设置为第一电压；
    在阈值电压建立阶段，向所述第一控制信号输入端和所述第二控制信号输入端输入高电平信号，向所述扫描信号输入端和所述复位信号输入端输入低电平信号，所述充电子电路设置第二节点的电压，并将所述第一节点的电压调整为第二电压；
    在数据扫描输入阶段，向所述扫描信号输入端输入高电平信号，向所述第一控制信号输入端、所述第二控制信号输入端和所述复位信号输入端输入低电平信号，所述充电子电路向所述第一电容和所述第二电容充电，以存储所述数据信号输入端输入的显示数据；以及
    在发光阶段，向所述第二控制信号输入端输入高电平信号，向所述第一控制信号输入端、所述扫描信号输入端和所述复位信号输入端输入低电平信号，所述驱动子电路向所述发光子电路输入驱动电流，以驱动所述发光子电路发光。
  9. 根据权利要求8所述的方法，其中，在显示的场消隐阶段设置并调整所述第一节点的电压。
  10. 根据权利要求8所述的方法，其中，设置所述第一节点的电压时，所述第三控制信号输入端的电压小于所述第一电压输入端的电压与所述发光子电路的导通电压之和；并且
    设置所述第二节点的电压时，所述数据信号输入端输入的参考电压大于所述第三控制信号输入端的电压与所述第四晶体管的阈值电压之和。
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