WO2019191895A1

WO2019191895A1 - Phase-locked loop and terminal device

Info

Publication number: WO2019191895A1
Application number: PCT/CN2018/081728
Authority: WO
Inventors: 易律凡
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2018-04-03
Filing date: 2018-04-03
Publication date: 2019-10-10
Also published as: CN110612666A; CN110612666B

Abstract

Provided are a phase-locked loop and a terminal device. The phase-locked loop comprises: a phase detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator. The phase detector is connected to the low-pass filter by means of the charge pump. The low-pass filter is connected to the voltage-controlled oscillator. The charge pump comprises multiple charging circuits and/or multiple discharging circuits, and is used for powering on, according to a first control signal output by the phase detector and a control voltage output by the low-pass filter, one of the multiple charging circuit or one of the multiple discharging circuits, and charging/discharging the low-pass filter by means of the one discharging circuit or the first discharging circuit. That is, the charge pump powers on, on the basis of a control voltage, the one charging circuit or the one discharging circuit so that the absolute value of the difference between a charging current and a discharging current is less than a preset threshold when the low-pass filter is charged/discharged by means of the one charging circuit and the one discharging circuit, respectively.

Description

Phase-locked loop and terminal equipment

Technical field

Embodiments of the present application relate to the field of electronic technologies, and more particularly, to a phase locked loop and a terminal device.

Background technique

Phase Locked Loop (PLL) is widely used in electronic devices. The PLL of the ring oscillator structure uses the control voltage of the output of the charge pump (CHP) to lock the range of its output signal.

Specifically, referring to FIG. 1 , the phase locked loop generally includes a first frequency divider 100, a Frequency Phase Detector (PFD) 200, a charge pump (CHP) 300, and a low pass filter (Low-pass filter). , LPF) 600 and a Voltage Controlled Oscillator (VCO) 400, a third frequency divider 500, and a second frequency divider 700, the second frequency divider 700 constitutes a frequency phase feedback path. The working principle of the phase locked loop is that the PFD 200 detects the phase difference between the output signal of the first frequency divider 100 and the output signal of the VCO 400, and converts the detected phase difference signal into a voltage signal output through the PFD 200, via the LPF. After 600 filtering, the control voltage of the VCO 400 is formed, the frequency of the VCO 400 output signal is controlled, and the frequency and phase of the VCO 400 output signal are fed back to the PFD 200 through the feedback path.

It can be found that the range of the control voltage (VCTRL) is affected by the power supply voltage of the charge pump. When the power supply voltage of the charge pump is relatively high, the range of the control voltage is relatively wide, which is less affected by the power supply voltage, but with the charge When the power supply voltage of the pump is lowered, when the power supply voltage of the charge pump is too low, the range of the control voltage is compressed to be small.

Therefore, there is an urgent need in the art for a circuit that can extend the range of control voltages of a phase locked loop.

Summary of the invention

A phase locked loop and terminal device are provided that are capable of extending the range of control voltages of the phase locked loop.

In a first aspect, a phase locked loop is provided, comprising:

Phase detector, charge pump, low pass filter and voltage controlled oscillator;

The phase detector is connected to the low pass filter by the charge pump, and the low pass filter is connected to the voltage controlled oscillator;

The charge pump includes a plurality of charging circuits and/or a plurality of discharging circuits;

The charge pump is configured to turn on one of the plurality of charging circuits according to a first control signal output by the phase detector and a control voltage output by the low pass filter, and pass the one The charging circuit charges the low pass filter, or the charge pump is configured to turn on one of the plurality of discharge circuits according to the first control signal and the control voltage, and pass The one discharge circuit discharges the low pass filter such that at the same control voltage, a charging current when the low pass filter is charged by the one charging circuit, and a discharge through the one discharge The absolute value of the difference between the discharge currents when the circuit discharges the low pass filter is less than a predetermined threshold.

Thereby, the charge pump can turn on one of the plurality of charging circuits based on the control voltage, or turn on one of the plurality of discharging circuits, so that the charging circuit is passed through the same charging voltage And charging and discharging the low-pass filter with the one discharge circuit, the absolute value of the difference between the charging current and the discharging current is less than a preset threshold.

In some possible implementations, the plurality of charging circuits include a first charging circuit, and the plurality of discharging circuits include a first discharging circuit;

a charging current for charging the low pass filter by the first charging circuit and the same by the first discharging circuit at the same control voltage within a range of a first threshold to a second threshold The absolute value of the difference between the discharge currents when the low-pass filter performs discharge is less than or equal to the preset threshold;

Wherein, the first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than a first threshold and less than a second threshold, the charge pump turns on the first charging circuit Or the first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than a first threshold and less than a second threshold, the charge pump turns on the first discharge Circuit.

In some possible implementations, the multiple charging circuits further include a second charging circuit;

Wherein, at the same control voltage greater than or equal to the second threshold, a charging current when the low pass filter is charged by the second charging circuit is greater than that of the first charging circuit a charging current when the low pass filter is being charged;

The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the second charging circuit.

In some possible implementations, the multiple charging circuits further include a third charging circuit;

Wherein, at the same control voltage less than or equal to the first threshold, a charging current when the low-pass filter is charged by the third charging circuit is smaller than that of the first charging circuit a charging current when the low pass filter is being charged;

The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the third charging circuit.

In some possible implementations, the first charging circuit includes:

a first metal oxide semiconductor MOS transistor, a first current mirror, a first switch, and a second switch;

The first current mirror includes a second MOS transistor and a third MOS transistor;

a source of the first MOS transistor is configured to receive an operating voltage, a gate of the first MOS transistor is configured to receive the first control signal, and a drain of the first MOS transistor is connected through the first switch To the source of the third MOS transistor;

a drain of the third MOS transistor is connected to the low pass filter;

a gate of the third MOS transistor is connected to a gate of the second MOS transistor through the second switch, and a source of the second MOS transistor is connected to a first current source;

Wherein the first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than the first threshold and less than the second threshold, the charge pump conducts the a first switch and the second switch.

In some possible implementations, the second charging circuit includes:

The first MOS transistor, the second current mirror, the third switch, and the fourth switch;

The second current mirror includes the second MOS transistor and the fourth MOS transistor;

a source of the first MOS transistor is configured to receive the operating voltage, a gate of the first MOS transistor is configured to receive the first control signal, and a drain of the first MOS transistor passes the third a switch connected to a source of the fourth MOS transistor;

a drain of the fourth MOS transistor is connected to the low pass filter;

a gate of the fourth MOS transistor is connected to a gate of the second MOS transistor through the fourth switch, and a source of the second MOS transistor is connected to the first current source;

The ratio of the channel length L of the fourth MOS transistor to the channel width W of the fourth MOS transistor is greater than the ratio of the L of the third MOS transistor to the W of the third MOS transistor;

The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the third switch and the first Four switches.

In some possible implementations, the fourth MOS transistor is a multi-stage cascaded MOS transistor.

In some possible implementations, the third charging circuit includes:

The first MOS transistor, the third current mirror, the fifth switch, and the sixth switch;

The third current mirror includes the second MOS transistor and the fifth MOS transistor;

a source of the first MOS transistor is configured to receive the operating voltage, a gate of the first MOS transistor is configured to receive the first control signal, and a drain of the first MOS transistor passes the fifth a switch connected to a source of the fifth MOS transistor;

a drain of the fifth MOS transistor is connected to the low pass filter;

a gate of the fifth MOS transistor is connected to a gate of the second MOS transistor through the sixth switch, and a source of the second MOS transistor is connected to the first current source;

The ratio of the channel length L of the fifth MOS transistor to the channel width W of the fifth MOS transistor is smaller than the ratio of the L of the third MOS transistor to the W of the third MOS transistor;

The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the fifth switch and the first Six switches.

In some possible implementations, the plurality of discharge circuits further includes a second discharge circuit;

Wherein, at the same control voltage greater than or equal to the second threshold, a discharge current when the low-pass filter is discharged by the second discharge circuit is smaller than that of the first discharge circuit a discharge current when the low pass filter is discharged;

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the second discharge circuit.

In some possible implementations, the plurality of discharge circuits further includes a third discharge circuit;

Wherein, in a case where the control voltage is less than or equal to the first threshold, a discharge current when the low-pass filter is discharged by the third discharge circuit is greater than that by the first discharge circuit a discharge current when the low pass filter is discharged;

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the third discharge circuit.

In some possible implementations, the first discharge circuit includes:

a sixth metal oxide semiconductor MOS transistor, a fourth current mirror, a seventh switch, and an eighth switch;

The fourth current mirror includes a seventh MOS transistor and an eighth MOS transistor;

a drain of the sixth MOS transistor is grounded, a gate of the sixth MOS transistor is configured to receive the first control signal, and a source of the sixth MOS transistor is connected to the first The drain of the eight MOS transistors;

a source of the eighth MOS transistor is connected to the low pass filter;

a gate of the eighth MOS transistor is connected to a gate of the seventh MOS transistor through the eighth switch, and a drain of the seventh MOS transistor is connected to a second current source;

Wherein, the first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than a first threshold and less than a second threshold, the charge pump turns on the seventh switch and The eighth switch.

In some possible implementations, the second discharge circuit includes:

The sixth MOS transistor, the fifth current mirror, the ninth switch, and the tenth switch;

The fifth current mirror includes the seventh MOS transistor and the ninth MOS transistor;

a drain of the sixth MOS transistor is grounded, a gate of the sixth MOS transistor is configured to receive the first control signal, and a source of the sixth MOS transistor is connected to the first The drain of the nine MOS tube;

a source of the ninth MOS transistor is connected to the low pass filter;

a gate of the ninth MOS transistor is connected to a gate of the seventh MOS transistor through the tenth switch, and a drain of the seventh MOS transistor is connected to the second current source;

The ratio of the channel width W of the ninth MOS transistor to the channel length L of the ninth MOS transistor is greater than the ratio of the W of the eighth MOS transistor to the L of the eighth MOS transistor;

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the ninth switch and the first Ten switches.

In some possible implementations, the third discharge circuit includes:

The sixth MOS transistor, the sixth current mirror, the eleventh switch and the twelfth switch;

The sixth current mirror includes the seventh MOS transistor and the tenth MOS transistor;

a drain of the sixth MOS transistor is grounded, a gate of the sixth MOS transistor is configured to receive the first control signal, and a source of the sixth MOS transistor is connected to the The drain of the tenth MOS transistor;

a source of the tenth MOS transistor is connected to the low pass filter;

a gate of the tenth MOS transistor is connected to a gate of the seventh MOS transistor through the twelfth switch, and a drain of the seventh MOS transistor is connected to the second current source;

The ratio of the channel width W of the tenth MOS transistor to the channel length L of the tenth MOS transistor is smaller than the ratio of the W of the eighth MOS transistor to the L of the eighth MOS transistor;

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the eleventh switch and the Twelfth switch.

In some possible implementations, the tenth MOS transistor is a multi-stage cascaded MOS transistor.

In some possible implementations, the phase locked loop further includes:

a control signal generating circuit, the control signal generating circuit is coupled to the low pass filter, the control signal generating circuit is configured to receive the control voltage, and generate a plurality of control signals based on the control voltage;

The plurality of control signals are configured to: when the first control signal controls the charge pump to charge the low pass filter, turn on the one charging circuit and turn off the plurality of charging circuits a charging circuit other than the charging circuit; the plurality of control signals are further configured to: when the first control signal controls the charge pump to discharge the low-pass filter, turn on the one discharging circuit and Discharging a discharge circuit other than the one of the plurality of discharge circuits.

In some possible implementations, the control signal generating circuit includes:

a first resistor, a second resistor, a first inverter, and a second inverter;

One end of the first resistor is for receiving the control voltage, the other end of the first resistor is connected to the ground through the second resistor, and the second resistor is further connected to the ground through the first inverter The second inverter, the control signal output by the first inverter and the control signal output by the second inverter are used to turn on or off a group of charge and discharge circuits, respectively.

In a second aspect, a terminal device is provided, including:

The first aspect and the phase locked loop described in any of the possible implementations of the first aspect.

DRAWINGS

1 is a schematic structural block diagram of a prior art phase locked loop.

2 is a schematic diagram of a prior art circuit consisting of a charge pump and a low pass filter.

Figure 3 is a schematic illustration of prior art current mismatch.

4 is a schematic diagram of a circuit composed of a charge pump and a low pass filter in accordance with an embodiment of the present invention.

Fig. 5 is a schematic diagram of a control signal generating circuit of an embodiment of the present invention.

6 is another schematic circuit diagram of a charge pump in combination with a low pass filter in accordance with an embodiment of the present invention.

Figure 7 is a schematic illustration of current mismatch after the common implementation of Figures 5 and 6 of the present invention.

detailed description

It should be understood that the phase locked loop of embodiments of the present invention may be suitable for use in a clock generation circuit of a portable electronic device or in a circuit for implementing frequency synthesis. In particular, the accuracy of the clock is not high, but the power supply voltage is required to be as low as possible.

In order to facilitate the understanding of the technical solutions of the embodiments of the present invention, the effective range of the output voltage of the existing charge pump is analyzed as follows:

Specifically, it consists of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). For example, "N-type" MOS (NMOS) tubes and "P-type" MOS (PMOS) tubes.

More specifically, as shown in FIG. 2, the charge pump circuit includes a charge pump 300 and a low pass filter 600.

The charge pump 300 includes: a charging circuit composed of a first PMOS transistor 101, a second PMOS transistor 102, and a third PMOS transistor 103, and a first NMOS transistor 104, a second NMOS transistor 105, and a third NMOS transistor 106. A discharge circuit composed of. Specifically, when the first signal (UP) received by the charge pump 300 controls the first PMOS transistor 101 to be turned on, the charge pump 300 charges the first capacitor 602 and the second capacitor 603 in the low pass filter 600. Charging is performed. When the second signal (DN) received by the charge pump 300 controls the first NMOS transistor 104 to be turned on, the charge pump 300 charges the first capacitor 602 and the second capacitor 603 in the low pass filter 600. Discharge. In the circuit shown in FIG. 2, the low pass filter 600 further includes a low pass filter resistor 601.

In the circuit shown in FIG. 2, when the control voltage (VCTRL) deviates from the center point, specifically, as shown in FIG. 3, such as when the control voltage is close to the ground potential (AVSS) (ie, less than Vout_min), due to the MOS tube With limited source-drain output resistance, the NMOS current will drop and the PMOS current will increase, which will cause a large mismatch between the charge (UP) current and the discharge (DOWN, DN) current. Similarly, when the control voltage is close to the charge pump supply voltage (AVDD) (ie, greater than Vout_max), the mismatch between the UP current and the DN current is also large. It can be seen that the effective range of the charge pump is between the minimum control voltage (Vout_min) and the maximum control voltage (Vout_max).

It should be understood that in the current mismatch diagram shown in FIG. 3, the control voltage is the output voltage of the charge pump (ie, VCTRL shown in FIG. 2), and the I _{pmos tube} is the PMOS tube current, which can be understood as the UP current or the charging current. The I _{nmos tube} is the NMOS tube current, which can understand the DOWN current or the discharge current. _Mismatch of I I I _NMOS _{PMOS tube} subtracting the _tube obtained.

In the embodiment of the present invention, a phase-locked loop with extremely low voltage and low power consumption is provided, and the purpose thereof is to expand the output range of the control voltage of the charge pump of the phase-locked loop in order to greatly reduce the power supply voltage.

Optionally, the phase locked loop in the embodiment of the present invention may include:

Phase detector, charge pump, low pass filter and voltage controlled oscillator;

The phase detector is connected to the low pass filter through the charge pump, and the low pass filter is connected to the voltage controlled oscillator;

The charge pump is configured to turn on a charging circuit of the plurality of charging circuits according to a first control signal output by the phase detector and a control voltage output by the low-pass filter, and pass the low charging circuit through the one charging circuit Charging, or the charge pump is configured to turn on one of the plurality of discharge circuits according to the first control signal and the control voltage, and pass the low-pass filter through the one discharge circuit Discharging is performed such that the difference between the charging current when the low-pass filter is charged by the one charging circuit and the discharging current when the low-pass filter is discharged by the one discharging circuit is performed under the same control voltage The absolute value of the value is less than the preset threshold.

Thereby, the charge pump can turn on one of the plurality of charging circuits or turn on one of the plurality of discharging circuits based on the control voltage, so that the same charging voltage passes through the one charging circuit and the When a discharge circuit charges and discharges the low pass filter, the absolute value of the difference between the charge current and the discharge current is less than a preset threshold.

It should be understood that the same control voltage can be any voltage between the ground voltage (AVSS) and the supply voltage (AVDD) of the charge pump.

Further, the plurality of charging circuits may include a first charging circuit, and the plurality of discharging circuits may include a first discharging circuit; wherein the first control voltage is passed through the first control voltage within a range of the first threshold to the second threshold The absolute value of the difference between the charging current of the charging circuit for charging the low-pass filter and the discharging current when the low-pass filter is discharged by the first discharging circuit is less than or equal to the preset threshold; In operation, the first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than the first threshold and less than the second threshold, the charge pump turns on the first charging circuit; or The charge pump turns on the first discharge circuit when a control signal controls the charge pump to discharge the low pass filter, and the control voltage is greater than the first threshold and less than the second threshold.

It should be understood that the first charging circuit and the first discharging circuit in the embodiment of the present invention are understood to be that the effective range of the first charging circuit and the first discharging circuit is between the first threshold and the second threshold. It can be understood that, in the embodiment of the present invention, by designing a charging circuit and a discharging circuit suitable for the frequency range except the first threshold to the second threshold interval in the charge pump, the charge pump is in a range as large as possible. When the charge pump charges and discharges the low-pass filter, the absolute value of the difference between the charging current and the discharging current is less than a preset threshold.

The phase-locked loop provided in the embodiment of the present invention expands the linear output range of the charge pump by extending the voltage of the low-voltage charge pump close to the power supply section and the output section close to the ground, thereby improving the ability to suppress temperature fluctuations and power fluctuations. .

4 and 6 are schematic views of a circuit composed of a charge pump and a low pass filter in accordance with an embodiment of the present invention. It should be understood that the control voltage (VCX) of the charge pump output shown in FIG. 4 and FIG. 6 is the control voltage (VCTRL) of the charge pump output shown in FIG. 2, and the following is the embodiment of the present invention with reference to FIG. 4 and FIG. A charging circuit and the first discharging circuit are described:

Referring to FIG. 4 and FIG. 6, the first charging circuit may include:

a first MOS transistor, a first current mirror, a first switch 233 and a second switch 231; the first current mirror includes a second MOS transistor 214 and a third MOS transistor 212; a source of the first MOS transistor 211 is configured to receive The operating voltage, the gate of the first MOS transistor 211 is configured to receive the first control signal, and the drain of the first MOS transistor 211 is connected to the source of the third MOS transistor 212 through the first switch 233; The drain of the third MOS transistor 212 is connected to the low pass filter; the gate of the third MOS transistor 212 is connected to the gate of the second MOS transistor 214 through the second switch 231, the source of the second MOS transistor 214 The pole is connected to the first current source.

Wherein, the first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than the first threshold and less than the second threshold, the charge pump turns on the first switch 233 and the second Switch 231.

Referring to FIG. 4 and FIG. 6, the first discharge circuit may include:

a sixth MOS transistor, a fourth current mirror, a seventh switch 234, and an eighth switch 232; the fourth current mirror includes a seventh MOS transistor 224 and an eighth MOS transistor 222; the drain of the sixth MOS transistor 221 is grounded, The gate of the sixth MOS transistor 221 is configured to receive the first control signal, and the source of the sixth MOS transistor 221 is connected to the drain of the eighth MOS transistor 222 through the seventh switch 234; the eighth MOS transistor 222 The source is connected to the low pass filter; the gate of the eighth MOS transistor 222 is connected to the gate of the seventh MOS transistor 224 through the eighth switch 232, and the drain and the second of the seventh MOS transistor 224 Current source connection.

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than the first threshold and less than the second threshold, the charge pump turns on the seventh switch 234 and the eighth switch 232. .

The implementation manner of extending the linear output range of the charge pump in the case where the control voltage in the embodiment of the present invention is greater than or equal to the second threshold (the low-voltage charge pump is close to the power supply section) is exemplified below with reference to FIG. 4:

In one embodiment, the plurality of charging circuits may further include a second charging circuit.

Wherein, at a same control voltage greater than or equal to the second threshold, a charging current when the low pass filter is charged by the second charging circuit is greater than charging the low pass filter by the first charging circuit a charging current; the first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the second charging circuit.

For example, referring to FIG. 4, the second charging circuit may include:

The first MOS transistor 211, the second current mirror, the third switch 235, and the fourth switch 236; the second current mirror includes the second MOS transistor 214 and the fourth MOS transistor 213; the source of the first MOS transistor 211 For receiving the operating voltage, the gate of the first MOS transistor 211 is configured to receive the first control signal, and the drain of the first MOS transistor 211 is connected to the source of the fourth MOS transistor 213 through the third switch 235. a drain of the fourth MOS transistor 213 is connected to the low pass filter; a gate of the fourth MOS transistor 213 is connected to a gate of the second MOS transistor 214 through the fourth switch 236, the second MOS A source of the tube 214 is coupled to the first current source.

The ratio of the channel length L of the fourth MOS transistor 213 to the channel width W of the fourth MOS transistor 213 is greater than the ratio of the L of the third MOS transistor 212 to the W of the third MOS transistor 212; The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the third switch 235 and the fourth switch 236. Further, the fourth MOS transistor 213 is a multi-stage cascaded MOS transistor.

Since the fourth MOS transistor 213 is a PMOS transistor having an inverted ratio tube (L is larger than W), at the same time, a PMOS transistor is formed by cascading a plurality of PMOS transistors. At the same time, the operating voltage (Vth) threshold of the 3-stage cascaded PMOS transistor is very low, and when the control voltage is greater than the second threshold, there is still a certain PMOS current.

Referring to FIG. 3, if the control voltage ranges from Vout_max to AVDD, and the charge pump uses the first discharge circuit to charge the low-pass filter, the charging current I _pmos can be increased to some extent. Further, the degree of mismatch between the charging current and the discharging current can be reduced.

Correspondingly, in the embodiment of the present invention, the plurality of discharge circuits may further include a second discharge circuit;

Wherein, at the same control voltage greater than or equal to the second threshold, the discharge current when the low-pass filter is discharged by the second discharge circuit is smaller than the discharge of the low-pass filter by the first discharge circuit a discharge current when the first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the second discharge circuit.

For example, referring to FIG. 4, the second discharge circuit can include:

The sixth MOS transistor 221, the fifth current mirror, the ninth switch 238, and the tenth switch 237; the fifth current mirror includes the seventh MOS transistor 224 and the ninth MOS transistor 223; the drain of the sixth MOS transistor 221 Grounding, the gate of the sixth MOS transistor 221 is configured to receive the first control signal, and the source of the sixth MOS transistor 221 is connected to the drain of the ninth MOS transistor 223 through the ninth switch 238; The source of the MOS transistor 223 is connected to the low pass filter; the gate of the ninth MOS transistor 223 is connected to the gate of the seventh MOS transistor 224 through the tenth switch 237, and the drain of the seventh MOS transistor 224 Connected to the second current source;

The ratio of the channel width W of the ninth MOS transistor 223 to the channel length L of the ninth MOS transistor 223 is greater than the ratio of the W of the eighth MOS transistor 222 to the L of the eighth MOS transistor 222; The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the ninth switch 238 and the tenth switch 237.

Since the ninth MOS transistor 223 is a NMOS transistor having a large W/L, the Vth of the ninth MOS transistor 223 is large, and the NMOS current can be reduced to some extent.

Referring to FIG. 3, if the control voltage ranges from Vout_max to AVDD, and the charge pump discharges the low-pass filter by the second discharge circuit, the discharge current I _{nmos tube} can be reduced to some extent. Further, the degree of mismatch between the charging current and the discharging current can be reduced.

Further, it can be found that when the control voltage is greater than the second threshold, if the low-pass filter is charged and discharged by the second charging circuit and the second discharging circuit involved above, the PMOS is maintained to some extent. The charging current and the NMOS discharge current are substantially the same. Further, the degree of mismatch between the charging current I _{pmos tube} and the discharge current I _{nmos tube} can be reduced.

Furthermore, a plurality of charging circuits and a plurality of discharging circuits are added in the embodiment of the present invention. Therefore, when the charge pump in the embodiment of the present invention controls the charge pump to charge or discharge the low-pass filter according to the control signal sent by the phase detector, it is further required that the plurality of charging circuits are turned on to match the control voltage. a charging circuit or a discharge circuit that matches the control voltage is turned on in the plurality of discharge circuits.

Therefore, an embodiment of the present invention further provides a control signal generating circuit.

Optionally, the phase locked loop may further include:

a control signal generating circuit, the control signal generating circuit is connected to the low pass filter, the control signal generating circuit is configured to receive the control voltage, and generate a plurality of control signals based on the control voltage;

The plurality of control signals are configured to: when the first control signal controls the charge pump to charge the low pass filter, turn on the one charging circuit and turn off the charging circuit except the one charging circuit The plurality of control signals are further configured to: when the first control signal controls the charge pump to discharge the low pass filter, turn on the one discharge circuit and turn off the discharge in the plurality of discharge circuits A discharge circuit outside the circuit.

For example, as shown in FIG. 5, the control signal generating circuit includes:

a first resistor 261, a second resistor 262, a first inverter 263 and a second inverter 264;

One end of the first resistor 261 is configured to receive the control voltage, the other end of the first resistor 261 is connected to the ground through the second resistor 262, and the second resistor 262 is further connected to the first through the first inverter 263. The two inverters 264, the control signals output by the first inverter 263 and the control signals output by the second inverter 264 are used to turn on or off a group of charge and discharge circuits, respectively.

It should be understood that the values of the first resistor 261 and the second resistor 262 are on the order of several hundred KΩ (kiloohms). For example, the first resistor 261 may be selected to be smaller than the appropriate value of the second resistor 262 to generate a control signal Φi1 and a control signal. Φi2. When the control voltage is larger than Vout_max, the switch controlled by the control signal Φ12 can be turned on, and the switch controlled by the control signal Φ11 is turned off.

The implementation manner of extending the linear output range of the charge pump in the case where the control voltage in the embodiment of the present invention is less than or equal to the first threshold (the low-voltage charge pump is close to ground) is exemplified in the following with reference to FIG. 6:

In one embodiment, the plurality of charging circuits may further include a third charging circuit.

Wherein, at a same control voltage less than or equal to the first threshold, a charging current when the low-pass filter is charged by the third charging circuit is smaller than charging the low-pass filter by the first charging circuit a charging current; the first control signal controls the charge pump to charge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the third charging circuit.

Specifically, referring to FIG. 6, the third charging circuit may include:

The first MOS transistor 211, the third current mirror, the fifth switch 235, and the sixth switch 236; the third current mirror includes the second MOS transistor 214 and the fifth MOS transistor 251; the source of the first MOS transistor 211 For receiving the operating voltage, the gate of the first MOS transistor 211 is configured to receive the first control signal, and the drain of the first MOS transistor 211 is connected to the source of the fifth MOS transistor 251 through the fifth switch 235. a drain of the fifth MOS transistor 251 is connected to the low pass filter; a gate of the fifth MOS transistor 251 is connected to a gate of the second MOS transistor 214 through the sixth switch 236, the second MOS A source of the tube 214 is coupled to the first current source.

The ratio of the channel length L of the fifth MOS transistor 251 to the channel width W of the fifth MOS transistor 251 is smaller than the ratio of the L of the third MOS transistor 212 to the W of the third MOS transistor 212; The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the fifth switch 235 and the sixth switch 236.

Since the fifth MOS transistor 251 is a PMOS transistor having a large W/L, and the Vth of the PMOS transistor is large, the PMOS current (charging current) can be reduced to some extent.

Referring to FIG. 3, if the control voltage ranges from ground to Vout_min, the charge pump can reduce the charging current I _{pmos tube to} some extent when the charge pump charges the low pass filter. Further, the degree of mismatch between the charging current and the discharging current can be reduced.

Correspondingly, in the embodiment of the present invention, the plurality of discharge circuits may further include a third discharge circuit;

Wherein, when the control voltage is less than or equal to the first threshold, the discharge current when discharging the low-pass filter by the third discharge circuit is greater than that of the low-pass filter by the first discharge circuit a discharge current during discharge; the first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the third discharge circuit.

Specifically, referring to FIG. 6, the third discharge circuit may include:

The sixth MOS transistor 221, the sixth current mirror, the eleventh switch 238, and the twelfth switch 237; the sixth current mirror includes the seventh MOS transistor 224 and the tenth MOS transistor 252; the sixth MOS transistor 221 The drain is grounded, the gate of the sixth MOS transistor 221 is for receiving the first control signal, and the source of the sixth MOS transistor 221 is connected to the drain of the tenth MOS transistor 252 through the eleventh switch 238; The source of the tenth MOS transistor 252 is connected to the low pass filter; the gate of the tenth MOS transistor 252 is connected to the gate of the seventh MOS transistor 224 through the twelfth switch 237, the seventh MOS transistor A drain of 224 is coupled to the second current source.

The ratio of the channel width W of the tenth MOS transistor 252 to the channel length L of the tenth MOS transistor 252 is smaller than the ratio of the W of the eighth MOS transistor 222 to the L of the eighth MOS transistor 222; The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the eleventh switch 238 and the twelfth switch 237.

Further, the tenth MOS transistor 252 may be a multi-stage cascaded MOS transistor.

Since the tenth MOS transistor 252 is an NMOS transistor having an inverse ratio tube (L is larger than W), further, it may be an NMOS transistor in which a plurality of NMOS transistors are cascaded together. At the same time, since the operating voltage (Vth) threshold of the 3-level cascaded NMOS transistor is very low, when the control voltage is less than the first threshold, there is still a certain NMOS current.

Referring to FIG. 3, if the control voltage ranges from the ground to the first threshold (Vout_min), and the charge pump discharges the low-pass filter through the third discharge circuit, the discharge current I _nmos can be increased to some extent. _Tube . Further, the degree of mismatch between the charging current and the discharging current can be reduced.

Further, it can be found that when the control voltage is less than the first threshold, if the low-pass filter is charged and discharged through the third charging circuit and the third discharging circuit involved above, it will be maintained to some extent. The PMOS charging current and the NMOS discharging current are substantially the same. Further, the degree of mismatch between the charging current I _{pmos tube} and the discharge current I _{nmos tube} can be reduced.

Fig. 7 is a view showing the result of charge and discharge mismatch when the low-pass filter is charged and discharged by the charging circuit and the discharging circuit of Figs. 4 and 6.

As shown in FIG. 7, when the control voltage in the embodiment of the present invention is less than the first threshold, the charge pump uses the third charging circuit and the third discharging circuit to charge and discharge the low-pass filter, and the control voltage is greater than the first When the threshold is less than the second threshold, the charge pump uses the first charging circuit and the first discharging circuit to charge and discharge the low-pass filter. When the control voltage is greater than the second threshold, the charge pump adopts the second The charging circuit and the second discharging circuit charge and discharge the low-pass filter, so that the charge-discharge mismatch of the control voltages belonging to Vout_max to AVDD and AVSS to Vout_min can be greatly reduced to become a charge pump effective output. Further, the temperature change suppressing ability of the entire phase locked loop is improved.

It should be noted that when the charging circuit and the discharging circuit of FIG. 4 and FIG. 6 are used to charge and discharge the low-pass filter, it is necessary to configure a control signal generating circuit for the FIG. 4 and FIG. 6, respectively, and the control signal generating circuit and the A low pass filter is coupled to the control signal generating circuit for receiving the control voltage and generating a plurality of control signals based on the control voltage. In an embodiment, a control signal generating circuit as shown in FIG. 5 may be configured for FIG. 4 and FIG. 6, respectively, wherein the control signal Φi1 and the control signal Φi2 generated by the control signal generating circuit shown in FIG. 5 may pass the A resistor 261 and a second resistor 262 are controlled. For example, when the control voltage is greater than Vout_max, the first resistor 261 <the second resistor 262 is selected such that the control signal Φi1 and the control signal Φi2 generated by the control signal generating circuit configured for the circuit shown in FIG. 4 are respectively the control signal Φ11, The control signal Φ12 is controlled, and the switch on the second charging circuit and the second discharging circuit is controlled by the control signal Φ12, and the switch on the first charging circuit and the first discharging circuit is controlled to be turned off by the control signal Φ11. When the control voltage is smaller than Vout_min, the first resistor 261>the second resistor 262 is selected such that the control signal Φi1 and the control signal Φi2 generated by the other control signal generating circuit configured for the circuit shown in FIG. 6 are respectively the control signal Φ21 and the control The signal Φ22 is controlled by the control signal Φ22 to control the switches on the third charging circuit and the third discharging circuit, and the control signal Φ21 controls the switches on the first charging circuit and the first discharging circuit to be turned off. Further, when the charging circuit and the discharging circuit of FIGS. 4 and 6 are simultaneously used for charging and discharging the low-pass filter, only one first charging circuit and one first discharging circuit may be reserved.

In addition, the phase-locked loop in the embodiment of the present invention is suitable for a very low power supply voltage, and only increases the branch that is higher than Vout_max and the branch that is lower than Vout_min, and does not require special devices.

It should be understood that, in the embodiment of the present invention, the second discharge circuit and the second charging circuit shown in FIG. 4, and the third discharge circuit and the third charging circuit shown in FIG. 6 are only a plurality of charging circuits and a plurality of discharging circuits. Schematic diagram. The embodiment of the present invention is not limited thereto, that is, the specific structure of the circuit diagram of the embodiment of the present invention is not limited.

For example, in one possible implementation, the charge pump can include more than three sets of charging circuits and discharging circuits,

In addition, a terminal device is provided in the embodiment of the present invention, including: the phase locked loop provided above.

It is to be understood that the terminology of the embodiments of the invention and the claims

For example, the singular forms "a", "the", and "the"

Those of ordinary skill in the art will appreciate that the components of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in this description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

It will be apparent to those skilled in the art that the described devices and components may or may not be physically separated for convenience and conciseness of the description. Some or all of the components may be selected according to actual needs to achieve the objectives of the embodiments of the present invention. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.

The above is only a specific embodiment of the embodiments of the present invention, but the scope of protection of the embodiments of the present invention is not limited thereto, and any person skilled in the art can easily think of the technical scope disclosed in the embodiments of the present invention. Variations or substitutions are intended to be included within the scope of the embodiments of the invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope of protection of the claims.

Claims

A phase locked loop, comprising:

Phase detector, charge pump, low pass filter and voltage controlled oscillator;

The phase detector is connected to the low pass filter by the charge pump, and the low pass filter is connected to the voltage controlled oscillator;

The charge pump includes a plurality of charging circuits and/or a plurality of discharging circuits;

The charge pump is configured to turn on one of the plurality of charging circuits according to a first control signal output by the phase detector and a control voltage output by the low pass filter, and pass the one The charging circuit charges the low pass filter, or the charge pump is configured to turn on one of the plurality of discharge circuits according to the first control signal and the control voltage, and pass The one discharge circuit discharges the low pass filter such that at the same control voltage, a charging current when the low pass filter is charged by the one charging circuit, and a discharge through the one discharge The absolute value of the difference between the discharge currents when the circuit discharges the low pass filter is less than a predetermined threshold.
The phase locked loop of claim 1 wherein said plurality of charging circuits comprise a first charging circuit, said plurality of discharging circuits comprising a first discharging circuit;

a charging current for charging the low pass filter by the first charging circuit and the same by the first discharging circuit at the same control voltage within a range of a first threshold to a second threshold The absolute value of the difference between the discharge currents when the low-pass filter performs discharge is less than or equal to the preset threshold;

Wherein, the first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than a first threshold and less than a second threshold, the charge pump turns on the first charging circuit Or the first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than a first threshold and less than a second threshold, the charge pump turns on the first discharge Circuit.
The phase locked loop of claim 2, wherein the plurality of charging circuits further comprise a second charging circuit;

Wherein, at the same control voltage greater than or equal to the second threshold, a charging current when the low pass filter is charged by the second charging circuit is greater than that of the first charging circuit a charging current when the low pass filter is being charged;

The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the second charging circuit.
The phase locked loop according to claim 2 or 3, wherein the plurality of charging circuits further comprise a third charging circuit;

Wherein, at the same control voltage less than or equal to the first threshold, a charging current when the low-pass filter is charged by the third charging circuit is smaller than that of the first charging circuit a charging current when the low pass filter is being charged;

The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the third charging circuit.
The phase locked loop according to any one of claims 2 to 4, wherein the first charging circuit comprises:

a first metal oxide semiconductor MOS transistor, a first current mirror, a first switch, and a second switch;

The first current mirror includes a second MOS transistor and a third MOS transistor;

a source of the first MOS transistor is configured to receive an operating voltage, a gate of the first MOS transistor is configured to receive the first control signal, and a drain of the first MOS transistor is connected through the first switch To the source of the third MOS transistor;

a drain of the third MOS transistor is connected to the low pass filter;

a gate of the third MOS transistor is connected to a gate of the second MOS transistor through the second switch, and a source of the second MOS transistor is connected to a first current source;

Wherein the first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than the first threshold and less than the second threshold, the charge pump conducts the a first switch and the second switch.
The phase locked loop of claim 5, wherein the second charging circuit comprises:

The first MOS transistor, the second current mirror, the third switch, and the fourth switch;

The second current mirror includes the second MOS transistor and the fourth MOS transistor;

a source of the first MOS transistor is configured to receive the operating voltage, a gate of the first MOS transistor is configured to receive the first control signal, and a drain of the first MOS transistor passes the third a switch connected to a source of the fourth MOS transistor;

a drain of the fourth MOS transistor is connected to the low pass filter;

a gate of the fourth MOS transistor is connected to a gate of the second MOS transistor through the fourth switch, and a source of the second MOS transistor is connected to the first current source;

The ratio of the channel length L of the fourth MOS transistor to the channel width W of the fourth MOS transistor is greater than the ratio of the L of the third MOS transistor to the W of the third MOS transistor;

The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the third switch and the first Four switches.
The phase locked loop according to claim 6, wherein the fourth MOS transistor is a multi-stage cascaded MOS transistor.
The phase locked loop of claim 5, wherein the third charging circuit comprises:

The first MOS transistor, the third current mirror, the fifth switch, and the sixth switch;

The third current mirror includes the second MOS transistor and the fifth MOS transistor;

a source of the first MOS transistor is configured to receive the operating voltage, a gate of the first MOS transistor is configured to receive the first control signal, and a drain of the first MOS transistor passes the fifth a switch connected to a source of the fifth MOS transistor;

a drain of the fifth MOS transistor is connected to the low pass filter;

a gate of the fifth MOS transistor is connected to a gate of the second MOS transistor through the sixth switch, and a source of the second MOS transistor is connected to the first current source;

The ratio of the channel length L of the fifth MOS transistor to the channel width W of the fifth MOS transistor is smaller than the ratio of the L of the third MOS transistor to the W of the third MOS transistor;

The first control signal controls the charge pump to charge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the fifth switch and the first Six switches.
The phase locked loop according to any one of claims 2 to 8, wherein the plurality of discharge circuits further comprise a second discharge circuit;

Wherein, at the same control voltage greater than or equal to the second threshold, a discharge current when the low-pass filter is discharged by the second discharge circuit is smaller than that of the first discharge circuit a discharge current when the low pass filter is discharged;

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the second discharge circuit.
The phase locked loop according to any one of claims 2 to 9, wherein the plurality of discharge circuits further comprise a third discharge circuit;

Wherein, in a case where the control voltage is less than or equal to the first threshold, a discharge current when the low-pass filter is discharged by the third discharge circuit is greater than that by the first discharge circuit a discharge current when the low pass filter is discharged;

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the third discharge circuit.
The phase locked loop according to any one of claims 2 to 10, wherein the first discharge circuit comprises:

a sixth metal oxide semiconductor MOS transistor, a fourth current mirror, a seventh switch, and an eighth switch;

The fourth current mirror includes a seventh MOS transistor and an eighth MOS transistor;

a drain of the sixth MOS transistor is grounded, a gate of the sixth MOS transistor is configured to receive the first control signal, and a source of the sixth MOS transistor is connected to the first The drain of the eight MOS transistors;

a source of the eighth MOS transistor is connected to the low pass filter;

a gate of the eighth MOS transistor is connected to a gate of the seventh MOS transistor through the eighth switch, and a drain of the seventh MOS transistor is connected to a second current source;

Wherein, the first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than a first threshold and less than a second threshold, the charge pump turns on the seventh switch and The eighth switch.
The phase locked loop of claim 11 wherein said second discharge circuit comprises:

The sixth MOS transistor, the fifth current mirror, the ninth switch, and the tenth switch;

The fifth current mirror includes the seventh MOS transistor and the ninth MOS transistor;

a drain of the sixth MOS transistor is grounded, a gate of the sixth MOS transistor is configured to receive the first control signal, and a source of the sixth MOS transistor is connected to the first The drain of the nine MOS tube;

a source of the ninth MOS transistor is connected to the low pass filter;

a gate of the ninth MOS transistor is connected to a gate of the seventh MOS transistor through the tenth switch, and a drain of the seventh MOS transistor is connected to the second current source;

The ratio of the channel width W of the ninth MOS transistor to the channel length L of the ninth MOS transistor is greater than the ratio of the W of the eighth MOS transistor to the L of the eighth MOS transistor;

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is greater than or equal to the second threshold, the charge pump turns on the ninth switch and the first Ten switches.
The phase locked loop of claim 11 wherein said third discharge circuit comprises:

The sixth MOS transistor, the sixth current mirror, the eleventh switch and the twelfth switch;

The sixth current mirror includes the seventh MOS transistor and the tenth MOS transistor;

a drain of the sixth MOS transistor is grounded, a gate of the sixth MOS transistor is configured to receive the first control signal, and a source of the sixth MOS transistor is connected to the The drain of the tenth MOS transistor;

a source of the tenth MOS transistor is connected to the low pass filter;

a gate of the tenth MOS transistor is connected to a gate of the seventh MOS transistor through the twelfth switch, and a drain of the seventh MOS transistor is connected to the second current source;

The ratio of the channel width W of the tenth MOS transistor to the channel length L of the tenth MOS transistor is smaller than the ratio of the W of the eighth MOS transistor to the L of the eighth MOS transistor;

The first control signal controls the charge pump to discharge the low pass filter, and when the control voltage is less than or equal to the first threshold, the charge pump turns on the eleventh switch and the Twelfth switch.
The phase locked loop according to claim 13, wherein the tenth MOS transistor is a multi-stage cascaded MOS transistor.
The phase locked loop according to any one of claims 1 to 13, wherein the phase locked loop further comprises:

a control signal generating circuit, the control signal generating circuit is coupled to the low pass filter, the control signal generating circuit is configured to receive the control voltage, and generate a plurality of control signals based on the control voltage;

The plurality of control signals are configured to: when the first control signal controls the charge pump to charge the low pass filter, turn on the one charging circuit and turn off the plurality of charging circuits a charging circuit other than the charging circuit; the plurality of control signals are further configured to: when the first control signal controls the charge pump to discharge the low-pass filter, turn on the one discharging circuit and Discharging a discharge circuit other than the one of the plurality of discharge circuits.
The phase locked loop of claim 15 wherein said control signal generating circuit comprises:

a first resistor, a second resistor, a first inverter, and a second inverter;

One end of the first resistor is for receiving the control voltage, the other end of the first resistor is connected to the ground through the second resistor, and the second resistor is further connected to the ground through the first inverter The second inverter, the control signal output by the first inverter and the control signal output by the second inverter are used to turn on or off a group of charge and discharge circuits, respectively.
A terminal device, comprising:

A phase locked loop as claimed in any one of claims 1 to 16.