WO2019188175A1 - Procédé pour éviter un blocage et dispositif pour éviter un blocage - Google Patents

Procédé pour éviter un blocage et dispositif pour éviter un blocage Download PDF

Info

Publication number
WO2019188175A1
WO2019188175A1 PCT/JP2019/009627 JP2019009627W WO2019188175A1 WO 2019188175 A1 WO2019188175 A1 WO 2019188175A1 JP 2019009627 W JP2019009627 W JP 2019009627W WO 2019188175 A1 WO2019188175 A1 WO 2019188175A1
Authority
WO
WIPO (PCT)
Prior art keywords
deadlock
processing
provisional
graph structure
start node
Prior art date
Application number
PCT/JP2019/009627
Other languages
English (en)
Japanese (ja)
Inventor
祐次郎 谷
一嘉 石渡
Original Assignee
株式会社デンソー
株式会社エヌエスアイテクス
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デンソー, 株式会社エヌエスアイテクス filed Critical 株式会社デンソー
Publication of WO2019188175A1 publication Critical patent/WO2019188175A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation

Definitions

  • the present disclosure relates to a deadlock avoidance method and a deadlock avoidance device that avoid a deadlock in a processor that executes a program described in a graph structure.
  • Patent Document 1 discloses a method for avoiding a deadlock that occurs with interrupt processing.
  • Patent Document 1 discloses that a deadlock is avoided in a processor system that performs processing on a coprocessor by interrupt processing during execution of a coprocessor instruction.
  • Patent Document 1 it is not possible to avoid a deadlock unique to a processor that operates by dividing a program into data and processing into a graph structure and reading it.
  • This disclosure is intended to provide a deadlock avoidance method and a deadlock avoidance device that avoid a deadlock in a processor that executes a program described in a graph structure.
  • the present disclosure relates to a deadlock avoidance method for avoiding a deadlock in a processor that executes a program described in a graph structure.
  • a program having a graph structure an input / output buffer loops in units of buffers and apparently becomes a deadlock.
  • a process start node for starting the process at the provisional deadlock point is specified, and a start specifying process for specifying a series of processes to be started from the process start node is executed.
  • the present disclosure also relates to a deadlock avoidance device that avoids deadlock in a processor that executes a program described in a graph structure.
  • a program having a graph structure an input / output buffer is looped in units of buffers and apparently deadlocks.
  • the deadlock elimination unit identifies a process start node that starts processing at the provisional deadlock location, and executes a start identification process that identifies a series of processes to be started from the process start node.
  • FIG. 1 is a diagram for explaining parallel processing which is a premise of the present embodiment.
  • FIG. 2 is a diagram showing a system configuration example for executing the parallel processing shown in FIG.
  • FIG. 3 is a diagram illustrating a configuration example of the DFP used in FIG.
  • FIG. 4 is a diagram for explaining a functional configuration example of the compiler.
  • FIG. 5 is a diagram for explaining an example of deadlock avoidance.
  • FIG. 6 is a diagram for explaining an example of deadlock avoidance.
  • FIG. 7 is a diagram for explaining an example of deadlock avoidance.
  • FIG. 8 is a diagram for explaining an example of deadlock avoidance.
  • FIG. 1A shows program code described in a graph structure
  • FIG. 1B shows the state of a thread
  • FIG. 1C shows the state of parallel processing. .
  • the program to be processed in this embodiment has a graph structure in which data and processing are divided. This graph structure maintains the task parallelism and graph parallelism of the program.
  • Parallel execution as shown in FIG. 1C can be performed on a large number of threads shown in FIG. 1B by dynamic register placement and thread scheduling by hardware. By dynamically allocating register resources during execution, a plurality of threads can be executed in parallel for different instruction streams.
  • a data processing system 2 which is a system configuration example including a DFP (Data Flow Processor) 10 as an accelerator for performing dynamic register placement and thread scheduling, will be described with reference to FIG.
  • DFP Data Flow Processor
  • the data processing system 2 includes a DFP 10, an event handler 20, a host CPU 21, a ROM 22, a RAM 23, an external interface 24, and a system bus 25.
  • the host CPU 21 is an arithmetic unit that mainly performs data processing.
  • the host CPU 21 supports the OS.
  • the event handler 20 is a part that generates an interrupt process.
  • ROM 22 is a read-only memory.
  • the RAM 23 is a read / write memory.
  • the external interface 24 is an interface for exchanging information with the outside of the data processing system 2.
  • the system bus 25 is for transmitting and receiving information between the DFP 10, the host CPU 21, the ROM 22, the RAM 23, and the external interface 24.
  • the DFP 10 is positioned as an individual master provided to cope with the heavy computation load of the host CPU 21.
  • the DFP 10 is configured to support the interrupt generated by the event handler 20.
  • the DFP 10 includes a command unit 12, a thread scheduler 14, an execution core 16, and a memory subsystem 18.
  • the command unit 12 is configured to be able to communicate information with the config interface.
  • the command unit 12 also functions as a command buffer.
  • the thread scheduler 14 is a part that schedules processing of a large number of threads as exemplified in FIG.
  • the thread scheduler 14 can perform scheduling across threads.
  • the execution core 16 has four processing elements, PE # 0, PE # 1, PE # 2, and PE # 3.
  • the execution core 16 has a number of pipelines that can be scheduled independently.
  • the memory subsystem 18 includes an arbiter 181, an L1 cache 18a, and an L2 cache 18b.
  • the memory subsystem 18 is configured to allow information communication between the system bus interface and the ROM interface.
  • a compiler 50 as an example of the deadlock avoidance device of the present disclosure will be described with reference to FIG.
  • the embodiment of the deadlock avoidance device according to the present disclosure is not limited to the compiler 50, and if the program described in the graph structure illustrated in FIG.
  • the compiler 50 includes a graph structure analysis unit 501 and a deadlock elimination unit 502 as functional components.
  • the graph structure analysis unit 501 is a part for extracting a provisional deadlock portion where an input / output buffer loops in buffer units and apparently becomes a deadlock in a program described in a graph structure.
  • the graph structure analysis unit 501 extracts a location as shown in FIG. 5 as a temporary deadlock location where the input / output buffer loops in buffer units and apparently becomes a deadlock (graph structure analysis step).
  • the deadlock elimination unit 502 is a part for eliminating deadlock at the provisional deadlock location.
  • the deadlock elimination unit 502 identifies a process start node that starts processing at the provisional deadlock location, and executes a start identification process that identifies a series of processes to be started from the process start node (deadlock resolution step). .
  • the deadlock canceling unit 502 executes the start specifying process, so that the deadlock state is canceled and the process illustrated in FIG. 6 can be performed.
  • start instruction information for the function start node func1 is added so that the process starts from the process start node func1.
  • a kick command is used as the start instruction information.
  • process order information for instructing the order of the process is given so as to start the process from func1, which is the process start node.
  • the present embodiment is a deadlock avoidance method for avoiding a deadlock in a processor that executes a program described in a graph structure.
  • the input / output buffer is a buffer unit.
  • a graph structure analysis step for extracting a provisional deadlock portion that loops and becomes an apparent deadlock, and a deadlock elimination step for eliminating a deadlock at the provisional deadlock portion are provided.
  • a process start node for starting the process at the provisional deadlock point is specified, and a start specifying process for specifying a series of processes to be started from the process start node is executed.
  • a device If considered as a device, it is a deadlock avoidance device that avoids deadlock in a processor that executes a program described in a graph structure.
  • a graph structure analysis unit 501 that extracts a provisional deadlock location that becomes a deadlock, and a deadlock elimination unit 502 that eliminates a deadlock at the provisional deadlock location.
  • the deadlock elimination unit 502 identifies a process start node that starts processing at the provisional deadlock location, and executes a start identification process that identifies a series of processes to be started from the process start node.
  • start instruction information for the process start node can be given so as to start the process from the process start node.
  • the deadlock elimination unit 502 can give start instruction information to the process start node so that the start specifying process starts the process from the process start node.
  • the deadlock elimination unit 502 can add processing order information that instructs the processing order so that the processing is started from the processing start node in the start specifying processing. In this way, by adding the processing order information, the processing order can be specified, and parallel processing becomes possible.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Devices For Executing Special Programs (AREA)
  • Debugging And Monitoring (AREA)

Abstract

L'invention concerne un processeur destiné à exécuter un programme dans une structure de graphe qui comprend : une unité d'analyse de structure de graphique (501) qui extrait un point d'interblocage provisoire au niveau duquel des tampons d'entrée/sortie forment une boucle dans des unités de tampon et qui est apparemment en blocage ; et une unité d'élimination d'interblocage (502) qui élimine l'interblocage au niveau du point d'interblocage provisoire. L'unité d'élimination d'interblocage (502) identifie un nœud de début de traitement auquel un traitement est démarré dans le point d'interblocage provisoire, et réalise un processus d'identification de début pour exécuter une identification de façon à démarrer une série de traitements à partir du nœud de début de traitement.
PCT/JP2019/009627 2018-03-30 2019-03-11 Procédé pour éviter un blocage et dispositif pour éviter un blocage WO2019188175A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-068429 2018-03-30
JP2018068429A JP7064367B2 (ja) 2018-03-30 2018-03-30 デッドロック回避方法、デッドロック回避装置

Publications (1)

Publication Number Publication Date
WO2019188175A1 true WO2019188175A1 (fr) 2019-10-03

Family

ID=68061541

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/009627 WO2019188175A1 (fr) 2018-03-30 2019-03-11 Procédé pour éviter un blocage et dispositif pour éviter un blocage

Country Status (2)

Country Link
JP (1) JP7064367B2 (fr)
WO (1) WO2019188175A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102531567B1 (ko) * 2020-04-03 2023-05-15 서울대학교산학협력단 데드락 회피 방법 및 시스템

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001500656A (ja) * 1997-04-28 2001-01-16 エービー イニティオ ソフトウェア コーポレーション データフロー計算におけるバッファデッドロックの防止方法
JP2009512089A (ja) * 2005-10-18 2009-03-19 マイトリオニクス エービー データフローマシンにおけるデッドロックを回避するための方法
WO2016151710A1 (fr) * 2015-03-20 2016-09-29 株式会社日立製作所 Dispositif et procédé de configuration de spécification

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001500656A (ja) * 1997-04-28 2001-01-16 エービー イニティオ ソフトウェア コーポレーション データフロー計算におけるバッファデッドロックの防止方法
JP2009512089A (ja) * 2005-10-18 2009-03-19 マイトリオニクス エービー データフローマシンにおけるデッドロックを回避するための方法
WO2016151710A1 (fr) * 2015-03-20 2016-09-29 株式会社日立製作所 Dispositif et procédé de configuration de spécification

Also Published As

Publication number Publication date
JP2019179412A (ja) 2019-10-17
JP7064367B2 (ja) 2022-05-10

Similar Documents

Publication Publication Date Title
US9891949B2 (en) System and method for runtime scheduling of GPU tasks
JP4756553B2 (ja) 分散処理方法、オペレーティングシステムおよびマルチプロセッサシステム
JP2010140290A (ja) マルチプロセッサシステム及びその排他制御の調停方法
JP2009151645A (ja) 並列処理装置及びプログラム並列化装置
WO2020121840A1 (fr) Dispositif de commande arithmétique
WO2019188175A1 (fr) Procédé pour éviter un blocage et dispositif pour éviter un blocage
US20100169889A1 (en) Multi-core system
US11301304B2 (en) Method and apparatus for managing kernel services in multi-core system
US11481250B2 (en) Cooperative workgroup scheduling and context prefetching based on predicted modification of signal values
EP2750045A1 (fr) Procédé et appareil d'attribution d'interruptions dans système multic ur
US20220300322A1 (en) Cascading of Graph Streaming Processors
WO2019188179A1 (fr) Procédé et dispositif d'évitement de blocage
JP6817827B2 (ja) アクセラレータ処理管理装置、ホスト装置、アクセラレータ処理実行システム、方法およびプログラム
WO2019188177A1 (fr) Dispositif de traitement d'informations
US10261817B2 (en) System on a chip and method for a controller supported virtual machine monitor
JP4017005B2 (ja) 演算装置
US10360652B2 (en) Wavefront resource virtualization
JP7112058B2 (ja) リアルタイム処理装置及びその作製方法
WO2019188171A1 (fr) Procédé de génération de code et dispositif de génération de code
WO2019188181A1 (fr) Procédé et dispositif de programmation
WO2019188172A1 (fr) Dispositif de traitement d'informations
JP2019204387A (ja) プログラム実行制御方法およびプログラム変換装置
JP7456437B2 (ja) プロセッサおよびプログラム
WO2019188182A1 (fr) Dispositif de commande de pré-extraction
JP6255721B2 (ja) 処理割り当て装置、処理割り当て方法及び処理割り当てプログラム

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19775798

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19775798

Country of ref document: EP

Kind code of ref document: A1