WO2020121840A1 - Dispositif de commande arithmétique - Google Patents

Dispositif de commande arithmétique Download PDF

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Publication number
WO2020121840A1
WO2020121840A1 PCT/JP2019/046724 JP2019046724W WO2020121840A1 WO 2020121840 A1 WO2020121840 A1 WO 2020121840A1 JP 2019046724 W JP2019046724 W JP 2019046724W WO 2020121840 A1 WO2020121840 A1 WO 2020121840A1
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Prior art keywords
task
parallelization
subtask
processing
cores
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PCT/JP2019/046724
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English (en)
Japanese (ja)
Inventor
辰也 堀口
祐 石郷岡
裕弘 小田
成沢　文雄
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日立オートモティブシステムズ株式会社
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Priority to DE112019005584.4T priority Critical patent/DE112019005584T5/de
Publication of WO2020121840A1 publication Critical patent/WO2020121840A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration

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  • the present invention relates to an arithmetic and control unit, and more particularly to an arithmetic and control unit for controlling a processor having a plurality of cores called multi-core or many-core.
  • control unit Electronic Control Unit
  • a control unit that utilizes a processor having multiple cores such as a multi-core or many-core processor is adopted, and its processing performance is required to be improved.
  • Patent Document 1 discloses an example of efficiently allocating a plurality of tasks to a multi-core processor (providing suboptimal scheduling).
  • Patent Document 1 static scheduling in which processing is assigned to each processor core is normally used based on a scheduling method defined in advance, but tasks are efficiently executed in a heavy load situation.
  • An example of performing dynamic scheduling for is shown.
  • static scheduling Even if the designer performs appropriate scheduling (when it works), it is difficult to guarantee the execution time constraint at least when the scheduling is performed dynamically.
  • one process may affect the execution time of another process. In this case, it may be difficult to guarantee execution time constraints. Therefore, in order to satisfy the execution time constraint, it is necessary to provide a method for coping with fluctuations in processing time when operations are simultaneously performed on a plurality of cores.
  • An object of the present invention is to make it possible to reduce fluctuations in processing time when different processes are simultaneously performed on a plurality of cores in a system using a processor having a plurality of cores as described above. It is an object of the present invention to provide an arithmetic and control unit capable of improving the behavior predictability of, and increasing the assurance possibility of the execution time constraint.
  • the arithmetic and control unit is an arithmetic and control unit including a processor having a plurality of cores and a task allocation unit that allocates tasks to the plurality of cores.
  • the task allocation unit determines whether or not it is possible to target a plurality of subtasks forming the task for parallelization processing, and when the parallelization processing is possible, under a predetermined condition. It is configured to assign the plurality of subtasks to the plurality of cores.
  • the arithmetic and control unit using a multi-core processor it is possible to reduce the fluctuation of the processing time when different processing is simultaneously performed on a plurality of cores, thereby enhancing the behavior predictability of the system, The guarantee possibility of the execution time constraint can be increased.
  • FIG. 3 is a schematic block diagram showing a configuration part related to arithmetic processing in the arithmetic control device of the multi-core processor according to the first embodiment.
  • FIG. 3 is a schematic diagram showing the relationship between the arithmetic and control unit 1 and software components (installed functions) in the first embodiment. It is a schematic diagram explaining an example of the dependency of a software component (installed function).
  • 6 is a table showing the relationship between software components (installed functions) and corresponding tasks. It is the figure which expressed the loading function which is allotted to arithmetic and control unit 1 with the model base design method. It is a table showing the task corresponding to the mounted function assigned to the arithmetic and control unit 1 at the time of model-based design.
  • 9 is a table illustrating an example of various parameters given to each of the tasks in the first embodiment.
  • 6 is an example of a task graph showing a data dependency relationship in the first embodiment.
  • 7 is a table showing an example of priority parameters given to each task in the first embodiment.
  • 6 is an example of a time chart in the case where subtasks are not parallelized within task D in the first embodiment.
  • 9 is a table showing a relationship between a task graph and a set average execution time when a submask that can be parallelized is parallelized in task D. 7 is an example of a time chart when the subtasks in the task D are parallelized in the first embodiment.
  • FIG. 9 is an example of a time chart in the case where a time constraint violation occurs due to the occurrence of the event driven processing task H in the first embodiment.
  • FIG. 16 is a diagram showing a method of parallelizing task D and a priority setting method in the first modification of the first embodiment.
  • 11 is a list showing a setting example of task priority parameters in Modification 1 of the first embodiment.
  • 9 is an example of a time chart showing an operation in Modification 2 of the first embodiment.
  • FIG. 11 is a schematic block diagram showing a configuration part related to arithmetic processing in the arithmetic control device of the multi-core processor according to the second embodiment.
  • 11 is a table for explaining an example of various parameters given to each of the tasks in the second embodiment.
  • 9 is a list showing an example of setting deadline parameters in the second embodiment.
  • FIG. 1 is a schematic block diagram showing the components related to the arithmetic processing in the arithmetic control device of the multi-core processor according to the first embodiment.
  • the arithmetic and control unit 1 includes a parameter assigning unit 101, a multicore processor 102, and a task assigning unit 103.
  • the parameter assigning unit 101 has a function of assigning information about hardware and software necessary for controlling the vehicle to the task as parameters and storing the information in the storage unit.
  • the parameters related to hardware include the multi-core configuration of the multi-core processor 102, bus wiring information, sensing information (sensor value) of a sensor (not shown), and the like.
  • the parameters stored in the parameter assigning unit 101 can also serve as a judgment index when the task allocating unit 103 performs allocation.
  • the parameter assignment unit 101 includes a task control cycle parameter storage unit 1011, a task priority parameter storage unit 1012, and a task dependency relationship parameter 1013.
  • the task control cycle parameter storage unit 1011 stores parameters that define the control cycle of each task executed by the multicore processor 102.
  • the task priority parameter storage unit 1012 stores a parameter that defines a priority indicating the degree to which each task is preferentially processed (executed) in relation to other tasks.
  • the task dependency relationship parameter storage unit 1013 stores a dependency relationship parameter indicating a dependency relationship between tasks.
  • the dependency relationship parameter indicates a relationship in which the end of task A is the start condition of task B, for example, because the result of processing by certain task A is processed as the input of the next task B.
  • the multi-core processor 102 has a plurality of cores 1 to 8, and each core 1 to 8 is configured to be able to execute task processing in parallel.
  • the multi-core processor 102 can include two cores each having two different performances, four cores each.
  • cores 1 to 4 having relatively high performance are referred to as high-speed operating cores 1021
  • cores 5 to 8 having low performance are referred to as low-speed operating cores 1022.
  • the number of performance stages is not limited to two, and may be three or more, or all cores may have the same performance.
  • the task allocation unit 103 allocates each task to each core of the multi-core processor 102 based on the parameters (task control period, task priority, task dependency relationship, etc.) acquired from the parameter assignment unit 101.
  • the on-board functions required for such an arithmetic and control unit 1 are given in several formats. For example, as shown in FIG. 2, consider a case where various functions 1, 2, 3, 4,... Are described as software components in source code such as C language and given to the arithmetic and control unit 1.
  • the dependency relationships among the functions 1, 2, 3, 4,... are decoded. For example, it is determined based on the source code that the function 2 can be executed after the execution of the function 1 is completed and the function 3 can be executed after the execution of the function 2 is completed.
  • FIG. 4 shows an example of the relationship between each function 1, 2, 3, 4 (software component) and the task.
  • the task is defined in a form corresponding to each function as shown in Fig. 6.
  • the corresponding tasks are defined for the sub-functions 2-1, 2-2, 2-3, 4-1, 4-2 in the functions 2 and 4, respectively.
  • various parameters are generated for each task based on the source code of the software component, for example, as shown in the table of FIG. 7.
  • parameters such as average execution time (when a high-speed core is used), parallelization of subtasks included in each task, and task control cycle are generated.
  • the task control cycle parameter is stored in the task control cycle parameter storage unit 1011. Note that FIG. 7 shows the case where the average execution time is calculated and the parameters are determined for the task H corresponding to the event driven processing (interrupt processing), which is different from the functions 1 to 4.
  • FIG. 8 shows an example of a task graph when executing the tasks shown in FIG.
  • the task graph is generated by the arithmetic and control unit 1 according to the task control cycle, the task dependency, and other parameters.
  • Each task is classified for each task having the same task control cycle, and is ordered according to the task dependency relationship.
  • one task graph is formed for tasks A to E operating in the control period of 30 ms, and another task graph is formed for tasks F and G operating in the control period of 50 ms.
  • the inter-task dependency relationships are represented by the arrows between the tasks. This dependency relationship is described in the task dependency relationship parameter 1013.
  • a set of multiple tasks arranged in series is executed in one core in the multiprocessor 102, and different sets of tasks can be executed in different cores. For example, tasks A, B, and E can be executed in core 1, tasks C and D can be executed in core 2, and tasks F and G can be executed in core 3.
  • FIG. 9 shows an example of priorities defined for each task.
  • the numbers in FIG. 9 mean that the smaller the number, the higher the priority. For example, tasks F and G have priority “15”, and tasks A to E have higher priority “10”.
  • the task H has a higher priority “5” than this.
  • a priority and a task control cycle are given to each task by a control policy that a task having a shorter task control cycle is given a higher priority.
  • FIG. 10 shows an example of a time chart when each task is executed (calculation is executed) according to the task control cycle, the dependency, and the priority determined as described above. In this FIG. 10, it is assumed that task switching on the core and time overhead associated with task division do not occur.
  • Tasks A to E having a task control period of 30 ms are executed based on the dependency relationship according to the task dependency parameter.
  • the tasks A and B and the tasks C and D can be executed in parallel (simultaneously) by the different cores 1 and 2.
  • A, C, D, and E must be executed in that order, so that the processing becomes a neck (critical path), and depending on the execution time of each task, the periodic constraint of 30 [ms] is satisfied. It is not possible to do so, and time constraint violation will occur.
  • a task that is further divided into a plurality of subtasks, and the subtasks can be parallelized are The execution time is shortened by executing parallelization.
  • the division into subtasks can be determined and executed by the task allocation unit 103 based on the task control period parameter, the task priority parameter, the task dependency relationship, and the like.
  • FIG. 11 shows a task graph when the task D is divided into a plurality of subtasks D pre , D p0 to D p3 , and D post , and some of the subtasks (for example, subtasks D p0 to D p3 ) are parallelized.
  • An example of the determined average execution time (when using a high-speed core) is shown.
  • At least two or more of the plurality of subtasks generated from one task D are parallelized and can be simultaneously executed in different cores, so that the total execution time (average) of the tasks can be shortened. ..
  • the plurality of subtasks are pre- parallelized subtask D pre (21), parallelization target subtask D p (22) (D p0 to D p3 ), and parallel. It can be divided into post- task subtasks D post (23).
  • the pre-parallelization subtask D pre1 is the first subtask to be executed among the subtasks in the task D.
  • a plurality of parallelization target subtasks D p can be executed in parallel in a plurality of cores.
  • the post- parallelization subtask D post is a task executed when the execution of all the parallelization target subtasks D p1 to D p3 is completed. In this way, by placing subtasks that are not the target of parallelization before and after the parallelization target subtask D p , it is possible to easily predict the execution time and reduce the processing load on the arithmetic and control unit 1. ..
  • the total Ttotal of the average execution time of each subtask is equal to or less than the average execution time Td of the original task D.
  • the newly created subtasks D pre , D p0 to D p3 , and the dependency relationship among D post , and the average execution time are stored in the parameter assigning unit 101.
  • FIG. 12 shows an example of a time chart when the task D is divided into a plurality of subtasks and parallelized as shown in FIG.
  • the subtasks D p0 to D p3 that can be parallelized are preferentially processed, and before that, the pre-parallelization subtask D pre processes after the execution of the task C. Be started.
  • the pre-parallelization subtask D pre processes after the execution of the task C. Be started.
  • the pre-parallelization subtask D pre processes after the execution of the task C. Be started.
  • the pre-parallelization subtask D pre processes after the execution of the task C. Be started.
  • the pre-parallelization subtask D pre processes after the execution of the task C. Be started.
  • the subtasks D p0 to D p3 can be assigned to the four cores 1 to 4 to start processing at the same time.
  • the parallelized subtask D post can be started thereafter. Further, the core 1 can resume the execution of the suspended task B.
  • task F which has a task control cycle of 50 ms and is being executed in core 3, suspends the processing once parallel processing can be started. Then, the core 3 starts executing the subtask D p2 which is the target of the parallelization process. After the end of sub D p3 , the processing of task F, which has been suspended, is restarted in core 3.
  • task F can be decomposed into subtasks for parallel processing (see FIG. 7), it can be the target of parallel processing.
  • the task F has a long task control cycle, and therefore has a lower priority than the tasks A to E. Therefore, the processing can be ended within a predetermined task control cycle without executing the parallelization processing. Therefore, in the example of FIG. 12, the task F does not execute the subtask parallelization process. In this way, even for tasks that can be parallelized, it is possible to choose not to execute parallelization if it is possible to complete the processing within a predetermined task control cycle.
  • the priority of the subtasks Fp can be set lower than the priority of the task F before the division.
  • ⁇ Modification 1> 13 to 15 show a modified example 1 of the first embodiment.
  • This modification 1 assumes a case where an interrupt task H occurs during processing in the cores 1 to 4 of the parallelization target subtasks D p0 to D p3 , and FIG. 13 shows an example of the time chart. ..
  • the task H When the task H occurs, the task H is executed by interrupting the execution of the subtask D p3 in the core 4, for example.
  • the task H which is an event-driven processing task, is randomly generated in response to the occurrence of an event regardless of the task control cycle, unlike the tasks A to G having a task control cycle. Therefore, it is difficult for the designer to design the execution timing of the task H in advance. Note that the priority of the task H can be generally set higher than that of other tasks in order to enable execution of the task H on an occurrence basis.
  • the post- parallelization subtask D post can be executed after the completion of the parallelization target subtask D p . Therefore, if the execution start time of the task D post is delayed due to the operation of the task H, as a result, the processing for the tasks A to E may not be completed during the task control cycle, and a time constraint violation may occur (FIG. 13). reference).
  • the priority of the parallelization target subtask D p is set. Is changed to a higher priority P high as compared with the pre-parallelization processing subtask and the post-parallelization processing tab task.
  • This priority P high is set higher than the priority of the event driven processing task H.
  • the priorities before the parallelization are inherited and the priorities are adjusted in relation to other tasks A to C, E to H, and the like. You can For example, if there is another task that has a higher priority than the original task D, the priority can be adjusted so that that task is given priority and executed.
  • the parallelization target subtasks D p0 to D p3 the execution fluctuation when the operation inhibition by another task occurs directly leads to the violation of the execution time constraint. Therefore, only the parallelization target subtasks D p0 to D p3 are given the highest possible priority. This makes it possible to guarantee the operation of a series of tasks including the parallelization target subtask.
  • FIG. 16 shows a modification 2 of the first embodiment.
  • This modified example 2 shows an example in which the interrupt task H occurs during the processing in the cores 1 to 4 of the tasks A to G as in the modified example 1.
  • the task allocation unit 103 is configured to use the core 5 only for processing the interrupt task H when the interrupt task H occurs.
  • a dedicated core for task H When applying the first embodiment, if it is not possible to block the operation of task H, which is an event-driven process, it is possible to define a dedicated core for task H separately.
  • a multi-core processor 102 having two kinds of core groups (cores 1 to 4) for processing tasks A to G having a task control cycle and a core group (core 5) dedicated to event driven processing is used. be able to.
  • the multi-core processor 102 has such a configuration, the overall processor usage efficiency may be reduced by separately providing the event-driven processing dedicated core (core 5).
  • the parallelization target subtask is described as one case, and in this case, the parallelization target subtask can be given the highest priority.
  • the parallelization target subtask can be given the highest priority.
  • the above embodiment has been described on the premise that the multi-core processor 102 has one core type.
  • the method of this embodiment can be applied to a heterogeneous multi-core or many-core processor having a plurality of types of cores in one chip.
  • the tasks A to G having the task control cycle have a high processing load with respect to the task H which is the event driven processing, and the case where the frequency of appearance of the task H which is the event driven processing is low, such a heterogeneous core is used.
  • a heterogeneous core is used.
  • FIG. 17 is a schematic block diagram showing the components related to the arithmetic processing in the arithmetic control device of the multi-core processor according to the second embodiment.
  • the same parts as those in the first embodiment (FIG. 1) are designated by the same reference numerals in FIG. 17 as in FIG.
  • the parameter assignment unit 101 does not have the task priority parameter storage unit 1012, and instead, a dead deadline indicating an absolute deadline, which is the time when each task should absolutely complete processing.
  • a deadline parameter storage unit 1014 that stores line parameters is provided. That is, in the second embodiment, when a certain task is decomposed into subtasks and parallel processing is executed, the absolute deadline is changed instead of increasing the priority of the subtask, and the parameter is set as a parameter. It is supposed to be remembered. By changing the absolute deadline of a subtask to be parallelized, a task with a close absolute deadline is preferentially executed, and as a result, it becomes possible to comply with the time constraint of task execution.
  • the absolute deadline which is the absolute deadline
  • the absolute deadline is generated and stored as a parameter, but instead of the absolute deadline, for example, a relative time from the start time of the task control cycle is generated and stored as a deadline. It is also possible.
  • FIG. 18 is a table showing various parameters for each task generated based on the source code of the software component in the second embodiment.
  • the absolute deadline can be made shorter than the absolute deadline of the original task D.
  • the absolute deadline is set back to 20 ms by calculating backward from the calculation limit time, and is set shorter than the original absolute deadline (30 ms).
  • the execution of the interrupt task H makes it difficult to guarantee the deadline of the parallelization target subtasks D p0 to D p3 .
  • cores for processing tasks having a task control cycle and cores (cores dedicated to processing event-driven processing tasks (cores) are used. It is also possible to adopt a multi-core processor having two types of 5). When such a configuration is adopted, there is a demerit that the overall processor usage efficiency decreases by providing a dedicated event-driven processing core, but the predictability of task behavior on a multi-core processor is improved and the cycle constraint is satisfied. It becomes possible to guarantee.
  • Information such as a program, a table, and a file that realizes each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.
  • SSD Solid State Drive
  • a recording medium such as an IC card, an SD card, or a DVD.
  • a combination of a task group with a control period of 30 ms, a task group with a control period of 50 ms, and an event driven task is shown, but the present invention is not limited to this.
  • the present invention reduces the fluctuation of the processing time by changing the processing priority of the task generated by parallelization regardless of the existence of a plurality of types of control cycles, different deadline times, the presence or absence of event-driven processing, etc. It is possible to increase the guarantee possibility of the execution time constraint.
  • SYMBOLS 1 Arithmetic control device, 101... Parameter providing part, 1011... Task control period parameter storage part, 1012... Task priority parameter storage part, 1013... Task dependency parameter storage part, 1014... Deadline parameter storage part, 102... Multi-core Processors 1021, 1022... Core, 103... Task assigning unit.

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Abstract

L'invention concerne un système qui utilise un processeur ayant une pluralité de cœurs, des fluctuations de temps de traitement pouvant être réduites lorsque différents processus sont effectués simultanément dans la pluralité de cœurs, ce qui améliore la prévisibilité de comportement du système et augmente la probabilité de garantir des contraintes de temps d'exécution. Un dispositif de commande arithmétique selon l'invention comprend un processeur ayant une pluralité de cœurs et une unité d'attribution de tâche qui attribue une tâche à la pluralité de cœurs. L'unité d'attribution de tâche détermine s'il est possible ou non d'effectuer un traitement parallèle sur une pluralité de sous-tâches constituant la tâche et, si un traitement parallèle est possible, l'unité d'attribution de tâche attribue la pluralité de sous-tâches à la pluralité de cœurs dans des conditions prescrites.
PCT/JP2019/046724 2018-12-12 2019-11-29 Dispositif de commande arithmétique WO2020121840A1 (fr)

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JP7188693B2 (ja) 2018-09-12 2022-12-13 国立研究開発法人物質・材料研究機構 グラフェンを用いた電極、その製造方法およびそれを用いた蓄電デバイス

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