WO2019181279A1 - Chip position measurement device - Google Patents

Chip position measurement device Download PDF

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Publication number
WO2019181279A1
WO2019181279A1 PCT/JP2019/004973 JP2019004973W WO2019181279A1 WO 2019181279 A1 WO2019181279 A1 WO 2019181279A1 JP 2019004973 W JP2019004973 W JP 2019004973W WO 2019181279 A1 WO2019181279 A1 WO 2019181279A1
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WO
WIPO (PCT)
Prior art keywords
chip
imaging
unit
substrate
divided
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PCT/JP2019/004973
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French (fr)
Japanese (ja)
Inventor
比佐史 山本
浩平 岡
Original Assignee
東レエンジニアリング株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 東レエンジニアリング株式会社 filed Critical 東レエンジニアリング株式会社
Priority to CN201980007898.6A priority Critical patent/CN111587358B/en
Publication of WO2019181279A1 publication Critical patent/WO2019181279A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment

Definitions

  • the present invention relates to a chip position measuring apparatus that measures the position of each of a plurality of chip components spaced apart on a substrate such as a wafer.
  • chip components are placed on a substrate such as semiconductor wafer, glass, or resin (for example, patterning or mounting), or diced chip components are picked up from the expanded wafer. There is a process. Then, a process of inspecting whether these chip parts are arranged with a predetermined accuracy, or measuring a position where the chip parts are held, and mounting / stacking these chip parts and other parts, wiring, etc. (For example, Patent Documents 1 to 3).
  • JP-A-10-189672 JP 2006-135237 A Japanese Patent No. 4776831
  • the position of each chip component can be measured by measuring the relative position (XY coordinates, etc.) with the reference mark. Therefore, the positioning accuracy required for the stage mechanism is not excessively required.
  • the position of each chip component is determined based on the stationary position information of the location where the divided field of view is captured and the position information of the chip component in the divided field of view.
  • the position needs to be measured. For this reason, an imaging position accuracy higher than that of chip measurement is required, and it is necessary to use a high-accuracy stage using a laser length measuring device or the like.
  • An object of the present invention is to provide an apparatus capable of measuring the position of a part.
  • a chip position measuring device that measures the position of each of a plurality of chip components spaced apart on a substrate, A substrate holder for holding the substrate; An imaging unit that divides a predetermined area set on the substrate into a plurality of divided imaging areas and images the image; A chip position calculation unit that calculates the position of each chip component included in the divided imaging area based on an image captured by the imaging unit; A relative movement unit that relatively moves the substrate holding unit and the imaging unit; A control unit that drives and controls the relative movement unit and outputs an imaging trigger to the imaging unit while changing the location of the divided imaging area set on the substrate;
  • the divided imaging area includes at least two or more chip parts, and at least one chip part among the chip parts is set as an overlapping imaging chip part included in both adjacent divided imaging areas.
  • the chip position calculator Calculate the position of each overlapping imaging chip component from the positional relationship with other chip components included in the divided imaging area previously imaged, The position of each of the other chip components excluding the overlapping imaging chip component included in the divided imaging area that is imaged later is calculated from the positional relationship with the overlapping imaging chip component.
  • the position of the chip component can be measured with higher accuracy than the positioning accuracy of the positioning mechanism.
  • the three axes of the orthogonal coordinate system are represented as X, Y, and Z
  • the horizontal direction is represented as the X direction and the Y direction
  • the direction perpendicular to the XY plane that is, the gravitational direction
  • the Z direction is expressed as the direction against gravity and the direction in which gravity works as down.
  • a direction rotating around the Z direction as a central axis is defined as a ⁇ direction.
  • FIG. 1 is a schematic diagram showing an overall configuration of an example of a form embodying the present invention.
  • FIG. 1 schematically shows each part of a chip position measuring apparatus 1 according to the present invention.
  • the chip position measuring apparatus 1 measures the position of each of a plurality of chip components C that are spaced apart from each other on the substrate W.
  • the chip position measuring apparatus 1 includes a substrate holding unit 2, an imaging unit 3, a relative moving unit 4, a chip position calculating unit 5, a control unit CN, and the like.
  • the substrate holding unit 2 holds the substrate W.
  • the substrate holding part 2 supports the substrate W while maintaining a horizontal state from the lower surface side.
  • the substrate holding part 2 includes a substrate mounting table 20 having a horizontal upper surface.
  • the substrate mounting table 20 is provided with a groove and a hole at a portion in contact with the substrate W, and the groove and the hole are connected to a negative pressure generating means such as a vacuum pump via a switching valve.
  • maintenance part 2 can hold
  • the imaging unit 3 divides a predetermined area set on the substrate W into a plurality of divided imaging areas for imaging.
  • the predetermined area set on the substrate W is an area (in other words, a large area) that includes all the chip components to be position-measured arranged on the substrate W.
  • the imaging unit 3 divides the predetermined area into a plurality of divided imaging areas (in other words, a small area, also referred to as a local area) and captures an image.
  • the size and position of the divided imaging area are different from each other in the type of chip parts (number, pitch, etc.) and required measurement accuracy, and are associated with each type and registered in the control unit CN or the like.
  • the imaging unit 3 includes a lens barrel 30, an illumination unit 31, a half mirror 32, objective lenses 33a and 33b, a revolver mechanism 34, an imaging camera 35, and the like.
  • the lens barrel 30 fixes the illumination unit 31, the half mirror 32, the objective lenses 33a and 33b, the revolver mechanism 34, the imaging camera 35, and the like in a predetermined posture, and guides illumination light and observation light.
  • the lens barrel 30 is attached to the apparatus frame 1f via a connection fitting or the like (not shown).
  • the illumination unit 31 emits illumination light L1 necessary for imaging.
  • the illumination unit 31 may be a laser diode, a metal halide lamp, a xenon lamp, an LED illumination, or the like.
  • the half mirror 32 reflects the illumination light L1 emitted from the illumination unit 31 to irradiate the substrate W side, and allows the light (reflected light, scattered light) L2 incident from the substrate W side to pass to the imaging camera 35 side. It is.
  • the objective lenses 33a and 33b form images of the imaging area on the workpiece W on the imaging camera 35 at different predetermined observation magnifications.
  • the revolver mechanism 34 switches which of the objective lenses 33a and 33b is used. Specifically, the revolver mechanism 34 rotates and stops by a predetermined angle based on manual or external signal control.
  • the imaging camera 35 captures an imaging area F on the workpiece W and acquires an image. The acquired image is output to the outside (in the present invention, a chip position calculation unit whose details will be described later) as a video signal or video data.
  • the relative movement unit 4 relatively moves the substrate holding unit 2 and the imaging unit 3.
  • the relative movement unit 4 includes an X-axis slider 41, a Y-axis slider 42, and a rotation mechanism 43.
  • the X-axis slider 41 is mounted on the device frame 1f, and moves the Y-axis slider 42 in the X direction at an arbitrary speed and stops it at an arbitrary position.
  • the X-axis slider includes a pair of rails extending in the X direction, a slider portion that moves on the rails, and a slider drive unit that moves and stops the slider portion.
  • the slider drive unit can be configured by a combination of a servo motor or a pulse motor that rotates and stops by signal control from the control unit CN and a ball screw mechanism, a linear motor mechanism, or the like.
  • the X-axis slider 41 is provided with an encoder for detecting the current position and movement amount of the slider portion. Examples of this encoder include a linear member called a linear scale in which fine irregularities are carved at a predetermined pitch, and a rotary encoder that detects a rotation angle of a motor that rotates a ball screw.
  • the Y-axis slider 42 moves the rotation mechanism 43 at an arbitrary speed in the Y direction based on a control signal output from the control unit CN and stops at an arbitrary position.
  • the Y-axis slider includes a pair of rails extending in the Y direction, a slider portion that moves on the rails, and a slider drive unit that moves and stops the slider portion.
  • the slider drive unit can be configured by a combination of a servo motor or a pulse motor that rotates and stops by signal control from the control unit CN and a ball screw mechanism, a linear motor mechanism, or the like.
  • the Y-axis slider 42 is provided with an encoder for detecting the current position and movement amount of the slider portion. Examples of this encoder include a linear member called a linear scale in which fine irregularities are carved at a predetermined pitch, and a rotary encoder that detects a rotation angle of a motor that rotates a ball screw.
  • the rotating mechanism 43 rotates the substrate mounting table 20 in the ⁇ direction at an arbitrary speed and stops at an arbitrary angle.
  • the rotation mechanism 43 can be exemplified by a mechanism that rotates / stops at an arbitrary angle by signal control from an external device, such as a direct drive motor.
  • an external device such as a direct drive motor.
  • the substrate mounting table 20 of the substrate holding unit 2 is attached.
  • the relative movement unit 4 Since the relative movement unit 4 has such a configuration, the substrate W is held in the XY ⁇ direction independently of the imaging unit 3 while holding the substrate W to be inspected, or in combination, in a predetermined manner. They can be moved relative to each other at a speed or angle, or can be stopped at an arbitrary position / angle.
  • the controller CN has the following functions and roles, for example. -Holding / releasing control of the substrate W with respect to the substrate holding unit 2-Switching the objective lens by controlling the revolver mechanism 34-Outputting an imaging trigger to the imaging camera 35-Drive control of the relative moving unit 4: A function to output a driving signal while monitoring the current position of the X-axis slider 41, the Y-axis slider 22, and the rotation mechanism 23, registration of an imaging position, switching of board types
  • control unit CN can drive and control the relative moving unit 4 and can output an imaging trigger to the imaging unit 3 while changing the location of the divided imaging area set on the substrate W. Furthermore, an imaging trigger can be output while switching the imaging magnification and field of view size and changing the imaging interval according to the inspection type, and a desired divided captured image can be acquired.
  • the imaging trigger output can be exemplified by the following method.
  • a method of emitting illumination light L1 for a very short time (so-called strobe light emission) every time a predetermined distance is moved while scanning in the X direction.
  • a method of moving and stopping at a predetermined position and irradiating the illumination light L1 to take an image (so-called step and repeat) method.
  • the imaging trigger means an instruction for capturing an image to the imaging camera 35 or an image processing apparatus (not shown), an instruction for emitting the illumination light L1, and the like.
  • an imaging trigger (Case 1) the illumination light L1 is flashed or (Case 2) the illumination light L1 is emitted during the time (so-called exposure time) that can be imaged by the imaging camera 35. Or take an image within the given time.
  • the imaging trigger is not limited to an instruction to the imaging camera 35 (Case 3), but may be an image capture instruction to an image processing apparatus that acquires an image. By doing so, it is possible to cope with a form in which video signals and video data are sequentially output from the imaging camera 35.
  • control unit CN is configured by a computer, a programmable logic controller or the like (that is, hardware), and an execution program or the like (that is, software). Further, the control unit CN includes a chip position calculation unit 5, a scaling correction unit 6 and the like according to the present invention as a part of functional blocks configured by hardware and software.
  • FIG. 2 is a conceptual diagram showing a state of imaging in an example of a form embodying the present invention.
  • the imaging camera 45 of the imaging unit 3 moves relative to the substrate W in the direction indicated by the arrow Vs, and is separated from the plurality of chip components C (1, 1) to C on the substrate W.
  • a state in which C (9, 2) is imaged is shown.
  • imaging is performed in the order of the divided imaging areas F (1), F (2), F (3), and F (4).
  • the divided imaging area F (1) the chip component C (1, 1 ) To C (3, 2) are picked up, chip parts C (3, 1) to C (5, 2) are picked up in the divided image pickup area F (2), and chip parts C are picked up in the divided image pickup area F (3).
  • (5,1) to C (7,2) are imaged, and chip parts C (7,1) to C (9,2) are imaged in the divided imaging area F (4).
  • the divided imaging area F (1) and the divided imaging area F (2) are set so that not only are adjacent to each other, but also a part of the area is overlapped and imaged.
  • An area that is adjacently overlapped and imaged is referred to as an overlapped imaging area M (1).
  • the overlapping imaging area of the divided imaging area F (2) and the divided imaging area F (3) is M (2)
  • the overlapping imaging area of the divided imaging area F (3) and the divided imaging area F (4) is M ( 3).
  • the divided imaging area includes at least two or more chip components, and at least one of the chip components is set as an overlapping imaging chip component included in both adjacent divided imaging areas. ing.
  • the overlapping imaging region M (1) includes chip components C (3, 1) and C (3, 2)
  • the overlapping imaging region M (2) includes the chip component C (5, 5). 1), C (5, 2), and the divided imaging area F (1) so that the overlapping imaging area M (3) includes the chip parts C (7, 1), C (7, 2).
  • the imaging positions of F to (4) are set.
  • the chip position calculation unit 5 calculates the position of each chip component included in the divided imaging area based on the image captured by the imaging unit 3. Further, the chip position calculation unit 5 calculates the position of each overlapping imaging chip component from the positional relationship with the other chip components included in the divided imaging area previously captured, and the divided imaging area captured later. The position of each of the other chip components excluding the overlapping imaging chip component included in is calculated from the positional relationship with the overlapping imaging chip component.
  • FIG. 3 is a plan view showing the positional relationship of each chip component in an example embodying the present invention.
  • FIG. 3 illustrates the positional relationship between the divided imaging areas F (1) and F (2) and the chip components C (1,1) to C (5,2).
  • the chip position calculation unit 5 calculates the mutual positions of the chip components C (1,1) to C (3,2) included in the captured divided imaging area F (1). For example, the following is calculated based on the position of the lower left corner of each chip component.
  • the chip position calculation unit 5 calculates the position of each chip component based on the following calculation formula.
  • the position (X21, Y21) of the chip component C (2, 1) (X11 + dx1, Y11 + dy1)
  • the position (X31, Y31) of the chip component C (3, 1) (X11 + dx1 + dx2, Y11 + dy1 + dy2)
  • the position (X12, Y12) of the chip component C (1, 2) (X11 + dx20, Y11 + dy20)
  • the position (X22, Y22) of the chip component C (2, 2) (X11 + dx20 + dx21, Y11 + dy20 + dy21)
  • the position (X32, Y32) of the chip part C (3, 2) (X11 + dx20 + dx21 + dx22, Y11 + dy21)
  • the mutual positions of the chip components C (3, 1) to C (5, 2) included in the imaged divided imaging area F (2) are calculated. As described above, the following is calculated based on the position of the lower left corner of each chip component.
  • the chip position calculation unit 5 calculates each position based on the following calculation formula. Since the positions of the chip part C (3, 1) and the chip part C (3, 2) are as described above, the position of the chip part C (4, 1) is (X11 + dx1 + dx2 + dx3, Y11 + dy1 + dy2 + dy3) The position of the chip component C (5, 1) is (X11 + dx1 + dx2 + dx3 + dx4, Y11 + dy1 + dy2 + dy3 + dy4) The position of the chip part C (4, 2) is (X11 + dx20 + dx21 + dx22 + dx23, Y11 + dy20 + dy21 + dy22 + dy23) The position of the chip part C (5, 2) is (X11 + dx20 + dx21 + dx22 + dx23 + dx24, Y11 + dy
  • the chip position measuring apparatus 1 can calculate the position of each of the other chip components based on the position of one chip component included in the first imaging area. it can.
  • FIG. 4 is a plan view showing the positional relationship between chip components in another example embodying the present invention.
  • FIG. 4 illustrates the positional relationship between the divided imaging areas F (1) and F (2) and the chip components C (1,1) to C (5,2).
  • the chip position calculation unit 5 performs chip parts C (1,1), C (2,1), C (5) included in the divided imaging area F (1) that has been imaged as follows. , 1), C (6, 1), etc. can be calculated.
  • the position (X21, Y21) of the chip part C (2, 1) is based on the amount of deviation dx1 in the X direction and the amount of deviation dy1 in the Y direction of the chip part C (2, 1) with respect to the chip part C (1, 1).
  • (X21, Y21) (X11 + dx1, Y11 + dy1)
  • the position (X51, Y51) of the chip part C (5, 1) is based on the amount of deviation dx4 in the X direction and the amount of deviation dy4 in the Y direction of the chip part C (5, 1) with respect to the chip part C (1, 1).
  • (X51, Y51) (X11 + dx4, Y11 + dy4)
  • the position (X61, Y61) of the chip part C (6, 1) is based on the amount of deviation dx5 in the X direction and the amount of deviation dy5 in the Y direction of the chip part C (6, 1) with respect to the chip part C (1, 1).
  • (X51, Y51) (X11 + dx5, Y11 + dy5)
  • the chip position calculation unit 5 performs chip parts C (6, 1), C (7, 1), C (11, 1) included in the divided imaging area F (2) that has been imaged as follows. And so on.
  • the position (X71, Y71) of the chip part C (7, 1) is based on the amount of deviation dx6 in the X direction and the amount of deviation dy6 in the Y direction of the chip part C (7, 1) with respect to the chip part C (6, 1).
  • (X71, Y71) (X61 + dx6, Y61 + dy6)
  • the position (X111, Y111) of the chip part C (11, 1) is based on the amount of deviation dx10 in the X direction and the amount of deviation dy10 in the Y direction of the chip part C (11, 1) with respect to the chip part C (6, 1).
  • (X111, Y111) (X61 + dx10, Y61 + dy10)
  • a configuration including a scaling correction unit is adopted. Then, the chip calculated by the chip position calculation unit based on the mutual position of the reference marks arranged on the master substrate is held by the substrate holding unit a master substrate in which the mutual positions of a plurality of reference marks are known Correction for the position of each part is performed.
  • FIG. 5 is a plan view showing a positional relationship between the master substrate and the divided imaging area in another example embodying the present invention.
  • FIG. 5 illustrates a plan view of the master substrate MW in which the mutual positions of the plurality of reference marks FMa, FMk, FMq, and FMz are known.
  • the reference marks FMa and FMk are observed in the field of view of the divided imaging areas F (a) and F (k). It has become the arrangement.
  • Each of the reference marks FMa and FMk is circular, and the centers of these circles are arranged at an interval Rxm in the X direction.
  • the distance dxm is an accurate position (also referred to as a relative distance or relative coordinate) by a highly accurate length measuring device (for example, a combination of a moving mechanism using a laser interferometer and a mark position detecting device). Is known. Specifically, the following description will be made assuming that the interval Rxm is 100.00 mm.
  • the mutual position of the chip component C (a, 1) observed in the divided imaging area F (a) and C (k, 1) observed in the divided imaging area F (k) is the chip position calculation unit 5.
  • the distance dxk in the X direction is 100.10 mm.
  • the amount of deviation in the X direction of the chip part C (a, 1) with respect to the reference mark FMa is ⁇ xa
  • the amount of deviation in the X direction of the chip part C (k, 1) with respect to the reference mark FMk is ⁇ xk. It is assumed that ⁇ xa is 0.01 mm and ⁇ xk is 0.01 mm, for example, as calculated by the chip position calculation unit 5. Then, the chip position calculation unit 5 calculates the distance dxm between the reference marks FMa and FMk as 100.12 mm.
  • the scaling correction for the chip part C (k, 1) is exemplified.
  • the scaling correction coefficient calculated in this way can also be applied to the calculation of the position of another chip part.
  • the procedure for performing the scaling correction in the X direction has been described above, the scaling correction coefficient is calculated in the same manner in the Y direction (in the case of the Y direction, based on the interval Ryq between the reference marks FMa and FMq). The position in the Y direction of each chip component can be calculated in consideration of this scaling correction coefficient.
  • the orthogonality is corrected using the master substrate MW.
  • the center positions of the reference marks FMa, FMk, FMq, and FMz are arranged at the vertices of a rectangle or square rectangle of vertical Ryq ⁇ horizontal Rxm. Therefore, the X-axis slider 41 and the Y-axis slider 42 of the relative movement unit 4 are moved, and the reference marks FMa, FMk, FMq, and FMz are imaged by the imaging unit 3, and the respective center positions are acquired.
  • the chip position calculation unit 5 corrects and calculates the position of each chip component so that the deviation amount due to the orthogonality is canceled.
  • the position of each chip component calculated by the chip position calculation unit 5 is determined by the position measurement caused by the deviation of the orthogonality between the X-axis slider 41 and the Y-axis slider 42 of the relative movement unit 4. Errors can be reduced or prevented.
  • the straightness also referred to as straightness and straightness
  • the device configuration may meander slightly in the direction orthogonal to the moving direction, and the divided imaging area may be inclined in the ⁇ direction.
  • the X direction and the Y direction in the divided imaging area include an error that occurs due to a shift in the ⁇ direction, which may cause an influence on the position measurement of each chip component.
  • the divided imaging area includes at least two rows of the chip parts, and It is preferable that at least one row of chip components among the chip components is set as an overlapping imaging chip component included in both of the adjacent divided imaging areas.
  • the chip position calculation unit 5 calculates the position of each of the other chip components excluding the overlapping imaging chip components included in the divided imaging area captured later, the positional relationship between the plurality of overlapping imaging chip components (that is, X).
  • the deviation component in the ⁇ direction is calculated from the direction and the position in the Y direction, and the deviation component is corrected to calculate the position of each chip component.
  • FIG. 4 shows an example in which a single chip component is arranged (FIG. 4), and a detailed description is given while illustrating a mode in which chip components in one vertical column are imaged in both adjacent divided imaging areas as overlapping imaging chips. did.
  • the present invention can be applied by appropriately increasing or decreasing the number of vertical and horizontal chip parts.
  • the number of vertical and horizontal chip parts is increased (for example, set to 30 ⁇ 40)
  • the number of substrates that can be processed per unit time can be increased.
  • the imaging visual field size can be narrowed (also referred to as increasing the imaging magnification)
  • the pixel resolution can be increased, and the measurement accuracy can be improved.
  • At least two chips are included in one divided imaging area, and one of them may be set as an overlapping imaging chip.
  • the divided imaging areas F (1), F (2), F (3), F ( In the order of 4), a specific procedure for measuring the position of each chip component included in the divided imaging area while changing the divided imaging area in the X direction is shown.
  • the overlapping imaging area is set in the X direction and relatively moved in the X direction, but the overlapping imaging area is set in the Y direction and relatively moved in the Y direction.
  • the position of each of the other chip components may be calculated based on the positional relationship between the overlapping imaging chips included in the captured image. Alternatively, as illustrated in FIG.
  • the overlapping imaging regions M (1) to M (4) are set in both the XY directions, and the chip position calculation unit 5 calculates the position of each chip component as follows. You can also. Calculate the position of each of the chip components C (1,1) to C6,2) in the divided imaging area F (1) with reference to the position of C (1,1). Calculate the positions of the chip components C (7, 1) to C11, 2) in the divided imaging area F (2) with reference to the position of C (6, 1) or the like. Calculate the positions of the chip components C (6, 4) to C (11, 5) in the divided imaging area F (m) with reference to the position of C (6, 3) or the like. Calculate the positions of the chip components C (1, 4) to C (5, 5) in the divided imaging area F (m + 1) with reference to the position of C (6, 3) or the like.
  • the coaxial falling method is exemplified as the illumination unit 31.
  • transmission illumination oblique illumination, ring illumination, dome illumination, and the like may be used.

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Abstract

Provided is a device capable of measuring the position of a chip component with high accuracy without using a very highly accurate positioning mechanism even when no reference mark as a positioning reference is included in a visual field obtained by division imaging. Specifically, the chip position measurement device is provided with a substrate holding part, an imaging unit that performs imaging so as to achieve division into a plurality of division imaging areas, a chip position calculation unit that calculates the position of a chip component, a relatively moving unit, and a control unit, wherein: the division imaging areas each include two or more chip components, and at least one of the chip components is set as a redundantly imaged chip component which is included in both adjacent division imaging areas; and the chip position calculation unit calculates the position of each of the redundantly imaged chip components, from the positional relationship with respect to the other chip components included in a previously imaged division imaging area, and calculates the position of each of the other chip components which are included in a subsequently imaged division imaging area and which are other than the redundantly imaged chip components, from the positional relationship with respect to the redundantly imaged chip components.

Description

チップ位置測定装置Chip position measuring device
　本発明は、ウエーハなどの基板上に離間配置された複数のチップ部品それぞれの位置を測定するチップ位置測定装置に関するものである。 The present invention relates to a chip position measuring apparatus that measures the position of each of a plurality of chip components spaced apart on a substrate such as a wafer.
　半導体デバイスや電子デバイス等の製造工程では、半導体ウエーハやガラス、樹脂などの基板上にチップ部品を配置（例えば、パターニングや実装など）したり、エキスパンドされたウエーハからダイシング済のチップ部品をピックアップしたりする工程がある。そして、これらチップ部品が所定の精度で配置されているか良否検査したり、どの位置に保持されているか位置測定して、これらチップ部品と他の部品や配線等を実装・積層等させたりする工程がある（例えば、特許文献１～３）。 In the manufacturing process of semiconductor devices and electronic devices, chip components are placed on a substrate such as semiconductor wafer, glass, or resin (for example, patterning or mounting), or diced chip components are picked up from the expanded wafer. There is a process. Then, a process of inspecting whether these chip parts are arranged with a predetermined accuracy, or measuring a position where the chip parts are held, and mounting / stacking these chip parts and other parts, wiring, etc. (For example, Patent Documents 1 to 3).
特開平１０－１８９６７２号公報JP-A-10-189672 特開２００６－１３５２３７号公報JP 2006-135237 A 特許第４７６８７３１号号公報Japanese Patent No. 4776831
　分割撮像した視野内に位置決め基準の参照用マークがあれば、参照マークとの相対位置（ＸＹ座標など）を測定することで、チップ部品それぞれの位置を測定することができる。そのため、ステージ機構に求められる位置決め精度は、過度に要求されない。 If there is a positioning reference mark in the divided image field of view, the position of each chip component can be measured by measuring the relative position (XY coordinates, etc.) with the reference mark. Therefore, the positioning accuracy required for the stage mechanism is not excessively required.
　しかし、分割撮像した視野内に位置決め基準の参照用マークが無い場合、分割視野内を撮像する場所の静止位置情報と、当該分割視野内のチップ部品の位置情報に基づいて、それぞれのチップ部品の位置を測定する必要がある。そのため、チップ測定の位置精度よりも高精度な撮像位置精度が求められ、レーザ測長器等を用いた高精度なステージを用いる必要があった。 However, if there is no positioning reference mark in the divided field of view, the position of each chip component is determined based on the stationary position information of the location where the divided field of view is captured and the position information of the chip component in the divided field of view. The position needs to be measured. For this reason, an imaging position accuracy higher than that of chip measurement is required, and it is necessary to use a high-accuracy stage using a laser length measuring device or the like.
　そこで本発明は、上記問題点に鑑みてなされたものであり、分割撮像した視野内に位置決め基準の参照用マークが無い場合でも、さほど高精度な位置決め機構を用いるまでも無く、高精度でチップ部品の位置を測定できる装置を提供することを目的としている。 Accordingly, the present invention has been made in view of the above problems, and even when there is no reference mark for positioning reference in the divided image field of view, there is no need to use a highly accurate positioning mechanism, and the chip is highly accurate. An object of the present invention is to provide an apparatus capable of measuring the position of a part.
　以上の課題を解決するために、本発明に係る一態様は、
　基板上に離間配置された複数のチップ部品それぞれの位置を測定するチップ位置測定装置であって、
　基板を保持する基板保持部と、
　基板上に設定された所定領域を複数の分割撮像エリアに分割して撮像する撮像部と、
　撮像部で撮像された画像に基づいて、分割撮像エリア内に含まれるチップ部品それぞれの位置を算出するチップ位置算出部と、
　基板保持部と撮像部とを相対移動させる相対移動部と、
　相対移動部を駆動制御すると共に、基板上に設定された分割撮像エリアの場所を変更しながら撮像部に対して撮像トリガを出力する制御部とを備え、
　分割撮像エリアには少なくとも２つ以上のチップ部品が含まれ、かつ、当該チップ部品のうち少なくとも１つのチップ部品が、隣接する分割撮像エリアの双方に含まれた重複撮像チップ部品として設定されており、
　チップ位置算出部は、
重複撮像チップ部品それぞれの位置を、先に撮像された分割撮像エリアに含まれた他のチップ部品との位置関係から算出し、
後に撮像した分割撮像エリアに含まれる重複撮像チップ部品を除く他のチップ部品それぞれの位置を、当該重複撮像チップ部品との位置関係から算出する
ことを特徴としている。 In order to solve the above problems, an aspect of the present invention is as follows.
A chip position measuring device that measures the position of each of a plurality of chip components spaced apart on a substrate,
A substrate holder for holding the substrate;
An imaging unit that divides a predetermined area set on the substrate into a plurality of divided imaging areas and images the image;
A chip position calculation unit that calculates the position of each chip component included in the divided imaging area based on an image captured by the imaging unit;
A relative movement unit that relatively moves the substrate holding unit and the imaging unit;
A control unit that drives and controls the relative movement unit and outputs an imaging trigger to the imaging unit while changing the location of the divided imaging area set on the substrate;
The divided imaging area includes at least two or more chip parts, and at least one chip part among the chip parts is set as an overlapping imaging chip part included in both adjacent divided imaging areas. ,
The chip position calculator
Calculate the position of each overlapping imaging chip component from the positional relationship with other chip components included in the divided imaging area previously imaged,
The position of each of the other chip components excluding the overlapping imaging chip component included in the divided imaging area that is imaged later is calculated from the positional relationship with the overlapping imaging chip component.
　上記の発明によれば、位置決め機構の位置決め精度よりも高精度で、チップ部品の位置を測定できる。 According to the above invention, the position of the chip component can be measured with higher accuracy than the positioning accuracy of the positioning mechanism.
本発明を具現化する形態の一例の全体構成を示す概略図である。It is the schematic which shows the whole structure of an example of the form which embodies this invention. 本発明を具現化する形態の一例における撮像の様子を示す概念図である。It is a conceptual diagram which shows the mode of the imaging in an example of the form which embodies this invention. 本発明を具現化する形態の一例におけるチップ部品それぞれの位置関係を示す平面図である。It is a top view which shows the positional relationship of each chip component in an example of the form which embodies this invention. 本発明を具現化する別の形態の一例におけるチップ部品それぞれの位置関係を示す平面図である。It is a top view which shows the positional relationship of each chip component in an example of another form which embodies this invention. 本発明を具現化する別の形態の一例におけるマスター基板と分割撮像エリアとの位置関係を示す平面図である。It is a top view which shows the positional relationship of the master board | substrate and division | segmentation imaging area in an example of another form which embodies this invention. 本発明を具現化する別の形態の一例における分割撮像エリアとチップ部品それぞれの位置関係を示す平面図である。It is a top view which shows the positional relationship of the division | segmentation imaging area and each chip component in an example of another form which embodies this invention.
　以下に、本発明を実施するための形態について、図を用いながら説明する。なお、以下の説明では、直交座標系の３軸をＸ、Ｙ、Ｚとし、水平方向をＸ方向、Ｙ方向と表現し、ＸＹ平面に垂直な方向（つまり、重力方向）をＺ方向と表現する。また、Ｚ方向は、重力に逆らう方向を上、重力がはたらく方向を下と表現する。また、Ｚ方向を中心軸として回転する方向をθ方向とする。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following description, the three axes of the orthogonal coordinate system are represented as X, Y, and Z, the horizontal direction is represented as the X direction and the Y direction, and the direction perpendicular to the XY plane (that is, the gravitational direction) is represented as the Z direction. To do. The Z direction is expressed as the direction against gravity and the direction in which gravity works as down. A direction rotating around the Z direction as a central axis is defined as a θ direction.
　図１は、本発明を具現化する形態の一例の全体構成を示す概略図である。図１には、本発明に係るチップ位置測定装置１を構成する各部が概略的に示されている。 FIG. 1 is a schematic diagram showing an overall configuration of an example of a form embodying the present invention. FIG. 1 schematically shows each part of a chip position measuring apparatus 1 according to the present invention.
　チップ位置測定装置１は、基板Ｗ上に離間配置された複数のチップ部品Ｃそれぞれの位置を測定するものである。具体的には、チップ位置測定装置１は、基板保持部２、撮像部３、相対移動部４、チップ位置算出部５、制御部ＣＮ等を備えている。 The chip position measuring apparatus 1 measures the position of each of a plurality of chip components C that are spaced apart from each other on the substrate W. Specifically, the chip position measuring apparatus 1 includes a substrate holding unit 2, an imaging unit 3, a relative moving unit 4, a chip position calculating unit 5, a control unit CN, and the like.
　基板保持部２は、基板Ｗを保持するものである。
具体的には、基板保持部２は、基板Ｗを下面側から水平状態を保ちつつ支えるものである。より具体的には、基板保持部２は、上面が水平な基板載置台２０を備えている。
基板載置台２０は、基板Ｗと接触する部分に溝部や孔部が設けられており、これら溝部や孔部は、切替バルブなどを介して真空ポンプなどの負圧発生手段と接続されている。そして、基板保持部２は、これら溝部や孔部を負圧状態若しくは大気解放状態に切り替えることで、基板Ｗを保持したり保持解除したりすることができる。 The substrate holding unit 2 holds the substrate W.
Specifically, the substrate holding part 2 supports the substrate W while maintaining a horizontal state from the lower surface side. More specifically, the substrate holding part 2 includes a substrate mounting table 20 having a horizontal upper surface.
The substrate mounting table 20 is provided with a groove and a hole at a portion in contact with the substrate W, and the groove and the hole are connected to a negative pressure generating means such as a vacuum pump via a switching valve. And the board | substrate holding | maintenance part 2 can hold | maintain and cancel | release holding | maintenance W by switching these groove parts and hole parts to a negative pressure state or an air release state.
　撮像部３は、基板Ｗ上に設定された所定領域を複数の分割撮像エリアに分割して撮像するものである。ここで言う、基板Ｗ上に設定された所定領域とは、基板Ｗ上に配置された位置測定対象となるチップ部品すべてが含まれる領域（換言すれば、大きな領域）である。そして、撮像部３は、この所定領域を複数の分割撮像エリア（換言すれば、小さな領域。局所領域とも言う）に分割して撮像するものである。
具体的には、分割撮像エリアのサイズや位置は、チップ部品の配列（個数やピッチなど）や要求測定精度が品種毎で異なり、それぞれの品種毎に紐付けて制御部ＣＮ等に登録されている。
より具体的には、撮像部３は、鏡筒３０、照明部３１、ハーフミラー３２、対物レンズ３３ａ，３３ｂ、レボルバー機構３４、撮像カメラ３５等を備えている。 The imaging unit 3 divides a predetermined area set on the substrate W into a plurality of divided imaging areas for imaging. Here, the predetermined area set on the substrate W is an area (in other words, a large area) that includes all the chip components to be position-measured arranged on the substrate W. Then, the imaging unit 3 divides the predetermined area into a plurality of divided imaging areas (in other words, a small area, also referred to as a local area) and captures an image.
Specifically, the size and position of the divided imaging area are different from each other in the type of chip parts (number, pitch, etc.) and required measurement accuracy, and are associated with each type and registered in the control unit CN or the like. Yes.
More specifically, the imaging unit 3 includes a lens barrel 30, an illumination unit 31, a half mirror 32, objective lenses 33a and 33b, a revolver mechanism 34, an imaging camera 35, and the like.
　鏡筒３０は、照明部３１、ハーフミラー３２、対物レンズ３３ａ，３３ｂ、レボルバー機構３４、撮像カメラ３５等を所定の姿勢で固定し、照明光や観察光を導光するものである。鏡筒３０は、連結金具など（不図示）を介して装置フレーム１ｆに取り付けられている。
照明部３１は、撮像に必要な照明光Ｌ１を放出するものである。具体的には、照明部３１は、レーザダイオードやメタルハライドランプ、キセノンランプ、ＬＥＤ照明などが例示できる。
ハーフミラー３２は、照明部３１から放出された照明光Ｌ１を反射させて基板Ｗ側に照射し、基板Ｗ側から入射した光（反射光、散乱光）Ｌ２を撮像カメラ３５側に通過させるものである。
対物レンズ３３ａ，３３ｂは、ワークＷ上の撮像エリアの像を、それぞれ異なる所定の観察倍率で撮像カメラ３５に結像させるものである。
レボルバー機構３４は、対物レンズ３３ａ，３３ｂのいずれを使用するか切り替えるものである。具体的には、レボルバー機構３４は、手動または外部からの信号制御に基づいて、所定の角度ずつ回転および静止するものである。
撮像カメラ３５は、ワークＷ上の撮像エリアＦを撮像し、画像を取得するものである。取得した画像は、映像信号や映像データとして外部（本発明では、詳細を後述するチップ位置算出部）に出力される。 The lens barrel 30 fixes the illumination unit 31, the half mirror 32, the objective lenses 33a and 33b, the revolver mechanism 34, the imaging camera 35, and the like in a predetermined posture, and guides illumination light and observation light. The lens barrel 30 is attached to the apparatus frame 1f via a connection fitting or the like (not shown).
The illumination unit 31 emits illumination light L1 necessary for imaging. Specifically, the illumination unit 31 may be a laser diode, a metal halide lamp, a xenon lamp, an LED illumination, or the like.
The half mirror 32 reflects the illumination light L1 emitted from the illumination unit 31 to irradiate the substrate W side, and allows the light (reflected light, scattered light) L2 incident from the substrate W side to pass to the imaging camera 35 side. It is.
The objective lenses 33a and 33b form images of the imaging area on the workpiece W on the imaging camera 35 at different predetermined observation magnifications.
The revolver mechanism 34 switches which of the objective lenses 33a and 33b is used. Specifically, the revolver mechanism 34 rotates and stops by a predetermined angle based on manual or external signal control.
The imaging camera 35 captures an imaging area F on the workpiece W and acquires an image. The acquired image is output to the outside (in the present invention, a chip position calculation unit whose details will be described later) as a video signal or video data.
　相対移動部４は、基板保持部２と撮像部３とを相対移動させるものである。
具体的には、相対移動部４は、Ｘ軸スライダー４１と、Ｙ軸スライダー４２と、回転機構４３とを備えて構成されている。 The relative movement unit 4 relatively moves the substrate holding unit 2 and the imaging unit 3.
Specifically, the relative movement unit 4 includes an X-axis slider 41, a Y-axis slider 42, and a rotation mechanism 43.
　Ｘ軸スライダー４１は、装置フレーム１ｆ上に取り付けられており、Ｙ軸スライダー４２をＸ方向に任意の速度で移動させ、任意の位置で静止させるものである。具体的には、Ｘ軸スライダーは、Ｘ方向に延びる１対のレールと、そのレール上を移動するスライダー部と、スライダー部を移動および静止させるスライダー駆動部とで構成されている。スライダー駆動部は、制御部ＣＮからの信号制御により回転し静止するサーボモータやパルスモータとボールネジ機構を組み合わせたものや、リニアモータ機構などで構成することができる。また、Ｘ軸スライダー４１には、スライダー部の現在位置や移動量を検出するためのエンコーダが備えられている。なお、このエンコーダは、リニアスケールと呼ばれる直線状の部材に細かな凹凸が所定ピッチで刻まれたものや、ボールネジを回転させるモータの回転角度を検出するロータリエンコーダ等が例示できる。 The X-axis slider 41 is mounted on the device frame 1f, and moves the Y-axis slider 42 in the X direction at an arbitrary speed and stops it at an arbitrary position. Specifically, the X-axis slider includes a pair of rails extending in the X direction, a slider portion that moves on the rails, and a slider drive unit that moves and stops the slider portion. The slider drive unit can be configured by a combination of a servo motor or a pulse motor that rotates and stops by signal control from the control unit CN and a ball screw mechanism, a linear motor mechanism, or the like. In addition, the X-axis slider 41 is provided with an encoder for detecting the current position and movement amount of the slider portion. Examples of this encoder include a linear member called a linear scale in which fine irregularities are carved at a predetermined pitch, and a rotary encoder that detects a rotation angle of a motor that rotates a ball screw.
　Ｙ軸スライダー４２は、制御部ＣＮから出力される制御信号に基づいて、回転機構４３をＹ方向に任意の速度で移動させ、任意の位置で静止させるものである。具体的には、Ｙ軸スライダーは、Ｙ方向に延びる１対のレールと、そのレール上を移動するスライダー部と、スライダー部を移動および静止させるスライダー駆動部とで構成されている。スライダー駆動部は、制御部ＣＮからの信号制御により回転し静止するサーボモータやパルスモータとボールネジ機構を組み合わせたものや、リニアモータ機構などで構成することができる。また、Ｙ軸スライダー４２には、スライダー部の現在位置や移動量を検出するためのエンコーダが備えられている。なお、このエンコーダは、リニアスケールと呼ばれる直線状の部材に細かな凹凸が所定ピッチで刻まれたものや、ボールネジを回転させるモータの回転角度を検出するロータリエンコーダ等が例示できる。 The Y-axis slider 42 moves the rotation mechanism 43 at an arbitrary speed in the Y direction based on a control signal output from the control unit CN and stops at an arbitrary position. Specifically, the Y-axis slider includes a pair of rails extending in the Y direction, a slider portion that moves on the rails, and a slider drive unit that moves and stops the slider portion. The slider drive unit can be configured by a combination of a servo motor or a pulse motor that rotates and stops by signal control from the control unit CN and a ball screw mechanism, a linear motor mechanism, or the like. Further, the Y-axis slider 42 is provided with an encoder for detecting the current position and movement amount of the slider portion. Examples of this encoder include a linear member called a linear scale in which fine irregularities are carved at a predetermined pitch, and a rotary encoder that detects a rotation angle of a motor that rotates a ball screw.
　回転機構４３は、基板載置台２０をθ方向に任意の速度で回転させ、任意の角度で静止させるものである。具体的には、回転機構４３は、ダイレクトドライブモータなどの、外部機器からの信号制御により任意の角度に回転／静止させるものが例示できる。回転機構４３の回転する側の部材の上には、基板保持部２の基板載置台２０が取り付けられている。 The rotating mechanism 43 rotates the substrate mounting table 20 in the θ direction at an arbitrary speed and stops at an arbitrary angle. Specifically, the rotation mechanism 43 can be exemplified by a mechanism that rotates / stops at an arbitrary angle by signal control from an external device, such as a direct drive motor. On the rotating member of the rotation mechanism 43, the substrate mounting table 20 of the substrate holding unit 2 is attached.
　相対移動部４は、この様な構成をしているため、検査対象となる基板Ｗを保持したまま、基板Ｗを撮像部３に対してＸＹθ方向にそれぞれ独立させて又は複合的に、所定の速度や角度で相対移動させたり、任意の位置・角度で静止させたりすることができる。 Since the relative movement unit 4 has such a configuration, the substrate W is held in the XYθ direction independently of the imaging unit 3 while holding the substrate W to be inspected, or in combination, in a predetermined manner. They can be moved relative to each other at a speed or angle, or can be stopped at an arbitrary position / angle.
　制御部ＣＮは、例えば、以下の様な機能や役割を担っている。
・基板保持部２に対して基板Ｗの保持／解除制御
・レボルバー機構３４を制御して、対物レンズを切り替える
・撮像カメラ３５に対して、撮像トリガを出力する
・相対移動部４の駆動制御：Ｘ軸スライダー４１、Ｙ軸スライダー２２、回転機構２３の現在位置をモニタリングしつつ、駆動用信号を出力する機能
・撮像位置の登録
・基板品種の切替 The controller CN has the following functions and roles, for example.
-Holding / releasing control of the substrate W with respect to the substrate holding unit 2-Switching the objective lens by controlling the revolver mechanism 34-Outputting an imaging trigger to the imaging camera 35-Drive control of the relative moving unit 4: A function to output a driving signal while monitoring the current position of the X-axis slider 41, the Y-axis slider 22, and the rotation mechanism 23, registration of an imaging position, switching of board types
　つまり、制御部ＣＮは、相対移動部４を駆動制御すると共に、基板Ｗ上に設定された分割撮像エリアの場所を変更しながら撮像部３に対して撮像トリガを出力することができる。さらに、検査品種に応じて、撮像倍率や視野サイズを切り替え、撮像する間隔を変えながら撮像トリガを出力することができ、所望の分割撮像画像を取得することができる。 That is, the control unit CN can drive and control the relative moving unit 4 and can output an imaging trigger to the imaging unit 3 while changing the location of the divided imaging area set on the substrate W. Furthermore, an imaging trigger can be output while switching the imaging magnification and field of view size and changing the imaging interval according to the inspection type, and a desired divided captured image can be acquired.
　なお、撮像トリガの出力は、下記の様な方式が例示できる。
・Ｘ方向にスキャン移動させながら、所定距離移動する毎に照明光Ｌ１を極短時間発光（いわゆる、ストロボ発光）させる方式。
・或いは、所定位置に移動および静止させて照明光Ｌ１を照射して撮像する（いわゆる、ステップ＆リピート）方式。 The imaging trigger output can be exemplified by the following method.
A method of emitting illumination light L1 for a very short time (so-called strobe light emission) every time a predetermined distance is moved while scanning in the X direction.
Alternatively, a method of moving and stopping at a predetermined position and irradiating the illumination light L1 to take an image (so-called step and repeat) method.
　また、撮像トリガとは、撮像カメラ３５や画像処理装置（不図示）に対する画像取り込み指示、照明光Ｌ１の発光指示などを意味する。具体的には、撮像トリガとして、（ケース１）撮像カメラ３５で撮像可能な時間（いわゆる、露光時間）の間に、照明光Ｌ１をストロボ発光させたり、（ケース２）照明光Ｌ１が照射されている時間内に、撮像させたり、する。或いは、撮像トリガは、撮像カメラ３５に対する指示に限らず、（ケース３）画像を取得する画像処理装置に対する画像取込指示でも良い。そうすることで、撮像カメラ３５から映像信号や映像データが逐次出力される形態にも対応できる。 Further, the imaging trigger means an instruction for capturing an image to the imaging camera 35 or an image processing apparatus (not shown), an instruction for emitting the illumination light L1, and the like. Specifically, as an imaging trigger, (Case 1) the illumination light L1 is flashed or (Case 2) the illumination light L1 is emitted during the time (so-called exposure time) that can be imaged by the imaging camera 35. Or take an image within the given time. Alternatively, the imaging trigger is not limited to an instruction to the imaging camera 35 (Case 3), but may be an image capture instruction to an image processing apparatus that acquires an image. By doing so, it is possible to cope with a form in which video signals and video data are sequentially output from the imaging camera 35.
　より具体的には、制御部ＣＮは、コンピュータやプログラマブルロジックコントローラ等（つまり、ハードウェア）と、その実行プログラム等（つまり、ソフトウェア）で構成されている。さらに、制御部ＣＮは、ハードウェアおよびソフトウェアで構成された機能ブロックの一部として、本発明に係るチップ位置算出部５、スケーリング補正部６等を備えている。 More specifically, the control unit CN is configured by a computer, a programmable logic controller or the like (that is, hardware), and an execution program or the like (that is, software). Further, the control unit CN includes a chip position calculation unit 5, a scaling correction unit 6 and the like according to the present invention as a part of functional blocks configured by hardware and software.
　図２は、本発明を具現化する形態の一例における撮像の様子を示す概念図である。
図２には、撮像部３の撮像カメラ４５が、基板Ｗに対して矢印Ｖｓで示す方向に相対移動しながら、基板Ｗ上に離間配置されている複数のチップ部品Ｃ（１，１）～Ｃ（９，２）を撮像する様子が示されている。 FIG. 2 is a conceptual diagram showing a state of imaging in an example of a form embodying the present invention.
In FIG. 2, the imaging camera 45 of the imaging unit 3 moves relative to the substrate W in the direction indicated by the arrow Vs, and is separated from the plurality of chip components C (1, 1) to C on the substrate W. A state in which C (9, 2) is imaged is shown.
　具体的には、分割撮像エリアＦ（１）、Ｆ（２）、Ｆ（３）、Ｆ（４）の順で撮像が行われ、分割撮像エリアＦ（１）ではチップ部品Ｃ（１，１）～Ｃ（３，２）が撮像され、分割撮像エリアＦ（２）ではチップ部品Ｃ（３，１）～Ｃ（５，２）が撮像され、分割撮像エリアＦ（３）ではチップ部品Ｃ（５，１）～Ｃ（７，２）が撮像され、分割撮像エリアＦ（４）ではチップ部品Ｃ（７，１）～Ｃ（９，２）が撮像される。 Specifically, imaging is performed in the order of the divided imaging areas F (1), F (2), F (3), and F (4). In the divided imaging area F (1), the chip component C (1, 1 ) To C (3, 2) are picked up, chip parts C (3, 1) to C (5, 2) are picked up in the divided image pickup area F (2), and chip parts C are picked up in the divided image pickup area F (3). (5,1) to C (7,2) are imaged, and chip parts C (7,1) to C (9,2) are imaged in the divided imaging area F (4).
　そして、分割撮像エリアＦ（１）と分割撮像エリアＦ（２）は、互いが隣接するのみならず、一部の領域が双方に重複して撮像されるように設定されている。この隣接しつつ重複撮像される領域を重複撮像領域Ｍ（１）と呼ぶ。同様に、分割撮像エリアＦ（２）と分割撮像エリアＦ（３）の重複撮像領域をＭ（２）、分割撮像エリアＦ（３）と分割撮像エリアＦ（４）の重複撮像領域をＭ（３）と呼ぶ。
そして、分割撮像エリアには少なくとも２つ以上のチップ部品が含まれ、かつ、当該チップ部品のうち少なくとも１つのチップ部品が、隣接する分割撮像エリアの双方に含まれた重複撮像チップ部品として設定されている。 The divided imaging area F (1) and the divided imaging area F (2) are set so that not only are adjacent to each other, but also a part of the area is overlapped and imaged. An area that is adjacently overlapped and imaged is referred to as an overlapped imaging area M (1). Similarly, the overlapping imaging area of the divided imaging area F (2) and the divided imaging area F (3) is M (2), and the overlapping imaging area of the divided imaging area F (3) and the divided imaging area F (4) is M ( 3).
The divided imaging area includes at least two or more chip components, and at least one of the chip components is set as an overlapping imaging chip component included in both adjacent divided imaging areas. ing.
　具体的には、重複撮像領域Ｍ（１）には、チップ部品Ｃ（３，１），Ｃ（３，２）が含まれ、重複撮像領域Ｍ（２）には、チップ部品Ｃ（５，１），Ｃ（５，２）が含まれ、重複撮像領域Ｍ（３）には、チップ部品Ｃ（７，１），Ｃ（７，２）が含まれるよう、分割撮像エリアＦ（１）～Ｆ（４）の撮像位置が設定されている。 Specifically, the overlapping imaging region M (1) includes chip components C (3, 1) and C (3, 2), and the overlapping imaging region M (2) includes the chip component C (5, 5). 1), C (5, 2), and the divided imaging area F (1) so that the overlapping imaging area M (3) includes the chip parts C (7, 1), C (7, 2). The imaging positions of F to (4) are set.
　チップ位置算出部５は、撮像部３で撮像された画像に基づいて、分割撮像エリア内に含まれるチップ部品それぞれの位置を算出するものである。さらに、チップ位置算出部５は、重複撮像チップ部品それぞれの位置を、先に撮像された前記分割撮像エリアに含まれた他のチップ部品との位置関係から算出し、後に撮像した前記分割撮像エリアに含まれる前記重複撮像チップ部品を除く他のチップ部品それぞれの位置を、当該重複撮像チップ部品との位置関係から算出するものである。 The chip position calculation unit 5 calculates the position of each chip component included in the divided imaging area based on the image captured by the imaging unit 3. Further, the chip position calculation unit 5 calculates the position of each overlapping imaging chip component from the positional relationship with the other chip components included in the divided imaging area previously captured, and the divided imaging area captured later. The position of each of the other chip components excluding the overlapping imaging chip component included in is calculated from the positional relationship with the overlapping imaging chip component.
　図３は、本発明を具現化する形態の一例におけるチップ部品それぞれの位置関係を示す平面図である。図３には、分割撮像エリアＦ（１），Ｆ（２）と、各チップ部品Ｃ（１，１）～Ｃ（５，２）の位置関係が例示されている。 FIG. 3 is a plan view showing the positional relationship of each chip component in an example embodying the present invention. FIG. 3 illustrates the positional relationship between the divided imaging areas F (1) and F (2) and the chip components C (1,1) to C (5,2).
　具体的には、チップ位置算出部５は、撮像された分割撮像エリアＦ（１）に含まれるチップ部品Ｃ（１，１）～Ｃ（３，２）の相互位置を算出するものである。例えば、チップ部品それぞれの左下隅の位置を基準にして、以下を算出する。
・チップ部品Ｃ（１，１）に対するチップ部品Ｃ（２，１）のＸ方向のずれ量ｄｘ１およびＹ方向のずれ量ｄｙ１
・チップ部品Ｃ（２，１）に対するチップ部品Ｃ（３，１）のＸ方向のずれ量ｄｘ２およびＹ方向のずれ量ｄｙ２
・チップ部品Ｃ（１，１）に対するチップ部品Ｃ（１，２）のＸ方向のずれ量ｄｘ２０およびＹ方向のずれ量ｄｙ２０
・チップ部品Ｃ（１，２）に対するチップ部品Ｃ（２，２）のＸ方向のずれ量ｄｘ２１およびＹ方向のずれ量ｄｙ２１
・チップ部品Ｃ（２，２）に対するチップ部品Ｃ（３，２）のＸ方向のずれ量ｄｘ２２およびＹ方向のずれ量ｄｙ２２ Specifically, the chip position calculation unit 5 calculates the mutual positions of the chip components C (1,1) to C (3,2) included in the captured divided imaging area F (1). For example, the following is calculated based on the position of the lower left corner of each chip component.
The amount of deviation dx1 in the X direction and the amount of deviation dy1 in the Y direction of the chip component C (2,1) with respect to the chip component C (1,1).
The amount of deviation dx2 in the X direction and the amount of deviation dy2 in the Y direction of the chip component C (3, 1) with respect to the chip component C (2, 1).
The amount of displacement dx20 in the X direction and the amount of displacement dy20 in the Y direction of the chip component C (1,2) with respect to the chip component C (1,1).
The amount of deviation dx21 in the X direction and the amount of deviation dy21 in the Y direction of the chip component C (2, 2) with respect to the chip component C (1, 2).
The amount of deviation dx22 in the X direction and the amount of deviation dy22 in the Y direction of the chip part C (3, 2) with respect to the chip part C (2, 2)
　より具体的には、チップ部品Ｃ（１，１）の位置が（Ｘ１１，Ｙ１１）とすると、チップ位置算出部５は、以下のような計算式に基づいてチップ部品それぞれの位置を算出する。
・チップ部品Ｃ（２，１）の位置（Ｘ２１，Ｙ２１）＝（Ｘ１１＋ｄｘ１，Ｙ１１＋ｄｙ１）
・チップ部品Ｃ（３，１）の位置（Ｘ３１，Ｙ３１）＝（Ｘ１１＋ｄｘ１＋ｄｘ２，Ｙ１１＋ｄｙ１＋ｄｙ２）
・チップ部品Ｃ（１，２）の位置（Ｘ１２，Ｙ１２）＝（Ｘ１１＋ｄｘ２０，Ｙ１１＋ｄｙ２０）
・チップ部品Ｃ（２，２）の位置（Ｘ２２，Ｙ２２）＝（Ｘ１１＋ｄｘ２０＋ｄｘ２１，Ｙ１１＋ｄｙ２０＋ｄｙ２１）
・チップ部品Ｃ（３，２）の位置（Ｘ３２，Ｙ３２）＝（Ｘ１１＋ｄｘ２０＋ｄｘ２１＋ｄｘ２２，Ｙ１１＋ｄｙ２０＋ｄｙ２１＋ｄｙ２２） More specifically, assuming that the position of the chip component C (1, 1) is (X11, Y11), the chip position calculation unit 5 calculates the position of each chip component based on the following calculation formula.
The position (X21, Y21) of the chip component C (2, 1) = (X11 + dx1, Y11 + dy1)
The position (X31, Y31) of the chip component C (3, 1) = (X11 + dx1 + dx2, Y11 + dy1 + dy2)
The position (X12, Y12) of the chip component C (1, 2) = (X11 + dx20, Y11 + dy20)
The position (X22, Y22) of the chip component C (2, 2) = (X11 + dx20 + dx21, Y11 + dy20 + dy21)
The position (X32, Y32) of the chip part C (3, 2) = (X11 + dx20 + dx21 + dx22, Y11 + dy20 + dy21 + dy22)
　続いて、撮像された分割撮像エリアＦ（２）に含まれるチップ部品Ｃ（３，１）～Ｃ（５，２）の相互位置を算出する。上述と同様に、チップ部品それぞれの左下隅の位置を基準にして、以下を算出する。
・チップ部品Ｃ（３，１）に対するチップ部品Ｃ（４，１）のＸ方向のずれ量ｄｘ３およびＹ方向のずれ量ｄｙ３
・チップ部品Ｃ（４，１）に対するチップ部品Ｃ（５，１）のＸ方向のずれ量ｄｘ４およびＹ方向のずれ量ｄｙ４
・チップ部品Ｃ（３，２）に対するチップ部品Ｃ（４，２）のＸ方向のずれ量ｄｘ２３およびＹ方向のずれ量ｄｙ２３
・チップ部品Ｃ（４，２）に対するチップ部品Ｃ（５，２）のＸ方向のずれ量ｄｘ２４およびＹ方向のずれ量ｄｙ２４ Subsequently, the mutual positions of the chip components C (3, 1) to C (5, 2) included in the imaged divided imaging area F (2) are calculated. As described above, the following is calculated based on the position of the lower left corner of each chip component.
The amount of displacement dx3 in the X direction and the amount of displacement dy3 in the Y direction of the chip component C (4, 1) with respect to the chip component C (3, 1)
The amount of deviation dx4 in the X direction and the amount of deviation dy4 in the Y direction of the chip part C (5, 1) with respect to the chip part C (4, 1).
The amount of displacement dx23 in the X direction and the amount of displacement dy23 in the Y direction of the chip component C (4, 2) with respect to the chip component C (3, 2).
The amount of deviation dx24 in the X direction and the amount of deviation dy24 in the Y direction of the chip part C (5, 2) with respect to the chip part C (4, 2).
　より具体的には、チップ位置算出部５は、以下のような計算式に基づいてそれぞれの位置を算出する。
・チップ部品Ｃ（３，１）やチップ部品Ｃ（３，２）の位置が上述の通りなので、チップ部品Ｃ（４，１）の位置は（Ｘ１１＋ｄｘ１＋ｄｘ２＋ｄｘ３，Ｙ１１＋ｄｙ１＋ｄｙ２＋ｄｙ３）
・チップ部品Ｃ（５，１）の位置は（Ｘ１１＋ｄｘ１＋ｄｘ２＋ｄｘ３＋ｄｘ４，Ｙ１１＋ｄｙ１＋ｄｙ２＋ｄｙ３＋ｄｙ４）
・チップ部品Ｃ（４，２）の位置は（Ｘ１１＋ｄｘ２０＋ｄｘ２１＋ｄｘ２２＋ｄｘ２３，Ｙ１１＋ｄｙ２０＋ｄｙ２１＋ｄｙ２２＋ｄｙ２３）
・チップ部品Ｃ（５，２）の位置は（Ｘ１１＋ｄｘ２０＋ｄｘ２１＋ｄｘ２２＋ｄｘ２３＋ｄｘ２４，Ｙ１１＋ｄｙ２０＋ｄｙ２１＋ｄｙ２２＋ｄｙ２３＋ｄｙ２４）
この他のチップ部品Ｃ（６，１）等の位置については、上述と同様に算出する。 More specifically, the chip position calculation unit 5 calculates each position based on the following calculation formula.
Since the positions of the chip part C (3, 1) and the chip part C (3, 2) are as described above, the position of the chip part C (4, 1) is (X11 + dx1 + dx2 + dx3, Y11 + dy1 + dy2 + dy3)
The position of the chip component C (5, 1) is (X11 + dx1 + dx2 + dx3 + dx4, Y11 + dy1 + dy2 + dy3 + dy4)
The position of the chip part C (4, 2) is (X11 + dx20 + dx21 + dx22 + dx23, Y11 + dy20 + dy21 + dy22 + dy23)
The position of the chip part C (5, 2) is (X11 + dx20 + dx21 + dx22 + dx23 + dx24, Y11 + dy20 + dy21 + dy22 + dy23 + dy24)
The positions of other chip parts C (6, 1) and the like are calculated in the same manner as described above.
　この様な構成をしているため、発明に係るチップ位置測定装置１は、最初の撮像エリアに含まれた１つのチップ部品の位置を基準として、他のチップ部品それぞれの位置を算出することができる。 Because of such a configuration, the chip position measuring apparatus 1 according to the invention can calculate the position of each of the other chip components based on the position of one chip component included in the first imaging area. it can.
　［別の形態］
　なお上述では、チップ部品それぞれの位置を算出するために、隣り合うチップ部品どうしのＸ方向の間隔やＹ方向のずれ量を測定し、累積的に算出する手順を示した。
この場合、最も後に撮像された分割撮像エリアにあるチップ部品それぞれの位置は、
先のチップ部品どうしの間隔やずれ量の足し算である。そのため、それぞれの間隔やずれ量に測定分解能以下の誤差が蓄積され、最初の基準となるチップ部品から遠く離れた場所にあるチップ部品の算出位置には誤差が累積される。そうすると、すべてのチップ部品に対して、所望の精度で測定できない懸念が生じる。その様な懸念を無くす（つまり、累積誤差の発生を防止する）ために、下記（１），（２）のいずれか又は双方に示す様な手順で位置を算出することが好ましい。 [Another form]
In the above description, in order to calculate the position of each chip component, the procedure of measuring the interval between the adjacent chip components in the X direction and the amount of deviation in the Y direction and calculating the cumulative value is shown.
In this case, the position of each chip component in the divided imaging area imaged most recently is
This is the addition of the distance between the previous chip parts and the amount of deviation. Therefore, errors below the measurement resolution are accumulated in the respective intervals and deviation amounts, and the errors are accumulated at the calculated positions of the chip parts far from the first reference chip part. Then, there is a concern that all chip parts cannot be measured with a desired accuracy. In order to eliminate such a concern (that is, to prevent the occurrence of a cumulative error), it is preferable to calculate the position by a procedure as shown in one or both of the following (1) and (2).
　（１）１つの分割撮像エリア内でのチップ部品それぞれの位置を、１つの基準となるチップ部品に対する間隔やずれ量から算出する。 (1) The position of each chip component in one divided imaging area is calculated from the interval and the amount of deviation with respect to one reference chip component.
　図４は、本発明を具現化する別の形態の一例におけるチップ部品それぞれの位置関係を示す平面図である。図４には、分割撮像エリアＦ（１），Ｆ（２）と、各チップ部品Ｃ（１，１）～Ｃ（５，２）の位置関係が例示されている。 FIG. 4 is a plan view showing the positional relationship between chip components in another example embodying the present invention. FIG. 4 illustrates the positional relationship between the divided imaging areas F (1) and F (2) and the chip components C (1,1) to C (5,2).
　具体的には、チップ位置算出部５は、以下の様にして、撮像された分割撮像エリアＦ（１）に含まれるチップ部品Ｃ（１，１），Ｃ（２，１），Ｃ（５，１），Ｃ（６，１）等の相互位置を算出することができる。
・チップ部品Ｃ（２，１）の位置（Ｘ２１，Ｙ２１）は、チップ部品Ｃ（１，１）に対するチップ部品Ｃ（２，１）のＸ方向のずれ量ｄｘ１およびＹ方向のずれ量ｄｙ１より、（Ｘ２１，Ｙ２１）＝（Ｘ１１＋ｄｘ１，Ｙ１１＋ｄｙ１）
・チップ部品Ｃ（５，１）の位置（Ｘ５１，Ｙ５１）は、チップ部品Ｃ（１，１）に対するチップ部品Ｃ（５，１）のＸ方向のずれ量ｄｘ４およびＹ方向のずれ量ｄｙ４より、（Ｘ５１，Ｙ５１）＝（Ｘ１１＋ｄｘ４，Ｙ１１＋ｄｙ４）
・チップ部品Ｃ（６，１）の位置（Ｘ６１，Ｙ６１）は、チップ部品Ｃ（１，１）に対するチップ部品Ｃ（６，１）のＸ方向のずれ量ｄｘ５およびＹ方向のずれ量ｄｙ５より、（Ｘ５１，Ｙ５１）＝（Ｘ１１＋ｄｘ５，Ｙ１１＋ｄｙ５） Specifically, the chip position calculation unit 5 performs chip parts C (1,1), C (2,1), C (5) included in the divided imaging area F (1) that has been imaged as follows. , 1), C (6, 1), etc. can be calculated.
The position (X21, Y21) of the chip part C (2, 1) is based on the amount of deviation dx1 in the X direction and the amount of deviation dy1 in the Y direction of the chip part C (2, 1) with respect to the chip part C (1, 1). , (X21, Y21) = (X11 + dx1, Y11 + dy1)
The position (X51, Y51) of the chip part C (5, 1) is based on the amount of deviation dx4 in the X direction and the amount of deviation dy4 in the Y direction of the chip part C (5, 1) with respect to the chip part C (1, 1). , (X51, Y51) = (X11 + dx4, Y11 + dy4)
The position (X61, Y61) of the chip part C (6, 1) is based on the amount of deviation dx5 in the X direction and the amount of deviation dy5 in the Y direction of the chip part C (6, 1) with respect to the chip part C (1, 1). , (X51, Y51) = (X11 + dx5, Y11 + dy5)
　さらに、チップ位置算出部５は、以下の様にして、撮像された分割撮像エリアＦ（２）に含まれるチップ部品Ｃ（６，１），Ｃ（７，１），Ｃ（１１，１）等の相互位置を算出することができる。
・チップ部品Ｃ（７，１）の位置（Ｘ７１，Ｙ７１）は、チップ部品Ｃ（６，１）に対するチップ部品Ｃ（７，１）のＸ方向のずれ量ｄｘ６およびＹ方向のずれ量ｄｙ６より、（Ｘ７１，Ｙ７１）＝（Ｘ６１＋ｄｘ６，Ｙ６１＋ｄｙ６）
・チップ部品Ｃ（１１，１）の位置（Ｘ１１１，Ｙ１１１）は、チップ部品Ｃ（６，１）に対するチップ部品Ｃ（１１，１）のＸ方向のずれ量ｄｘ１０およびＹ方向のずれ量ｄｙ１０より、（Ｘ１１１，Ｙ１１１）＝（Ｘ６１＋ｄｘ１０，Ｙ６１＋ｄｙ１０） Further, the chip position calculation unit 5 performs chip parts C (6, 1), C (7, 1), C (11, 1) included in the divided imaging area F (2) that has been imaged as follows. And so on.
The position (X71, Y71) of the chip part C (7, 1) is based on the amount of deviation dx6 in the X direction and the amount of deviation dy6 in the Y direction of the chip part C (7, 1) with respect to the chip part C (6, 1). , (X71, Y71) = (X61 + dx6, Y61 + dy6)
The position (X111, Y111) of the chip part C (11, 1) is based on the amount of deviation dx10 in the X direction and the amount of deviation dy10 in the Y direction of the chip part C (11, 1) with respect to the chip part C (6, 1). , (X111, Y111) = (X61 + dx10, Y61 + dy10)
　なお、ここではチップ部品Ｃ（１，１）～Ｃ（６，１）に着目して位置を算出する手順を説明したが、他のチップＣ（２，１）～Ｃ（１１，３）についても、同様にして（つまり、チップ部品Ｃ（１，１），Ｃ（６，１）を基準として）それぞれの位置を算出することができる。 Here, the procedure for calculating the position by focusing on the chip parts C (1,1) to C (6,1) has been described, but the other chips C (2,1) to C (11,3) are described. Similarly, the respective positions can be calculated (that is, based on the chip components C (1, 1) and C (6, 1)).
　（２）マスター基板を用いて分割撮像エリアの測定位置を算出し、チップ部品それぞれの位置に対してスケーリング補正を行う。 (2) The measurement position of the divided imaging area is calculated using the master substrate, and the scaling correction is performed on the position of each chip component.
　具体的には、上述のチップ位置測定装置１の構成に加え、スケーリング補正部を備えた
構成とする。そして、複数の基準マークの相互位置が既知であるマスター基板を前記基板保持部に保持させ、マスター基板に配置された前記基準マークの相互位置に基づいて、前記チップ位置算出部で算出した前記チップ部品それぞれの位置に対する補正を行う。 Specifically, in addition to the configuration of the chip position measuring apparatus 1 described above, a configuration including a scaling correction unit is adopted. Then, the chip calculated by the chip position calculation unit based on the mutual position of the reference marks arranged on the master substrate is held by the substrate holding unit a master substrate in which the mutual positions of a plurality of reference marks are known Correction for the position of each part is performed.
　図５は、本発明を具現化する別の形態の一例におけるマスター基板と分割撮像エリアとの位置関係を示す平面図である。図５には、複数の基準マークＦＭａ，ＦＭｋ，ＦＭｑ，ＦＭｚの相互位置が既知であるマスター基板ＭＷの平面図が例示されている。 FIG. 5 is a plan view showing a positional relationship between the master substrate and the divided imaging area in another example embodying the present invention. FIG. 5 illustrates a plan view of the master substrate MW in which the mutual positions of the plurality of reference marks FMa, FMk, FMq, and FMz are known.
　マスター基板ＭＷは、チップ位置測定装置１の基板保持部２に保持させて相対移動させると、分割撮像エリアＦ（ａ），Ｆ（ｋ）の視野に、基準マークＦＭａ，ＦＭｋが観察されるような配置となっている。そして、基準マークＦＭａ，ＦＭｋは、それぞれが円形で、これら円の中心は、Ｘ方向に間隔Ｒｘｍで配置されている。なお、この間隔ｄｘｍは、高精度な測長装置（例えば、レーザ干渉計を用いた移動機構と、マーク位置検出装置などを組み合わせたもの）により、正確な位置（相対距離、相対座標とも言う）が既知である。具体的には、この間隔Ｒｘｍが１００．００ｍｍとして、以下説明する。 When the master substrate MW is held on the substrate holding unit 2 of the chip position measuring device 1 and relatively moved, the reference marks FMa and FMk are observed in the field of view of the divided imaging areas F (a) and F (k). It has become the arrangement. Each of the reference marks FMa and FMk is circular, and the centers of these circles are arranged at an interval Rxm in the X direction. The distance dxm is an accurate position (also referred to as a relative distance or relative coordinate) by a highly accurate length measuring device (for example, a combination of a moving mechanism using a laser interferometer and a mark position detecting device). Is known. Specifically, the following description will be made assuming that the interval Rxm is 100.00 mm.
　まず、分割撮像エリアＦ（ａ）で観察されたチップ部品Ｃ（ａ，１）と分割撮像エリアＦ（ｋ）で観察されたＣ（ｋ，１）との相互位置が、チップ位置算出部５において上述の手順で算出され、例えば、互いのＸ方向の間隔ｄｘｋが１００．１０ｍｍだったとする。 First, the mutual position of the chip component C (a, 1) observed in the divided imaging area F (a) and C (k, 1) observed in the divided imaging area F (k) is the chip position calculation unit 5. , And the distance dxk in the X direction is 100.10 mm.
　そして、基準マークＦＭａに対するチップ部品Ｃ（ａ，１）のＸ方向のずれ量をδｘａ、基準マークＦＭｋに対するチップ部品Ｃ（ｋ，１）のＸ方向のずれ量をδｘｋとし、それぞれのずれ量をチップ位置算出部５にて算出したところ、例えばδｘａが０．０１ｍｍ、δｘｋが０．０１ｍｍだったとする。そうすると、チップ位置算出部５では、基準マークＦＭａ，ＦＭｋの間隔ｄｘｍが１００．１２ｍｍとして算出されてしまう。しかし、本来は１００．００ｍｍとして算出すべきであるので、これらの値の比率Ｒｘｍ／ｄｘｍ（＝１００．００／１００．１２＝０．９９８８）をスケーリング補正係数として登録しておき、この係数を加味してチップ部品それぞれのＸ方向の位置を算出する。つまり、上述の例の場合、補正前のｄｘｋが１００．１０ｍｍで算出されれば、スケーリング補正係数を加味して、１００．１０×０．９９８８＝９９．９８ｍｍとして補正後のｄｘｋの値を出力する。 The amount of deviation in the X direction of the chip part C (a, 1) with respect to the reference mark FMa is δxa, and the amount of deviation in the X direction of the chip part C (k, 1) with respect to the reference mark FMk is δxk. It is assumed that δxa is 0.01 mm and δxk is 0.01 mm, for example, as calculated by the chip position calculation unit 5. Then, the chip position calculation unit 5 calculates the distance dxm between the reference marks FMa and FMk as 100.12 mm. However, since it should originally be calculated as 100.00 mm, the ratio Rxm / dxm (= 100.00 / 100.12 = 0.99888) of these values is registered as a scaling correction coefficient, and this coefficient is In consideration, the position in the X direction of each chip component is calculated. In other words, in the case of the above-described example, if dxk before correction is calculated as 100.10 mm, the value of dxk after correction is output as 100.10 × 0.9988 = 99.98 mm in consideration of the scaling correction coefficient. To do.
　なお、上述ではチップ部品Ｃ（ｋ，１）に対するスケーリング補正を例示したが、このように算出したスケーリング補正係数は、他のチップ部品の位置を算出する場合にも適応できる。また、上述ではＸ方向についてスケーリング補正を行う手順を説明したが、Ｙ方向についても同様に（Ｙ方向の場合は、基準マークＦＭａ，ＦＭｑの間隔Ｒｙｑ等を基準にして）スケーリング補正係数を算出し、このスケーリング補正係数を考慮してチップ部品それぞれのＹ方向の位置を算出することができる。 In the above description, the scaling correction for the chip part C (k, 1) is exemplified. However, the scaling correction coefficient calculated in this way can also be applied to the calculation of the position of another chip part. Although the procedure for performing the scaling correction in the X direction has been described above, the scaling correction coefficient is calculated in the same manner in the Y direction (in the case of the Y direction, based on the interval Ryq between the reference marks FMa and FMq). The position in the Y direction of each chip component can be calculated in consideration of this scaling correction coefficient.
　この様な構成とすることで、離れた場所にあるチップ部品の測定位置の累積誤差を軽減ないし無くすことができる。 With such a configuration, it is possible to reduce or eliminate the accumulated error of the measurement positions of chip parts located at remote locations.
　［別の形態］　
　なお上述では、相対移動部４のＸ軸スライダー４１とＹ軸スライダー４２との直交度が所望の精度で組み付けられている前提で詳細な説明をした。しかし、機器組立の都合上、Ｘ軸スライダー４１とＹ軸スライダー４２の直交度が少しずれたり、ずれの改善が期待できない場合や、より高精度な測定が求められる場合、下記の様な手順や構成で、チップ部品それぞれの位置を補正して算出することが好ましい。 [Another form]
In the above description, the detailed description has been given on the assumption that the orthogonality between the X-axis slider 41 and the Y-axis slider 42 of the relative movement unit 4 is assembled with a desired accuracy. However, if the degree of orthogonality of the X-axis slider 41 and the Y-axis slider 42 is slightly shifted due to equipment assembly, or if improvement of the shift cannot be expected, or more accurate measurement is required, the following procedure or It is preferable to calculate by correcting the position of each chip component in the configuration.
　具体的には、マスター基板ＭＷを用いて、直交度を補正する。マスター基板ＭＷには、図５に示す様に、基準マークＦＭａ、ＦＭｋ、ＦＭｑ、ＦＭｚそれぞれの中心位置は、縦Ｒｙｑ×横Ｒｘｍの長方形ないし正方形の矩形の頂点に配置されている。そのため、相対移動部４のＸ軸スライダー４１やＹ軸スライダー４２を移動させて、撮像部３でこれら基準マークＦＭａ、ＦＭｋ、ＦＭｑ、ＦＭｚを撮像し、それぞれの中心位置を取得する。そして、相対移動部４のＸ軸スライダー４１を移動させて基準マークＦＭａ，ＦＭｋを撮像したときの、Ｘ方向の間隔およびＹ方向のずれ量と、Ｙ軸スライダー４２を移動させて基準マークＦＭａ，ＦＭｑを撮像したときの、Ｙ方向の間隔およびＸ方向のずれ量とから、Ｘ軸スライダー４１とＹ軸スライダー４２との直交度がどの程度ずれているかを算出する。そして、チップ位置算出部５では、この直交度に起因するずれ量がキャンセルされるよう、チップ部品それぞれの位置を補正して算出する。 Specifically, the orthogonality is corrected using the master substrate MW. On the master substrate MW, as shown in FIG. 5, the center positions of the reference marks FMa, FMk, FMq, and FMz are arranged at the vertices of a rectangle or square rectangle of vertical Ryq × horizontal Rxm. Therefore, the X-axis slider 41 and the Y-axis slider 42 of the relative movement unit 4 are moved, and the reference marks FMa, FMk, FMq, and FMz are imaged by the imaging unit 3, and the respective center positions are acquired. Then, when the X-axis slider 41 of the relative movement unit 4 is moved and the reference marks FMa and FMk are imaged, the distance in the X direction and the amount of deviation in the Y direction and the Y-axis slider 42 are moved to move the reference marks FMa, The degree of orthogonality between the X-axis slider 41 and the Y-axis slider 42 is calculated from the interval in the Y direction and the amount of deviation in the X direction when FMq is imaged. Then, the chip position calculation unit 5 corrects and calculates the position of each chip component so that the deviation amount due to the orthogonality is canceled.
　この様な構成であれば、チップ位置算出部５で算出されるチップ部品それぞれの位置は、相対移動部４のＸ軸スライダー４１とＹ軸スライダー４２との直交度のずれに起因した位置測定の誤差を低減ないし防止できる。 With such a configuration, the position of each chip component calculated by the chip position calculation unit 5 is determined by the position measurement caused by the deviation of the orthogonality between the X-axis slider 41 and the Y-axis slider 42 of the relative movement unit 4. Errors can be reduced or prevented.
　［別の形態］
　なお上述では、相対移動部４のＸ軸スライダー４１とＹ軸スライダー４２の真直度（直真度、直進度とも言う）が、チップ部品それぞれの位置測定に影響が無い前提で詳細な説明をした。しかし、機器構成上、移動方向と直交する方向に僅かに蛇行し、分割撮像エリアがθ方向に傾斜することがある。そうすると、分割撮像エリアにおけるＸ方向とＹ方向には、θ方向にずれたことにより生じる誤差が含まれてしまうため、チップ部品それぞれの位置測定に影響を与えるという懸念が生じる。 [Another form]
In the above description, detailed explanation is given on the assumption that the straightness (also referred to as straightness and straightness) of the X-axis slider 41 and the Y-axis slider 42 of the relative movement unit 4 does not affect the position measurement of each chip component. . However, the device configuration may meander slightly in the direction orthogonal to the moving direction, and the divided imaging area may be inclined in the θ direction. In this case, the X direction and the Y direction in the divided imaging area include an error that occurs due to a shift in the θ direction, which may cause an influence on the position measurement of each chip component.
　この様な懸念（つまり、取得画像のθ方向のずれの影響）を軽減ないし無くすために、本発明を適用する上では、分割撮像エリアには少なくとも２列以上の前記チップ部品が含まれ、かつ、当該チップ部品のうち少なくとも１列のチップ部品が、隣接する前記分割撮像エリアの双方に含まれた重複撮像チップ部品として設定しておくことが好ましい。そして、チップ位置算出部５において、後に撮像した前記分割撮像エリアに含まれる重複撮像チップ部品を除く他のチップ部品それぞれの位置を算出する際、複数の重複撮像チップ部品の位置関係（つまり、Ｘ方向およびＹ方向の位置）から、θ方向のずれ成分を算出し、このずれ成分を補正して、チップ部品それぞれの位置を算出する。 In order to reduce or eliminate such a concern (that is, the influence of the deviation of the acquired image in the θ direction), in applying the present invention, the divided imaging area includes at least two rows of the chip parts, and It is preferable that at least one row of chip components among the chip components is set as an overlapping imaging chip component included in both of the adjacent divided imaging areas. When the chip position calculation unit 5 calculates the position of each of the other chip components excluding the overlapping imaging chip components included in the divided imaging area captured later, the positional relationship between the plurality of overlapping imaging chip components (that is, X The deviation component in the θ direction is calculated from the direction and the position in the Y direction, and the deviation component is corrected to calculate the position of each chip component.
　この様な形態であれば、相対移動しながら取得した分割撮像エリアの画像が、θ方向に少し傾斜したとしても、その傾斜の影響を無くして所望の精度でそれぞれのチップ部品の位置を算出することができる。 In such a form, even if the image of the divided imaging area acquired while relatively moving is slightly inclined in the θ direction, the position of each chip component is calculated with a desired accuracy without the influence of the inclination. be able to.
　［別の形態］
　なお上述では、１つの分割撮像エリアに縦２×横３、計６個のチップ部品が配列されている例（図２，３）や、１つの分割撮像エリアに縦３×横６、計１８個のチップ部品が配列されている例（図４）を示し、そのうち縦１列のチップ部品が重複撮像チップとして、隣接する分割撮像エリアの双方で撮像される形態を例示しつつ詳細な説明をした。 [Another form]
In the above description, an example in which a total of six chip components are arranged in a single divided imaging area (2 × 3 in the vertical direction) (FIGS. 2 and 3), or a total of 18 × 3 × 6 in the single divided imaging area is provided. FIG. 4 shows an example in which a single chip component is arranged (FIG. 4), and a detailed description is given while illustrating a mode in which chip components in one vertical column are imaged in both adjacent divided imaging areas as overlapping imaging chips. did.
　しかし、この縦横のチップ部品の数は、適宜増減させて本発明を適用できる。例えば、縦横のチップ部品の数を増やす（例えば、縦３０×横４０に設定する）と、単位時間当たりに処理できる基板の枚数（いわゆる、ＷＰＨ）を増やすことができる。一方、縦横のチップ数を減らすと、撮像視野サイズを狭くして（撮像の倍率を上げるとも言う）、画素分解能を上げて測定精度の向上を図ることができる。 However, the present invention can be applied by appropriately increasing or decreasing the number of vertical and horizontal chip parts. For example, when the number of vertical and horizontal chip parts is increased (for example, set to 30 × 40), the number of substrates that can be processed per unit time (so-called WPH) can be increased. On the other hand, when the number of vertical and horizontal chips is reduced, the imaging visual field size can be narrowed (also referred to as increasing the imaging magnification), the pixel resolution can be increased, and the measurement accuracy can be improved.
　つまり、本発明を適用する上では、１つの分割撮像エリアに少なくとも２つのチップが含まれており、その内１つが、重複撮像チップとして設定されていれば良い。 That is, in applying the present invention, at least two chips are included in one divided imaging area, and one of them may be set as an overlapping imaging chip.
　［変形例］
　なお上述では、基板上に離間配置されたチップ部品Ｃ（１，１）～Ｃ（９，２）に対して、分割撮像エリアＦ（１）、Ｆ（２）、Ｆ（３）、Ｆ（４）の順で、Ｘ方向に分割撮像エリアを変更しながら、当該分割撮像エリアに含まれるチップ部品それぞれの位置を測定する具体的な手順等を示した。しかし、本発明を適用する上では、Ｘ方向に重複撮像領域を設定してＸ方向に相対移動させるのみならず、Ｙ方向に重複撮像領域を設定してＹ方向に相対移動させて、先に撮像した画像に含まれた重複撮像チップの位置関係に基づいて、他のチップ部品それぞれの位置を算出しても良い。或いは、図６に例示するように、ＸＹ方向双方に重複撮像領域Ｍ（１）～Ｍ（４）を設定し、チップ位置算出部５において、下記の様にチップ部品それぞれの位置を算出することもできる。
・Ｃ（１，１）の位置を基準にして分割撮像エリアＦ（１）におけるチップ部品Ｃ（１，１）～Ｃ６，２）それぞれの位置を算出。
・Ｃ（６，１）等の位置を基準にして分割撮像エリアＦ（２）におけるチップ部品Ｃ（７，１）～Ｃ１１，２）それぞれの位置を算出。
・Ｃ（６，３）等の位置を基準にして分割撮像エリアＦ（ｍ）におけるチップ部品Ｃ（６，４）～Ｃ（１１，５）それぞれの位置を算出。
・Ｃ（６，３）等の位置を基準にして分割撮像エリアＦ（ｍ＋１）におけるチップ部品Ｃ（１，４）～Ｃ（５，５）それぞれの位置を算出。 [Modification]
In the above description, the divided imaging areas F (1), F (2), F (3), F ( In the order of 4), a specific procedure for measuring the position of each chip component included in the divided imaging area while changing the divided imaging area in the X direction is shown. However, in applying the present invention, not only the overlapping imaging area is set in the X direction and relatively moved in the X direction, but the overlapping imaging area is set in the Y direction and relatively moved in the Y direction. The position of each of the other chip components may be calculated based on the positional relationship between the overlapping imaging chips included in the captured image. Alternatively, as illustrated in FIG. 6, the overlapping imaging regions M (1) to M (4) are set in both the XY directions, and the chip position calculation unit 5 calculates the position of each chip component as follows. You can also.
Calculate the position of each of the chip components C (1,1) to C6,2) in the divided imaging area F (1) with reference to the position of C (1,1).
Calculate the positions of the chip components C (7, 1) to C11, 2) in the divided imaging area F (2) with reference to the position of C (6, 1) or the like.
Calculate the positions of the chip components C (6, 4) to C (11, 5) in the divided imaging area F (m) with reference to the position of C (6, 3) or the like.
Calculate the positions of the chip components C (1, 4) to C (5, 5) in the divided imaging area F (m + 1) with reference to the position of C (6, 3) or the like.
　［その他、変形例］
　なお上述では、チップ位置算出部５における各チップ部品の位置を算出する具体例として、各チップ部品の左下隅の位置を基準とする例を示した。しかし、本発明を適用する上では、各チップ部品の中央や重心位置、他の隅の位置を基準に算出しても良い。 [Other variations]
In the above description, an example in which the position of the lower left corner of each chip component is used as a reference is shown as a specific example of calculating the position of each chip component in the chip position calculation unit 5. However, in applying the present invention, the calculation may be performed on the basis of the center, the center of gravity position, and the other corner positions of each chip component.
　また上述では、照明部３１として、同軸落斜方式を例示したが、透過照明や斜光照明、リング照明、ドーム照明等であっても良い。 In the above description, the coaxial falling method is exemplified as the illumination unit 31. However, transmission illumination, oblique illumination, ring illumination, dome illumination, and the like may be used.
　［応用例］
　なお上述では、チップ位置測定に着目して詳細な説明をした。しかし、チップ部品の割れや欠け、キズや汚れを検査する機能を備えた検査装置や、レーザ照射やディスペンサ、インクジェットなどによる加工機能を備えた装置などに、本発明が組み込まれた（利用される）構成であっても良い。 [Application example]
In the above description, the detailed description has been given focusing on the chip position measurement. However, the present invention is incorporated in (used for) an inspection apparatus having a function of inspecting chip parts for cracks, chips, scratches and dirt, an apparatus having a processing function by laser irradiation, a dispenser, an ink jet, or the like. ) Configuration may also be used.
　　１　　チップ位置測定装置
　　２　　基板保持部
　　３　　撮像部
　　４　　相対移動部
　　５　　チップ位置算出部
　　６　　スケーリング補正部
　　ＣＮ　制御部
　　１ｆ　装置フレーム
　　２０　基板載置台
　　３０　鏡筒
　　３１　照明部
　　３２　ハーフミラー
　　３３ａ，３３ｂ　対物レンズ
　　３４　レボルバー機構
　　３５　撮像カメラ
　　４１　Ｘ軸スライダー
　　４２　Ｙ軸スライダー
　　４３　回転機構
　　Ｗ　　基板
　　Ｃ　　チップ部品（かっこ内の数字は配列位置）
　　Ｆ　　分割撮像エリア（かっこ内の数字は撮像の順序）
　　Ｍ　　重複撮像領域
　　Ｌ１　照明光
　　Ｌ２　基板側から入射した光（反射光、散乱光） DESCRIPTION OF SYMBOLS 1 Chip position measuring device 2 Substrate holding part 3 Imaging part 4 Relative movement part 5 Chip position calculation part 6 Scaling correction part CN Control part 1f Device frame 20 Substrate mounting table 30 Lens barrel 31 Illumination part 32 Half mirror 33a, 33b Objective lens 34 Revolver mechanism 35 Imaging camera 41 X-axis slider 42 Y-axis slider 43 Rotating mechanism W Substrate C Chip component (Numbers in parentheses are array positions)
F Divided imaging area (numbers in parentheses are imaging order)
M Overlapping imaging region L1 Illumination light L2 Light incident from the substrate side (reflected light, scattered light)

Claims (3)

  1. 　基板上に離間配置された複数のチップ部品それぞれの位置を測定するチップ位置測定装置であって、
    　前記基板を保持する基板保持部と、
    　前記基板上に設定された所定領域を複数の分割撮像エリアに分割して撮像する撮像部と、
    　前記撮像部で撮像された画像に基づいて、前記分割撮像エリア内に含まれる前記チップ部品それぞれの位置を算出するチップ位置算出部と、
    　前記基板保持部と前記撮像部とを相対移動させる相対移動部と、
    　前記相対移動部を駆動制御すると共に、前記基板上に設定された前記分割撮像エリアの場所を変更しながら前記撮像部に対して撮像トリガを出力する制御部とを備え、
    　前記分割撮像エリアには少なくとも２つ以上の前記チップ部品が含まれ、かつ、当該チップ部品のうち少なくとも１つのチップ部品が、隣接する前記分割撮像エリアの双方に含まれた重複撮像チップ部品として設定されており、
    　前記チップ位置算出部は、
    前記重複撮像チップ部品それぞれの位置を、先に撮像された前記分割撮像エリアに含まれた他のチップ部品との位置関係から算出し、
    後に撮像した前記分割撮像エリアに含まれる前記重複撮像チップ部品を除く他のチップ部品それぞれの位置を、当該重複撮像チップ部品との位置関係から算出する
    ことを特徴とする、チップ位置測定装置。     A chip position measuring device that measures the position of each of a plurality of chip components spaced apart on a substrate,
    A substrate holder for holding the substrate;
    An imaging unit configured to divide and image a predetermined area set on the substrate into a plurality of divided imaging areas;
    A chip position calculation unit that calculates the position of each of the chip components included in the divided imaging area based on an image captured by the imaging unit;
    A relative movement unit that relatively moves the substrate holding unit and the imaging unit;
    A drive unit that controls the relative movement unit, and a controller that outputs an imaging trigger to the imaging unit while changing the location of the divided imaging area set on the substrate;
    The divided imaging area includes at least two or more chip components, and at least one of the chip components is set as an overlapping imaging chip component included in both of the adjacent divided imaging areas. Has been
    The chip position calculation unit
    Calculate the position of each of the overlapping imaging chip parts from the positional relationship with other chip parts included in the divided imaging area previously imaged,
    A chip position measuring apparatus, characterized in that the position of each of the other chip parts excluding the overlapping imaging chip part included in the divided imaging area imaged later is calculated from the positional relationship with the overlapping imaging chip part.
  2. 　前記分割撮像エリアには少なくとも２列以上の前記チップ部品が含まれ、かつ、当該チップ部品のうち少なくとも１列のチップ部品が、隣接する前記分割撮像エリアの双方に含まれた重複撮像チップ部品として設定されている
    ことを特徴とする、請求項１に記載のチップ位置測定装置。     The divided imaging area includes at least two rows of the chip components, and at least one row of chip components among the chip components is an overlapping imaging chip component included in both of the adjacent divided imaging areas. The chip position measuring apparatus according to claim 1, wherein the chip position measuring apparatus is set.
  3. 　複数の基準マークの相互位置が既知であるマスター基板を前記基板保持部に保持させ、
    　前記マスター基板に配置された前記基準マークの相互位置に基づいて、前記チップ位置算出部で算出した前記チップ部品それぞれの位置に対する補正を行う、スケーリング補正部を備えた
    ことを特徴とする、請求項１又は請求項２に記載のチップ位置測定装置。     A master substrate in which the mutual positions of a plurality of reference marks are known is held by the substrate holder,
    The scaling correction unit for correcting the position of each of the chip components calculated by the chip position calculation unit based on the mutual position of the reference marks arranged on the master substrate. The chip position measuring apparatus according to claim 1 or 2.
PCT/JP2019/004973 2018-03-19 2019-02-13 Chip position measurement device WO2019181279A1 (en)

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Publication number Priority date Publication date Assignee Title
JP7373436B2 (en) * 2020-03-09 2023-11-02 ファスフォードテクノロジ株式会社 Die bonding equipment and semiconductor device manufacturing method
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09275126A (en) * 1996-04-02 1997-10-21 Komatsu Ltd Appearance inspecting equipment and height measuring equipment of wafer bump
JP2001202520A (en) * 2000-01-24 2001-07-27 Nippon Avionics Co Ltd Method for composing pattern
JP2002181729A (en) * 2000-12-12 2002-06-26 Saki Corp:Kk Apparatus and method for visual inspection
JP2010237225A (en) * 2010-06-25 2010-10-21 Olympus Corp Inspection device
JP2014206547A (en) * 2008-01-16 2014-10-30 オルボテック リミテッド Inspection of substrate using multiple cameras

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923467B2 (en) * 1979-04-16 1984-06-02 株式会社日立製作所 Position detection method
US6208419B1 (en) * 1998-11-18 2001-03-27 Fuji Photo Film Co., Ltd. Method of and apparatus for bonding light-emitting element
KR100519789B1 (en) * 2003-03-20 2005-10-10 삼성전자주식회사 An align method of a semiconductor substrate
JP4954738B2 (en) * 2007-02-02 2012-06-20 東京エレクトロン株式会社 Electrode pad position detection method and electrode pad position detection apparatus
JP5311143B2 (en) * 2008-01-09 2013-10-09 株式会社ニコン Measuring apparatus and method, and program
US8299446B2 (en) * 2009-08-12 2012-10-30 Ultratech, Inc. Sub-field enhanced global alignment
JP2012186249A (en) * 2011-03-04 2012-09-27 Nec Corp Semiconductor chip mounting apparatus and semiconductor chip mounting method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09275126A (en) * 1996-04-02 1997-10-21 Komatsu Ltd Appearance inspecting equipment and height measuring equipment of wafer bump
JP2001202520A (en) * 2000-01-24 2001-07-27 Nippon Avionics Co Ltd Method for composing pattern
JP2002181729A (en) * 2000-12-12 2002-06-26 Saki Corp:Kk Apparatus and method for visual inspection
JP2014206547A (en) * 2008-01-16 2014-10-30 オルボテック リミテッド Inspection of substrate using multiple cameras
JP2010237225A (en) * 2010-06-25 2010-10-21 Olympus Corp Inspection device

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