WO2019175168A1 - Puce multipixel et procédé de fabrication d'une puce multipixel - Google Patents

Puce multipixel et procédé de fabrication d'une puce multipixel Download PDF

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Publication number
WO2019175168A1
WO2019175168A1 PCT/EP2019/056156 EP2019056156W WO2019175168A1 WO 2019175168 A1 WO2019175168 A1 WO 2019175168A1 EP 2019056156 W EP2019056156 W EP 2019056156W WO 2019175168 A1 WO2019175168 A1 WO 2019175168A1
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Prior art keywords
semiconductor region
pixels
contact
multipixel
chip
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PCT/EP2019/056156
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German (de)
English (en)
Inventor
Clemens VIERHEILIG
Tobias Meyer
Dominik Scholz
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Osram Opto Semiconductors Gmbh
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Publication of WO2019175168A1 publication Critical patent/WO2019175168A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

Definitions

  • a multipixel chip is specified.
  • a method for producing a multipixel chip is specified.
  • An object to be solved is to specify a multipixel chip that is efficiently structured into individual pixels.
  • Optoelectronic Multipixelchip a variety of pixels.
  • the pixels are electrically controllable in groups or individually.
  • the pixels are set up to generate and emit light.
  • the multipixel chip is in particular a pixelated LED chip.
  • Multipixel chip a first semiconductor region.
  • the first semiconductor region is n-type.
  • Semiconductor region may consist of a single semiconductor layer or of a plurality of semiconductor layers
  • the multipixel chip comprises a second semiconductor region, which
  • the second semiconductor region thus has a different conductivity type than the first semiconductor region. Furthermore, the second semiconductor region is structured to the pixels.
  • Multipixel chip an active zone.
  • the active zone is set up to generate the light.
  • the active zone is between the first and the second semiconductor region
  • the first form is a first form
  • the active zone preferably contains a pn junction, a single quantum well structure or a radiation generator for generating the radiation
  • the semiconductor layer sequence is preferably based on a III-V compound semiconductor material.
  • the semiconductor material is, for example, a nitride
  • Compound semiconductor material such as Al n In ] __ nm Ga m N or a phosphide compound semiconductor material such as
  • Compound semiconductor material such as Al n In ] __ nm Ga m As or as Al n Ga m In ] __ nm As P ] _-k, where each 0 dn ⁇ 1, 0 dm ⁇ 1 and n + m ⁇ 1 and 0 dk ⁇ 1 is.
  • at least one layer or all layers of the Semiconductor layer sequence 0 ⁇ n ⁇ 0.8, 0.4 ⁇ m ⁇ 1 and n + m ⁇ 0.95 and 0 ⁇ k ⁇ 0.5. It can the
  • Multipixel chip a first contact and a second
  • the first and the second contact are for
  • the first and the second contact are preferably metallic contacts, but may optionally also comprise transparent conductive oxides, in short TCOs.
  • the second contact is also structured to the pixels, so that the second contact preferably by a plurality of island-shaped
  • Subareas is formed to the pixels over the second
  • the active zone is only in regions parallel to an emission side of the
  • Multipixel chips are oriented, set up to generate the light.
  • the emission side is oriented in particular perpendicular to a main growth direction of the semiconductor layer sequence.
  • the active zone has areas that are oblique to the emission side. However, these areas of the active zone are not designed to generate the light and contribute to a total luminous intensity of the multipixel chip preferably at most 5% or 1% or 0.2% and are thus negligible with regard to the light emission.
  • Semiconductor region per pixel seen in cross-section mushroom-shaped that is, starting from a contiguous base layer, the first semiconductor region in the direction away from the emission side per pixel first has narrower feet. Starting from the feet, a broadening follows per pixel, so that broader heads are formed opposite the feet. Both the base layer and the feet and the heads are parts of the first semiconductor region. In particular, the feet and the heads can be epitaxially grown without temporal interruption in one another.
  • Optoelectronic Multipixelchip a variety of electrically individually controllable pixels for generating and emitting light.
  • a first semiconductor region extends with at least one semiconductor layer continuously over at least some of the pixels.
  • a second semiconductor region having a different conductivity type than the first one
  • Semiconductor area is structured to the pixels.
  • An active zone for generating the light is located between the first and the second semiconductor region.
  • a first contact is for electrical contacting of the first
  • the active zone is only parallel to one direction
  • the first semiconductor region is designed mushroom-shaped per pixel in cross-section, so that the first semiconductor region starts from a contiguous one
  • Base layer in the direction away from the emission side per pixel each have at least narrower feet and subsequently wider heads.
  • Monolithic, ie of a contiguous semiconductor designed pixelated chips are usually with
  • Semiconductor materials are dispensed with plasma processes, along with the prevention of plasma damage
  • the pixels become epitaxial Are defined.
  • a n-contact in particular a dielectric layer is to be opened for this purpose.
  • a pn junction and / or an active zone is buried in the epitaxial layer and is not exposed as in conventionally structured mesaflanks.
  • a growth mask is preferably formed on an n-GaN layer
  • Silicon dioxide or silicon nitride structured. Openings in the mask material define the later pixels, especially the feet. By this method are also very small
  • the preferably p-doped second semiconductor region is also grown on the side edges of the pixels, so that the entire structure has no laterally exposed pn junction. This facilitates passivation of the semiconductor material.
  • a large reflective surface on a p-doped surface, a large reflective
  • n-GaN surface can be contacted directly. Alternatively, a pre-application of the growth mask may occur
  • Contact material can be applied to a larger one Connection surface to allow the n-GaN.
  • n-contact can also be applied in the area between pixels from an n-side.
  • a contact material that is applied between the pixels, ie on the n-side and / or on the p-side, can additionally reduce or prevent optical crosstalk between the individual pixels.
  • a contrast between the pixels can be increased.
  • the mask layer is designed to be patterned into the pixels.
  • the mask layer is made of a material on which the
  • Semiconductor material of the semiconductor layer sequence does not grow or grows poorly.
  • Multipixel chip a second mirror.
  • the second mirror is preferably located directly on the second
  • the second mirror may be a metal mirror, a TCO mirror or a combination mirror, ie a
  • Metal mirror with a TCO contact layer and optionally with a dielectric mirror act Metal mirror with a TCO contact layer and optionally with a dielectric mirror act.
  • Mask layer parallel to the emission side and covers the base layer in part. The feet are out of openings of the
  • Mask layer grown out.
  • the entire Base layer seen in plan view and covered on a contact side facing the mask layer together with the feet and an electrical contact of the base layer.
  • Mask layer the feet seen in top view. That is, the mask layer preferably extends in each case in a continuous path around the associated foot.
  • the mask layer is partially covered by the heads. That is, the heads are in particular three-dimensional starting from the feet
  • a thickness of the heads can approximately correspond to a projection of the heads on the mask layer, for example, with a tolerance of at most a factor of 5 or 3 or 1.5.
  • the mask layer completely fills a region between the base layer and the heads. This is especially true in the direction perpendicular to the emission side.
  • the mask layer has a recess between at least some of the pixels. Through the recess, the first contact is in
  • the first contact can touch the first semiconductor region.
  • the Multipixel chip a first mirror.
  • the first mirror is preferably located directly on the first
  • the first mirror is electrically contacted directly via the first contact.
  • the first mirror can be set up to impress current from the first contact into the first semiconductor region.
  • the first mirror is a metal mirror.
  • a TCO mirror or in turn a combination mirror made of metal and TCO and optionally at least one dielectric or even a possibly electrically conductive Bragg mirror can be used.
  • the first mirror lies partially or completely between the base layer and the mask layer. That is, the first mirror may be partially or completely buried under the mask layer. In this way, compared with the use of only the first contact, an enlarged electrical contact surface can be realized towards the first semiconductor region.
  • the first mirror in particular for an n-contact, it is also possible to use a transparent conductive oxide, TCO for short, which does not reflect or does not significantly reflect.
  • an absorbing component may be present to increase, for example, a contrast between the pixels.
  • the mask layer and the first mirror are between the base layer and the first mirror
  • Mask layer preferably covers the first mirror. That is, per foot, a plurality of recesses are formed in the mask layer and in the first mirror. At a The side facing away from the base region of the mask layer, the first semiconductor region is then to each in themselves
  • the recesses in the mask layer form individual growth islands, starting from which the islands make up the corresponding foot
  • a thickness of the feet preferably corresponds to a thickness of the mask layer or a thickness of the mask layer together with the first mirror located between the mask layer and the base layer.
  • Multipixel chip one or more electrically insulating
  • Passivation layer is located at one of the
  • Mask layer is enough and the mask layer at least
  • the passivation layer preferably completely fills a region between the base layer and the heads, in particular in the direction perpendicular to the emission side. That is, when removing the
  • Mask layer remain undercuts below the heads and towards the base layer. These undercuts are used in creating the passivation layer of a Material of the passivation layer preferably completely filled. This remains despite the removal of the
  • the passivation layer partially covers the optionally present first mirror, such that the first mirror may be buried under the passivation layer together with the first contact.
  • the second mirror predominantly or completely covers the side surfaces of the second semiconductor region in the region of the heads.
  • Predominantly means preferably at least 50% or 70% or 90%. This makes it possible to achieve a high reflectivity of the radiation generated in the active zone towards the emission side.
  • the second mirror is a combination of a metallic mirror and a mirror
  • dielectric mirror in particular to minimize losses adjacent to the metal mirror.
  • the second contact of the respectively associated pixel covered in plan view covers at least 25% or 50% or 70% or 90%.
  • the second contact itself can act as a mirror and the second mirror can optionally be omitted.
  • the first contact is partially or completely in trenches between
  • the ditches reach to the
  • the multipixel chip can be designed as a flip-chip.
  • the first contact extends from the trenches to one of the trenches
  • the first and the second contact can lie in a common plane.
  • the first contact is attached to the emission layer on the base layer.
  • recesses or openings through the mask layer and / or the passivation layer can be avoided.
  • the first and second contacts may be attached to different sides of the base layer.
  • a preferably electrically insulating planarization is located between adjacent pixels. It is possible that the planarization in Direction away from the base layer is flush with the second semiconductor region.
  • the second contact extends to the planarization.
  • the planarization is partially covered by the second contact and optionally by the second mirror.
  • Planarization formed through a via By way of the at least one via, it is possible to dispose the first contact away from one of the base layers
  • several or all of the pixels have a common first contact.
  • the first contact is a common voltage potential, such as a ground contact.
  • each pixel has or small
  • the first contact provided for a plurality of the pixels is in
  • the first contact may be punctiform or shaped like a grid.
  • punctiform means that the associated recess in the mask layer and / or the
  • Passivation layer for the first contact an area of at most 20% or 5% or 2% of an area of at least having an associated pixel. This is especially true in plan view.
  • the pixels are in
  • Phosphors for different colors efficiently interconnect to a pixel.
  • an area ratio of the pixels on a total area of the emission side is at least 60% or 70% or 80%.
  • this area percentage is at most 95% or 90% or 80%.
  • This high area ratio can be achieved in particular by a hexagonal arrangement of the pixels.
  • the active zone is preferably configured to produce near ultraviolet radiation or blue light or, less preferably, green light.
  • the wavelength of maximum intensity of the light generated in the active zone is preferably at least 405 nm or 430 nm and / or at most 550 nm or 520 nm or 480 nm or 470 nm. If the semiconductor layer sequence is based on a different material system, then in the active zone
  • green, orange or red light or infrared radiation can be generated.
  • the feet have a width of at least 2 ym or 4 ym or 10 ym.
  • this width is at most 150 ym or 100 ym or 50 ym or 20 ym.
  • a lateral projection of the heads over the feet is preferably around at least 0.1 ym or 0.2 ym or 0.4 ym
  • a thickness of the heads is preferably at least 30 nm or 50 nm or 100 nm and / or at most 2 ym or 1 ym or 0.6 ym.
  • the pixels have an aspect ratio of a width and a height of
  • the aspect ratio is at most 300 or 100 or 50 or 20.
  • the base layer is provided with a roughening on the emission side.
  • Roughening is preferably limited to the base layer so that the feet are not affected by the roughening.
  • the multipixel chip is arranged on a carrier.
  • the carrier can be a silicon carrier, which has, for example on the basis of CMOS, a plurality of drive devices, in particular for the second contact and thus for the individual pixels.
  • the carrier can also without control electronics
  • TSV Through Silicon Via
  • Multipixel chip one or more phosphors.
  • the at least one phosphor it is possible that the
  • Pixels are interconnected, in particular to RGB pixels.
  • a phosphor is preferred for
  • an RBG light source can be built.
  • Multipixel chips specified.
  • the multi-pixel chip is configured as indicated in connection with one or more of the above embodiments. Features of the method are therefore also disclosed for the multipixel chip and vice versa.
  • the method comprises the following steps, preferably in the order given:
  • Figure 1 is a schematic sectional view of a
  • FIGS. 2A to 2F are schematic sectional views of FIG.
  • FIGS 3 to 8 are schematic sectional views of
  • Figures 9A, 9B, 10A, 10B and IOC are schematic plan views of embodiments of multipixel chips described herein.
  • Figure 1 is an embodiment of a
  • Multipixel chip 1 comprises a semiconductor layer sequence 2.
  • the semiconductor layer sequence 2 has a first one
  • the first semiconductor region 21 which is preferably n-type.
  • the first semiconductor region 21 is composed of a continuous base layer 24 and respective feet 25 and heads 26 associated with a pixel 3, between the first semiconductor region 21 and a second semiconductor region 22 there is an active zone 23 for light generation.
  • the second semiconductor region 22 is preferably p-type doped.
  • the active zone 23 extends mainly parallel to an emission side 10 of the multipixel chip 1.
  • the emission side 10 may be provided with a roughening.
  • only areas of the active zone 23 for light generation are set up, which are oriented parallel to the emission side 10. Regions of the active region 23 located on side surfaces of the heads 26 of the first semiconductor region 21 are not provided for light generation.
  • quantum well structures on the side surfaces of the heads 26 have lower thicknesses and hence higher energy levels, so that the quantum wells on the side surfaces effectively act as barrier layers.
  • the mask layer 5 is preferred
  • the grid-shaped mask layer 5 in the direction parallel to the emission side 10 in each case directly adjoins the feet 25.
  • a respective second mirror 62 On the emission side 10 facing away from upper sides 20 of the insular patterned second semiconductor region 22 is preferably a respective second mirror 62. Der second mirror 62 is limited according to Figure 1 on the top 20 and covers the top 20 almost completely.
  • a preferably continuous passivation layer 71 is applied, for example of an oxide such as silicon dioxide, Al 2 O 3, TaO, HfO, NbO or of a nitride such as silicon nitride or of an oxynitride like SiO x Ny.
  • the passivation layer 71 has openings. Via these openings, in the trenches between the pixels 3, a first electrical contact 41 is attached, which electrically contacts the base layer 24.
  • a second electrical contact 42 is used for electrically connecting the second mirror 62.
  • the contacts 41, 42 are preferably metallic contacts.
  • the multipixel chip 1 according to FIG. 1 can be produced without an etching process of the semiconductor layer sequence 2 being required.
  • a corresponding manufacturing process is in
  • a sapphire substrate the base layer 24 grown epitaxially.
  • the base layer 24 is made of n-doped GaN, for example.
  • a thickness of the base layer 24 is, for example, at least 1 ⁇ m and / or at most 7 ⁇ m.
  • the mask layer 5 is applied to the base layer 24.
  • a material for the mask layer 5 can already be patterned and thus applied only locally, or the material for the mask layer is applied continuously and patterned only below.
  • the mask layer 5 is made of silicon dioxide.
  • a thickness of Mask layer 5 is preferably at least 10 nm or 50 nm and / or at most 1 ⁇ m.
  • the feet 25 and the heads 26 for the pixels 3 are grown. As the heads 26 grow, the mask layer 5 is partially overmolded. However, a space between adjacent pixels above the mask layer 5 remains free.
  • Semiconductor material for the first semiconductor region 21 does not grow on the mask layer 5, or does not grow significantly.
  • the active zone 23 and the second semiconductor region 22 are deposited on the heads 26.
  • the mask layer 5 remains free in places.
  • the active zone 23 and the second semiconductor region 22 can extend to the mask layer 5.
  • Passivation layer 71 deposited. This covers the
  • Passivation layer 71 the mask layer 5 in certain areas directly. A thickness of the passivation layer 71 is located
  • the openings in the passivation layer 71 are produced. Then the openings in the passivation layer 71 are produced.
  • the contacts 41, 42 are individually processed.
  • the growth substrate 29 is finally removed and the roughening is generated in order to arrive at the embodiment of FIG.
  • Semiconductor region 21 is located below the mask layer 5 according to Figure 3, a first mirror 61.
  • the first mirror 61 is generated in front of the mask layer 5.
  • the first mirror 61 is preferably made of a
  • the first mirror 61 is made of palladium, platinum, titanium and / or chromium. Due to the elevated temperatures during the growth of the following semiconductor materials 22, 23, the material of the first mirror 61 can be alloyed into the base layer 24. As a result, an improved electrical contact can be achieved.
  • a transparent conductive oxide, TCO for short, may also be used, in particular in order to achieve larger electrical contact areas.
  • the component is the one above each labeled with the first mirror 61, not
  • FIG. 4 illustrates that the mask layer 4
  • Base layer 24 preferably each of the first mirror 61.
  • the mask layer 5 and the first mirror 61 are thus arranged congruently in the feet 25, wherein the mask layer 5 preferably covers side surfaces of the first mirror 61.
  • a transparent conductive material in particular a TCO such as ITO, instead of the metallic first mirror 61.
  • a distance between adjacent regions of the mask layer 5 within a pixel 3 is preferably at least three times a width of the individual regions
  • a width of webs with the mask layer 5 within the pixels 3 is preferably at most 3 ym.
  • a total coverage of the pixels 3 in the region of the feet 25 with a material of the mask layer 5 is preferably at most 20%,
  • a lateral extent of the first contact 41 within the trench is preferably at least 0.4 ⁇ m and / or at most 2 ⁇ m.
  • Semiconductor regions 22 of adjacent pixels 3 is preferably at least 0.3 ym or 0.5 ym and / or at most 2 ym or 1.5 ym.
  • a width of the mask layer 5 between adjacent pixels 3 is preferably at least 1 ⁇ m or 1.5 ⁇ m and / or at most 10 ⁇ m or 5 ⁇ m.
  • FIG. 5 illustrates that the mask layer is removed after the heads 26 have grown, for example by wet-chemical etching.
  • This formed undercuts 73 are preferably completely through the material of
  • Passivation layer 71 filled.
  • the first mirror 61 can be deposited congruently with the first contact 41.
  • the two mirrors 61, 62nd are illustrated in FIG. 5 that the first mirror 61 can be deposited congruently with the first contact 41.
  • the two mirrors 61, 62nd are illustrated in FIG. 5 that the two mirrors 61, 62nd
  • the passivation layer 71 also extends to a small extent on the first mirror 61.
  • both mirrors 61, 62 are preferably in the same
  • the passivation layer 71 each extends to the mirrors 61, 62 and the passivation layer 71 is then partially covered by the respective contact 41, 42.
  • openings of the passivation layer 71 and the contacts 41, 42 may also be congruent.
  • the second mirror 62 extends to the mask layer 5. This is possible in all other embodiments. in the
  • FIG. 6 is identical to FIG.
  • FIG. 7 shows that the trenches between adjacent pixels 3 are filled with a planarization 72.
  • the planarization is for example made of a spin on glass or of a thick coating with a subsequent coating
  • planarization 72 is
  • reflective materials such as metals or combinations thereof can be used.
  • the passivation layer may additionally be present, not shown in FIG. Analogous to FIG. 5, it is possible for the mask layer to be removed before the planarization 72 is generated.
  • Mask layer 5 is still present to the same extent as in the growth of the heads 25 and the feet 26th
  • the second mirror 62 and the second contact 42 extend partially onto the planarization 72.
  • the first contact 41 is located on the emission side 10.
  • the first contact 41 may be designed to be light-absorbing for increased contrast or else reflective or transparent, for example from a TCO, in order to achieve increased brightness.
  • FIG. 8 it is shown that the planarization 72 is penetrated by a via, so that the first contact 41 can be attached to the same side as the second contact 42. Thus, the first contact 41 can be partially buried in the planarization 72.
  • the semiconductor layer sequence 2 with the contacts 41, 42 it is in each case possible for the semiconductor layer sequence 2 with the contacts 41, 42 to be attached to a carrier 8.
  • the carrier 8 is, for example, a
  • At least one phosphor 9 may be present.
  • blue light from the active zone 23 can be used to generate green and / or red light via the phosphor 9, so that a total of RGB pixels are formed, for example, three or four of the pixels 3, to which the
  • Semiconductor layer sequence 2 is structured, are composed.
  • the individual pixels 3 are each arranged in a square grid and in
  • Top view seen in approximately square shape.
  • FIG. 9A it can be seen that a plurality of the pixels 3 are electrically connected by a punctiform first contact 41
  • the first contact 41 is located in the trench between the adjacent pixels 3 or at the
  • Contact 41 frame around the pixels 3 around.
  • the pixels 3 are thus formed by islands in the first contact 41. If the first contact 41 is located on the emission side 10, an increased contrast ratio can be achieved by means of an opaque first contact 41.
  • the pixels 3 are hexagonal, viewed in plan view in each case.
  • FIGS. 10A and 10B correspond to FIGS. 9A and 9B. Furthermore, it can be seen from FIG. 10A that the first contact 41 does not need to be of a square design, but may also be diamond-shaped. Likewise, the first contact 41, unlike drawn, also be round or hexagonal shaped, each seen in plan view.
  • hexagonal patterns are arranged. This allows a high filling factor of the pixels 3 in a total area of the

Abstract

Selon un mode de réalisation, l'invention concerne une puce multipixel (1) optoélectronique qui comprend une pluralité de pixels (3) commandables individuels électriques pour la production et le rayonnement de lumière. Une première zone semi-conductrice (21) s'étend en continu sur les pixels (3). Une deuxième zone semi-conductrice (22) est structurée pour constituer les pixels (3). Une zone active (23) pour la production de la lumière se trouve entre la première et la deuxième zone semi-conductrice (21, 22). Un premier contact (41) sert à l'établissement du contact électrique de la première zone semi-conductrice (21) et un deuxième contact (42) sert à l'établissement du contact électrique de la deuxième zone semi-conductrice (42). La zone active (23) ne sert à la production de la lumière que dans une direction parallèle à un côté d'émission (10) de la puce multipixel (1). La première zone semi-conductrice (21) est conçue par pixel (3) de manière fongiforme en vue de section transversale.
PCT/EP2019/056156 2018-03-13 2019-03-12 Puce multipixel et procédé de fabrication d'une puce multipixel WO2019175168A1 (fr)

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DE102018105786.5A DE102018105786A1 (de) 2018-03-13 2018-03-13 Multipixelchip und Verfahren zur Herstellung eines Multipixelchips
DE102018105786.5 2018-03-13

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DE102020116871A1 (de) 2020-06-26 2021-12-30 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronischer halbleiterchip

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DE102011056888A1 (de) * 2011-12-22 2013-06-27 Osram Opto Semiconductors Gmbh Anzeigevorrichtung und Verfahren zur Herstellung einer Anzeigevorrichtung
DE102012109460A1 (de) * 2012-10-04 2014-04-10 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Leuchtdioden-Displays und Leuchtdioden-Display
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DE102013104273A1 (de) * 2013-04-26 2014-10-30 Osram Opto Semiconductors Gmbh Anordnung mit säulenartiger Struktur und einer aktiven Zone
US20140326945A1 (en) * 2013-05-02 2014-11-06 Commissariat A L'energie Atomique Et Aux Energies Optoelectronic Arrangement Provided with a Semiconductor Nanowire with a Longitudinal Section that is Surrounded by a Part of a Mirror

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DE102012109460A1 (de) * 2012-10-04 2014-04-10 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Leuchtdioden-Displays und Leuchtdioden-Display
US20140246647A1 (en) * 2013-01-29 2014-09-04 Samsung Electronics Co., Ltd. Nanostructure light emitting device and method of manufacturing the same
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US20140326945A1 (en) * 2013-05-02 2014-11-06 Commissariat A L'energie Atomique Et Aux Energies Optoelectronic Arrangement Provided with a Semiconductor Nanowire with a Longitudinal Section that is Surrounded by a Part of a Mirror

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