WO2019175168A1

WO2019175168A1 - Multi-pixel chip and method for producing a multi-pixel chip

Info

Publication number: WO2019175168A1
Application number: PCT/EP2019/056156
Authority: WO
Inventors: Clemens VIERHEILIG; Tobias Meyer; Dominik Scholz
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2018-03-13
Filing date: 2019-03-12
Publication date: 2019-09-19
Also published as: DE102018105786A1

Abstract

In one embodiment, the optoelectronic multi-pixel chip (1) comprises a plurality of pixels (3) which can be individually electrically activated to generate and emit light. A first semiconductor region (21) extends continuously across the pixels (3). A second semiconductor region (22) is structured on the pixels (3). An active zone (23) for generating the light is disposed between the first and second semiconductor regions (21, 22). A first contact (41) is provided for making electrical contact with the first semiconductor region (21), and a second contact (42) is provided for making electrical contact with the second semiconductor region (42). The active zone (23) is designed to generate the light only in a direction parallel to an emission side (10) of the multi-pixel chip (1). The first semiconductor region (21) has a mushroom-shaped cross-section per pixel (3).

Description

description

MULTIPIXELCHIP AND METHOD FOR THE PRODUCTION OF A

MULTI PIXEL CHIPS

A multipixel chip is specified. In addition, a method for producing a multipixel chip is specified.

An object to be solved is to specify a multipixel chip that is efficiently structured into individual pixels.

This object is achieved inter alia by a multipixel chip having the features of claim 1. preferred

Further developments are the subject of the other claims.

According to at least one embodiment, the

Optoelectronic Multipixelchip a variety of pixels. The pixels are electrically controllable in groups or individually. The pixels are set up to generate and emit light. In other words, the multipixel chip is in particular a pixelated LED chip.

According to at least one embodiment, the

Multipixel chip a first semiconductor region. For example, the first semiconductor region is n-type. The first

Semiconductor region may consist of a single semiconductor layer or of a plurality of semiconductor layers

be composed. At least one semiconductor layer of the first semiconductor region extends continuously over some or all of the pixels. In accordance with at least one embodiment, the multipixel chip comprises a second semiconductor region, which

for example, p-doped. The second semiconductor region thus has a different conductivity type than the first semiconductor region. Furthermore, the second semiconductor region is structured to the pixels.

According to at least one embodiment, the

Multipixel chip an active zone. The active zone is set up to generate the light. The active zone is between the first and the second semiconductor region

arranged. In all the pixels in the active zone, light of the same color and / or the same is preferred

generated spectral composition, in the context of

Production stamping.

In accordance with at least one embodiment, the first form

Semiconductor region, the active zone and the second

Semiconductor region a semiconductor layer sequence. The active zone preferably contains a pn junction, a single quantum well structure or a radiation generator for generating the radiation

Multiple quantum well structure.

The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride

Compound semiconductor material such as Al _n In _] __ _nm Ga _m N or a phosphide compound semiconductor material such as

Al _n In _] __ _nm Ga _m P or even an arsenide

Compound semiconductor material such as Al _n In _] __ _nm Ga _m As or as Al _n Ga _m In _] __ _nm As P _] _-k, where each 0 dn <1, 0 dm <1 and n + m <1 and 0 dk <1 is. Preferably, at least one layer or all layers of the Semiconductor layer sequence 0 <n <0.8, 0.4 <m <1 and n + m <0.95 and 0 <k <0.5. It can the

Semiconductor layer sequence dopants and additional

Have constituents. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, that is to say Al, As, Ga, In, N or P, are indicated, even if these may be partially replaced and / or supplemented by small amounts of further substances.

According to at least one embodiment, the

Multipixel chip a first contact and a second

Contact. The first and the second contact are for

designed electrical contacting of the first semiconductor region and the second semiconductor region. The first and the second contact are preferably metallic contacts, but may optionally also comprise transparent conductive oxides, in short TCOs. In particular, the second contact is also structured to the pixels, so that the second contact preferably by a plurality of island-shaped

Subareas is formed to the pixels over the second

Contact electrically independently of each other to be able to control.

According to at least one embodiment, the active zone is only in regions parallel to an emission side of the

Multipixel chips are oriented, set up to generate the light. The emission side is oriented in particular perpendicular to a main growth direction of the semiconductor layer sequence. In geometric terms, the active zone has areas that are oblique to the emission side. However, these areas of the active zone are not designed to generate the light and contribute to a total luminous intensity of the multipixel chip preferably at most 5% or 1% or 0.2% and are thus negligible with regard to the light emission.

The terms "parallel" and "vertical" are understood here and below preferably with a tolerance of at most 10 ° or 5 ° or 1 °.

In accordance with at least one embodiment, the first one

Semiconductor region per pixel seen in cross-section mushroom-shaped. That is, starting from a contiguous base layer, the first semiconductor region in the direction away from the emission side per pixel first has narrower feet. Starting from the feet, a broadening follows per pixel, so that broader heads are formed opposite the feet. Both the base layer and the feet and the heads are parts of the first semiconductor region. In particular, the feet and the heads can be epitaxially grown without temporal interruption in one another.

In at least one embodiment, the

Optoelectronic Multipixelchip a variety of electrically individually controllable pixels for generating and emitting light. A first semiconductor region extends with at least one semiconductor layer continuously over at least some of the pixels. A second semiconductor region having a different conductivity type than the first one

Semiconductor area, is structured to the pixels. An active zone for generating the light is located between the first and the second semiconductor region. A first contact is for electrical contacting of the first

Semiconductor region provided and a second contact for electrically contacting the second semiconductor region. The active zone is only parallel to one direction

Emission side of the multi-pixel chip for generating the light set. The first semiconductor region is designed mushroom-shaped per pixel in cross-section, so that the first semiconductor region starts from a contiguous one

Base layer in the direction away from the emission side per pixel each have at least narrower feet and subsequently wider heads.

Monolithic, ie of a contiguous semiconductor designed pixelated chips are usually with

comparatively great effort from planar

Epitaxy structures produced. Due to high demands on an accuracy of structuring processes, an achievable pixel size and thus a resolution of such chips is limited. In particular, plasma processes leading to

Dividing the semiconductor into which pixels are used, damage to side edges, resulting in poorer performance and stability of the pixels. This here

described multipixel chip and the one described here

In contrast, methods allow the production of monolithically pixelated chips with very small distances between the pixels, without the use of plasma processes for

Structuring the semiconductor layer sequence.

In particular, due to a mask layer already while growing the pixel can be completely based on a structuring of

Semiconductor materials are dispensed with plasma processes, along with the prevention of plasma damage

Side faces. Such plasma damage can lead to leakage current paths or be responsible for degradation mechanisms. In the multipixel chip described herein and the method described herein, the pixels become epitaxial Are defined. For a n-contact, in particular a dielectric layer is to be opened for this purpose. In addition, a pn junction and / or an active zone is buried in the epitaxial layer and is not exposed as in conventionally structured mesaflanks.

For the epitaxial definition of the pixels, a growth mask is preferably formed on an n-GaN layer

Silicon dioxide or silicon nitride structured. Openings in the mask material define the later pixels, especially the feet. By this method are also very small

Distances between the individual pixels possible. In the

Openings, the semiconductor layer sequence for the pixels grown, so in particular the feet and the heads.

As a result of this growth method, the preferably p-doped second semiconductor region is also grown on the side edges of the pixels, so that the entire structure has no laterally exposed pn junction. This facilitates passivation of the semiconductor material. In addition, on a p-doped surface, a large reflective

Contact layer can be applied without the pn junction is shorted. With this method can a

reflective surface and be larger than an active area of the active zone in the individual pixels. As a result, optical losses at edge regions of the pixels can be minimized.

In particular, for the n-contact is only the

Growth mask between the pixels to open. The n-GaN surface can be contacted directly. Alternatively, a pre-application of the growth mask may occur

Contact material can be applied to a larger one Connection surface to allow the n-GaN. For the

Contacting a metal layer on the n-GaN reach smaller recesses in the overlying growth mask. Furthermore, alternatively, the n-contact can also be applied in the area between pixels from an n-side.

A contact material that is applied between the pixels, ie on the n-side and / or on the p-side, can additionally reduce or prevent optical crosstalk between the individual pixels. Thus, a contrast between the pixels can be increased.

According to at least one embodiment, the

Multipixel chip a mask layer. The mask layer is designed to be patterned into the pixels. In particular, the mask layer is made of a material on which the

Semiconductor material of the semiconductor layer sequence does not grow or grows poorly.

According to at least one embodiment, the

Multipixel chip a second mirror. The second mirror is preferably located directly on the second

Semiconductor region. Above the second mirror, it is possible to impress current in the second semiconductor region. The second mirror may be a metal mirror, a TCO mirror or a combination mirror, ie a

Metal mirror with a TCO contact layer and optionally with a dielectric mirror act.

According to at least one embodiment, the

Mask layer parallel to the emission side and covers the base layer in part. The feet are out of openings of the

Mask layer grown out. In particular, the entire Base layer seen in plan view and covered on a contact side facing the mask layer together with the feet and an electrical contact of the base layer.

According to at least one embodiment, the frame framed

Mask layer the feet seen in top view. That is, the mask layer preferably extends in each case in a continuous path around the associated foot.

In accordance with at least one embodiment, the mask layer is partially covered by the heads. That is, the heads are in particular three-dimensional starting from the feet

grown, so that a thickness of the heads can approximately correspond to a projection of the heads on the mask layer, for example, with a tolerance of at most a factor of 5 or 3 or 1.5.

In accordance with at least one embodiment, the mask layer completely fills a region between the base layer and the heads. This is especially true in the direction perpendicular to the emission side. Thus it is possible that in the

Semiconductor layer sequence no gaps occur, especially not in the area of the feet.

In accordance with at least one embodiment, the mask layer has a recess between at least some of the pixels. Through the recess, the first contact is in

Direction led to the first semiconductor region. In this case, the first contact can touch the first semiconductor region.

According to at least one embodiment, the

Multipixel chip a first mirror. The first mirror is preferably located directly on the first

Semiconductor region. In particular, the first mirror is electrically contacted directly via the first contact. Thus, the first mirror can be set up to impress current from the first contact into the first semiconductor region. Preferably, the first mirror is a metal mirror. Alternatively, as in the second mirror, a TCO mirror or in turn a combination mirror made of metal and TCO and optionally at least one dielectric or even a possibly electrically conductive Bragg mirror can be used.

In accordance with at least one embodiment, the first mirror lies partially or completely between the base layer and the mask layer. That is, the first mirror may be partially or completely buried under the mask layer. In this way, compared with the use of only the first contact, an enlarged electrical contact surface can be realized towards the first semiconductor region.

Alternatively, instead of the first mirror, in particular for an n-contact, it is also possible to use a transparent conductive oxide, TCO for short, which does not reflect or does not significantly reflect. Also, instead of the first mirror, an absorbing component may be present to increase, for example, a contrast between the pixels.

According to at least one embodiment, the mask layer and the first mirror are between the base layer and the

Heads each designed grid-shaped, the

Mask layer preferably covers the first mirror. That is, per foot, a plurality of recesses are formed in the mask layer and in the first mirror. At a The side facing away from the base region of the mask layer, the first semiconductor region is then to each in themselves

contiguous and per pixel gapless heads

grown together. In other words, the recesses in the mask layer form individual growth islands, starting from which the islands make up the corresponding foot

is composed to the one-piece head

grow together.

A thickness of the feet preferably corresponds to a thickness of the mask layer or a thickness of the mask layer together with the first mirror located between the mask layer and the base layer.

According to at least one embodiment, the

Multipixel chip one or more electrically insulating

Passivation layers. The at least one

Passivation layer is located at one of the

Emission side facing away from the first and / or the second semiconductor region. It is possible that the

Passivation layer from one of the emission side facing away from the top of the second semiconductor region to the

Mask layer is enough and the mask layer at least

partially covered and touched.

According to at least one embodiment, no mask layer is present. In this case, the passivation layer preferably completely fills a region between the base layer and the heads, in particular in the direction perpendicular to the emission side. That is, when removing the

Mask layer remain undercuts below the heads and towards the base layer. These undercuts are used in creating the passivation layer of a Material of the passivation layer preferably completely filled. This remains despite the removal of the

Mask layer in the area of the feet no gaps in the

Semiconductor layer sequence.

According to at least one embodiment, the

Passivation layer between at least some of the pixels on a recess, in particular a punctiform

Recess. Through the recess is the first

Contact led in the direction of the first semiconductor region. Thus, an electrical contacting of the first semiconductor region can take place through the passivation layer. It is possible that the passivation layer partially covers the optionally present first mirror, such that the first mirror may be buried under the passivation layer together with the first contact.

According to at least one embodiment, the second mirror predominantly or completely covers the side surfaces of the second semiconductor region in the region of the heads. Predominantly means preferably at least 50% or 70% or 90%. This makes it possible to achieve a high reflectivity of the radiation generated in the active zone towards the emission side. Optionally, the second mirror is a combination of a metallic mirror and a mirror

dielectric mirror, in particular to minimize losses adjacent to the metal mirror.

In accordance with at least one embodiment, the second contact of the respectively associated pixel covered in plan view covers at least 25% or 50% or 70% or 90%. Thus, the second contact itself can act as a mirror and the second mirror can optionally be omitted. According to at least one embodiment, the first contact is partially or completely in trenches between

neighboring pixels. The ditches reach to the

Mask layer, the passivation layer or the

Base layer, so in particular together with the first mirror, an electrical contact of the first

Semiconductor region is given. By arranging the first contacts at least partially in the trenches, the first and the second contact on the same side of the

Base layer be attached. Thus, the multipixel chip can be designed as a flip-chip.

In accordance with at least one embodiment, the first contact extends from the trenches to one of the trenches

Base layer facing away from the top of the second

Semiconductor region. Thus, the first and the second contact can lie in a common plane. Thus, for the electrical contacting of the first and the second

Contact prefers to bridge no height difference between the first and the second contact.

In accordance with at least one embodiment, the first contact is attached to the emission layer on the base layer. By this arrangement, recesses or openings through the mask layer and / or the passivation layer can be avoided. Thus, the first and second contacts may be attached to different sides of the base layer.

According to at least one embodiment, a preferably electrically insulating planarization is located between adjacent pixels. It is possible that the planarization in Direction away from the base layer is flush with the second semiconductor region.

In accordance with at least one embodiment, the second contact extends to the planarization. In other words, the planarization is partially covered by the second contact and optionally by the second mirror.

According to at least one embodiment is by the

Planarization formed through a via. By way of the at least one via, it is possible to dispose the first contact away from one of the base layers

Top of the planarization to the first mirror or lead to the first semiconductor region.

In accordance with at least one embodiment, several or all of the pixels have a common first contact.

For example, the first contact is a common voltage potential, such as a ground contact.

At the same time, preferably, each pixel has or small

Groups of pixels via a separate second contact, so that despite the common first contact, the pixels or groups are individually controlled electrically.

In accordance with at least one embodiment, the first contact provided for a plurality of the pixels is in

Top view seen between the associated pixels. In this case, the first contact may be punctiform or shaped like a grid. For example, punctiform means that the associated recess in the mask layer and / or the

Passivation layer for the first contact an area of at most 20% or 5% or 2% of an area of at least having an associated pixel. This is especially true in plan view.

In accordance with at least one embodiment, the pixels are in

Top view seen arranged in a square, rectangular or hexagonal grid. This can be achieved that several pixels, especially with downstream

Phosphors for different colors, efficiently interconnect to a pixel.

According to at least one embodiment, an area ratio of the pixels on a total area of the emission side is at least 60% or 70% or 80%. Alternatively or

in addition, this area percentage is at most 95% or 90% or 80%. This high area ratio can be achieved in particular by a hexagonal arrangement of the pixels.

According to at least one embodiment, the

Semiconductor layer sequence on the AlInGaN material system. In this case, the active zone is preferably configured to produce near ultraviolet radiation or blue light or, less preferably, green light. A

The wavelength of maximum intensity of the light generated in the active zone is preferably at least 405 nm or 430 nm and / or at most 550 nm or 520 nm or 480 nm or 470 nm. If the semiconductor layer sequence is based on a different material system, then in the active zone

Alternatively, green, orange or red light or infrared radiation can be generated.

According to at least one embodiment, the feet have a width of at least 2 ym or 4 ym or 10 ym.

Alternatively or additionally, this width is at most 150 ym or 100 ym or 50 ym or 20 ym. In this case, a lateral projection of the heads over the feet is preferably around at least 0.1 ym or 0.2 ym or 0.4 ym

and / or at most 1.5 ym or 1 ym or 0.6 ym. A thickness of the heads is preferably at least 30 nm or 50 nm or 100 nm and / or at most 2 ym or 1 ym or 0.6 ym.

In accordance with at least one embodiment, the pixels have an aspect ratio of a width and a height of

at least 1 or 3 or 5 or 8 on. Alternatively or additionally, the aspect ratio is at most 300 or 100 or 50 or 20.

In accordance with at least one embodiment, the base layer is provided with a roughening on the emission side. The

Roughening is preferably limited to the base layer so that the feet are not affected by the roughening.

In accordance with at least one embodiment, the multipixel chip is arranged on a carrier. The carrier can be a silicon carrier, which has, for example on the basis of CMOS, a plurality of drive devices, in particular for the second contact and thus for the individual pixels. Likewise, the carrier can also without control electronics

be executed, for example, as mechanically stable

Silicon carrier with TSV vias of each pixel. TSV stands for Through Silicon Via, ie

Through-hole through silicon.

According to at least one embodiment, the

Multipixel chip one or more phosphors. About the at least one phosphor, it is possible that the

single pixel to different colors emitting Pixels are interconnected, in particular to RGB pixels. In this case, a phosphor is preferred for

Generation of white light downstream of all pixels or there is a structured application of several

different phosphors each for a full conversion for green and red, possibly for white, with blue light directly and a phosphor can be generated. Thus, an RBG light source can be built.

In addition, a method of producing a

Multipixel chips specified. The multi-pixel chip is configured as indicated in connection with one or more of the above embodiments. Features of the method are therefore also disclosed for the multipixel chip and vice versa.

In at least one embodiment, the method comprises the following steps, preferably in the order given:

A) growing the base layer,

B) applying and structuring the mask layer directly onto the base layer,

C) growing the feet from the openings of the mask layer,

D) growing the heads starting from the feet, so that the heads partly cover the mask,

E) growing the active zone and the second

Semiconductor region, so that the second semiconductor regions of adjacent pixels remain spaced, and

F) Applying the first and the second contact and optionally before the passivation layer.

In the following, a multipixel chip described here and a method described here will be explained in more detail with reference to the drawing with reference to exemplary embodiments. The same reference numerals indicate the same elements in the individual figures. However, there are no scale relationships shown, but individual elements can be exaggerated for better understanding

be shown.

Show it:

Figure 1 is a schematic sectional view of a

Embodiment of one described here

Multipixel chips,

FIGS. 2A to 2F are schematic sectional views of FIG

Method steps for producing a multipixel chip described here,

Figures 3 to 8 are schematic sectional views of

Embodiments of described here

Multipixel chips, and

Figures 9A, 9B, 10A, 10B and IOC are schematic plan views of embodiments of multipixel chips described herein.

In Figure 1 is an embodiment of a

optoelectronic multipixel chips 1 shown. Of the

Multipixel chip 1 comprises a semiconductor layer sequence 2. The semiconductor layer sequence 2 has a first one

Semiconductor region 21, which is preferably n-type. The first semiconductor region 21 is composed of a continuous base layer 24 and respective feet 25 and heads 26 associated with a pixel 3, between the first semiconductor region 21 and a second semiconductor region 22 there is an active zone 23 for light generation. The second semiconductor region 22 is preferably p-type doped.

The active zone 23 extends mainly parallel to an emission side 10 of the multipixel chip 1. In this case, the emission side 10 may be provided with a roughening. However, only areas of the active zone 23 for light generation are set up, which are oriented parallel to the emission side 10. Regions of the active region 23 located on side surfaces of the heads 26 of the first semiconductor region 21 are not provided for light generation.

In particular, growth of the semiconductor layer sequence 2 is optimized for growth perpendicular to the emission side 10. Therefore, quantum well structures on the side surfaces of the heads 26 have lower thicknesses and hence higher energy levels, so that the quantum wells on the side surfaces effectively act as barrier layers. Regarding one

Light generation is thus the active zones 23 effectively

two-dimensional and flat, whereas geometrically the active zone 23 per pixel 3 is dish-shaped.

Between adjacent pixels 3, areas of a mask layer 5 are respectively located on the bottom sides of trenches

As seen in plan view, the mask layer 5 is preferred

contiguous and surrounds the respective pixels 3 all around. In particular, the grid-shaped mask layer 5 in the direction parallel to the emission side 10 in each case directly adjoins the feet 25.

On the emission side 10 facing away from upper sides 20 of the insular patterned second semiconductor region 22 is preferably a respective second mirror 62. Der second mirror 62 is limited according to Figure 1 on the top 20 and covers the top 20 almost completely.

On side surfaces of the second semiconductor region 22 and on the mask layer 5 and on the second mirror 62, a preferably continuous passivation layer 71 is applied, for example of an oxide such as silicon dioxide, Al 2 O 3, TaO, HfO, NbO or of a nitride such as silicon nitride or of an oxynitride like SiO _x Ny. The passivation layer 71 has openings. Via these openings, in the trenches between the pixels 3, a first electrical contact 41 is attached, which electrically contacts the base layer 24. For electrically connecting the second mirror 62, a second electrical contact 42 is used. The contacts 41, 42 are preferably metallic contacts.

The multipixel chip 1 according to FIG. 1 can be produced without an etching process of the semiconductor layer sequence 2 being required. A corresponding manufacturing process is in

Compound explained with Figure 2.

According to FIG. 2A, a growth substrate 29,

For example, a sapphire substrate, the base layer 24 grown epitaxially. The base layer 24 is made of n-doped GaN, for example. A thickness of the base layer 24 is, for example, at least 1 μm and / or at most 7 μm.

According to FIG. 2B, the mask layer 5 is applied to the base layer 24. A material for the mask layer 5 can already be patterned and thus applied only locally, or the material for the mask layer is applied continuously and patterned only below. For example, the mask layer 5 is made of silicon dioxide. A thickness of Mask layer 5 is preferably at least 10 nm or 50 nm and / or at most 1 μm.

In the method step of FIG. 2C, it is illustrated that, starting from the openings in the mask layer 5, the feet 25 and the heads 26 for the pixels 3 are grown. As the heads 26 grow, the mask layer 5 is partially overmolded. However, a space between adjacent pixels above the mask layer 5 remains free. The

Semiconductor material for the first semiconductor region 21 does not grow on the mask layer 5, or does not grow significantly.

According to FIG. 2D, the active zone 23 and the second semiconductor region 22 are deposited on the heads 26. Here, too, the mask layer 5 remains free in places. The active zone 23 and the second semiconductor region 22 can extend to the mask layer 5.

In FIG. 2E, it is shown that the second mirror 62

is applied. Furthermore, the entire area is the

Passivation layer 71 deposited. This covers the

Passivation layer 71, the mask layer 5 in certain areas directly. A thickness of the passivation layer 71 is located

preferably at least 50 nm and / or at most 400 nm.

In the method step of FIG. 2F, the openings in the passivation layer 71 are produced. Then the

Contacts 41, 42 deposited. In this case, the contacts 41,

42 are applied in the same process step of the same material and with the same photomask, not

drawn, generated. Alternatively, the contacts 41, 42 are individually processed. Optionally, the growth substrate 29 is finally removed and the roughening is generated in order to arrive at the embodiment of FIG.

To an electrical contact surface to the first

Semiconductor region 21 is located below the mask layer 5 according to Figure 3, a first mirror 61. The first mirror 61 is generated in front of the mask layer 5.

According to Figure 1, the contacts 41, 42 in the direction away from the emission side 10, a height difference, the

for example, is about 0.5 ym. In order to avoid such a height difference, it is possible, as shown in FIG. 3, for the first contact 41 to be guided from the opening in the mask layer in the trench to the upper side 20. This is shown in FIG. 3 as a dashed line

illustrated.

The first mirror 61 is preferably made of a

temperature-resistant metal, the following

relatively high temperatures during the growth of the active zone 23 and the second semiconductor region 22 survives. In particular, the first mirror 61 is made of palladium, platinum, titanium and / or chromium. Due to the elevated temperatures during the growth of the following semiconductor materials 22, 23, the material of the first mirror 61 can be alloyed into the base layer 24. As a result, an improved electrical contact can be achieved.

Alternatively, for or in place of the first mirror 61, a transparent conductive oxide, TCO for short, may also be used, in particular in order to achieve larger electrical contact areas. In this case, the component is the one above each labeled with the first mirror 61, not

metallic and not mirror-like.

Otherwise, with regard to FIG. 3, the statements relating to FIGS. 1 and 2 apply.

FIG. 4 illustrates that the mask layer 4

within the Pixel 3 mesh-like structure. It is located between the mask layer 5 and the

Base layer 24 preferably each of the first mirror 61. The

The mask layer 5 and the first mirror 61 are thus arranged congruently in the feet 25, wherein the mask layer 5 preferably covers side surfaces of the first mirror 61.

In order to ensure greater efficiency, in particular with regard to light extraction, it is possible to use a transparent conductive material, in particular a TCO such as ITO, instead of the metallic first mirror 61.

Above the mask layer 5 becomes 3 per pixel

coherent head 26 grown.

A distance between adjacent regions of the mask layer 5 within a pixel 3 is preferably at least three times a width of the individual regions

Mask layer 5 to ensure high quality coalescence of the heads 26 during epitaxy. A width of webs with the mask layer 5 within the pixels 3 is preferably at most 3 ym. A total coverage of the pixels 3 in the region of the feet 25 with a material of the mask layer 5 is preferably at most 20%,

in particular at most 10%. A lateral extent of the first contact 41 within the trench is preferably at least 0.4 μm and / or at most 2 μm. A distance between the second

Semiconductor regions 22 of adjacent pixels 3 is preferably at least 0.3 ym or 0.5 ym and / or at most 2 ym or 1.5 ym. Thus, a width of the mask layer 5 between adjacent pixels 3 is preferably at least 1 μm or 1.5 μm and / or at most 10 μm or 5 μm. These small distances make it possible to achieve dense arrangements of the pixels 3.

The stated values and the explanations for the mask layer 5 and for the first mirror 61 can be present in the same way in all other exemplary embodiments.

FIG. 5 illustrates that the mask layer is removed after the heads 26 have grown, for example by wet-chemical etching. This formed undercuts 73 are preferably completely through the material of

Passivation layer 71 filled. Thus, after the generation of the passivation layer 71, there are preferably no longer any gaps in the region of the feet 25.

In addition, it is illustrated in FIG. 5 that the first mirror 61 can be deposited congruently with the first contact 41. In this case, the two mirrors 61, 62nd

simultaneously and from the same materials and with the same photomask, not drawn, are made. Thus, it is possible that the passivation layer 71 also extends to a small extent on the first mirror 61.

In this case, both mirrors 61, 62 are preferably in the same

Process step applied, then the Passivation layer 71 applied and patterned.

Subsequently, both contacts 41, 42 can be applied again in the same process step. In Figure 5 is

illustrates that the passivation layer 71 each extends to the mirrors 61, 62 and the passivation layer 71 is then partially covered by the respective contact 41, 42. Optionally, openings of the passivation layer 71 and the contacts 41, 42 may also be congruent.

Incidentally, the explanations apply in particular to FIG. 1 in the same way as in FIG. 5.

In the embodiment of Figure 6 is illustrated that the second mirror 62 and the side surfaces of the second

Semiconductor region 22 completely covered. Thus, the second mirror 62 extends to the mask layer 5. This is possible in all other embodiments. in the

Otherwise, the embodiment of FIG. 6 is identical to FIG.

FIG. 7 shows that the trenches between adjacent pixels 3 are filled with a planarization 72. The planarization is for example made of a spin on glass or of a thick coating with a subsequent coating

Planarisierungsschritt, for example, a chemical

mechanical polishing. The planarization 72 is

for example, from a transparent material such as

Silica or even from an absorbent material such as silicon nitride. Likewise, reflective materials such as metals or combinations thereof can be used.

Optionally, the passivation layer may additionally be present, not shown in FIG. Analogous to FIG. 5, it is possible for the mask layer to be removed before the planarization 72 is generated. When

Dotted line it is thus possible that the

Mask layer 5 is still present to the same extent as in the growth of the heads 25 and the feet 26th

The second mirror 62 and the second contact 42 extend partially onto the planarization 72. The first contact 41 is located on the emission side 10.

As in all other embodiments can

In particular, the first contact 41 may be designed to be light-absorbing for increased contrast or else reflective or transparent, for example from a TCO, in order to achieve increased brightness.

In FIG. 8, it is shown that the planarization 72 is penetrated by a via, so that the first contact 41 can be attached to the same side as the second contact 42. Thus, the first contact 41 can be partially buried in the planarization 72.

As in all other embodiments, it is in each case possible for the semiconductor layer sequence 2 with the contacts 41, 42 to be attached to a carrier 8. The carrier 8 is, for example, a

Electronics carrier, via the targeted control

single pixel 3 is possible.

Further, as in all embodiments, at least one phosphor 9 may be present. For example, blue light from the active zone 23 can be used to generate green and / or red light via the phosphor 9, so that a total of RGB pixels are formed, for example, three or four of the pixels 3, to which the

Semiconductor layer sequence 2 is structured, are composed.

According to the plan views in Figure 9, the individual pixels 3 are each arranged in a square grid and in

Top view seen in approximately square shape.

In FIG. 9A, it can be seen that a plurality of the pixels 3 are electrically connected by a punctiform first contact 41

are connected. The first contact 41 is located in the trench between the adjacent pixels 3 or at the

Emission side 10. For each of the pixels 3, a separate second contact 42 is provided.

In contrast, see Figure 9B, the first extends

Contact 41 frame around the pixels 3 around. The pixels 3 are thus formed by islands in the first contact 41. If the first contact 41 is located on the emission side 10, an increased contrast ratio can be achieved by means of an opaque first contact 41.

In the exemplary embodiments of FIG. 10, the pixels 3 are hexagonal, viewed in plan view in each case. As the material system AlInGaN typically with a

Hexagon geometry grows, such pixels can be 3

produce efficiently.

FIGS. 10A and 10B correspond to FIGS. 9A and 9B. Furthermore, it can be seen from FIG. 10A that the first contact 41 does not need to be of a square design, but may also be diamond-shaped. Likewise, the first contact 41, unlike drawn, also be round or hexagonal shaped, each seen in plan view.

In FIG. 1C, it can be seen that the pixels 3 are in one

hexagonal patterns are arranged. This allows a high filling factor of the pixels 3 in a total area of the

Achieve multipixel chips 1.

The components shown in the figures follow, unless otherwise indicated, preferably in the specified

Sequence directly on each other. Layers not in contact with the figures are preferably spaced apart from one another. As far as lines are drawn parallel to each other, the corresponding surfaces are preferably also aligned parallel to each other. Also, unless otherwise indicated, the relative positions of the drawn components relative to one another are correctly represented in the figures.

The invention described here is not by the

Description limited to the embodiments.

Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

This patent application claims the priority of German patent application 10 2018 105 786.5, the disclosure of which is hereby incorporated by reference. LIST OF REFERENCE NUMBERS

1 optoelectronic multipixel chip

10 emission side

2 semiconductor layer sequence

20 top

21 (n-type) first semiconductor region

22 (p-type) second semiconductor region

23 active zone

24 base layer

25 feet

26 head

29 growth substrate

3 pixels

41 first electrical contact

42 second electrical contact

5 mask layer

61 first mirror for the first semiconductor region

62 second mirror for the second semiconductor region

71 passivation layer

72 planarization

73 Undercut

8 carriers

9 fluorescent

Claims

claims

1. Optoelectronic Multipixelchip (1) with

a plurality of individually controllable pixels (3) for generating and emitting light,

a first semiconductor region (21) extending continuously over at least some of the pixels (3),

a second semiconductor region (22), which exhibits a different conductivity type than the first semiconductor region (21) and which is structured to the pixels (2),

an active zone (23) between the first and second semiconductor regions (21, 22) for generating the light,

- A first contact (41) for electrically contacting the first semiconductor region (21), and

a second contact (42) for electrically contacting the second semiconductor region (22),

in which

- The first semiconductor region (21), the active region (23) and the second semiconductor region (22) a

Forming a semiconductor layer sequence (2) based on a III-V compound semiconductor material,

- The active zone (23) only in areas oriented in the direction parallel to an emission side (10) of the Multipixelchips (1) is arranged to generate the light, and

the first semiconductor region (21) per pixel (3) in

Cross-section is mushroom-shaped, so the first

Semiconductor region (21) starting from a continuous base layer (24) in the direction away from the emission side (10) per pixel (3) each first narrower feet (25) and subsequently wider heads (26) and the base layer (24), the feet (25) and the heads (26) each a part of the first

Semiconductor region (21) are.

2. Multipixel chip (1) according to the preceding claim, further comprising a mask layer (5) and a second mirror (62) for the second semiconductor region (22),

in which

the mask layer (5) runs parallel to the emission side (10), covers the base layer (24) and the feet (25) are grown out of openings of the mask layer (5),

- The mask layer (5) the feet (25) seen in plan view each framed, and

- The mask layer (5) is partially covered by the heads (26).

A multipixel chip (1) according to the preceding claim, wherein the mask layer (5) completely fills a region between the base layer (24) and the heads (26), the mask layer (5) interposing between at least some of the pixels (3) Recess has, through which the first contact (41) is guided in the direction of the first semiconductor region (21).

4. Multipixel chip (1) according to the preceding claim, further comprising a first mirror (61) for the first semiconductor region (21) made of at least one metal and / or at least one transparent conductive oxide,

wherein the first mirror (61) lies at least in part between the base layer (24) and the mask layer (5) and contacts the first contact (41).

A multipixel chip (1) as claimed in the preceding claim, wherein the mask layer (5) and the first mirror (61) are each grid-shaped between the base layer (24) and the heads (25).

wherein for each foot (25) of a pixel (3) each have a plurality of recesses in the mask layer (5) and in the first Mirror (61) is formed, and

wherein the first semiconductor region (21) at one of

Base region (24) facing away from the mask layer (5) per pixel (3) each grown together to the associated, coherent, gapless head (26).

6. Multipixel chip (1) according to claim 1,

further comprising an electrically insulating

Passivation layer (71) on one of the emission side (10) facing away from the first and / or the second

Semiconductor region (21, 22),

wherein the passivation layer (71) completes a portion between the base layer (24) and the heads (26)

fills in, and

wherein the passivation layer (71) has, between at least some of the pixels (3), a recess through which the first contact (41) moves in the direction of the first

Semiconductor region (21) is guided.

7. Multipixel chip (1) according to at least claim 2,

in which the second mirror (62) predominantly or completely covers side surfaces of the second semiconductor region (21) in the region of the heads (26),

wherein the second contact (42) covers at least 25% of the associated pixel (3) in plan view, and wherein the second contact (42) electrically connects the second mirror (62) and the second mirror (62)

Stromeinprägung is set up directly in the second semiconductor region (22).

8. Multipixel chip (1) according to one of the preceding

Claims,

in which the first contact (41) partially or

completely in trenches between adjacent pixels (3) is located so that the first and the second contacts (41, 42) on the same side of the base layer (24) are located.

9. Multipixel chip (1) according to the preceding claim, in which the first contact (41), starting from the trenches, is directed away from an upper side (20) of the second semiconductor region (22) facing away from the base layer (24), such that the first and the second Contact (41, 42) lie in a common plane.

The multipixel chip (1) according to any one of claims 1 to 8, wherein the first contact (41) is attached to the emission side (10) on the base layer (24) such that the first and second contacts (41, 42) abut various sides of the base layer (24) are mounted.

11. Multipixel chip (1) according to one of the preceding

Claims,

in which there is an electrically insulating planarization (72) between adjacent pixels (3) which is flush with the second one in the direction away from the base layer (24)

Semiconductor region (22) completes,

wherein the second contact (42) extends to the planarization (72).

12. Multipixel chip (1) according to one of the preceding

Claims,

in which several or all pixels (3) have a common first contact (41),

wherein each of the pixels (3) has its own second contact (42).

13. Multipixel chip (1) according to the preceding claim, wherein one of the first contacts (41), for a plurality of the pixel (3) is provided, seen in plan view

punctiform between the associated pixels (3).

14. Multipixel chip (1) according to one of claims 1 to 12, in which the first contact (41), seen in plan view, is in the form of a grid between the assigned pixels (3).

extends.

15. Multipixel chip (1) according to one of the preceding

Claims,

wherein the pixels (3) seen in plan view in a

hexagonal lattices are arranged

wherein an area ratio of the pixels (3) on a total area of the emission side (10) is between 60% and 95% inclusive.

16. Multipixel chip (1) after one of the preceding

Claims,

in which the first and the second semiconductor region (21, 22) are based on the AlInGaN material system,

wherein a width of the feet (25) is between 3 ym and 150 ym inclusive,

wherein a projection of the heads (26) over the feet (25) is hermetically around, including 0.1 ym and 1.5 ym, and

wherein a thickness of the heads (26) is hiss including 30 nm and 2 ym.

17. Multipixel chip (1) after one of the preceding

Claims,

wherein an aspect ratio of a width and a height of the pixels (3) is between 3 and 300 inclusive, wherein the first and second contacts (41, 42) are metallic contacts, respectively, and wherein the base layer (24) on the emission side (10) is provided with a roughening.

18. A method for producing a multipixel chip (1) according to any one of the preceding claims with the following steps in the order given:

A) growing the base layer (24),

B) applying and structuring the mask layer (5) directly onto the base layer (24),

C) growing the feet (25) from the openings of the mask layer (5),

D) growing the heads (26) from the feet (25) so that the heads (26) partially cover the mask (5),

E) growing the active zone (23) and the second

Semiconductor region (22), so that the second

Remain spaced semiconductor regions (22) of adjacent pixels (3), and

F) applying the first and second contacts (41, 42).