DE102018105786A1 - Multipixel chip and method of manufacturing a multi-pixel chip - Google Patents

Abstract

In one embodiment, the optoelectronic multipixel chip (1) comprises a plurality of electrically individually controllable pixels (3) for generating and emitting light. A first semiconductor region (21) extends continuously over the pixels (3). A second semiconductor region (22) is structured to the pixels (3). An active zone (23) for generating the light is located between the first and the second semiconductor region (21, 22). A first contact (41) is provided for electrical contacting of the first semiconductor region (21) and a second contact (42) for electrical contacting of the second semiconductor region (42). The active zone (23) is set up only in the direction parallel to an emission side (10) of the multipixel chip (1) for generating the light. The first semiconductor region (21) is designed mushroom-shaped per pixel (3) in cross section.

Description

A multipixel chip is specified. In addition, a method for producing a multipixel chip is specified.

An object to be solved is to specify a multipixel chip that is efficiently structured into individual pixels.

This object is achieved inter alia by a multipixel chip having the features of claim 1. Preferred developments are the subject of the other claims.

In accordance with at least one embodiment, the optoelectronic multipixel chip has a multiplicity of pixels. The pixels are electrically controllable in groups or individually. The pixels are set up to generate and emit light. In other words, the multipixel chip is in particular a pixelated LED chip.

In accordance with at least one embodiment, the multipixel chip comprises a first semiconductor region. For example, the first semiconductor region is n-type. The first semiconductor region can consist of a single semiconductor layer or can also be composed of a plurality of semiconductor layers. At least one semiconductor layer of the first semiconductor region extends continuously over some or all of the pixels.

In accordance with at least one embodiment, the multipixel chip comprises a second semiconductor region, which is p-doped, for example. The second semiconductor region thus has a different conductivity type than the first semiconductor region. Furthermore, the second semiconductor region is structured to the pixels.

In accordance with at least one embodiment, the multipixel chip comprises an active zone. The active zone is set up to generate the light. The active zone is arranged between the first and the second semiconductor region. Preferably, in all pixels in the active zone, light of the same color and / or the same spectral composition is produced, within the manufacturing tolerances.

In accordance with at least one embodiment, the first semiconductor region, the active zone and the second semiconductor region form a semiconductor layer sequence. The active zone preferably contains a pn junction, a single quantum well structure or a multiple quantum well structure for generating the radiation.

The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material such as Al _n In _{1 nm} Ga _m N or a phosphide compound semiconductor material such as Al _n In _{1 nm} Ga _m P or an arsenide compound semiconductor material such as Al _n In _{1 nm} Ga _m As or as Al _n Ga _m In _{1 nm} As _k P _1-k , where 0 ≦ n ≦ 1, 0 ≦ m ≦ 1 and n + m ≦ 1 and 0 ≦ k <1. For at least one layer or for all layers of the semiconductor layer sequence, 0 <n ≦ 0.8, 0.4 ≦ m <1 and n + m ≦ 0.95 and 0 <k ≦ 0.5 preferably apply here. In this case, the semiconductor layer sequence may have dopants and additional constituents. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, that is to say Al, As, Ga, In, N or P, are indicated, even if these may be partially replaced and / or supplemented by small amounts of further substances.

In accordance with at least one embodiment, the multipixel chip comprises a first contact and a second contact. The first and the second contact are designed for electrically contacting the first semiconductor region or the second semiconductor region. The first and the second contact are preferably metallic contacts, but may optionally also comprise transparent conductive oxides, in short TCOs. In particular, the second contact is also structured to the pixels, so that the second contact is preferably formed by a plurality of island-shaped partial areas in order to be able to control the pixels electrically independently of one another via the second contact.

In accordance with at least one embodiment, the active zone is set up only in areas oriented parallel to an emission side of the multipixel chip for generating the light. The emission side is oriented in particular perpendicular to a main growth direction of the semiconductor layer sequence. In geometric terms, the active zone has areas that are oblique to the emission side. However, these regions of the active zone are not designed to generate the light and contribute to a total luminous intensity of the multipixel chip preferably at most 5% or 1% or 0.2% and are therefore negligible in terms of light emission.

The terms "parallel" and "vertical" are understood here and below preferably with a tolerance of at most 10 ° or 5 ° or 1 °.

In accordance with at least one embodiment, the first semiconductor region per pixel is mushroom-shaped when viewed in cross-section. That is, starting from a contiguous base layer, the first semiconductor region in the direction away from the emission side per pixel has first narrower ones Feet up. Starting from the feet, a broadening follows per pixel, so that broader heads are formed opposite the feet. Both the base layer and the feet and the heads are parts of the first semiconductor region. In particular, the feet and the heads can be epitaxially grown without temporal interruption in one another.

In at least one embodiment, the optoelectronic multipixel chip comprises a multiplicity of electrically individually controllable pixels for generating and emitting light. A first semiconductor region extends with at least one semiconductor layer continuously over at least some of the pixels. A second semiconductor region, which has a different conductivity type than the first semiconductor region, is structured to form the pixels. An active zone for generating the light is located between the first and the second semiconductor region. A first contact is provided for electrical contacting of the first semiconductor region and a second contact for electrical contacting of the second semiconductor region.

The active zone is set only in the direction parallel to an emission side of the multi-pixel chip for generating the light. The first semiconductor region has a mushroom-shaped design per pixel, so that the first semiconductor region, starting from a continuous base layer in the direction away from the emission side per pixel, has at least narrower feet and subsequently wider heads.

Monolithic, ie pixelated chips designed from a coherent semiconductor are usually produced from planar epitaxy structures with comparatively great effort. Due to high demands on an accuracy of structuring processes, an achievable pixel size and thus a resolution of such chips is limited. In particular, plasma processes used to divide the semiconductor into the pixels result in side edge damage, resulting in poorer pixel performance and stability. In contrast, the multipixel chip described here and the method described here permit the production of monolithically pixelated chips with very small spacings between the pixels, without the use of plasma processes for structuring the semiconductor layer sequence.

In particular due to a mask layer already during the growth of the pixels, structuring of semiconductor materials by plasma processes can be dispensed with completely, along with the avoidance of plasma damage on side surfaces. Such plasma damage can lead to leakage current paths or be responsible for degradation mechanisms. In the multipixel chip described herein and the method described herein, the pixels are epitaxially defined. For a n-contact, in particular a dielectric layer is to be opened for this purpose. In addition, a pn junction and / or an active zone is buried in the epitaxial layer and is not exposed as in conventionally structured mesaflanks.

For the epitaxial definition of the pixels, a growth mask, for example, of silicon dioxide or silicon nitride is preferably patterned on an n-GaN layer. Openings in the mask material define the later pixels, especially the feet. By this method, very small distances between the individual pixels are possible. In the openings, the semiconductor layer sequence is grown for the pixels, ie in particular the feet and the heads.

As a result of this growth method, the preferably p-doped second semiconductor region is also grown on the side edges of the pixels, so that the entire structure has no laterally exposed pn junction. This facilitates passivation of the semiconductor material. In addition, a large reflective contact layer can be deposited on a p-doped surface without shorting the pn junction. With this method, a reflecting surface can be enlarged and also be larger than an active area of the active zone in the individual pixels. As a result, optical losses at edge regions of the pixels can be minimized.

Especially for the n-contact, only the growth mask between the pixels can be opened. The n-GaN surface can be contacted directly. Alternatively, a contact material can be applied even before the application of the growth mask in order to allow a larger connection area to the n-type GaN. For the contacting of a metal layer on the n-GaN, smaller recesses in the overlying growth mask are sufficient. Furthermore, alternatively, the n-contact can also be applied in the area between pixels from an n-side.

A contact material that is applied between the pixels, ie on the n-side and / or on the p-side, can additionally reduce or prevent optical crosstalk between the individual pixels. Thus, a contrast between the pixels can be increased.

In accordance with at least one embodiment, the multipixel chip comprises a mask layer. The mask layer is designed to be patterned into the pixels. In particular, the mask layer is made of a material on which the semiconductor material the semiconductor layer sequence does not grow or grows poorly.

In accordance with at least one embodiment, the multipixel chip comprises a second mirror. The second mirror is preferably located directly on the second semiconductor region. Above the second mirror, it is possible to impress current in the second semiconductor region. The second mirror may be a metal mirror, a TCO mirror or a combination mirror, ie a metal mirror with a TCO contact layer and optionally with a dielectric mirror.

In accordance with at least one embodiment, the mask layer extends parallel to the emission side and partially covers the base layer. The feet have grown out of openings of the mask layer. In particular, the entire base layer is seen in plan view and covered on a contact side facing the mask layer together with the feet and an electrical contact of the base layer.

In accordance with at least one embodiment, the mask layer frames the feet as seen in plan view. That is, the mask layer preferably extends in each case in a continuous path around the associated foot.

In accordance with at least one embodiment, the mask layer is partially covered by the heads. That is, the heads are grown in particular three-dimensionally starting from the feet, so that a thickness of the heads can approximately correspond to a projection of the heads on the mask layer, for example with a tolerance of at most a factor of 5 or 3 or 1.5.

In accordance with at least one embodiment, the mask layer completely fills a region between the base layer and the heads. This is especially true in the direction perpendicular to the emission side. This makes it possible that no gaps occur in the semiconductor layer sequence, in particular not in the region of the feet.

In accordance with at least one embodiment, the mask layer has a recess between at least some of the pixels. Through the recess, the first contact is guided in the direction of the first semiconductor region. In this case, the first contact can touch the first semiconductor region.

In accordance with at least one embodiment, the multipixel chip comprises a first mirror. The first mirror is preferably located directly on the first semiconductor region. In particular, the first mirror is electrically contacted directly via the first contact. Thus, the first mirror can be set up to impress current from the first contact into the first semiconductor region. Preferably, the first mirror is a metal mirror. Alternatively, as in the second mirror, a TCO mirror or in turn a combination mirror made of metal and TCO and optionally at least one dielectric or even a possibly electrically conductive Bragg mirror can be used.

In accordance with at least one embodiment, the first mirror lies partially or completely between the base layer and the mask layer. That is, the first mirror may be partially or completely buried under the mask layer. In this way, compared with the use of only the first contact, an enlarged electrical contact surface can be realized towards the first semiconductor region.

Alternatively, instead of the first mirror, in particular for an n-contact, it is also possible to use a transparent conductive oxide, TCO for short, which does not reflect or does not significantly reflect. Also, instead of the first mirror, an absorbing component may be present to increase, for example, a contrast between the pixels.

In accordance with at least one embodiment, the mask layer and the first mirror each have a grid-like design between the base layer and the heads, the mask layer preferably covering the first mirror. That is, per foot, a plurality of recesses are formed in the mask layer and in the first mirror. At a side of the mask layer facing away from the base region, the first semiconductor region is then grown together to form the coherent and per pixel-free heads. In other words, the recesses in the mask layer form individual growth islands, from which, starting from the islands, from which the corresponding foot is composed, grow together to the one-piece head.

A thickness of the feet preferably corresponds to a thickness of the mask layer or a thickness of the mask layer together with the first mirror located between the mask layer and the base layer.

In accordance with at least one embodiment, the multipixel chip comprises one or more electrically insulating passivation layers. The at least one passivation layer is located on a side of the first and / or the second semiconductor region which faces away from the emission side. It is possible that the passivation layer extends from an upper side of the second semiconductor region facing away from the emission side up to the mask layer, and the mask layer at least partially covered and touched.

According to at least one embodiment, no mask layer is present. In this case, the passivation layer preferably completely fills a region between the base layer and the heads, in particular in the direction perpendicular to the emission side. That is, when the mask layer is removed, undercuts remain below the heads and toward the base layer. These undercuts are preferably completely filled when producing the passivation layer of a material of the passivation layer. Despite the removal of the mask layer in the region of the feet, no gaps remain in the semiconductor layer sequence.

In accordance with at least one embodiment, the passivation layer has a recess between at least some of the pixels, in particular a punctiform recess. Through the recess, the first contact is guided in the direction of the first semiconductor region. Thus, an electrical contacting of the first semiconductor region can take place through the passivation layer. It is possible that the passivation layer partially covers the optionally present first mirror, such that the first mirror may be buried under the passivation layer together with the first contact.

According to at least one embodiment, the second mirror predominantly or completely covers the side surfaces of the second semiconductor region in the region of the heads. Predominantly means preferably at least 50% or 70% or 90%. This makes it possible to achieve a high reflectivity of the radiation generated in the active zone towards the emission side. Optionally, the second mirror is a combination of a metallic mirror and a dielectric mirror, particularly to minimize losses adjacent to the metal mirror.

In accordance with at least one embodiment, the second contact of the respectively associated pixel covered in plan view covers at least 25% or 50% or 70% or 90%. Thus, the second contact itself can act as a mirror and the second mirror can optionally be omitted.

In accordance with at least one embodiment, the first contact is partially or completely located in trenches between adjacent pixels. The trenches extend to the mask layer, to the passivation layer or to the base layer, so that, in particular, together with the first mirror, electrical contacting of the first semiconductor region is provided. By arranging the first contacts at least partially in the trenches, the first and second contacts may be attached to the same side of the base layer. Thus, the multipixel chip can be designed as a flip-chip.

In accordance with at least one embodiment, the first contact extends from the trenches to an upper side of the second semiconductor region facing away from the base layer. Thus, the first and the second contact can lie in a common plane. Thus, for electrical contacting of the first and the second contact preferably no height difference between the first and the second contact to bridge.

In accordance with at least one embodiment, the first contact is attached to the emission layer on the base layer. By this arrangement, recesses or openings through the mask layer and / or the passivation layer can be avoided. Thus, the first and second contacts may be attached to different sides of the base layer.

According to at least one embodiment, a preferably electrically insulating planarization is located between adjacent pixels. It is possible that the planarization in the direction away from the base layer is flush with the second semiconductor region.

In accordance with at least one embodiment, the second contact extends to the planarization. In other words, the planarization is partially covered by the second contact and optionally by the second mirror.

In accordance with at least one embodiment, a via is formed by the planarization. Via the at least one via, it is possible to guide the first contact from an upper side of the planarization facing away from the base layer to the first mirror or to the first semiconductor region.

In accordance with at least one embodiment, several or all of the pixels have a common first contact. For example, the first contact is a common voltage potential, such as a ground contact. At the same time, each pixel or small groups of pixels preferably has its own second contact, so that, in spite of the common first contact, the pixels or the groups are individually electrically controllable.

In accordance with at least one embodiment, the first contact, which is provided for a plurality of the pixels, is located between the associated pixels when viewed in plan view. The first one can do this Contact punctiform or shaped like a grid. For example, dot-shaped means that the associated recess in the mask layer and / or the passivation layer for the first contact has an area of at most 20% or 5% or 2% of an area of the at least one associated pixel. This is especially true in plan view.

In accordance with at least one embodiment, the pixels are arranged in a quadratic, rectangular or hexagonal grid as seen in plan view. This makes it possible to achieve that several pixels, in particular with downstream phosphors for different colors, can be efficiently interconnected to form one pixel.

According to at least one embodiment, an area ratio of the pixels on a total area of the emission side is at least 60% or 70% or 80%. Alternatively or additionally, this area proportion is at most 95% or 90% or 80%. This high area ratio can be achieved in particular by a hexagonal arrangement of the pixels.

In accordance with at least one embodiment, the semiconductor layer sequence is based on the AlInGaN material system. In this case, the active zone is preferably configured to produce near ultraviolet radiation or blue light or, less preferably, green light. A wavelength of maximum intensity of the light generated in the active zone is preferably at least 405 nm or 430 nm and / or at most 550 nm or 520 nm or 480 nm or 470 nm. If the semiconductor layer sequence is based on a different material system, then in the active Zone alternatively green, orange or red light or infrared radiation can be generated.

In accordance with at least one embodiment, the feet have a width of at least 2 μm or 4 μm or 10 μm. Alternatively or additionally, this width is at most 150 μm or 100 μm or 50 μm or 20 μm. In this case, a lateral projection of the heads over the feet is preferably around at least 0.1 μm or 0.2 μm or 0.4 μm and / or at most 1.5 μm or 1 μm or 0.6 μm. A thickness of the heads is preferably at least 30 nm or 50 nm or 100 nm and / or at most 2 μm or 1 μm or 0.6 μm.

In accordance with at least one embodiment, the pixels have an aspect ratio of a width and a height of at least 1 or 3 or 5 or 8. Alternatively or additionally, the aspect ratio is at most 300 or 100 or 50 or 20.

In accordance with at least one embodiment, the base layer is provided with a roughening on the emission side. The roughening is preferably limited to the base layer, so that the feet are not affected by the roughening.

In accordance with at least one embodiment, the multipixel chip is arranged on a carrier. The carrier can be a silicon carrier, which has, for example on the basis of CMOS, a plurality of drive devices, in particular for the second contact and thus for the individual pixels. Likewise, the carrier can also be designed without control electronics, for example as a mechanically stable silicon carrier with TSV vias of the individual pixels. TSV stands for through silicon via.

In accordance with at least one embodiment, the multipixel chip comprises one or more phosphors. About the at least one phosphor, it is possible that the individual pixels are interconnected to different colors emitting pixels, in particular to RGB pixels. In this case, a phosphor for generating white light is preferably arranged downstream of all pixels or there is a structured application of several different phosphors depending on a full conversion for green and red, possibly for white, with blue light directly and a phosphor can be generated. This can be used to set up a RBG light source.

In addition, a method for producing a multipixel chip is specified. The multi-pixel chip is configured as indicated in connection with one or more of the above embodiments. Features of the method are therefore also disclosed for the multipixel chip and vice versa.

1. A) Wachsen der Basisschicht,
2. B) Aufbringen und Strukturieren der Maskenschicht direkt auf die Basisschicht,
3. C) Wachsen der Füße aus den Öffnungen der Maskenschicht,
4. D) Wachsen der Köpfe ausgehend von den Füßen, sodass die Köpfe die Maske zum Teil bedecken,
5. E) Wachsen der aktiven Zone und des zweiten Halbleiterbereichs, sodass die zweiten Halbleiterbereiche benachbarter Pixel beabstandet bleiben, und
6. F) Aufbringen des ersten und des zweiten Kontakts sowie optional zuvor der Passivierungsschicht.

In at least one embodiment, the method comprises the following steps, preferably in the order given:

1. A) growing the base layer,
2. B) applying and structuring the mask layer directly onto the base layer,
3. C) growing the feet from the openings of the mask layer,
4. D) growing the heads starting from the feet, so that the heads partly cover the mask,
5. E) growing the active region and the second semiconductor region such that the second semiconductor regions of adjacent pixels remain spaced, and
6. F) Applying the first and the second contact and optionally before the passivation layer.

In the following, a multipixel chip described here and a method described here will be explained in more detail with reference to the drawing with reference to exemplary embodiments. The same reference numerals indicate the same elements in the individual figures. However, there are no scale relationships shown, but individual elements can be shown exaggerated for better understanding.

• 1 eine schematische Schnittdarstellung eines Ausführungsbeispiels eines hier beschriebenen Multipixelchips,
• 2A bis 2F schematische Schnittdarstellungen von Verfahrensschritten zur Herstellung eines hier beschriebenen Multipixelchips,
• 3 bis 8 schematische Schnittdarstellungen von Ausführungsbeispielen von hier beschriebenen Multipixelchips, und
• 9A, 9B, 10A, 10B und 10C schematische Draufsichten auf Ausführungsbeispiele von hier beschriebenen Multipixelchips.

Show it:

• 1 FIG. 2 a schematic sectional illustration of an exemplary embodiment of a multipixel chip described here, FIG.
• 2A to 2F schematic sectional views of method steps for the production of a multipixel chip described here,
• 3 to 8th schematic sectional views of embodiments of multipixel chips described herein, and
• 9A . 9B . 10A . 10B and 10C schematic plan views of embodiments of multipixel chips described here.

In 1 is an embodiment of an optoelectronic multipixel chip 1 shown. The multipixel chip 1 comprises a semiconductor layer sequence 2 , The semiconductor layer sequence 2 has a first semiconductor region 21 on, which is preferably n-type. The first semiconductor area 21 consists of a continuous base layer 24 and one pixel each 3 associated feet 25 and minds 26 , Between the first semiconductor region 21 and a second semiconductor region 22 there is an active zone 23 for light generation. The second semiconductor area 22 is preferably doped p-type.

The active zone 23 extends mainly parallel to an emission side 10 of the multipixel chip 1 , This can be the issue side 10 be provided with a roughening. However, only areas of the active zone 23 set up for light generation, which is parallel to the emission side 10 are oriented. Areas of the active zone 23 , which are located on side surfaces of the heads 26 of the first semiconductor region 21 are not intended to produce light.

In particular, growth of the semiconductor layer sequence is 2 on a growth perpendicular to the emission side 10 optimized. Therefore, quantum well structures are on the side surfaces of the heads 26 lower thicknesses and thus higher energy levels, so that the quantum wells on the side surfaces effectively act as barrier layers. With regard to light generation, the active zones 23 thus effectively two-dimensional and flat, whereas geometrically the active zone 23 per pixel 3 is designed bowl-shaped.

Between adjacent pixels 3 There are areas of a mask layer at the bottom sides of trenches 5 , Seen in plan view is the mask layer 5 preferably contiguous and surrounds the respective pixels 3 all around. In particular, the grid-shaped mask layer closes 5 in the direction parallel to the emission side 10 each directly to the feet 25 at.

At the emission side 10 facing away from the tops 20 of the island-structured second semiconductor region 22 there is preferably a second mirror each 62 , The second mirror 62 is according to 1 on top 20 limits and covers the top 20 almost complete.

On side surfaces of the second semiconductor region 22 as well as on the mask layer 5 and on the second mirror 62 is a preferably continuous passivation layer 71 applied, for example, from an oxide such as silicon dioxide, Al ₂ O ₃ , TaO, HfO, NbO or from a nitride such as silicon nitride or from an oxynitride such as SiO _x N _y . The passivation layer 71 has openings. About these openings is in the trenches between the pixels 3 a first electrical contact 41 attached to the base layer 24 electrically contacted. To electrically connect the second mirror 62 serves a second electrical contact 42 , At the contacts 41 . 42 they are preferably metallic contacts.

The multipixel chip 1 according to 1 can be produced without an etching process of the semiconductor layer sequence 2 is required. A corresponding manufacturing method is in connection with 2 explained.

According to 2A gets onto a growth substrate 29 For example, a sapphire substrate, the base layer 24 grown epitaxially. The base layer 24 is, for example, n-doped GaN. A thickness of the base layer 24 is for example at least 1 micron and / or at most 7 microns.

According to 2 B gets on the base layer 24 the mask layer 5 applied. A material for the mask layer 5 can already be structured and thus applied only locally or the material for the mask layer is applied continuously and structured only below. For example, the mask layer 5 made of silicon dioxide. A thickness of the mask layer 5 is preferably at least 10 nm or 50 nm and / or at most 1 micron.

In the process step of 2C is illustrated that starting from the openings in the mask layer 5 the feet 25 and the heads 26 for the pixels 3 to be grown. When growing the heads 26 becomes the mask layer 5 partially overmoulded. However, a space between adjacent pixels remains above the mask layer 5 free. The semiconductor material for the first semiconductor region 21 grows on the mask layer 5 not or not significantly.

According to 2D be on your heads 26 the active zone 23 and the second semiconductor region 22 deposited. Again, the mask layer remains 5 in places free. The active zone 23 and the second semiconductor region 22 can go up to the mask layer 5 pass.

In 2E is shown that the second mirror 62 is applied. Furthermore, the entire surface of the passivation layer 71 deposited. This covers the passivation layer 71 the mask layer 5 partially directly. A thickness of the passivation layer 71 is preferably at least 50 nm and / or at most 400 nm.

In the process step of 2F become the openings in the passivation layer 71 generated. Then the contacts 41 . 42 deposited. The contacts can 41 . 42 applied in the same process step, are produced from the same material and with the same photomask, not drawn. Alternatively, the contacts 41 . 42 individually processed.

Optionally, finally, the growth substrate 29 removed and the roughening generated to the embodiment of the 1 to get.

To an electrical contact surface to the first semiconductor region 21 to enlarge is located below the mask layer 5 according to 3 a first mirror 61 , The first mirror 61 is in front of the mask layer 5 generated.

According to 1 assign the contacts 41 . 42 towards the emissions side 10 a height difference which is, for example, about 0.5 μm. In order to avoid such a height difference, it is possible, as in 3 shown that the first contact 41 from the opening in the mask layer in the trench coming to the top 20 to be led. This is in 3 illustrated as a dashed line.

The first mirror 61 is preferably made of a temperature-resistant metal, which the following comparatively high temperatures during the growth of the active zone 23 and the second semiconductor region 22 survives. In particular, the first mirror 61 made of palladium, platinum, titanium and / or chromium. Due to the increased temperatures during growth of the following semiconductor materials 22 . 23 may be an alloying of the material of the first mirror 61 into the base layer 24 respectively. As a result, an improved electrical contact can be achieved.

Alternatively, for or instead of the first mirror 61 Also, a transparent conductive oxide, TCO short, can be used, in particular to achieve larger electrical contact surfaces. In this case, the component is the one above each with the first mirror 61 is designated, non-metallic and not formed mirror-like.

Otherwise apply to 3 the remarks to the 1 and 2 ,

In 4 is illustrated that the mask layer 4 within the pixels 3 mesh-like structured. It is located between the mask layer 5 and the base layer 24 the first mirror is preferred 61 , The mask layer 5 and the first mirror 61 are in the feet with it 25 arranged congruently, wherein the mask layer 5 preferably side surfaces of the first mirror 61 covered.

In order to ensure a higher efficiency, in particular with regard to a light extraction, it is possible, instead of the metallic first mirror 61 to use a transparent conductive material, in particular a TCO such as ITO. Above the mask layer 5 becomes per pixel 3 a coherent head 26 grown.

A distance between adjacent areas of the mask layer 5 within a pixel 3 is preferably at least three times a width of the individual regions of the mask layer 5 to a high-quality convergence of the heads 26 during epitaxy. A width of lands with the mask layer 5 within the pixels 3 is preferably at most 3 microns. A total coverage of the pixels 3 in the area of the feet 25 with a material of the mask layer 5 is preferably at most 20%, in particular at most 10%.

A lateral extent of the first contact 41 within the trench is preferably at least 0.4 microns and / or at most 2 microns. A distance between the second semiconductor regions 22 neighboring pixels 3 is preferably at least 0.3 .mu.m or 0.5 .mu.m and / or at most 2 .mu.m or 1.5 .mu.m. This is a width of the mask layer 5 between neighboring pixels 3 preferably at least 1 μm or 1.5 μm and / or at most 10 μm or 5 μm. These small distances allow dense arrangements of the pixels 3 achieve.

The values mentioned and the mask layer versions 5 as well as the first mirror 61 may be present in the same way in all other embodiments.

In 5 It is illustrated that the mask layer after growing the heads 26 is removed, for example by wet chemical etching. This formed undercuts 73 are preferably completely through the material of the passivation layer 71 filled. This is after the generation of the passivation layer 71 prefers no gaps in the area of the feet 25 in front.

It is also in 5 illustrates that the first mirror 61 congruent with the first contact 41 can be deposited. The two mirrors can do this 61 . 62 simultaneously and from the same materials and with the same photomask, not drawn, are made. Thus, it is possible that the passivation layer 71 also to a small part on the first mirror 61 extends.

Both mirrors are preferred 61 . 62 applied in the same process step, then the passivation layer 71 applied and structured. Subsequently, both contacts can again 41 . 42 be applied in the same process step. In 5 is illustrated that the passivation layer 71 ever on the mirrors 61 . 62 extends and the passivation layer 71 then in places of the respective contact 41 . 42 is covered. Optionally, openings of the passivation layer 71 and the contacts 41 . 42 but also be congruent.

Otherwise, the statements apply in particular to 1 in the same way too 5 ,

In the embodiment of 6 is illustrated that the second mirror 62 also the side surfaces of the second semiconductor region 22 completely covered. This is enough for the second mirror 62 to the mask layer 5 approach. This is possible in all other embodiments. Incidentally, the embodiment of the 6 With 1 match.

In 7 is shown that the trenches between adjacent pixels 3 with a planarization 72 are filled. The planarization is for example of a spin on glass or of a thick coating with a subsequent planarization step, for example a chemical mechanical polishing. The planarization 72 is for example made of a transparent material such as silicon dioxide or also of an absorbing material such as silicon nitride. Likewise, reflective materials such as metals or combinations thereof can be used. Optionally, additionally the passivation layer may be present, in 7 not drawn.

Analogous to 5 It is possible that the mask layer before generating the planarization 72 Will get removed. Shown as a dashed line, it is possible that the mask layer 5 is still present to the same extent as the growth of the heads 25 and the feet 26 ,

The second mirror 62 and the second contact 42 extend in part to the planarization 72 , The first contact 41 is located on the emission side 10 ,

As in all other embodiments, in particular the first contact 41 be designed to be light-absorbing for increased contrast or even reflective or transparent, such as a TCO, to achieve increased brightness.

In 8th is shown that the planarization 72 is penetrated by a via, so that the first contact 41 may be attached to the same side as the second contact 42 , This can be the first contact 41 partly in the planarization 72 be buried.

As in all other embodiments, it is always possible that the semiconductor layer sequence 2 with the contacts 41 . 42 on a carrier 8th is appropriate. At the carrier 8th it is, for example, an electronics carrier, via the targeted control of individual pixels 3 is possible.

Furthermore, as in all embodiments, at least one phosphor 9 to be available. About the phosphor 9 can be, for example, blue light from the active zone 23 each generate green and / or red light, so that a total of RGB pixels are formed, for example, three or four of the pixels 3 to which the semiconductor layer sequence 2 is structured, composed.

According to the plan views in 9 are the individual pixels 3 each arranged in a square grid and seen in plan view approximately square shaped.

In 9A you can see that several of the pixels 3 through a point-shaped first contact 41 are electrically connected. The first contact 41 lies in the ditch between the neighboring pixels 3 or also on the emission side 10 , For each of the pixels 3 is a separate second contact 42 intended.

In contrast, see 9B , the first contact extends 41 frame around the pixels 3 around. The pixels 3 are thus through islands in the first contact 41 educated. Is the first contact? 41 on the emission side 10 , so may by an opaque first contact 41 an increased contrast ratio can be achieved.

In the embodiments of the 10 are the pixels 3 each seen in plan view designed hexagonal. Since the AlInGaN material system typically grows with a hexagonal geometry, such pixels can be used 3 produce efficiently.

The 10A and 10B according to the 9A and 9B , Furthermore, the 10A to infer that the first contact 41 does not need to be square shaped, but may also be diamond-shaped. Likewise, the first contact 41 , unlike drawn, also be round or hexagonal shaped, each seen in plan view.

In 10C you can see that the pixels 3 arranged in a hexagonal pattern. This allows a high fill factor of the pixels 3 on a total area of the multipixel chip 1 achieve.

Unless otherwise indicated, the components shown in the figures preferably each directly follow one another in the order indicated. Layers not in contact with the figures are preferably spaced apart from one another. As far as lines are drawn parallel to each other, the corresponding surfaces are preferably also aligned parallel to each other. Also, unless otherwise indicated, the relative positions of the drawn components relative to one another are correctly represented in the figures.

The invention described here is not limited by the description based on the embodiments. Rather, the invention encompasses any novel feature as well as any combination of features, which in particular includes any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

1

optoelectronic multipixel chip

10

emission side

2

Semiconductor layer sequence

20

top

21

(n-type) first semiconductor region

22

(p-type) second semiconductor region

23

active zone

24

base layer

25

foot

26

head

29

growth substrate

3

pixel

41

first electrical contact

42

second electrical contact

5

mask layer

61

first mirror for the first semiconductor region

62

second mirror for the second semiconductor region

71

passivation

72

planarization

73

undercut

8th

carrier

9

fluorescent

Claims (18)

Optoelectronic multipixel chip (1) with a plurality of individually controllable pixels (3) for generating and emitting light, a first semiconductor region (21) extending continuously over at least some of the pixels (3), a second semiconductor region (22), which exhibits a different conductivity type than the first semiconductor region (21) and which is structured to the pixels (2), an active zone (23) between the first and second semiconductor regions (21, 22) for generating the light, - A first contact (41) for electrically contacting the first semiconductor region (21), and - A second contact (42) for electrically contacting the second semiconductor region (22), wherein - The active zone (23) is arranged only in the direction parallel to an emission side (10) of the multi-pixel chip (1) for generating the light, and - The first semiconductor region (21) per pixel (3) is mushroom-shaped in cross section, so that the first semiconductor region (21) starting from a continuous base layer (24) in the direction away from the emission side (10) per pixel (3) the first narrower feet (25) and subsequently having wider heads (26). The multipixel chip (1) according to the preceding claim, further comprising a mask layer (5) and a second mirror (62) for the second semiconductor region (22), wherein - the mask layer (5) is parallel to the emission side (10), the base layer (24 ) covered and the Feet (25) have grown out of openings of the mask layer (5), - the mask layer (5) frames the feet (25) as seen in plan view, and - the mask layer (5) is partially covered by the heads (26). A multipixel chip (1) according to the preceding claim, wherein the mask layer (5) completely fills a region between the base layer (24) and the heads (26), the mask layer (5) having a recess between at least some of the pixels (3) through which the first contact (41) is guided in the direction of the first semiconductor region (21). A multipixel chip (1) according to the preceding claim, further comprising a first mirror (61) for the first semiconductor region (21) of at least one metal and / or at least one transparent conductive oxide, the first mirror (61) at least partially between the base layer (24) and the mask layer (5) and contacts the first contact (41). Multipixel chip (1) according to the preceding claim, in which the mask layer (5) and the first mirror (61) between the base layer (24) and the heads (25) are each in the form of a grid network, wherein a plurality of recesses are formed in the mask layer (5) and in the first mirror (61) per foot (25) of a pixel (3), and wherein the first semiconductor region (21) on a side facing away from the base region (24) side of the mask layer (5) per pixel (3) each grown together to the associated, coherent, gapless head (26). Multipixel chip (1) after Claim 1 , further comprising an electrically insulating passivation layer (71) on a side of the first and / or the second semiconductor region (21, 22) facing away from the emission side (10), wherein the passivation layer (71) forms a region between the base layer (24) and the heads (26) completely fills, and wherein the passivation layer (71) between at least some of the pixels (3) has a recess through which the first contact (41) is guided in the direction of the first semiconductor region (21). Multipixel chip (1) after at least Claim 2 in which the second mirror (62) predominantly or completely covers side surfaces of the second semiconductor region (21) in the region of the heads (26), the second contact (42) covering at least 25% of the associated pixel (3) in plan view and wherein the second contact (42) electrically connects the second mirror (62) and the second mirror (62) is adapted for current injection directly into the second semiconductor region (22). A multipixel chip (1) according to any one of the preceding claims, wherein the first contact (41) is partially or fully located in trenches between adjacent pixels (3) such that the first and second contacts (41, 42) are on the same side of the base layer (24). Multipixel chip (1) according to the preceding claim, in which the first contact (41) is led away from the trenches to an upper layer (24) facing away from the top (20) of the second semiconductor region (22), so that the first and the second contact ( 41, 42) lie in a common plane. Multipixel chip (1) after one of the Claims 1 to 8th in that the first contact (41) is attached to the emission layer (10) on the base layer (24) so that the first and second contacts (41, 42) are attached to different sides of the base layer (24). Multipixel chip (1) according to one of the preceding claims, in which there is an electrically insulating planarization (72) between adjacent pixels (3), which terminates flush with the second semiconductor region (22) in the direction away from the base layer (24), wherein the second contact (42) extends to the planarization (72). Multipixel chip (1) according to one of the preceding claims, in which several or all pixels (3) have a common first contact (41), wherein each of the pixels (3) has its own second contact (42). A multipixel chip (1) according to the preceding claim, wherein one of the first contacts (41) provided for a plurality of the pixels (3) is punctiform between the associated pixels (3) when viewed in plan. Multipixel chip (1) after one of the Claims 1 to 12 in which the first contact (41) extends in a grid-like manner between the assigned pixels (3) when viewed in plan view. Multipixel chip (1) according to one of the preceding claims, in which the pixels (3) are arranged in a hexagonal lattice when viewed in plan view, with an area fraction of the pixels (3) on a total area of the emission side (10) between 60% and 95% inclusive. lies. Multipixel chip (1) according to one of the preceding claims, in which the first and the second semiconductor region (21, 22) are based on the AlInGaN material system, wherein a width of the feet (25) is between 3 μm and 150 μm inclusive, wherein a supernatant of the heads (26) over the feet (25) around hisses including 0.1 microns and 1.5 microns, and wherein a thickness of the heads (26) is hiss including 30 nm and 2 μm. Multipixel chip (1) according to one of the preceding claims, wherein an aspect ratio of a width and a height of the pixels (3) is between 3 and 300 inclusive, wherein the first and second contacts (41, 42) are metallic contacts, respectively, and wherein the base layer (24) on the emission side (10) is provided with a roughening. Method for producing a multipixel chip (1) according to one of the preceding claims, comprising the following steps in the order indicated: A) growing the base layer (24), B) applying and structuring the mask layer (5) directly onto the base layer (24), C) growing the feet (25) from the openings of the mask layer (5), D) growing the heads (26) from the feet (25) so that the heads (26) partially cover the mask (5), E) growing the active region (23) and the second semiconductor region (22) such that the second semiconductor regions (22) of adjacent pixels (3) remain spaced, and F) applying the first and second contacts (41, 42).

Images