WO2019174554A1 - 一种补偿时延的方法和设备 - Google Patents

一种补偿时延的方法和设备 Download PDF

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Publication number
WO2019174554A1
WO2019174554A1 PCT/CN2019/077715 CN2019077715W WO2019174554A1 WO 2019174554 A1 WO2019174554 A1 WO 2019174554A1 CN 2019077715 W CN2019077715 W CN 2019077715W WO 2019174554 A1 WO2019174554 A1 WO 2019174554A1
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WIPO (PCT)
Prior art keywords
delay value
data stream
physical port
port
delay
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PCT/CN2019/077715
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English (en)
French (fr)
Inventor
祁云磊
李春荣
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22154687.2A priority Critical patent/EP4060913A1/en
Priority to EP19767738.8A priority patent/EP3758272B1/en
Publication of WO2019174554A1 publication Critical patent/WO2019174554A1/zh
Priority to US17/018,538 priority patent/US11641266B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0676—Mutual
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
    • H04J2203/0082—Interaction of SDH with non-ATM protocols
    • H04J2203/0085—Support of Ethernet

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for compensating for delay.
  • IP Internet Protocol
  • FlexE Flexible Ethernet
  • MAC Media Access Control
  • FlexE crossover is an emerging Ethernet switching technology. It is used in 5G mobile service bearers and power relay service bearers due to its ultra-low latency and ultra-low jitter forwarding characteristics. These services often have stringent requirements for the transmission of delay information. Therefore, controlling the delay of devices in the bearer network is an important issue to achieve time synchronization.
  • the traditional mobile bearer network solves the time synchronization method by connecting a time server to each base station to implement time synchronization.
  • the solution needs to deploy a large number of time servers and GPS, which is costly and difficult to deploy;
  • the solution is to deploy one or several time servers in the bearer network, and the time server transmits the time information to the base station through the bearer network.
  • the solution needs to support the accurate clock synchronization protocol for each device in the bearer network. :Precision Time Protocol (PTP) packet processing capability, as well as complex protocol state machine operations, which make configuration, management, and maintenance more complicated.
  • PTP Precision Time Protocol
  • the embodiment of the present invention provides a method and a device for compensating a delay, and the device delays the delay of the bidirectional data stream to implement the device to control the data flow delay.
  • the present application provides a method for compensating for a delay, the method comprising: determining, by a device, a first delay value of a first data flow from a first physical port of the device to a second physical port of the device, where The first physical port is an ingress port of the first data stream, and the second physical port is an egress port of the first data stream.
  • the device determines a second delay value of the second data flow from the second physical port to the first physical port, where the second physical port is an ingress port of the second data stream, and the first physical port is an egress port of the second data stream .
  • the device determines the first target delay value based on the first delay value and the second delay value, under the condition that the first delay value is less than the second delay value.
  • the device adjusts the delay value of the first data stream to the first target delay value.
  • the device determines the first target delay value by using the first delay value of the first data stream and the second delay value of the second data stream, and adjusts the delay value of the first data stream to A target delay value is equal, and the device adjusts the delay value of the first data stream in the bidirectional data stream.
  • the first target delay value and the second delay value are equal.
  • the device determines that the first target delay value and the second delay value are equal, so that the delay value of the first data stream is adjusted to be equal to the second delay value of the second data stream, so that the device can be implemented.
  • the symmetry compensation of the bidirectional data stream is such that the delay value of the first physical port to the second physical port of the slave device of the first data stream and the second data port of the second data port of the first data stream from the second physical port of the device to the first physical port.
  • the time delay is equal, and the time synchronization packet can be transparently transmitted.
  • the device that transmits the time synchronization packet needs to have the capability of processing the 1588 protocol.
  • the method further includes: the device adjusting the delay value of the second data stream to the first Target delay value.
  • the device when the first target delay value is greater than the second delay value, the device adjusts the delay value of the second data stream to the first target delay value, so that the delay value of the first data stream is obtained.
  • the time delay value of the second data stream is equal to that of the second data stream, that is, the device adjusts the delay value of the first data stream and the delay value of the second data stream to the first target delay value, so that the first data stream is first by the device.
  • the delay value of the physical port to the second physical port is equal to the delay value of the second data port from the second physical port to the first physical port, that is, the delay of the bidirectional data stream of the device is equal by the device compensating the delay. .
  • the method further includes: determining, by the device, the second target delay value based on the first delay value and the second delay value. The device adjusts the delay value of the second data stream to a second target delay value.
  • the device determines the second target delay value according to the first delay value and the second delay value, and adjusts the delay value of the second data stream to the second target delay value, so that the device can implement the second The delay of the data stream is adjusted.
  • the determining, by the second physical port, the first delay value and the determining, by the first physical port, the second delay value, the second physical port adds the first delay value to In the second data stream.
  • the first physical port receives the first delay value carried in the second data stream.
  • the device determines a first target delay value based on the first delay value received by the first physical port and the second delay value determined by the first physical port.
  • the second physical port adds the first delay value to the second data stream, and the first physical port determines the first target delay value according to the received first delay value and the determined second delay value.
  • the implementation device determines the first target delay value according to the first delay value of the first data stream.
  • the present application provides an apparatus for performing the method of any of the first aspect or the first aspect of the first aspect.
  • the device comprises means for performing the method of the first aspect or any of the possible embodiments of the first aspect.
  • the application provides an apparatus comprising: a network interface, a processor, and a memory.
  • the network interface, the processor and the memory can be connected by a bus system.
  • the memory is for storing a program, an instruction or a code
  • the processor is configured to execute a program, an instruction or a code in the memory, to perform information performed by the device in a method in any of the first aspect or any possible design of the first aspect Operations other than sending and receiving.
  • the present application provides a computer readable storage medium having instructions stored therein that, when run on a computer, cause the computer to perform any of the first aspect and the first aspect The instructions of the method in the implementation.
  • FIG. 1 is a schematic diagram of an application scenario of a method for compensating a delay according to an embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a method for compensating a delay according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a device according to an embodiment of the present invention.
  • FIG. 1 provides a schematic diagram of a system architecture for compensating for a delay.
  • the system may be a conventional mobile bearer network, and the devices 101 to 104 in the network system may be devices supporting the FlexE technology.
  • the related method for solving the time synchronization may be to deploy one or several time servers in the bearer network, and the time server sends the time information to the base station through the bearer network.
  • the time synchronization method is specifically such that the time server 105 in FIG. 1 obtains delay information from a GPS satellite or a Precision Time Protocol (PTP) or the like and issues time information to the device 104.
  • PTP Precision Time Protocol
  • the clock synchronization is then performed in accordance with the relationship from the master device to the slave device, for example, the master device 104 issues time information to the slave device 103, and the device 103 acts as the master device to issue time information to the slave device 102.
  • the delay is uncertain and the two-way delay is not equal. Therefore, the devices 101 to 104 in the bearer network are required.
  • To run 1588 sync messages hop by hop. As shown in the process of synchronizing the 1588 synchronization packets, each device in the bearer network needs to support the sending and receiving of 1588 synchronous packets and complex protocol state machine operations, that is, configuration, management, and maintenance. quite complicated.
  • the device transparently transmits the time synchronization packet and reduces the complexity of the device processing the 1588 synchronization packet. Therefore, it is necessary to solve the problem of how the device controls the delay of the bidirectional data stream.
  • the compensation is performed to maintain a stable relationship between the delay values of the bidirectional data streams of the device.
  • the device can compensate the bidirectional data stream by using the compensation of the bidirectional data stream, and the delay of the bidirectional data stream can be compensated by the device.
  • the delay of the bidirectional data stream is kept stable, so that the transparent transmission of the time synchronization message is realized, and the device does not need to implement the delay of the measurement device processing the data stream through the 1588.
  • FIG. 2 a flow chart of a method for compensating a delay is provided in the present application.
  • the device described in FIG. 2 may be any one of the devices 101 to 104 in FIG. 1, and the method includes the following.
  • the device determines a first delay value of the first data flow from the first physical port of the device to the second physical port of the device.
  • the first data stream may be an Ethernet physical layer data stream, for example, a 1588 time synchronization message or a Network Time Protocol (NTP) message, or may be time division multiplexing ( Time Division Multiplexing (TDM) data flow, etc.
  • NTP Network Time Protocol
  • TDM Time Division Multiplexing
  • the present application does not specifically limit the type of the first data stream.
  • the description of the present application partially indicates the delay of the first data stream from the first physical port to the second physical port of the device, and the reverse data delay indicates the second data stream from the second physical port to the second physical port. The delay of the direction of the first physical port.
  • the first data stream is sent from the first physical port of the device to the second physical port, and the device may mark the first data packet with the first time stamp by using the first physical port,
  • the second physical port marks the second timestamp, wherein the mark timestamp can be in the form that the first physical port adds the first timestamp to the data block, or the first data flow arrives at the first physical port,
  • a physical port marks the first timestamp and reports the first timestamp to the processor of the device.
  • the device can also mark the timestamp by other known methods. The method does not impose any limitation on the manner of marking the timestamp.
  • the manner in which the second physical port marks the second timestamp may refer to the manner of marking the first timestamp described above.
  • the delay value of the first data stream from the first physical port of the device to the second physical port of the device is the value D1 obtained by subtracting the value of the first timestamp from the value of the second timestamp.
  • the device may, but is not limited to, determine the first timestamp by using the following types.
  • the device may be the device 102 or 103 in the bearer network of FIG. 1.
  • the ingress port and the egress port of the first data stream are both FlexE ports, that is, the first physical port and the second physical port are both FlexE ports.
  • the FlexE port can be divided into a single physical layer (physical layer, PHY for short) scenario and a multi-PHY scenario according to different application scenarios.
  • a multi-PHY scenario can be understood as a combination of multiple sets of single PHYs.
  • the method for determining the forward delay of the device by using the first physical port and the second physical port of the device as a single PHY is described in detail below.
  • the first physical port is configured to receive the first data stream and send the second data stream, and convert the received first data stream into an internal parallel signal or convert the sent second data stream from an internal parallel signal to an external medium
  • the first physical port of the device receives the first data stream and converts the first data stream into the first data block.
  • the physical medium attachment (English: Physical Medium Attachment Sublayer: PMA) of the first physical port may record the first timestamp t1 with the first bit of the first data block, and each set of data blocks is recorded.
  • the first data block carrying the tag t1 is processed into a 64/66-bit data block after being processed by the PMA and the Physical Coding Sublayer (PCS).
  • PCS Physical Coding Sublayer
  • the device can mark T1 at the entry time stamp of the 64/66-bit data block, wherein the time stamp T1 is the transit time.
  • the stamp t1 and the first data block first bit are converted from the 64/66-bit data block first bit position offset.
  • the 64/66-bit data block and the timestamp T1 are sent by the first physical port to the second physical port, that is, sent by the ingress port of the device to the egress port of the device, and the 64/66-bit data block carrying the timestamp tag T1 is Before being sent to the second physical port, it can also be processed by other modules of the device, which is not limited.
  • the second physical port of the device receives the 64/66-bit data block and the timestamp T1, identifies and extracts the timestamp T1, and obtains the value of T1.
  • the 64/66-bit data block is processed by the second physical port and sent to the PMA of the second physical port, and the PMA of the second physical port records the exit of the first data stream through the second physical port PMA with the first bit of the data block.
  • Timestamp T2 and convert the data block into a first data stream.
  • the calculation method of the forward delay value may be the difference between the above T2 and T1, or may be the difference between the above T2 and t1.
  • the first data stream can be sampled, and only the time stamp is marked in the sampled data block.
  • the device is an access device in the bearer network
  • the ingress port of the device is a common Ethernet (English: Ethernet, referred to as ETH) port
  • the egress port is For the FlexE port
  • the first physical port of the device is a normal Ethernet port
  • the second physical port is a FlexE port.
  • the measurement and calculation method of the device's forward delay refer to the ingress port and the egress port of the device. Both are measurement and calculation methods of the FlexE port, and the first data stream may be marked with a first timestamp by the first physical port, and the second physical port marks the second timestamp of the first data stream reaching the egress port.
  • the device can obtain the forward delay value by calculating the difference between the second timestamp and the first timestamp.
  • the specific method can be referred to as a method, and details are not described herein again.
  • the device may also be an access device of a common public radio interface (CPRI) service
  • CPRI common public radio interface
  • the CRPI is a remote radio unit in the mobile forwarding network (English: remote radio unit, referred to as: RRU) and the baseband unit (English: baseband unit, BBU for short), the device has extremely strict requirements on the difference between transmission delay and two-way delay.
  • RRU remote radio unit
  • BBU baseband unit
  • For the measurement method refer to the measurement of the ingress and egress of the device. The method of delay is not repeated here.
  • Mode 4 When the device is a fixed bit rate (CBR) service access device, the ingress port of the device is a CBR service port, which may be referred to as a first physical port, and the egress port is The FlexE port can be called the second physical port.
  • the service access part of the service access device is a CBR service port, and the service processing part of the CBR service port has no PMA.
  • the frame (Framer) module of the first physical port needs to receive the time stamp.
  • a timestamp The second physical port is a FlexE port, and when the first data stream reaches the second physical port, the second timestamp can be marked on the PMA of the second physical port.
  • the forward delay value can also be obtained by calculating the difference between the second timestamp and the first timestamp.
  • S220 The device determines a second delay value of the second data flow from the second physical port to the first physical port, where the first delay value is smaller than the second delay value.
  • the delay of the second data stream from the second physical to the first physical port of the device is referred to as a reverse delay.
  • the device determines that the forward delay value and the reverse delay value are not equal to each other, and may be a forward delay value greater than a reverse delay value or a reverse time.
  • the value of the delay is greater than the value of the forward delay.
  • the value of the forward delay value is less than the reverse delay value.
  • the method of measuring the reverse delay value may refer to the measurement method of the forward delay.
  • the ingress port and the egress port of the second data stream of the device may be both FlexE ports, that is, the first physical port and the second physical port are both FlexE ports, and the method may be determined by referring to the method of S1 in S210. Delay value.
  • the ingress port of the device can be a normal Ethernet port
  • the egress port is a FlexE port
  • the first physical port of the device is a normal Ethernet port
  • the second physical port is a FlexE port.
  • Second determine the reverse delay value of the device.
  • the device may also be an access device of the CPRI service.
  • the ingress and egress ports of the device are both FlexE ports.
  • the device is a CBR service access device, that is, the ingress port of the device is a CBR service port, and the device may determine the reverse delay value of the device by referring to method 4 in S210.
  • the device may determine a first delay value by using the second physical port, and determine a second delay value by using the first physical port, where the second physical port adds the first delay value to the In the second data stream.
  • the first physical port receives the first delay value carried in the second data stream.
  • the device determines a first target delay value based on the first delay value received by the first physical port and the second delay value determined by the first physical port.
  • the device determines a first target delay value based on the first delay value and the second delay value.
  • the device may determine the first target delay value according to the first delay value and the second delay value, where the first target delay value may be greater than or equal to the first delay value and the first The maximum of the two delay values.
  • the device determines that the first delay is 0.5 seconds, and the second delay is 0.8 seconds.
  • the first target delay value may be set to a value greater than or equal to the second delay value, for example, the first target time may be used.
  • the delay value is set to 0.8 seconds, and the first target delay value can also be set to 1 second.
  • the second physical port of the device may add the first delay value to the device.
  • the second data stream The second physical port sends the second data stream carrying the first delay value to the first physical port.
  • the first physical port may determine the second delay value of the second data stream and extract the first delay value by receiving the second data stream that carries the first delay value.
  • the second physical port determines the first target delay value according to the obtained first delay value and the second delay value.
  • the device adjusts a delay value of the first data stream to a first target delay value.
  • the device adjusts the delay value of the first data stream to the first target delay value by compensating the delay of the first data stream based on the first delay value of the first data stream.
  • the delay of the first data stream is compensated before the device sends the first data stream through the second physical port.
  • the device calculates that the difference between the first delay value and the first target delay value is D1, and the device configures D1 into the buffer of the device.
  • an idle data block is added to the first data block to compensate D1
  • the delay of the first data stream is adjusted to the first target delay value, so that the device adjusts
  • the forward delay value of a data stream is equal to the first target delay value.
  • the specific location where the device adds the idle data block to the first data stream may be placed according to the actual design. This application does not limit this.
  • the device may set the value of the first target delay value to be equal to the maximum value of the first delay value and the second delay value, or set the value of the first target delay value to be greater than the maximum The value, wherein, in the implementation, the maximum value is the second delay value.
  • the value of the first target delay value is set to be greater than the maximum value, not only the delay value of the first data stream may be adjusted to be equal to the first target delay value, but also the time of the second data stream. The delay is adjusted to be equal to the first target delay value.
  • the S240 may further include the device determining, according to the first delay value and the second delay value, a second target delay value that is different from the first target delay value.
  • the second target delay value is a value greater than the maximum value.
  • the device may adjust the delay value of the first data stream to be equal to the first target delay value, and may also adjust the delay value of the second data stream to be equal to the second target delay value.
  • the factors that cause delay uncertainty are mainly in the service initialization phase, or the frequency out-of-synchronization state.
  • the internal time stamp of the device consumes the service bandwidth during the time delay measurement process, the more the measurement times, the larger the bandwidth resource consumed.
  • the above delay compensation method can be started only after the service initialization ends and the frequency is synchronized.
  • the device when the device receives the bidirectional data stream, the delay of the data flow from the first physical port to the second physical port and the delay of the data flow from the second physical port to the first physical port are accurately measured. Got it.
  • the device adjusts the delay of the first data stream or the second data stream by setting a target delay value, thereby implementing a delay value for controlling the bidirectional flow through the device. For example, the device adjusts the forward delay of the first data stream or the reverse delay of the second data stream to make the forward delay value of the first data stream and the reverse delay value of the second data stream equal. Therefore, the transparent transmission of the time synchronization information can be implemented to solve the technical problem that the traditional device needs to rely on the 1588 technology to transmit the time information.
  • the device does not need to have the capability of processing the 1588 packet. The complexity of configuration, management, and maintenance is greatly reduced.
  • FIG. 3 is a schematic structural diagram of a device 300 according to an embodiment of the present disclosure.
  • the device 300 can be applied to the network architecture shown in FIG. 1 , for example, any of the devices 101 to 104 in the network architecture shown in FIG. 1 .
  • the device 300 can include a processor 310, a memory 320 coupled to the processor 310, and a network interface 330.
  • the processor 310 may be a central processing unit (English: central processing unit, abbreviated: CPU), a network processor (English: network processor, abbreviated: NP) or a combination of a CPU and an NP.
  • CPU central processing unit
  • NP network processor
  • the processor 310 may further include a hardware chip.
  • the hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (abbreviated as PLD), or a combination thereof.
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • the above PLD can be a complex programmable logic device (English: complex programmable logic device, abbreviation: CPLD), field-programmable gate array (English: field-programmable gate array, abbreviation: FPGA), general array logic (English: generic array Logic, abbreviation: GAL) or any combination thereof.
  • the processor 310 may be a processor or a plurality of processors.
  • the memory 320 may include a volatile memory (English: volatile memory), such as random-access memory (English: random-access memory, abbreviation: RAM); the memory may also include non-volatile memory (English: non-volatile memory) For example, read-only memory (English: read-only memory, abbreviation: ROM), flash memory (English: flash memory), hard disk (English: hard disk drive, abbreviation: HDD) or solid state drive (English: solid-state drive , abbreviation: SSD).
  • the memory 320 may also include a combination of the above types of memories.
  • the memory 320 can include a plurality of software modules, such as a determination module 321 and an adjustment module 322.
  • the processor 310 can be used to perform a plurality of operations by executing the instructions in the software modules described above.
  • the memory 320 may refer to one memory or may include a plurality of memories.
  • when a module is configured to perform an operation it may actually represent that processor 310 is configured to execute instructions in the module to perform the operations described above.
  • processor 310 can perform some or all of the operations performed by the device in methods 210-240. For example, processor 310 can receive the first data stream and the second data stream through network interface 330.
  • Bus 340 can include any number of interconnected buses and bridges that link together various circuits including one or more processors 310 represented by processor 310 and memory represented by memory 320. Bus 340 may also link various other circuits, such as peripherals, voltage regulators, and power management circuits, as is known in the art, and therefore, will not be further described herein.
  • the determining module 321 is configured to determine a first delay value of the first data flow from the first physical port of the device to the second physical port of the device, where the first physical port is an ingress port of the first data stream, and the second The physical port is the egress port of the first data stream.
  • the determining module 321 is further configured to determine a second delay value of the second data port from the second physical port to the first physical port, where the second physical port is an ingress port of the second data stream, and the first physical port is the first physical port The outbound port of the second data stream, where the first delay value is smaller than the second delay value.
  • the determining module 321 is further configured to determine a size of the first target delay value based on the first delay value and the second delay value.
  • the adjustment module 322 is configured to adjust the delay value of the first data stream to the first target delay value.
  • the first target delay value and the second delay value are equal.
  • the adjustment module 322 when the first target delay value is greater than the second delay value, is further configured to adjust the delay value of the second data flow to the first target delay value.
  • the determining unit 321 is further configured to determine a second target delay value based on the first delay value and the second delay value, where the adjusting module 322 is further configured to use the second data stream. The delay value is adjusted to the second target delay value.
  • the device 300 may further include an adding module 323, configured to add the first delay value in the second data stream.
  • the network interface 330 receives the first delay value carried in the second data stream.
  • the determining module 321 is configured to determine the first target delay value based on the first delay value received by the first physical port and the second delay value determined by the first physical port.
  • the specific implementations of the processor 310, the memory 320, and the network interface 330 may refer to the functions and operations of the device in FIG. 2, and are not described again for the sake of brevity.
  • the operations used by the various software modules for execution are actually performed directly or indirectly by processor 310 in accordance with instructions in various software modules.
  • the size of the sequence numbers of the foregoing methods does not mean the order of execution, and the order of execution of each method should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed methods and apparatus may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division.
  • there may be another division manner for example, multiple modules or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing unit, or each module may exist physically separately, or two or more modules may be integrated into one unit.
  • the above integrated modules can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the integrated unit may be stored in a computer readable storage medium if implemented in the form of hardware in conjunction with software and sold or used as a standalone product. Based on such understanding, some of the technical features of the technical solution of the present invention contributing to the prior art may be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for causing a computer
  • a device (which may be a personal computer, server, or device, etc.) performs some or all of the operations of the methods described in various embodiments of the present invention.
  • the foregoing storage medium may be a USB flash drive, a mobile hard disk, a read only memory (abbreviation: ROM, English: Read-Only Memory), a random access memory (abbreviation: RAM, English: Random Access Memory), a magnetic disk or an optical disk.
  • ROM read only memory
  • RAM random access memory
  • magnetic disk or an optical disk a magnetic disk or an optical disk.

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Abstract

本申请提供了一种补偿时延的方法和设备。该设备确定第一数据流从所述设备的第一物理端口到所述设备的第二物理端口的第一时延值和第二数据流从所述第二物理端口到所述第一物理端口的第二时延值，其中，所述第一时延值小于所述第二时延值。该设备基于第一时延值和第二时延值确定第一目标时延值。设备将第一数据流的时延值调整至第一目标时延值。通过上述方法，可以使该设备控制双向数据流的时延值。

Description

一种补偿时延的方法和设备
本申请要求于2018年3月13日提交中国国家知识产权局、申请号为201810203433.5、申请名称为“一种补偿时延的方法和设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，尤其涉及一种补偿时延的方法和设备。
背景技术
随着互联网协议(英文：Internet Protocol，简称：IP)网络的应用和业务的多样化，IP网络发展常需要解决在现有以太网接口速率等级下，满足更高带宽的需求。灵活以太网(英文：Flexible Ethernet，简称：FlexE)技术提供了一种支持多种以太网媒体接入控制(英文：Media Access Control，简称：MAC)速率的通用机制，其速度不再受物理层速率限制，可以满足多种业务速率的需求。
为了解决超低时延的问题，FlexE交叉作为一种新兴的以太网交换技术，因具备超低时延和超低抖动的转发特性，被用于5G移动业务承载以及电力继保业务承载等场景，而这些业务往往对时延信息的传递有着严苛的要求。因此，控制承载网中设备的时延是实现时间同步的重要问题。传统移动承载网解决时间同步的方法是通过在每一台基站上连接一台时间服务器来实现时间同步，但该方案需要部署大量的时间服务器和GPS，成本很高，部署难度很大；另外一种解决方案是通过在承载网络中部署一台或几台时间服务器，时间服务器通过承载网透传时间信息到基站，该方案需要承载网中的每台设备均需支持对精确时钟同步协议(英文：Precision Time Protocol，PTP)报文的处理能力，以及复杂的协议状态机运算，这样导致配置、管理和维护都比较复杂。
发明内容
本申请实施例提供了一种补偿时延的方法和设备，通过设备对双向数据流的时延进行补偿，以实现设备对数据流时延的控制。
第一方面，本申请提供了一种补偿时延的方法，该方法包括设备确定第一数据流从该设备的第一物理端口到该设备的第二物理端口的第一时延值，其中，第一物理端口为第一数据流的入端口，第二物理端口为第一数据流的出端口。设备确定第二数据流从第二物理端口到第一物理端口的第二时延值，其中，第二物理端口为第二数据流的入端口，第一物理端口为第二数据流的出端口。在第一时延值小于第二时延值的条件下，该设备基于第一时延值和第二时延值确定第一目标时延值。该设备将第一数据流的时延值调整至第一目标时延值。
采用上述方法，设备通过第一数据流的第一时延值和第二数据流的第二时延值来确定第一目标时延值，并将第一数据流的时延值调整到与第一目标时延值相等，实现 设备对双向数据流中第一数据流时延值的调整。
结合第一方面，在第一种可能的实现方式中，第一目标时延值和第二时延值相等。
上述方法，该设备确定第一目标时延值和第二时延值相等，使得第一数据流的时延值调整到与第二数据流的第二时延值相等，这样就可以实现该设备对双向数据流的对称性补偿，使第一数据流的从设备的第一物理端口到第二物理端口的时延值与第二数据流从该设备的第二物理端口到第一物理端口的时延相等，可以实现对时间同步报文的透传，避免传输时间同步报文的设备都需要具备处理1588协议的能力。
结合第一方面，在第二种可能的实现方式中，在第一目标时延值大于第二时延值时，该方法还包括：该设备将第二数据流的时延值调整至第一目标时延值。
上述方法，在第一目标时延值大于第二时延值时，该设备将第二数据流的时延值调整至第一目标时延值，这样就可以使第一数据流的时延值与第二数据流的时延值相等，即设备将第一数据流的时延值与第二数据流的时延值都调整到第一目标时延值，使第一数据流由设备第一物理端口到第二物理端口的时延值与第二数据流由第二物理端口到第一物理端口的时延值相等，即通过该设备补偿时延使设备的双向数据流的时延值相等。
结合第一方面，在第三种可能的实现方式中，该方法还包括，该设备基于第一时延值和第二时延值确定第二目标时延值。该设备将第二数据流的时延值调整至第二目标时延值。
上述方法，设备根据第一时延值和第二时延值确定第二目标时延值，并将第二数据流的时延值调整到第二目标时延值，这样可以实现设备对第二数据流的时延进行调整。
结合第一方面，在第四种可能的实现方式中，第二物理端口确定第一时延值和第一物理端口确定第二时延值包括：第二物理端口将第一时延值添加在第二数据流中。第一物理端口接收携带在第二数据流中的第一时延值。该设备基于第一物理端口接收的第一时延值和第一物理端口确定的第二时延值确定第一目标时延值。
上述方法，第二物理端口将第一时延值添加在第二数据流中，第一物理端口根据接收的第一时延值和确定的第二时延值来确定第一目标时延值，实现设备根据第一数据流的第一时延值确定第一目标时延值。
第二方面，本申请提供了一种设备，用于执行第一方面或第一方面任意可能的设计中的方法。具体地，该设备包括用于执行第一方面或第一方面任意可能的实施方式中的方法的模块。
第三方面，本申请提供了一种设备，包括：网络接口、处理器和存储器。其中，网络接口、处理器和存储器之间可以通过总线系统相连。该存储器用于存储程序、指令或代码，所述处理器用于执行所述存储器中的程序、指令或代码，完成第一方面或第一方面任意可能的设计中的方法中所述设备执行的信息收发以外的操作。
结合第四方面，本申请提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行第一方面和第一方面任意可能的实现方式中的方法的指令。
附图说明
图1为本发明实施例提供的一种补偿时延的方法的应用场景示意图；
图2为本发明实施例提供的一种补偿时延的方法流程示意图；
图3为本发明实施例提供的一种设备的结构示意图。
具体实施方式
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列操作或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些操作或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它操作或单元。
图1提供了一种补偿时延的系统架构示意图，该系统可以是传统的移动承载网，该网络系统中的设备101至104可以是支持FlexE技术的设备。在图1所示的网络系统中，解决时间同步的相关方法可以是在该承载网络中部署一台或几台时间服务器，时间服务器通过承载网将时间信息发送给基站。该时间同步方法具体如图1中的时间服务器105从GPS卫星或精确时钟同步协议(Precision Time Protocol，PTP)等获得时延信息编码并发出时间信息到设备104。然后按照由主设备到从设备的关系进行时钟同步，例如由主设备104向从设备103发布时间信息，设备103作为主设备向从设备102发布时间信息。而在使用上述方法实现时间同步的过程中，由于1588同步报文在支持FlexE的设备内转发存在时延不确定、双向时延不相等的问题，因此需要该承载网中的设备101至104都要逐跳运行1588同步报文。从1588同步报文的实现时间同步的过程中可以看出，承载网中的每台设备都需要支持对1588同步报文的收发处理以及复杂的协议状态机运算，即实现配置、管理和维护都比较复杂。
为了解决上述技术问题，实现设备对时间同步报文的透明传输，减少设备处理1588同步报文的复杂性，就需要解决设备如何控制双向数据流的时延，具体方法可以通过设备对数据流时延进行补偿，使设备的双向数据流的时延值保持稳定的关系，例如设备可以通过对双向数据流的补偿实现双向数据流时延值相等；还可以通过设备补偿双向数据流的时延，使双向数据流的时延保持稳定的差值，这样就实现对时间同步报文的透明传输，不需要设备通过1588来实现测量设备处理数据流的时延。图如2所示，为本申请提供了一种补偿时延的方法流程示意图，图2中所述的设备可以是图1中设备101至104中任意一个，该方法包括以下内容。
S210，设备确定第一数据流从所述设备的第一物理端口到所述设备的第二物理端口的第一时延值。
在一种实现方式中，第一数据流既可以是以太网物理层数据流，例如可以是1588时间同步报文或者网络时间协议(Network Time Protocol，NTP)报文，还可以是时分复用(Time Division Multiplexing，TDM)数据流等，本申请对第一数据流的类型不做具体限制。为了简便，本申请说明书部分用正向时延表示第一数据流从设备的第一物理端口到第二物理端口方向的时延，用反向时延表示第二数据流从第二物理端口 到第一物理端口方向的时延。
在一种实现方式中，第一数据流从该设备的第一物理端口到达该第二物理端口的过程中，该设备可以通过第一物理端口对第一数据流标记第一时间戳，通过第二物理端口标记第二时间戳，其中，标记时间戳的形式既可以是第一物理端口将第一时间戳添加在数据块中，还可以是在第一数据流到达第一物理端口时，第一物理端口标记第一时间戳并将该第一时间戳上报给设备的处理器，该设备还可以通过其它已知方式标记时间戳，本申请对标记时间戳的方式不做任何限制。第二物理端口标记第二时间戳的方式可以参考上述第一时间戳的标记方式。第一数据流从设备第一物理端口到该设备的第二物理端口的时延值为第二时延戳的值减去第一时间戳的值所获得的数值D1。
举例来说，不同的场景下该设备可以但不限于采用以下几种确定第一时间戳。
方式一、该设备可以为图1承载网中的设备102或103，该设备发送第一数据流的入端口和出端口均为FlexE端口，即第一物理端口和第二物理端口均为FlexE端口，其中，FlexE端口根据不同的应用场景，又可以区分为单物理层(英文：physical layer，简称：PHY)场景和多PHY场景，多PHY场景可以理解为多组单PHY的组合。
下面以该设备的第一物理端口和第二物理端口均为单PHY为例对该设备确定正向时延的方式进行详细描述。第一物理端口用于接收第一数据流和发送第二数据流，并将接收到的第一数据流转化为内部并行信号或者将发送的第二数据流由内部并行信号转换为可以在外部介质上传输的数据流。具体来说，该设备的第一物理端口接收第一数据流，并将第一数据流转换为第一数据块。第一物理端口的物理媒介附加(英文：Physical Medium Attachment Sublayer简称：PMA)接收到第一数据块时，可以用第一数据块首比特记录第一时间戳t1，每一组数据块都会记录。携带标记t1的第一数据块经过PMA和物理编码子层(英文：Physical Coding Sublayer，简称：PCS)处理后，会被转换为64/66比特数据块。为了更加精确计算正向时延，在第一数据块被转换为64/66比特数据块时，设备可以在64/66比特数据块的入口时戳标记T1，其中，该时间戳T1是通过时间戳t1和第一数据块首比特与64/66比特数据块首比特位置偏移转换得到的。该64/66比特数据块和该时间戳T1由第一物理端口发送到第二物理端口，即由设备的入端口发送到设备的出端口，携带时间戳标记T1的64/66比特数据块在被发送到第二物理端口之前，还可以经过设备其它模块的处理，对此不做限制。
该设备的第二物理端口接收到该64/66比特数据块和时间戳T1，识别并提取时间戳T1，获得T1的值。该64/66比特数据块经过第二物理端口的处理后发送给第二物理端口的PMA，第二物理端口的PMA用数据块的首比特记录第一数据流的经过第二物理端口PMA的出口时间戳T2，并将数据块转换为第一数据流。正向时延值的计算方法可以是上述T2与T1的差值，也可以是上述T2与t1的差值。
为了减少时间戳所占用的带宽，举例来说，可以对第一数据流采用抽样的方式，只在被抽样的数据块中标记时间戳。
方式二、当所述设备为图1中设备104，所述设备为承载网中的接入设备，所述设备的入端口为普通以太网(英文：Ethernet，简称：ETH)端口，出端口为FlexE端口时，即所述设备的第一物理端口为普通以太网端口，第二物理端口为FlexE端口，对所述设备正向时延的测量和计算方法可以参考上述设备的入端口和出端口均为 FlexE端口的测量和计算方法，可以通过第一物理端口对第一数据流标记第一时间戳，第二物理端口标记第一数据流到达出端口的第二时间戳。设备可以通过计算第二时间戳与第一时间戳差值获得正向时延值，具体方法可以参考方式一种所述，此处不再赘述。
方式三、所述设备还可以是通用公用无线接口(英文：common public radio interface，简称：CPRI)业务的接入设备，CRPI是移动前传网络中射频拉远单元(英文：remote radio unit，简称：RRU)和基带单元(英文：baseband unit，简称：BBU)之间的业务接口，该设备对传输时延和双向时延的差值要求极为苛刻。在CRPI业务中，同样可以采用设备的入端口和出端口均为FlexE端口场景下测量正向时延的方法，具体测量方法可参考设备的入端口和出端口均为FlexE端口场景下测量正向时延的方法，此处不再赘述。
方式四、当所述设备为固定比特率(英文：Constant Bit Rate，简称：CBR)业务接入设备，即所述设备的入端口为CBR业务端口，可称为第一物理端口，出端口为FlexE端口，可称为第二物理端口。由于业务接入设备的入端口为CBR业务端口，该CBR业务端口的业务处理部分无PMA，在CBR业务接入场景下需要在第一物理端口的帧(Framer)模块接收到所述报时标记第一时间戳。第二物理端口为FlexE端口，第一数据流到达第二物理端口时，可以在第二物理端口的PMA标记第二时间戳。同样可以通过计算第二时间戳与第一时间戳的差值获得正向时延值。
S220，该设备确定第二数据流从第二物理端口到第一物理端口的第二时延值，其中，第一时延值小于第二时延值。
在一种实现方式中，将第二数据流从该设备的第二物理到第一物理端口的时延称为反向时延。本领域普通技术人员可知，设备通过检测确定的正向时延值和反向时延值多数情况大并不相等，既可以是正向时延值大于反向时延值，也可以是反向时延值大于正向时延值，本申请下面以正向时延值小于反向时延值为例进行说明。
在一种实现方式中，反向时延值的测量方法可以参考正向时延的测量方法。
举例来说，该设备发送第二数据流的入端口和出端口可以均为FlexE端口，即第一物理端口和第二物理端口均为FlexE端口，可以参考S210中的方式一的方法确定反向时延值。
举例来说，该设备的入端口可以为普通以太网端口，出端口为FlexE端口，即所述设备的第一物理端口为普通以太网端口，第二物理端口为FlexE端口，可以参考S210中方式二确定该设备反向时延值。
举例来说，该设备还可以是CPRI业务的接入设备。在CPRI业务中，设备的入端口和出端口均为FlexE端口，具体确定反向时延的方法可参考设备的入端口和出端口均为FlexE端口场景下的方法确定该设备反向时延值。
举例来说，该设备为CBR业务接入设备，即所述设备的入端口为CBR业务端口，可参考S210中方式四确定该设备反向时延值。
在一种实现方式中，该设备可以通过第二物理端口确定第一时延值，通过第一物理端口确定第二时延值，其中，第二物理端口将第一时延值添加在所述第二数据流中。第一物理端口接收携带在第二数据流中的所述第一时延值。该设备基于第一物理端口 接收的第一时延值和第一物理端口确定的第二时延值确定第一目标时延值。
S230，所述设备基于第一时延值和第二时延值确定第一目标时延值。
在一种实现方式中，该设备可以根据第一时延值和第二时延值的大小来确定第一目标时延值，第一目标时延值可以大于或者等于第一时延值和第二时延值中的最大值。
举例来说，设备确定第一时延为0.5秒，第二时延为0.8秒，可将第一目标时延值设置为大于或者等于第二时延值的数值，例如可以将第一目标时延值设置为0.8秒，也可以将第一目标时延值设置为1秒。
在一种实现方式中，该设备在S210中通过第二物理端口确定该设备处理第一数据流的第一时延值之后，该设备的第二物理端口可以将该第一时延值添加在第二数据流。第二物理端口将携带第一时延值的第二数据流发送到第一物理端口。第一物理端口可以通过接收到携带第一时延值的第二数据流，确定第二数据流的第二时延值以及提取第一时延值。第二物理端口根据获的第一时延值和第二时延值的大小确定第一目标时延值。
S240，设备将第一数据流的时延值调整至第一目标时延值。
在一种实现方式中，该设备调整第一数据流的时延值至第一目标时延值是通过在第一数据流的第一时延值的基础上补偿第一数据流的时延。换句话说，就是在该设备将第一数据流通过第二物理端口发送出去之前，对第一数据流的时延进行补偿。具体可以是该设备计算获得第一时延值与第一目标时延值的差为D1，该设备将D1配置到该设备的缓冲器中。第一数据流被转化为第一数据块后，对第一数据块增加空闲(idle)数据块以补偿D1，即将第一数据流的时延调整到第一目标时延值，使设备调整第一数据流的正向时延值与第一目标时延值相等。设备对第一数据流增加空闲数据块的具体位置可以根据实际设计合理放置，本申请对此不做限制。
该设备可以将第一目标时延值的数值设置为与与第一时延值和第二时延值中的最大值相等，也可以将第一目标时延值的数值设置成大于所述最大值，其中，在本实现方式中，所述最大值为所述第二时延值。当将第一目标时延值的数值设置成大于所述最大值时，不仅可以将第一数据流的时延值调整至与第一目标时延值相等，还可以将第二数据流的时延值调整至与第一目标时延值相等。
S240还可以包括设备根据第一时延值和第二时延值的大小确定与第一目标时延值不等的第二目标时延值。其中第二目标时延值为大于所述最大值的数值。设备可以将第一数据流的时延值调整至与第一目标时延值相等，还可以将第二数据流的时延值调整至与第二目标时延值相等。
在一种实现方式中，由于引起时延不确定的因素主要发生在业务初始化阶段，或者频率失步状态。考虑到时延测量过程中设备内部传递时戳会消耗业务带宽，测量次数越多消耗的带宽资源越大。为了节省带宽，可以只在业务初始化结束且频率同步后启动上述时延补偿方法。
通过上述方法，该设备接收到双向数据流时，数据流从第一物理端口端口到第二物理端口的时延和数据流从第二物理端口到第一物理端口的时延均会被精确测得。该设备通过设定目标时延值，对第一数据流或者第二数据流的时延进行调整，从而实现控制双向流经过设备的时延值。例如该设备通过对第一数据流的正向时延或第二数据 流的反向时延进行调整，使第一数据流的正向时延值和第二数据流的反向时延值相等，这样就可以实现对时间同步信息的透明传输，以解决传统设备需要依赖1588技术才能透传时间信息的技术问题，不需要承载网中的所有设备都具备对1588报文处理的能力，使得网络的配置、管理和维护的复杂度均大大降低。
图3是本申请实施例提供的一种设备300的结构示意图，该设备300可以应用于图1所示的网络架构中，例如可以是图1所示的网络架构中的设备101至104中任意一个设备，可以实现该设备101至104中任意一个设备的功能。如图3所示，设备300可以包括处理器310，与处理器310耦合连接的存储器320，网络接口330。
处理器310可以是中央处理器(英文：central processing unit，缩写：CPU)，网络处理器(英文：network processor，缩写：NP)或者CPU和NP的组合。
处理器310还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(英文：application-specific integrated circuit，缩写：ASIC)，可编程逻辑器件(英文：programmable logic device，缩写：PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(英文：complex programmable logic device，缩写：CPLD)，现场可编程逻辑门阵列(英文：field-programmable gate array，缩写：FPGA)，通用阵列逻辑(英文：generic array logic,缩写：GAL)或其任意组合。处理器310可以是指一个处理器，也可以包括多个处理器。
存储器320可以包括易失性存储器(英文：volatile memory)，例如随机存取存储器(英文：random-access memory，缩写：RAM)；存储器也可以包括非易失性存储器(英文：non-volatile memory)，例如只读存储器(英文：read-only memory，缩写：ROM)，快闪存储器(英文：flash memory)，硬盘(英文：hard disk drive，缩写：HDD)或固态硬盘(英文：solid-state drive，缩写：SSD)。存储器320还可以包括上述种类的存储器的组合。
在一个实施方式中，存储器320可以包括多个软件模块，例如确定模块321和调整模块322。通过执行上述软件模块中的指令，处理器310可用于执行多个操作。存储器320可以是指一个存储器，也可以包括多个存储器。在一些实施方式中，当一个模块被配置用于执行一个操作，它可能实际表示处理器310被配置于执行模块中的指令以完成上述操作。通过执行存储器320中的指令，处理器310可以执行方法210至240中该设备所执行的部分或全部操作。例如，处理器310可以通过网络接口330接收第一数据流和第二数据流。
总线340可以包括任意数量的互联的总线和桥，总线340将包括由处理器310代表的一个或多个处理器310和存储器320代表的存储器的各种电路链接在一起。总线340还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。
确定模块321用于确定第一数据流从该设备的第一物理端口到该设备的第二物理端口的第一时延值，其中，第一物理端口为第一数据流的入端口，第二物理端口为第一数据流的出端口。该确定模块321还用于确定第二数据流从第二物理端口到第一物理端口的第二时延值，其中，第二物理端口为第二数据流的入端口，第一物理端口为第二数据流的出端口，第一时延值小于第二时延值。确定模块321还用于基于第一时 延值和第二时延值确定第一目标时延值的大小。
调整模块322用于将第一数据流的时延值调整至第一目标时延值。
在一个具体的实施方式中，第一目标时延值和第二时延值相等。
在一个具体的实施方式中，在第一目标时延值大于第二时延值时，调整模块322还用于将第二数据流的时延值调整至第一目标时延值。
在一个具体的实施方式中，确定单元321还用于基于所述第一时延值和第二时延值确定第二目标时延值，调整模块322还用于将所述第二数据流的时延值调整至所述第二目标时延值。
在一个具体的实施方式中，该设备300还可以包括添加模块323，该添加模块用于将所述第一时延值添加在所述第二数据流中。该网络接口330接收携带在第二数据流中的第一时延值。确定模块321用于基于第一物理端口接收的第一时延值和第一物理端口确定的第二时延值确定所述第一目标时延值。
在上述具体实施方式中，处理器310、存储器320以及网络接口330的具体实现可以参考图2中设备的功能和操作，为了简介，不再赘述。各个软件模块用于执行的操作实际上是由处理器310根据各个软件模块中的指令来直接或者间接执行的。
应理解，在本申请的各种实施例中，上述各方法的序号的大小并不意味着执行顺序的先后，各方法的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
在本申请所提供的几个实施例中，应该理解到，所公开的方法和设备，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理单元中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个单元中。上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
所述集成的单元如果以硬件结合软件的形式实现并作为独立的产品销售或使用时，所述软件可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案对现有技术做出贡献的部分技术特征可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者设备等)执行本发明各个实施例所述方法的部分或全部操作。而前述的存储介质可以是U盘、移动硬盘、只读存储器(简称：ROM，英文：Read-Only Memory)、随机存取存储器(简称：RAM，英文：Random Access Memory)、磁碟或者光盘。以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种补偿时延的方法，其特征在于，包括：
    设备确定第一数据流从所述设备的第一物理端口到所述设备的第二物理端口的第一时延值，所述第一物理端口为所述第一数据流的入端口，所述第二物理端口为所述第一数据流的出端口；
    所述设备确定第二数据流从所述第二物理端口到所述第一物理端口的第二时延值，所述第二物理端口为所述第二数据流的入端口，所述第一物理端口为所述第二数据流的出端口，其中所述第一时延值小于所述第二时延值；
    所述设备基于所述第一时延值和所述第二时延值确定第一目标时延值；
    所述设备将所述第一数据流的时延值调整至所述第一目标时延值。
  2. 根据权利要求1所述的方法，其特征在于，所述第一目标时延值和所述第二时延值相等。
  3. 根据权利要求1所述的方法，其特征在于，所述第一目标时延值大于所述第二时延值，所述方法还包括：
    所述设备将所述第二数据流的时延值调整至所述第一目标时延值。
  4. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    所述设备基于所述第一时延值和所述第二时延值确定第二目标时延值；
    所述设备将所述第二数据流的时延值调整至所述第二目标时延值。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，
    所述第二物理端口确定所述第一时延值，所述第一物理端口确定所述第二时延值；
    所述方法还包括：
    所述第二物理端口将所述第一时延值添加在所述第二数据流中；
    所述第一物理端口接收携带在所述第二数据流中的所述第一时延值；
    其中所述设备基于所述第一物理端口接收的所述第一时延值和所述第一物理端口确定的所述第二时延值确定所述第一目标时延值。
  6. 一种设备，其特征在于，包括：
    存储器，所述存储器包括指令；
    以及与所述存储器通信的处理器，所述处理器用于执行所述指令，从而：
    确定第一数据流从所述设备的第一物理端口到所述设备的第二物理端口的第一时延值，所述第一物理端口为所述第一数据流的入端口，所述第二物理端口为所述第一数据流的出端口；
    确定第二数据流从所述第二物理端口到所述第一物理端口的第二时延值，所述第二物理端口为所述第二数据流的入端口，所述第一物理端口为所述第二数据流的出端口，其中所述第一时延值小于第二时延值。
    基于所述第一时延值和所述第二时延值确定第一目标时延值；
    将所述第一数据流的时延值调整至所述第一目标时延值。
  7. 根据权利要求6所述的设备，其特征在于，所述第一目标时延值和所述第二时延值相等。
  8. 根据权利要求6所述的设备，其特征在于，
    所述第一目标时延值大于所述第二时延值，所述处理器还用于执行所述指令，从而：
    将所述第二数据流的时延值调整至所述第一目标时延值。
  9. 根据权利要求6所述的设备，其特征在于，所述处理器还用于执行所述指令，从而：
    基于所述第一时延值和所述第二时延值确定第二目标时延值；
    将所述第二数据流的时延值调整至所述第二目标时延值。
  10. 根据权利要求6至9中任一项所述的设备，其特征在于，
    所述处理器还用于执行所述指令，从而：
    将所述第一时延值添加在所述第二数据流中；
    接收携带在所述第二数据流中的所述第一时延值；
    基于所述第一时延值和所述第二时延值确定所述第一目标时延值。
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EP4060913A1 (en) 2022-09-21
US11641266B2 (en) 2023-05-02
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