WO2019173955A1 - 一种全频带接收机和电视调谐器 - Google Patents

一种全频带接收机和电视调谐器 Download PDF

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Publication number
WO2019173955A1
WO2019173955A1 PCT/CN2018/078752 CN2018078752W WO2019173955A1 WO 2019173955 A1 WO2019173955 A1 WO 2019173955A1 CN 2018078752 W CN2018078752 W CN 2018078752W WO 2019173955 A1 WO2019173955 A1 WO 2019173955A1
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Prior art keywords
signal
attenuation network
input
differential
full
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PCT/CN2018/078752
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English (en)
French (fr)
Inventor
金香菊
莫秉轩
张立国
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华为技术有限公司
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Priority to CN201880091067.7A priority Critical patent/CN111903119B/zh
Priority to CN202210555764.1A priority patent/CN115022566A/zh
Priority to PCT/CN2018/078752 priority patent/WO2019173955A1/zh
Publication of WO2019173955A1 publication Critical patent/WO2019173955A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/50—Tuning indicators; Automatic tuning control

Definitions

  • the present application relates to the field of television technologies, and in particular, to a full-band receiver and a television tuner.
  • the television tuner (TV tuner) is an important device in the set-top box, which can complete the process of amplifying, filtering, analog-to-digital conversion and demodulation of the radio frequency signal of the television.
  • TV tuner processing the radio frequency signal of the television, if there is a problem of excessive interference, poor linearity, or signal distortion, the received image and the accompanying sound quality are likely to be deteriorated.
  • CMOS complementary metal oxide semiconductor
  • a common method in the specific implementation process is to set up a crossover network in the set top box, as shown in Figure 1a.
  • the antenna in the set-top box After receiving the radio frequency signal of the full-band TV, the antenna in the set-top box obtains the low-band signal (50MHz-407MHz) and the high-band (407MHz-1008MHz) signal through the crossover network. Then, the low-band signal and the high-band signal are respectively input into the corresponding LNAs, thereby implementing frequency conversion and demodulation of the signals.
  • a tracking filter is provided at the front end of the LNA.
  • the frequency-following filter filters out the radio frequency signals of the narrow-band televisions of the frequency band in which the frequency band selected by the user is located from the radio frequency signals of the full-band television received from the antenna. Then, it is sent to the LNA or the like for subsequent signal processing.
  • the mixer, LPF, VGA, and ADC included in the narrowband receiver are usually implemented in a CMOS process.
  • the LNA implemented by the non-COMS process is processed by other devices in the narrowband receiver (such as a mixer). Incompatibility, resulting in the need for off-chip implementation, the cost is too high.
  • the above-mentioned television tuner can satisfy the user's demand for television program viewing in the case of processing only television signals.
  • the above-mentioned television tuners are limited by narrowband receivers and cannot handle signals of larger bandwidth.
  • the TV tuner can process the radio frequency signal after the user selects the channel to be played, so the signal processing speed is relatively slow.
  • higher requirements are imposed on the signal processing capabilities (such as bandwidth, signal processing speed, etc.) of the TV tuner.
  • the embodiment of the present application provides a full-band receiver and a TV tuner, which helps improve the anti-interference performance and linearity of the circuit, thereby improving the processing capability of the signal.
  • the full-band receiver includes: a single-turn dual circuit, a resistance attenuation network, and a differential amplifier, and the gain of the resistance attenuation network and the gain of the differential amplifier are adjustable;
  • the single-turn dual circuit is configured to convert a television signal into a first differential signal and input the first differential signal to the resistance attenuation network;
  • the resistance attenuation network is configured to attenuate the first differential signal Obtaining a second differential signal and inputting the second differential signal to the differential amplifier;
  • the differential amplifier is configured to amplify the second differential signal.
  • the full-band receiver since the full-band receiver has a differential structure, processing by converting the television signal into a differential signal helps to improve the anti-interference performance and the even-order linearity of the circuit. Therefore, when the set-top box adopts the full-band receiver of the embodiment of the present application to receive and process the television signal in the entire frequency band, since the television signal is converted into a differential signal for processing, the mutual interference between the signals during the processing can be reduced, and further It helps to avoid signal distortion on each channel and can output images and signals with high sound quality to the TV.
  • the single-turn dual circuit is an on-chip passive balun, or the single-turn dual circuit is an active balun.
  • the on-chip passive balun includes a first coil, a second coil, a first capacitor, and a second capacitor, wherein the first coil is connected in parallel with the first capacitor, the second The coil is connected in parallel with the second capacitor, and one end of the first coil connected in parallel with the first capacitor is used to receive the radio frequency signal, and the other end of the first coil connected in parallel with the first capacitor is grounded, One end of the second coil in parallel with the second capacitor is an output end of the on-chip passive balun connected to an input end of the resistance attenuation network, and the second coil is connected in parallel with the second capacitor The other end is the other output of the on-chip passive balun that is coupled to the other input of the resistive attenuation network.
  • the resistance decay network is a ⁇ -type resistance decay network.
  • the resistance of the resistor included in the ⁇ -type resistance attenuation network is adjustable for adjusting the gain of the ⁇ -type resistance attenuation network.
  • the resistance attenuation network includes a first portion and a second portion; the first portion of the resistance attenuation network is configured to correspondingly attenuate the first path signal to obtain the third path signal The second portion of the resistance attenuation network is configured to perform corresponding attenuation on the second path signal to obtain a fourth path signal; wherein the first path signal and the second path signal constitute the first a differential signal; the third signal and the fourth signal form the second differential signal; a first end of the first portion is an input of the resistance attenuation network, and a first portion of the first portion One end is connected to one output end of the single-turn dual circuit, the first end of the second part is another input end of the resistance attenuation network, and the first end of the second part is opposite to the single The other end of the dual circuit is connected; the second end of the first portion is an output of the resistor attenuation network, and the second end of the first portion is coupled to an input of the differential amplifier; Second a second end of the portion
  • the closed loop bandwidth of the differential amplifier is adjustable. By adjusting the closed-loop bandwidth of the differential amplifier, it helps to improve the stability of the differential amplifier.
  • the differential amplifier includes a first input resistor, a first feedback capacitor, a first feedback resistor, a second input resistor, a second feedback capacitor, a second feedback resistor, a first-stage operational amplifier, and Adjusting a capacitance and a second-stage operational amplifier; and the capacitance value of the first feedback capacitance, the capacitance value of the second feedback capacitance, and the capacitance value of the adjustable capacitance are adjustable for adjusting the differential amplifier a closed loop bandwidth; a resistance of the first input resistor, a resistance of the first feedback resistor, a resistance of the second input resistor, and a resistance of the second feedback resistor are adjustable for Adjusting the gain of the differential amplifier;
  • the first parallel circuit is a parallel circuit composed of the first feedback capacitor and the first feedback resistor; a negative-phase output terminal of the first-stage operational amplifier is respectively connected to one end of the adjustable capacitor and a non-inverting input terminal of the second-stage operational amplifier; a positive-phase output terminal of the second-stage operational amplifier and the One end of the first parallel circuit is connected; one end of the second input resistor is another input end of the differential amplifier, and one end of the second input resistor is connected to another output end of the resistance attenuation network, The other end of the second input resistor is respectively connected to one end of the second parallel circuit and the negative phase input end of the first stage operational amplifier, and the second parallel circuit is a parallel circuit composed of
  • the full-band receiver further includes: a filter and an ADC.
  • the filter is configured to filter the amplified second differential signal to obtain a third differential signal, and input the third differential signal to the ADC; the ADC is used to the third The differential signal is analog-to-digital converted to obtain a digital signal.
  • the full-band receiver is integrated on a single chip.
  • the resistance attenuation network included in the full-band receiver and the differential amplifier are integrated on one chip.
  • a television tuner includes a full-band receiver and a demod, wherein the full-band receiver includes a single-turn dual circuit, a resistance attenuation network, a differential amplifier, a filter, and an ADC;
  • the gain of the resistance attenuation network and the gain of the differential amplifier are adjustable;
  • the single-turn dual circuit is for converting a television signal into a first differential signal, and inputting the first differential signal to the resistance attenuation network
  • the resistance attenuation network attenuates the first differential signal to obtain a second differential signal, and inputs the second differential signal to the differential amplifier;
  • the differential amplifier is configured to the second differential signal Amplifying, and inputting the amplified second differential signal to the filter;
  • the filter is configured to filter the amplified second differential signal to obtain a third differential signal, and the a three differential signal is input to the ADC;
  • the ADC is configured to perform analog-to-digital conversion on the third differential signal to obtain a digital signal, and input the
  • the specific implementation manners of the single-turn dual circuit, the resistance attenuation network, and the differential amplifier included in the full-band receiver included in the TV tuner in the embodiment of the present application can be referred to the full-band receiver in the first aspect.
  • the specific implementation of the single-turn dual circuit, the resistance attenuation network, and the differential amplifier included in the description will not be repeated here.
  • the full-band receiver and the demot are integrated on a single chip; or the resistor-attenuating network, differential amplifier, filter, and analog-to-digital converter ADC in the full-band receiver And the demo is integrated on a chip.
  • the full-band receiver includes a single-turn dual circuit, a resistive attenuation network, a differential amplifier, a programmable gain amplifier, a filter, and an ADC
  • a programmable gain amplifier in the full-band receiver optionally, a programmable gain amplifier in the full-band receiver
  • the filter and the ADC, and the demod are integrated on a single chip
  • the full-band receiver includes a single-turn dual circuit, a resistor-attenuation network, a differential amplifier, a programmable gain amplifier, a filter, and an ADC And integrated on a chip
  • the full-band receiver includes a resistor attenuation network, a differential amplifier, a programmable gain amplifier, a filter, an ADC, and a demot integrated on one chip, which is not limited in this embodiment of the present application. .
  • the demod is further configured to select a gain adjustment mode from a preset first gain adjustment mode table according to the amplitude of the demodulated signal of the digital signal, and adjust the resistance attenuation network. Gain and gain of the differential amplifier.
  • the demod is further configured to adjust a closed loop bandwidth of the differential amplifier based on a bandwidth of a signal that is demodulated for the digital signal.
  • a television tuner includes a full-band receiver, and at least two mixing receivers and a demodulator; wherein the full-band receiver includes a single-turn dual circuit, a resistance attenuation network, and a differential An amplifier, wherein each of the at least two mixing receivers is configured to perform amplification, frequency conversion, filtering, and analog-to-digital conversion processing on a signal obtained by processing the full-band receiver, and after the processing The obtained signal is input to the demod; the demod is used for demodulating a signal processed by the at least two mixing receivers.
  • the specific implementation manners of the single-turn dual circuit, the resistance attenuation network, and the differential amplifier included in the full-band receiver included in the TV tuner in the embodiment of the present application can be referred to the full-band receiver in the first aspect.
  • the specific implementation of the single-turn dual circuit, the resistance attenuation network, and the differential amplifier included in the description will not be repeated here.
  • each of the at least two mixing receivers includes an amplifier, a mixer, a filter, and an ADC. It should be noted that, in the embodiment of the present application, the order of connection between the amplifier, the mixer, the filter, and the ADC included in the mixing receiver is not limited.
  • FIG. 1a and 1b are schematic diagrams showing the architecture of a conventional TV tuner
  • FIG. 2 is a schematic structural diagram of a full-band receiver according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a balun realized by a package trace or an on-chip metal wire according to an embodiment of the present application
  • FIGS. 4a to 4c are respectively a schematic structural diagram of a passive balun according to an embodiment of the present application.
  • 5a and 5b are respectively a schematic structural diagram of an active balun according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a resistor attenuation network according to an embodiment of the present application.
  • FIGS. 7a-7c are specific schematic diagrams of VSS implementation according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a differential amplifier according to an embodiment of the present application.
  • FIG. 9 is still another schematic structural diagram of a differential amplifier according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a full-band receiver according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a television tuner according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of still another embodiment of a television tuner according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a possible structure of a mixing receiver according to an embodiment of the present application.
  • FIG. 2 it is a schematic diagram of a full-band receiver, including a single-turn dual circuit, a resistance-attenuation network, and a differential amplifier, and the gain of the resistance-attenuation network and the gain of the differential amplifier are adjustable.
  • the single-turn dual circuit is used for converting the television signal into the first differential signal, and inputting the first differential signal to the resistance attenuation network.
  • the resistance attenuation network is configured to attenuate the first differential signal to obtain a second differential signal, and input the second differential signal to the differential amplifier.
  • a differential amplifier is used to amplify the second differential signal.
  • the television signals involved in the embodiments of the present application are radio frequency signals, such as satellite television signals, terrestrial television signals, closed circuit television signals, and the like.
  • a satellite television signal refers to a television signal transmitted by a satellite.
  • the terrestrial television signal refers to the television signal transmitted by the terrestrial television tower.
  • a closed-circuit television signal is a television signal transmitted through a wire, such as a closed-circuit television signal sent by a mounted camera in a building to a monitor.
  • the full-band receiver is a differential structure
  • by converting the television signal into a differential signal for processing it is helpful to improve the anti-interference performance and the even-order linearity of the circuit, so that the set-top box is as shown in FIG. 2
  • the full-band receiver is shown to receive and process the television signal in the entire frequency band
  • the television signal is converted into a differential signal for processing, the mutual interference between the signals during processing can be reduced, thereby helping to avoid the respective channels.
  • the signal is distorted and can output images and signals with higher sound quality to the TV.
  • the single-turn dual circuit of the embodiment of the present application matches the impedance of the resistance attenuation network.
  • the single ended to double ended (S2D) in the embodiment of the present application may be a passive balun, a passive on-chip balun or an active balun.
  • balun is a device capable of single-ended and differential mutual conversion
  • passive balun refers to a passive device that realizes single-ended and double-ended mutual conversion, which may not be integrated on the chip. Can be integrated on the chip or implemented with package traces.
  • the passive balun can also be called the passive on-chip balun, and the specific implementation forms include parallel winding, cross winding, stack winding, symmetrical balun, etc., as shown in Fig. 3.
  • the package traces shown are implemented as symmetric baluns.
  • the same balun as the on-chip balun can be achieved by encapsulating the traces.
  • a passive balun circuit structure may be as shown in FIG. 4a, including a first coil L1 and a second coil L2.
  • the structure of the passive balun may also be as shown in FIG. 4b, including a first coil L1, a second coil L2, a first capacitor C1 and a second capacitor C2, wherein L1 and C1 are connected in parallel, and L2 is connected in parallel with C2.
  • C1 and C2 may be capacitors with a fixed capacitance value, and may also be capacitors with adjustable capacitance values, which are not limited in this embodiment of the present application.
  • one end of the parallel connection of L1 and C1 is an input terminal for receiving a radio frequency signal.
  • the other end of L1 in parallel with C1 is an output for connection to an input of the resistor attenuation network.
  • One end of L2 in parallel with C2 is the other input for grounding.
  • the other end of L2 in parallel with C2 is the other output for connection to the other input of the resistor attenuation network.
  • the structure of the passive balun may also be as shown in FIG. 4c, including a first coil L1, a second coil L2, a first capacitor C1 and a second capacitor C2, wherein L1 and C1 are connected in parallel, and L2 and C2 are connected in parallel.
  • C1 and C2 may be capacitors of a fixed capacitance value or capacitors with adjustable capacitance values, which are not limited in this embodiment.
  • L1 and C1 in parallel are an input terminal for receiving radio frequency signals.
  • the other end of L1 in parallel with C1 is the other input for grounding.
  • One end of L2 in parallel with C2 is the other output for connection to an input of the resistor attenuation network.
  • the other end of L2 in parallel with C2 is the other output for connection to the other input of the resistor attenuation network.
  • a possible active balun circuit structure can be as shown in FIG. 5a, including a metal oxide semiconductor (metal oxide semiconductor).
  • MOS metal oxide semiconductor
  • MOS transistor M1, MOS transistor M2, MOS transistor M3, MOS transistor M4, capacitor C1, capacitor C2, resistor R1, resistor R2, current source I0, where M1 satisfies the input matching condition Rin 1/gm1, and gm1 is M1 Transconductance.
  • the input signal Vx is amplified by M1 to become a first current signal, and the first current signal is passed through M3 to obtain an output voltage Vo+.
  • the Vx signal obtains a voltage Vy after passing through M1, and Vy is amplified by M2 to obtain a first Two current signals, the second current signal passes through M4 to obtain the output voltage Vo-.
  • the obtained Vo+ and Vo- can be obtained. The same magnitude is reversed in the same direction, so that the single-ended signal is converted into a differential signal by the circuit structure as shown in FIG. 5a.
  • another possible active balun circuit structure diagram includes a resistor R1, a resistor R2, an operational amplifier A1, an operational amplifier A2, and an operational amplifier A3.
  • the input signal is reversed by the A1 signal.
  • Obtaining a second signal which obtains Vo+ and Vo- through A2 and A3, respectively, wherein Vo+ is opposite in direction to Vo-, and
  • A2 and A3 are cross-coupling structures in the circuit structure shown in FIG. 5b, which helps to improve
  • the resistor attenuation network in the embodiment of the present application may also be referred to as a resistor attenuation circuit.
  • the resistance attenuation network may be a T-type resistance attenuation network, or may be a ⁇ -type resistance attenuation network, etc., which is not limited thereto.
  • a schematic diagram of a possible ⁇ -type resistance attenuation network includes an adjustable resistor R1, an adjustable resistor R2, an adjustable resistor R3, an adjustable resistor R4, an adjustable resistor R5, and an adjustable resistor R6.
  • R1, R2 and R3 form a first part
  • R4, R5 and R6 form a second part
  • the first end A1 of the first part is connected with the output end P1 of the single-turn dual circuit
  • the first end A2 of the second part is double-turned
  • the output terminal P2 of the circuit is connected
  • the second terminal B1 of the first portion is connected to the input terminal Q1 of the differential amplifier
  • the second terminal B2 of the second portion is connected to the input terminal Q2 of the differential amplifier
  • the third terminal C1 and the fourth terminal of the first portion are connected.
  • the terminal D1 and the third terminal C2 and the fourth terminal D2 of the second portion are respectively connected to the node VSS.
  • the first part is used for corresponding attenuation of the first path signal to obtain a third path signal.
  • the second part is used to correspondingly attenuate the second signal to obtain a fourth signal.
  • the first differential signal is composed of the first path signal and the second path signal
  • the second differential signal is composed of the third path signal and the fourth path signal.
  • the third signal and the fourth signal that may be obtained cannot satisfy the equal size.
  • the phase phase difference of 180 degrees requires no signal with differential characteristics.
  • the signal attenuation gain of the resistive attenuation network becomes larger, the deviation of the amplitude and gain of the differential signal from the ideal differential signal is further increased. Therefore, in order to improve the differential characteristic of the second differential signal, optionally, one end of the node VSS is one end of the capacitor, and the other end of the capacitor is connected to the ground; or, the voltage of the node VSS is zero.
  • the gain of the resistance attenuation network and the gain of the differential amplifier are adjustable, it is helpful to increase the range of the amplitude of the dynamic adjustment signal.
  • the gain of the resistive attenuation network can be adjusted to A1, A2, and A3, and the gain of the differential amplifier can be adjusted to B1, B2, and B3, and the gain of the amplitude of up to nine adjusted signals can be combined by the resistive attenuation network and the differential amplifier. Therefore, the gain of the resistance-attenuation network can be adjusted and the larger the adjustable range of the differential amplifier, the larger the range of the amplitude of the dynamic adjustment signal is.
  • the amplitude of the signal may refer to the voltage value of the signal.
  • the amplitude of the first differential signal is K1
  • the gain of the resistance attenuation network is -0.25 and the gain of the differential amplifier is 2
  • the amplitude of the signal obtained by the first differential signal after being amplified by the resistance attenuation network and the differential amplifier is K1/2.
  • the amplitude of the first differential signal is K1
  • the gain of the resistance attenuation network is -0.5 and the gain of the differential amplifier is 6
  • the amplitude of the signal obtained by the first differential signal after being amplified by the resistance attenuation network and the differential amplifier is 3K1.
  • the gain of the resistor-attenuating network can be adjusted by adjusting the resistance of the resistor included in the resistor-attenuation network, and by adjusting the resistance of the resistor included in the differential amplifier.
  • the gain of the differential amplifier can be adjusted by adjusting the resistance of the resistor included in the resistor-attenuation network, and by adjusting the resistance of the resistor included in the differential amplifier.
  • the resistors R1, R2, R3, R4, R5, and R6 may be adjustable resistors or a resistor group.
  • the resistor R1 has one or more resistors connected in parallel. And/or in series, the connection of the plurality of resistors in the resistor R1 is controlled by the MOS switch, so that the resistance value of the resistor R1 is adjustable.
  • the gain of the resistance-attenuation network and the gain of the differential amplifier can be adjusted by demod, or the gain of the resistance-attenuation network and the differential amplifier can be realized by the control module.
  • Gain adjustment For a specific adjustment manner, refer to the method for adjusting the gain of the resistance attenuation network and the gain of the differential amplifier when the television tuner in the embodiment of the present application is introduced, and details are not described herein again.
  • the node VSS shown in FIG. 7a when the resistance in the resistance attenuation network shown in FIG. 6 is controlled by the MOS switch, the node VSS shown in FIG. 7a is connected to one end of the capacitor, and the other end of the capacitor is connected to the ground. , ground the substrate of the MOS switch, and set the gate oxide voltage of the MOS switch to VDD1.
  • the substrate of the MOS switch in the case where the node VSS is connected to the ground as shown in FIG. 7b, the substrate of the MOS switch is connected to a negative voltage, and the gate oxide voltage of the MOS switch is set to VDD2.
  • the differential amplifier may be an LNA. Because of the differential structure adopted by the full-band receiver in the embodiment of the present application, the differential signal has the characteristics that the amplitude of the signal is equal and the phases are 180 degrees out of phase, and the nonlinear characteristics of the even-order are very good.
  • the gain feedback structure adopted by the band receiver in the feedback the gain is provided by the resistor, and the linearity is good. Therefore, the differential amplifier used in the embodiment of the present application can be a low-noise differential amplifier of the CMOS process, which helps to reduce the cost.
  • FIG. 8 it is a schematic structural diagram of a possible differential amplifier.
  • the differential amplifier shown in FIG. 8 includes a first input resistor Rin1, a first feedback resistor Rf1, a first feedback capacitor Cf1, a second input resistor Rin2, a second feedback resistor Rf2, a second feedback capacitor Cf2, and a first operation.
  • Amplifier A1 and second operational amplifier A2. Normally, in order to ensure that the signal output from the differential amplifier shown in FIG. 8 is a differential signal, Rf1 and Rf2 are equal in magnitude, and Cf1 and Cf2 are equal in magnitude.
  • Gain represents the gain of the signal
  • Rf represents the magnitude of the feedback resistor
  • Rin represents the magnitude of the input resistor Rin
  • A represents the open-loop gain of the differential amplifier. It can be seen from the expression (1) that the gain of the signal of the differential amplifier does not change with changes in temperature, process, power supply voltage, etc., and is only related to the ratio of the input resistance and the feedback resistance, thereby contributing to broadband and high linearity. degree.
  • the differential amplifier shown in FIG. 8 in the embodiment of the present application includes a two-stage operational amplifier, the first-stage amplifier is used to amplify the signal, and the second-stage amplifier is used to provide a driving capability, which is helpful for driving a large load.
  • the full-band receiver adopts a fully differential structure, which is beneficial to improving the anti-interference of the circuit.
  • the gain of the differential amplifier can be adjusted by adjusting the resistances of Rin1, Rin2, Rf1, and Rf2. Therefore, in the above case, the adjustable range of the gain of the differential amplifier is related to the adjustable range of the resistances of the resistors Rin1, Rin2, Rf1, and Rf2, and the larger the adjustable range of the resistors Rin1, Rin2, Rf1, and Rf2 is. The adjustable range of the gain of the differential amplifier is larger.
  • the differential amplifier shown in Figure 8 may cause ring closure instability, because the gain-bandwidth product of the open-loop feedback amplifier is usually fixed, and the open-loop op amp is fixed.
  • the gain bandwidth product GBW also satisfies the following expression (2):
  • GBW represents the gain bandwidth product
  • Gain represents the amplification gain of the signal, ie closed-loop gain
  • BW represents the closed-loop bandwidth
  • the bandwidth of the signal that the differential amplifier can process becomes large, and thus the instability of the closed loop is liable to occur.
  • the bandwidth of the signal that can be processed exceeds the bandwidth of the entire frequency band of the TV. It is meaningless for a resistive feedback amplifier.
  • the closed loop bandwidth of the differential amplifier in the embodiment of the present application is adjustable.
  • One possible example is to reduce the bandwidth of the signal that the differential amplifier can process by adjusting the capacitance of the capacitor in the differential amplifier in order to improve the stability of the closed loop when the amplification gain of the signal is small.
  • the bandwidth of the signals that the differential amplifier can process can be reduced by adjusting the capacitance values of Cf1 and Cf2 in the differential amplifier.
  • a full-band receiver is applied to a television tuner
  • one possible implementation is to adjust the closed-loop bandwidth of the differential amplifier according to the bandwidth of the demodulated signal by a demodulator included in the television tuner. Taking the differential amplifier shown in FIG.
  • the capacitance values of Cf1 and Cf2 are adjusted, thereby realizing the adjustment of the closed-loop bandwidth of the differential amplifier.
  • one end of the Rin1 is an input terminal of the differential amplifier, and is connected to one output end of the resistance attenuation network, and the other end of the Rin1 is respectively connected to one end of the first parallel circuit and the positive phase input end of the A1, and the first parallel circuit is A parallel circuit composed of Cf1 and Rf1; a negative phase output terminal of A1 is respectively connected to one end of CL and a positive phase input terminal of A2; the positive phase output terminal of A2 is connected to the other end of the first parallel circuit; and one end of Rin2 is a differential amplifier
  • the other input is connected to another output of the resistor attenuation network, and the other end of the Rin2 is respectively connected to one end of the second parallel circuit and the negative input of the A1, and the second parallel circuit is a parallel connection of C
  • the positive phase output of A1 is connected to the other end of CL and the negative input of A2, respectively; the negative output of A2 is connected to the other end of the second parallel circuit.
  • the differential amplifier can adjust the capacitance of Cf1, Cf2 and CL according to the bandwidth of the second differential signal to reduce the bandwidth of the signal that the differential amplifier can process. the size of.
  • the fully differential receiver may further include a DC blocking capacitor.
  • the first differential signal outputted by the single-turn dual circuit is input to the resistance attenuation network after filtering the DC signal through the DC blocking capacitor.
  • FIG. 10 it is a schematic structural diagram of a possible fully differential receiver.
  • the fully differential receiver shown in FIG. 10 includes a single-turn dual circuit, a DC blocking capacitor, a resistance attenuation network, and a differential amplifier.
  • the single-turn dual circuit includes a coil L1 and a coil L2, and the resistance attenuation network includes an adjustable resistor R1, an adjustable resistor R2, an adjustable resistor R3, an adjustable resistor R4, an adjustable resistor R5, and an adjustable resistor R6, and a differential amplifier.
  • the full-band receiver of the embodiment of the present application includes a single-turn dual circuit, a resistance attenuation network, and a differential amplifier.
  • a single-turn dual circuit, a resistor-attenuation network, and a differential amplifier can be integrated on one chip, or a resistor-attenuation network and a differential amplifier can be integrated on one chip.
  • full-band receiver in the embodiment of the present application is not limited to include a single-turn dual circuit, a resistance attenuation network, and a differential amplifier.
  • a full-band receiver may also include a filter, an ADC, and a programmable gain amplifier (PGA).
  • full-band receivers include single-turn dual-circuit, resistance-attenuation networks, differential amplifiers, filters, and ADCs.
  • the filter is configured to filter the amplified second differential signal to obtain a third differential signal, and input the third differential signal to the ADC;
  • the ADC is configured to perform analog-to-digital conversion on the third differential signal to obtain a digital signal.
  • single-turn dual-circuit, resistive-attenuation networks, differential amplifiers, filters, and ADCs can be integrated on a single chip, or a resistor-attenuation network, differential amplifier, filter, and ADC can be integrated on a single chip.
  • the full-band receiver in the embodiment of the present application includes a single-turn dual circuit, a resistance attenuation network, and a differential amplifier, when the full-band receiver in the embodiment of the present application is applied to a signal receiving terminal such as a set-top box, the signal can be directly used.
  • the television signal received by the antenna in the receiving terminal is processed without narrowband processing of the radio frequency signal in advance.
  • the process of processing the radio frequency signal by the full-band receiver in the embodiment of the present application is independent of the signal of the channel selected by the user, and after the set-top box receives the control command sent by the controller (such as the remote controller), the control command is used for
  • the set top box can directly output the signal of the frequency band of the channel selected by the user to the television for corresponding playback, without processing the signal of the frequency band of the channel selected by the user after receiving the control command. And then output to the TV for corresponding playback, which helps to improve the speed of signal processing, thereby improving the user experience.
  • the full-band receiver in the embodiment of the present application can synchronously receive a TV signal of more than 16 channels (50 MHz to 1008 MHz), so that the signal bandwidth that the set-top box can process is close to 1 Gbps.
  • the full-band receiver of the embodiment of the present application can dynamically adjust the amplitude of the RF signal, and can use the low-pass filter to suppress the spurious signal of the ADC, thereby helping to reduce the dynamic range requirement of the ADC, usually In case of this, it can be reduced by 5dB to 8dB.
  • the embodiment of the present application also provides a possible television tuner.
  • the TV tuner includes a full-band receiver and a demodulator demod.
  • the full-band receiver includes a single-turn dual circuit, a resistance-attenuation network, a differential amplifier, a filter, and an ADC, and the gain of the resistance-attenuation network and the gain of the differential amplifier are adjustable.
  • the single-turn dual circuit is used to convert the television signal into a first differential signal and input the first differential signal to a resistance attenuation network.
  • the resistance attenuation network is configured to attenuate the first differential signal to obtain a second differential signal, and input the second differential signal to the differential amplifier.
  • the differential amplifier is used to amplify the second differential signal, and the amplified second differential signal is input to the filter; the filter is used to filter the amplified second differential signal to obtain a third differential signal, and the third The differential signal is input to the ADC.
  • the ADC is used for analog-to-digital conversion of the third differential signal to obtain a digital signal and input the digital signal to demod. Demod is used to demodulate digital signals.
  • At least one gain adjustment mode is pre-configured in the demod, wherein each gain adjustment mode corresponds to the adjustment of the amplitude of a signal, and a signal
  • the amplitude adjustment method corresponds to a combination of the gain of the resistance attenuation network and the gain of the differential amplifier.
  • the demod may select a gain adjustment mode from the pre-configured at least one gain adjustment mode according to the amplitude of the signal demodulated by the digital signal, and adjust the gain of the resistance attenuation network and the gain of the differential amplifier accordingly.
  • each of the gain adjustment modes pre-configured in the demod can pre-determine the manner in which the resistance of the resistor is attenuated in the network and the manner in which the resistor in the differential amplifier is adjusted. Then, the demod can be solved according to the digital signal.
  • the resistor attenuates the gain of the network and the purpose of the gain of the differential amplifier.
  • the pre-configured at least one gain adjustment mode may be configured in a form in a demod.
  • demod is pre-configured with gain adjustment modes F1, F2, F3, and F4, where the gain corresponding to F1 is A1, the gain corresponding to F2 is A2, the gain corresponding to F3 is A3, and the gain corresponding to F4 is A4.
  • the gain adjustment mode F1 specifies that the resistors R1, R2, R3, R4, R5, and R6 in the resistance attenuation network shown in FIG. 6 are respectively adjusted to S1, S2, and S3, S4, S5 and S6, the resistors Rin1, Rin2, Rf1 and Rf2 in the differential amplifier shown in Fig. 8 are adjusted to L1, L2, L3 and L6, respectively.
  • the gain adjustment mode set in the current demod is F1.
  • demod can directly select F4.
  • the gain of the resistor attenuation network and the gain of the differential amplifier are combined to be the gain A4.
  • the gain A4 corresponding to the gains A1 and F4 corresponding to F1 differs greatly, in order to prevent the demod from directly adjusting the gain adjustment mode from F1 to F4, the signal played on the television is garbled.
  • demod can first adjust F1 to F2, then adjust from F2 to F3, and adjust from F3 to F4.
  • demod can first adjust F1 to F3 and then from F3 to F4.
  • the embodiment of the present application does not limit how to adjust the currently set adjustment gain mode to the gain adjustment mode that needs to be set.
  • the embodiment of the present application may also set a control module, such as a power controller, etc., in the TV tuner.
  • a control module such as a power controller, etc.
  • the gain of the resistor attenuation network and the gain of the differential amplifier are adjusted by the amplitude of the signal from the differential amplifier received by the power controller.
  • control module adjusts the gain of the resistor attenuation network and the gain of the differential amplifier is similar to the manner in which the demod adjusts the gain of the resistor attenuation network and the gain of the differential amplifier, and will not be described herein.
  • the resistance attenuation network may be a ⁇ -type resistance attenuation network (which may be simply referred to as an R- ⁇ attenuation network), the differential amplifier may be an LNA, and the filter may be a low-pass filter. (low pass filter, LPF).
  • LPF low pass filter
  • FIG. 11 a schematic structural diagram of a possible television tuner.
  • the television tuner shown in Figure 11 includes a full band receiver and demod.
  • the full-band receiver includes single-turn dual-circuit (S2D), R- ⁇ attenuation network, LNA, LPF, and ADC.
  • the specific implementation manners of the single-turn dual circuit, the resistance attenuation network, and the differential amplifier included in the full-band receiver included in the television tuner of the embodiment of the present application can be referred to the full-band reception shown in FIG. 2 correspondingly.
  • the specific implementation of the single-turn dual circuit, the resistor attenuation network and the differential amplifier in the machine will not be described here.
  • a full-band receiver can include fewer devices, and can include more devices.
  • a full-band receiver may include only a single-turn dual circuit, a resistive attenuation network, and a differential amplifier, in which case the television tuner includes a full-band receiver, LPF, ADC, and demod.
  • a full-band receiver may also include a single-turn dual circuit, a resistive attenuation network, a differential amplifier, a low noise amplifier, an LPF, and an ADC, in which case the television tuner includes a full-band receiver and demod.
  • the full-band receiver and demod are integrated in On the same chip.
  • the resistor attenuation network included in the full-band receiver and the differential amplifier, filter, ADC, and demod are integrated on the same chip.
  • the differential amplifier, filter, ADC, and demod included in the full-band receiver are integrated on the same chip.
  • the full-band receiver of the embodiment of the present application may further include a programmable gain amplifier (PGA).
  • PGA programmable gain amplifier
  • the full-band receiver includes a single-turn dual circuit, a resistor-attenuation network, a differential amplifier, a PGA, a filter, and an ADC
  • the PGA and the filter in the full-band receiver of the embodiment of the present application may be selected.
  • the ADC and the demod are integrated on the same chip, and the resistor attenuation network and the differential amplifier, the PGA, the filter, the ADC and the demod in the full-band receiver of the embodiment of the present application can be integrated on the same chip, and the present invention can also be used.
  • the full-band receiver of the application embodiment includes a differential amplifier, a PGA, a filter, an ADC, and a demol integrated on the same chip, which is not limited in this embodiment.
  • FIG. 12 is a schematic structural diagram of another television tuner provided by an embodiment of the present application, including a full-band receiver, at least two mixing receivers, and a demodulator, wherein at least two mixing receivers are included.
  • Each of the mixing receivers is configured to amplify, convert, filter, and analog-to-digitally process the signal obtained by processing the full-band receiver, and input the processed signal to the demodulator; the demodulator is used to At least two mixing receivers respectively process the obtained signals for demodulation.
  • the above technical solutions help to improve the anti-interference performance.
  • the mixing receiver in the embodiment of the present application may include an amplifier, a mixer, a filter, and an ADC.
  • the embodiment of the present application does not limit the connection sequence between the amplifier, the mixer, the filter, and the ADC.
  • the mixing receiver of the embodiment of the present application is as shown in FIG.
  • differential amplifier in the embodiment of the present application can also be used as a PGA.
  • the filter involved in the embodiment of the present application is usually a low-pass filter, but the embodiment of the present application does not limit this.

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Abstract

一种全频带接收机和电视调谐器，涉及信号处理技术领域，其中全频带接收机包括将电视信号转换为第一差分信号的单转双电路、用于对第一差分信号进行衰减的电阻衰减网络，和用于对第二差分信号进行放大的差分放大器，且电阻衰减网络的增益和差分放大器的增益是可调的。通过上述技术方案有助于提高电路的抗干扰性能和线性度，从而提高全频带接收机可处理的信号带宽。

Description

一种全频带接收机和电视调谐器 技术领域
本申请涉及电视技术领域，特别涉及一种全频带接收机和电视调谐器。
背景技术
电视调谐器(television tuner，TV tuner)是机顶盒中的重要器件，能够完成对电视的射频信号的放大、滤波、模数转换、解调等过程。在TV tuner对电视的射频信号进行处理的过程中，若存在干扰过大、线性度较差或者信号失真等问题，则容易导致接收的图像和伴音质量变差。
目前，机顶盒中的电视调谐器主要包括窄带接收机和解调器(demod)。通常情况下，现有的窄带接收机包括低噪放大器(low noise amplifier，LNA)、混频器(mixer)、低通滤波器(low pass filter，LPF)、可变增益放大器(variable gain amplifier，VGA)和模数转换器(analog-to-digital converter，ADC)。而考虑到电视调谐器的成本和体积问题，一般采用互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺。基于现有的CMOS工艺的限制，当LNA处理的信号带宽过大，线性度的要求过高时，现有的基于CMOS工艺的窄带接收机中的LNA则无法达到上述要求。因此现有技术中为了保证较高的图像和伴音质量，LNA处理的为窄带的射频信号。在具体实现过程中常见的方式在机顶盒中设置一个分频网络，如图1a。机顶盒中的天线在接收到全频带的电视的射频信号后，通过分频网络，得到的低频段信号(50MHz-407MHz)和高频段(407MHz-1008MHz)信号。然后分别将低频段信号和高频段信号分别输入到对应的LNA中，进而实现信号的变频和解调。或者，如图1b，在LNA的前端设置频率跟随滤波器(tracking filter)。通过频率跟随滤波器，从天线接收到的全频带的电视的射频信号中筛选出用户选择的频带所在的频段的窄带的电视的射频信号。然后，发送给LNA等进行后续的信号处理。目前，通常情况下窄带接收机中包括的mixer、LPF、VGA和ADC等是采用CMOS工艺实现的，这种采用非COMS工艺实现的LNA由于跟窄带接收器中的其它器件(如mixer等)工艺不兼容，导致需要片外实现，成本过高。
上述电视调谐器在仅处理电视信号的情况下，能够满足用户对于电视节目观看的需求。然而，随着将视频点播、互联网、互动游戏和社交网络等应用到电视领域，上述电视调谐器受窄带接收机的限制，无法处理较大带宽的信号。而且，电视调谐器是在用户选择需要播放的频道后才能对射频信号进行处理，因此信号处理速度相对较慢。为了满足用户对于不同业务的需求，对于电视调谐器的信号处理能力(如带宽、信号处理速度等)如提出的了更高的要求。
发明内容
本申请实施例提供了一种全频带接收机和电视调谐器，有助于提高电路的抗干扰性能和线性度，进而提高对信号的处理能力。
第一方面，本申请实施例提供的全频带接收机包括：单转双电路、电阻衰减网络和差分放大器，且所述电阻衰减网络的增益和所述差分放大器的增益是可调的；其中，所述单转双电路用于将电视信号转换为第一差分信号，并将所述第一差分信号输入到所述电阻衰 减网络；所述电阻衰减网络用于对所述第一差分信号进行衰减，得到第二差分信号，并将所述第二差分信号输入到所述差分放大器；所述差分放大器用于对所述第二差分信号进行放大。
本申请实施例中由于全频带接收机为差分结构，通过将电视信号转换为差分信号进行处理，有助于提高电路的抗干扰性能和偶数阶的线性度。从而当机顶盒采用本申请实施例的全频带接收机来接收整个频段上的电视信号并进行处理时，由于将电视信号转换为差分信号进行处理，能够降低处理过程中信号之间的相互干扰，进而有助于避免各个频道上的信号失真，能够向电视输出图像和伴音质量较高的信号。
在一种可能的设计中，所述单转双电路为片上无源巴伦，或者，所述单转双电路为有源巴伦。通过上述技术方案，有助于简化单转双电路的实现方式。
在一种可能的设计中，所述片上无源巴伦包括第一线圈、第二线圈、第一电容和第二电容，其中所述第一线圈与所述第一电容并联，所述第二线圈与所述第二电容并联，所述第一线圈与所述第一电容并联的一端用于接收所述射频信号，所述第一线圈与所述第一电容并联的另一端接地，所述第二线圈与所述第二电容并联的一端为所述片上无源巴伦的一个输出端、与所述电阻衰减网络的一个输入端连接，所述第二线圈与所述第二电容并联的另一端为所述片上无源巴伦的另一个输出端、与所述电阻衰减网络的另一个输入端连接。
在一种可能的设计中，所述电阻衰减网络为π型电阻衰减网络。其中，所述π型电阻衰减网络中包括的电阻的阻值是可调的，用于调整所述π型电阻衰减网络的增益。
在一种可能的设计中，所述电阻衰减网络包括第一部分和第二部分；所述电阻衰减网络的第一部分用于对所述第一路信号进行相应的衰减，得到所述第三路信号；所述电阻衰减网络的第二部分用于对所述第二路信号进行相应的衰减，得到第四路信号；其中，所述第一路信号和所述第二路信号构成所述第一差分信号；所述第三路信号和所述第四路信号构成所述第二差分信号；所述第一部分的第一端为所述电阻衰减网络的一个输入端，且所述第一部分的第一端与所述单转双电路的一个输出端连接，所述第二部分的第一端为所述电阻衰减网络的另一个输入端，且所述第二部分的第一端与所述单转双电路的另一个输出端连接；所述第一部分的第二端为所述电阻衰减网络的一个输出端，且所述第一部分的第二端与所述差分放大器的一个输入端连接；所述第二部分的第二端为所述电阻衰减网络的另一个输出端，且所述第二部分的第二端与所述差分放大器的另一个输入端连接；所述第一部分的第三端、第四端以及所述第二部分的第三端和第四端分别与节点VSS连接；所述节点VSS为电容的一端，所述电容的另一端与地连接；或者，所述节点VSS的电压为0。
在一种可能的设计中，所述差分放大器的闭环带宽是可调的。通过调节所述差分放大器的闭环带宽，有助于提高差分放大器的稳定性。
在一种可能的设计中，所述差分放大器包括第一输入电阻、第一反馈电容、第一反馈电阻、第二输入电阻、第二反馈电容、第二反馈电阻、第一级运算放大器、可调电容和第二级运算放大器；且所述第一反馈电容的电容值、所述第二反馈电容的电容值和所述可调电容的电容值是可调的，用于调整所述差分放大器的闭环带宽；所述第一输入电阻的阻值、所述第一反馈电阻的阻值、所述第二输入电阻的阻值和所述第二反馈电阻的阻值是可调的，用于调整所述差分放大器的增益；
其中，所述第一输入电阻的一端为所述差分放大器的一个输入端，且所述第一输入电阻的一端与所述电阻衰减网络的一个输出端连接，所述第一输入电阻的另一端分别与第一 并联电路的一端、以及所述第一级运算放大器的正相输入端连接，所述第一并联电路为所述第一反馈电容和所述第一反馈电阻组成的并联电路；所述第一级运算放大器的负相输出端分别与所述可调电容的一端、所述第二级运算放大器的正相输入端连接；所述第二级运算放大器的正相输出端与所述第一并联电路的另一端连接；所述第二输入电阻的一端为所述差分放大器的另一个输入端，且所述第二输入电阻的一端与所述电阻衰减网络的另一输出端连接，所述第二输入电阻的另一端分别与第二并联电路的一端、以及所述第一级运算放大器的负相输入端连接，所述第二并联电路为所述第二反馈电容和所述第二反馈电阻组成的并联电路；所述第一级运算放大器的正相输出端分别与所述可调电容的另一端、所述第二级运算放大器的负相输入端连接；所述第二级运算放大器的负相输出端与所述第二并联电路的另一端连接；所述第二放大器，还用于根据所述第二差分信号的带宽大小，调整所述第一反馈电容的大小、所述第二反馈电容的大小和所述可调电容的大小。
在一种可能的设计中，所述全频带接收机还包括：滤波器和ADC。其中，所述滤波器用于对放大后的所述第二差分信号进行滤波，得到第三差分信号，并将所述第三差分信号输入到所述ADC；所述ADC用于对所述第三差分信号进行模数转换，得到数字信号。
在一种可能的设计中，所述全频带接收机集成在一个芯片上。或者，所述全频带接收机中包括的所述电阻衰减网络和所述差分放大器集成在一个芯片上。
第二方面，本申请实施例的电视调谐器，包括全频带接收机和demod，其中，所述全频带接收机包括单转双电路、电阻衰减网络、差分放大器、滤波器和ADC；且所述电阻衰减网络的增益和所述差分放大器的增益是可调的；所述单转双电路用于将电视信号转换为第一差分信号，并将所述第一差分信号输入到所述电阻衰减网络；所述电阻衰减网络对所述第一差分信号进行衰减，得到第二差分信号，并将所述第二差分信号输入到所述差分放大器；所述差分放大器用于对所述第二差分信号进行放大，并将放大后的所述第二差分信号输入到所述滤波器；所述滤波器用于对放大后的所述第二差分信号进行滤波，得到第三差分信号，并将所述第三差分信号输入到所述ADC；所述ADC用于对所述第三差分信号进行模数转换，得到数字信号，并将所述数字信号输入到所述demod；所述demod用于对所述数字信号进行解调。
需要说明的是，本申请实施例中电视调谐器所包括的全频带接收机中包括的单转双电路、电阻衰减网络和差分放大器的具体实现方式相应的可参见第一方面中全频带接收机中包括的单转双电路、电阻衰减网络和差分放大器的具体实现方式，在此不再赘述。
在一种可能的设计中，所述全频带接收机和所述demod集成在一个芯片上；或者，所述全频带接收机中的电阻衰减网络、差分放大器、滤波器、以及模数转换器ADC、和所述demod集成在一个芯片上。
此外，在全频带接收机包括单转双电路、电阻衰减网络、差分放大器、可编程增益放大器、滤波器和ADC的情况下，可选的，所述全频带接收机中的可编程增益放大器、所述滤波器以及所述ADC、和所述demod集成在一个芯片上；再可选的，全频带接收机包括单转双电路、电阻衰减网络、差分放大器、可编程增益放大器、滤波器、ADC和demod集成在一个芯片上；再可选的，全频带接收机包括电阻衰减网络、差分放大器、可编程增益放大器、滤波器、ADC和demod集成在一个芯片上，本申请实施例对此不作限定。
在一种可能的设计中，所述demod还用于根据对所述数字信号解调后信号的幅度，从预设的第一增益调节方式表中选择一个增益调节方式，调整所述电阻衰减网络的增益和所 述差分放大器的增益。
在一种可能的设计中，所述demod还用于根据对所述数字信号解调后信号的带宽，调整所述差分放大器的闭环带宽。
第三方面，本申请实施例的电视调谐器，包括全频带接收机、和至少两个混频接收器、解调器；其中所述全频带接收机包括单转双电路、电阻衰减网络和差分放大器，所述至少两个混频接收器中每个混频接收器用于对通过所述全频带接收机处理后得到的信号进行放大、变频、滤波和模数转换处理，并将所述处理后得到的信号输入到所述demod；所述demod用于对经过所述至少两个混频接收器分别处理得到的信号，进行解调。
需要说明的是，本申请实施例中电视调谐器所包括的全频带接收机中包括的单转双电路、电阻衰减网络和差分放大器的具体实现方式相应的可参见第一方面中全频带接收机中包括的单转双电路、电阻衰减网络和差分放大器的具体实现方式，在此不再赘述。
在一种可能的设计中，所述至少两个混频接收器中每个混频接收器包括放大器、混频器、滤波器和ADC。需要说明的是，本申请实施例中对混频接收器包括的放大器、混频器、滤波器和ADC之间的连接顺序不作限定。
附图说明
图1a和图1b分别为传统的TV tuner的架构示意图；
图2为本申请实施例涉及的一种全频带接收机的架构示意图；
图3为本申请实施例涉及的用封装走线或者片上金属线实现的巴伦的示意图；
图4a～图4c分别为本申请实施例无源巴伦的一种可能的结构示意图；
图5a和图5b分别为本申请实施例有源巴伦的一种可能的结构示意图；
图6为本申请实施例电阻衰减网络的一种可能的结构示意图；
图7a～图7c分别为本申请实施例VSS实现的具体示意图；
图8为本申请实施例差分放大器的一种可能的结构示意图；
图9为本申请实施例的差分放大器的又一种可能的结构示意图；
图10为本申请实施例的全频带接收机一种可能的结构示意图；
图11为本申请实施例电视调谐器的一种结构示意图；
图12为本申请实施例电视调谐器的又一种结构示意图；
图13为本申请实施例混频接收器的一种可能的结构示意图。
具体实施方式
下面结合说明书附图对本申请实施例进行详细说明。
如图2所示，为一种全频带接收机的结构示意图，包括单转双电路、电阻衰减网络和差分放大器，且电阻衰减网络的增益和差分放大器的增益是可调的。其中，单转双电路用于将电视信号转换为第一差分信号，并将第一差分信号输入到电阻衰减网络。电阻衰减网络用于对第一差分信号进行衰减，得到第二差分信号，并将第二差分信号输入到差分放大器。差分放大器用于对第二差分信号进行放大。
需要说明的是，本申请实施例中涉及到的电视信号为射频信号，例如卫星电视信号、地面电视信号、闭路电视信号等。具体的，卫星电视信号指的是由卫星发射的电视信号。地面电视信号指的是由地面电视塔发射的电视信号。闭路电视信号指的是通过导线传送的 电视信号，如大楼内的安装的摄像头向监视器发送的信号为闭路电视信号。
本申请实施例中，由于全频带接收机为差分结构，通过将电视信号转换为差分信号进行处理，有助于提高电路的抗干扰性能和偶数阶的线性度，从而当机顶盒采用如图2所示的全频带接收机来接收整个频段上的电视信号并进行处理时，由于将电视信号转换为差分信号进行处理，能够降低处理过程中信号之间的相互干扰，进而有助于避免各个频道上的信号失真，能够向电视输出图像和伴音质量较高的信号。
在具体实现时，可选的，本申请实施例的单转双电路与电阻衰减网络的阻抗匹配。示例的，本申请实施例中的单转双电路(single ended to double ended，简称S2D)可以为无源巴伦、无源片上巴伦或者有源巴伦。
应理解，巴伦(balun)是一种能够实现单端和差分相互转换的器件，而无源巴伦指的是实现单端和双端相互转换的无源器件，可以不集成在片上，也可以集成在片上或者用封装走线实现。当无源巴伦集成在片上时，无源巴伦还可以称之为无源片上巴伦，其中具体实现形式包括并行绕线、交叉绕线、堆叠绕线、对称巴伦等，如图3所示的封装走线实现方式为对称巴伦。此外，通过封装走线也可以实现与片上巴伦相同的巴伦。
可选的，一种无源巴伦的电路结构可以如图4a所示，包括第一线圈L1和第二线圈L2。可选的，无源巴伦的结构还可以如图4b所示，包括第一线圈L1、第二线圈L2、第一电容C1和第二电容C2，其中L1和C1并联，L2与C2并联。需要说明的是，C1和C2可以为固定电容值的电容，也可以为电容值可调的电容，本申请实施例对此不作限定。具体的，L1与C1并联的一端为一个输入端，用于接收射频信号。L1与C1并联的另一端为一个输出端，用于与电阻衰减网络的一个输入端连接。L2与C2并联的一端为另一个输入端，用于接地。L2与C2并联的另一端为另一个输出端，用于与电阻衰减网络的另一个输入端连接。可选的，无源巴伦的结构还可以如图4c所示，包括第一线圈L1、第二线圈L2、第一电容C1和第二电容C2，其中，L1和C1并联，L2和C2并联；需要说明的是，C1和C2可以为固定电容值的电容，也可以为电容值可调的电容，本申请实施例对此不作限定。具体的L1与C1并联的一端为一个输入端，用于接收射频信号。L1与C1并联的另一端为另一个输入端，用于接地。L2与C2并联的一端为另一个输出端，用于与电阻衰减网络的一个输入端连接。L2与C2并联的另一端为另一个输出端，用于与电阻衰减网络的另一个输入端连接。
此外，当本申请实施例中的单转双电路采用有源巴伦时，一种可能的有源巴伦的电路结构可以如图5a所示，包括金属-氧化物-半导体(metal oxide semiconductor，MOS)管MOS管M1、MOS管M2、MOS管M3、MOS管M4、电容C1、电容C2、电阻R1、电阻R2、电流源I0，其中M1满足输入匹配条件Rin＝1/gm1，gm1为M1的跨导。具体的，输入信号Vx通过M1放大后变为第一电流信号，第一电流信号通过M3后得到输出电压Vo+，类似的方式，Vx信号在通过M1后得到电压Vy，Vy通过M2放大后得到第二电流信号，第二电流信号通过M4后得到输出电压Vo-，通过配置合适的M1、M2、M3和M4器件尺寸和偏置电流，以及R1和R2的值，可以使得得到的Vo+与Vo-大小相同方向相反，从而通过如图5a所示的电路结构实现了单端信号转换为差分信号。
如图5b所示，为另一种可能的有源巴伦的电路结构示意图，包括电阻R1、电阻R2、运算放大器A1、运算放大器A2和运算放大器A3，输入信号通过器A1实现信号反向，得到第二信号，第二信号分别通过A2和A3得到Vo+和Vo-，其中Vo+与Vo-大小相同方向相反，由于图5b所示的电路结构中A2和A3为交叉耦合结构，有助于提高输出信号的差分特性，另外 由于要满足宽带匹配，阻抗部分需要满足在全频带内输入反射系数需要小于-8dBm。
此外，本申请实施例中电阻衰减网络又可称之为电阻衰减电路。例如，电阻衰减网络可以为T型电阻衰减网络，还可以为π型电阻衰减网络等，对此不作限定。
如图6所示，为一种可能的π型电阻衰减网络的示意图，包括可调电阻R1、可调电阻R2、可调电阻R3、可调电阻R4、可调电阻R5和可调电阻R6。其中R1、R2和R3组成第一部分，R4、R5、R6组成第二部分，第一部分的第一端A1与单转双电路的输出端P1连接，第二部分的第一端A2与单转双电路的输出端P2连接，第一部分的第二端B1与差分放大器的输入端Q1连接，第二部分的第二端B2与差分放大器的输入端Q2连接，第一部分的第三端C1、第四端D1以及第二部分的第三端C2、第四端D2分别与节点VSS连接。
其中，第一部分用于对第一路信号进行相应的衰减，得到第三路信号。第二部分用于对第二路信号进行相应的衰减，得到第四路信号。应理解，在本申请实施例中由第一路信号和第二路信号组成第一差分信号，由第三路信号和第四路信号组成第二差分信号。
由于单转双电路的非理想特性，在单转双电路输出的第一差分信号中的两路信号分别经过电阻衰减网络后，有可能得到的第三路信号和第四路信号不能满足大小相等、相位相相差180度的要求，得不到具有差分特性的信号。而且，当电阻衰减网络的信号衰减增益变大时，差分信号的幅度和增益与理想差分信号的偏差会进一步增大。因此，为了提高第二差分信号的差分特性，可选的，节点VSS的一端为电容的一端，电容的另一端与地连接；或者，节点VSS的电压为0。
本申请实施例中由于电阻衰减网络的增益和差分放大器的增益是可调的，因而有助于提高动态调整信号的幅度的范围。例如，电阻衰减网络的增益可以调节为A1、A2和A3，差分放大器的增益可以调节为B1、B2和B3，则可以由电阻衰减网络和差分放大器组合成最多九个调整信号的幅度的增益。因此，电阻衰减网络的增益可以调节范围和差分放大器的可调范围越大，则动态调整信号的幅度的范围也就有可能越大。示例的，以信号为电压信号为例，信号的幅度可以指的是信号的电压值。
例如，当第一差分信号的幅度为K1时，若电阻衰减网络的增益为-0.25、差分放大器的增益为2，则第一差分信号经过电阻衰减网络、差分放大器放大后得到的信号的幅度为K1/2。当第一差分信号的幅度为K1时，若电阻衰减网络的增益为-0.5、差分放大器的增益为6，则第一差分信号经过电阻衰减网络、差分放大器放大后得到的信号的幅度为3K1。
一种可能的示例，对于电阻衰减网络和差分放大器来说，可以通过调整电阻衰减网络中包括的电阻的阻值调整电阻衰减网络的增益，以及通过调整差分放大器中包括的电阻的阻值来调整差分放大器的增益。
以图6所示的电阻衰减网路为例，电阻R1、R2、R3、R4、R5和R6分别可以为可调电阻，也可以为一个电阻组，例如电阻R1是有一个或多个电阻并联和/或串联，通过MOS开关控制电阻R1中多个电阻的连接方式，从而使得电阻R1的电阻值是可调的。示例的，在全频带差分放大器应用于电视调谐器的情况下，可以通过demod实现对电阻衰减网络的增益和差分放大器的增益的调整，或者通过控制模块实现对电阻衰减网络的增益和差分放大器的增益的调整。具体的调整方式可以参见对本申请实施例中的电视调谐器进行介绍时，对电阻衰减网络的增益和差分放大器的增益的调整方式，在此不再赘述。
此外，一种示例中，当图6所示的电阻衰减网络中的电阻由MOS开关控制时，在如图7a所示的节点VSS与电容的一端连接，电容的另一端与地连接的情况下，则将MOS开关的 衬底接地，以及将MOS开关的栅氧电压置为VDD1。另外一种示例中，在如图7b所示节点VSS与地连接的情况下，则将MOS开关的衬底与一个负电压连接，MOS开关的栅氧电压置为VDD2。还有一种示例中，在如图7c所示的节点VSS通过第一开关K1与电容的一端连接，电容的另一端与地连接，节点VSS通过第二开关K2与地连接时，若第一开关K1闭合，第二开关K2断开，则MOS开关的栅氧电压为VDD1、衬底电压为0；若第一开关K1断开，第二开关K2闭合，则MOS开关的衬底与一个负电压连接，MOS开关的栅氧电压置为VDD2。
在本申请实施例中，一种可能的示例中，差分放大器可以为LNA。由于本申请实施例中的全频带接收机采用的差分结构，因此受差分信号具有信号的幅度大小相等、相位相差180度的特性的影响，偶数阶的非线性特性很好，本申请实施例全频带接收机在反馈上采用的电阻反馈结构，增益由电阻提供，其线性度较好，因此本申请实施例中采用的差分放大器可以为CMOS工艺的低噪差分放大器，有助于降低成本。
示例的，如图8所示，为一种可能的差分放大器的结构示意图。其中，如图8所示的差分放大器包括第一输入电阻Rin1、第一反馈电阻Rf1、第一反馈电容Cf1、第二输入电阻Rin2、第二反馈电阻Rf2、第二反馈电容Cf2、第一运算放大器A1和第二级运算放大器A2。通常情况下，为了保证图8所示的差分放大器输出的信号为差分信号，Rf1和Rf2的大小相等，Cf1和Cf2的大小相等。
由于图8所示的差分放大器采用了电阻的大环反馈技术，信号的增益满足表达式(1)：
Figure PCTCN2018078752-appb-000001
其中，Gain表示信号的增益；Rf表示反馈电阻的大小；Rin表示输入电阻Rin的大小，A表示差分放大器的开环增益。通过表达式(1)可以看出，差分放大器的信号的增益并不随温度、工艺、电源电压等的变化而变化，只与输入电阻和反馈电阻的比值有关，因而有助于实现宽带和高线性度。而且，由于本申请实施例中图8所示的差分放大器中包括两级运算放大器，第一级放大器用于对信号进行放大，第二级放大器用于提供驱动能力，有助于实现驱动大负载，本申请实施例全频带接收机采用了全差分结构，有利于提高电路的抗干扰性。
以图8所示的差分放大器为例，可以通过调节Rin1、Rin2、Rf1和Rf2的阻值，来调整差分放大器的增益。因此，在上述情况下，差分放大器的增益的可调范围与电阻Rin1、Rin2、Rf1和Rf2的阻值的可调节范围相关，在电阻Rin1、Rin2、Rf1和Rf2的可调节范围越大的情况下，差分放大器的增益的可调范围越大。
由于如图8所示的差分放大器在采用的信号放大增益较小时，有可能导致闭环不稳定，这是由于通常情况下开环反馈放大器的增益带宽积是固定不变的，而开环运放的增益带宽积GBW同时也满足下列表达式(2)：
GBW＝Gain×BW；          (2)
其中，GBW表示增益带宽积；Gain表示信号的放大增益，即闭环增益；BW表示闭环带宽。
从表达式(2)中可以看出，在增益带宽积不变、信号的放大增益变小的情况下，差分放大器能够处理的信号的带宽变大，因而容易导致闭环的不稳定。然而，在实际信号处理过程中，由于电视整个频段的信号带宽通常情况下是不变的，而差分放大器在信号的放大增益变小的情况下，能够处理的信号的带宽超过电视整个频段的带宽对于电阻反馈放大 器来说是无意义的。为了解决上述问题，可选的，本申请实施例中的差分放大器的闭环带宽是可调的。一种可能的示例为，在信号的放大增益较小的情况下，为了提高闭环的稳定性，通过调整差分放大器中的电容的容值，来减小差分放大器能够处理的信号的带宽的大小。以图8所示的差分放大器为例，可以通过调整差分放大器中的Cf1和Cf2的容值，来减小差分放大器能够处理的信号的带宽的大小。当全频带接收器应用于电视调谐器时，一种可能的实现方式为，通过电视调谐器中包括的解调器(demod)根据解调后的信号的带宽，来调整差分放大器的闭环带宽。以图8所示的差分放大器为例，在demod解调后的信号的带宽大于电视整个频段的带宽的情况下，调整Cf1和Cf2的容值，从而实现对差分放大器的闭环带宽的调整。
进一步的，还可以通过在如图8所示的差分放大器中的第一级运算放大器A1和第二级运算放大器之间设置可调电容CL。具体的差分放大器的结构可以如图9所示。其中，Rin1的一端为差分放大器的一个输入端、与电阻衰减网络的一个输出端连接，Rin1的另一端分别与第一并联电路的一端、以及A1的正相输入端连接，第一并联电路为Cf1和Rf1组成的并联电路；A1的负相输出端分别与CL的一端、A2的正相输入端连接；A2的正相输出端与第一并联电路的另一端连接；Rin2的一端为差分放大器的另一个输入端、与电阻衰减网络的另一输出端连接，Rin2的另一端分别与第二并联电路的一端、以及A1的负相输入端连接，第二并联电路为Cf2和Rf2组成的并联电路；A1的正相输出端分别与CL的另一端、A2的负相输入端连接；A2的负相输出端与第二并联电路的另一端连接。在信号的放大增益较小的情况下，为了提高闭环的稳定性差分放大器可以根据第二差分信号的带宽大小，调整Cf1、Cf2和CL的容值，来减小差分放大器能够处理的信号的带宽的大小。
另外，需要说明的是，全差分接收机还可以包括隔直电容。一种可能的实施方式中，单转双电路输出的第一差分信号在通过隔直电容滤除直流信号后，输入到电阻衰减网络。示例的，如图10所示，为一种可能的全差分接收机的结构示意图。其中，如图10所示的全差分接收机包括单转双电路、隔直电容、电阻衰减网络和差分放大器。具体的，单转双电路包括线圈L1和线圈L2，电阻衰减网络包括可调电阻R1、可调电阻R2、可调电阻R3、可调电阻R4、可调电阻R5和可调电阻R6，差分放大器包括第一输入电阻Rin1、第一反馈电阻Rf1、第一反馈电容Cf1、第二输入电阻Rin2、第二反馈电阻Rf2、第二反馈电容Cf2、可调电容CL、第一运算放大器A1和第二级运算放大器A2。
还需要说明的是，本申请实施例的全频带接收机包括单转双电路、电阻衰减网络和差分放大器。在具体实现时，可以将单转双电路、电阻衰减网络和差分放大器集成在一个芯片上，或者，将电阻衰减网络和差分放大器集成在一个芯片上。
应理解，本申请实施例中全频带接收机不仅限于包括单转双电路、电阻衰减网络和差分放大器。示例的，全频带接收机还可以包括滤波器、ADC和可编程增益放大器(programmable gain amplifier，PGA)等。例如，全频带接收机包括单转双电路、电阻衰减网络、差分放大器、滤波器和ADC。具体的，滤波器用于对放大后的第二差分信号进行滤波，得到第三差分信号，并将第三差分信号输入到ADC；ADC用于对第三差分信号进行模数转换，得到数字信号。可选的，单转双电路、电阻衰减网络、差分放大器、滤波器和ADC可以集成在一个芯片上，也可以将电阻衰减网络、差分放大器、滤波器和ADC集成在一个芯片上。
由于本申请实施例中的全频带接收机包括单转双电路、电阻衰减网络和差分放大器， 因而将本申请实施例中的全频带接收机应用于机顶盒等信号接收终端中时，可以直接对信号接收终端中天线接收到的电视信号进行处理，而无需事先对射频信号进行窄带处理。此外，本申请实施例中的全频带接收机对射频信号进行处理的过程与用户选择的频道的信号无关，在机顶盒接收到控制器(如遥控器)发送的控制指令后，其中控制指令用于指示用户选择的频道所在的频段，则机顶盒可以直接将用户选择的频道所在频段的信号输出给电视进行相应的播放，而无需在接收到控制指令后，对用户选择的频道所在频段的信号进行处理，然后再输出给电视进行相应的播放，有助于提高信号处理的速度，从而提高了用户体验。
具体的，本申请实施例中的全频带接收机可以实现同步接收超过16个频道(50MHz～1008MHz)的电视信号，使机顶盒能够处理的信号带宽接近1Gbps。本申请实施例的全频带接收机可以通过对射频信号的幅度的动态调整，同时可以利用到低通滤波器实现对ADC杂散信号的抑制，有助于降低对ADC的动态范围的要求，通常情况下可以降低5dB～8dB。
本申请实施例还提供了一种可能的电视调谐器。其中，电视调谐器包括全频带接收机和解调器demod。其中，全频带接收机包括单转双电路、电阻衰减网络、差分放大器、滤波器和ADC，且电阻衰减网络的增益和差分放大器的增益是可调的。单转双电路用于将电视信号转换为第一差分信号，并将第一差分信号输入到电阻衰减网络。电阻衰减网络用于对第一差分信号进行衰减，得到第二差分信号，并将第二差分信号输入到差分放大器。差分放大器用于对第二差分信号进行放大，并将放大后的第二差分信号输入到滤波器；滤波器用于对放大后的第二差分信号进行滤波，得到第三差分信号，并将第三差分信号输入到ADC。ADC用于对第三差分信号进行模数转换，得到数字信号，并将数字信号输入到demod。demod用于对数字信号进行解调。
一种可能的调节电阻衰减网络的增益和差分放大器的增益的示例，在demod中预先配置至少一个增益调节方式，其中每个增益调节方式对应一种信号的幅度的调整方式，而一种信号的幅度的调整方式对应一种电阻衰减网络的增益和差分放大器的增益的组合方式。其中，demod可以根据对数字信号解调后的信号的幅度，从预先配置的至少一个增益调节方式中选择一个增益调节方式，对电阻衰减网络的增益和差分放大器的增益进行相应的调整。
以图6所示的电阻衰减网络和图8所示的差分放大器为例。由于图6中所示的电阻衰减网络可以通过调整电阻R1、R2、R3、R4、R5和R6的阻值来调整电阻衰减网络的增益，图8所示的差分放大器中可以通过调整电阻Rin1、Rin2、Rf1和Rf2的阻值来调整差分放大器的大小。因此，在demod中预先配置的至少一个增益调节方式中每个增益调节方式可以预先规定调整电阻衰减网路中电阻的方式和调整差分放大器中的电阻的方式，然后，demod可以根据对数字信号解调后的信号的幅度，来从预先配置的至少一个增益调节方式中选择一个增益调节方式，来调节电阻衰减网络中包括的电阻的阻值和差分放大器中包括的电阻的阻值，从而达到调节电阻衰减网络的增益和差分放大器的增益的目的。
示例的，预先配置的至少一个增益调节方式可以以表格的形式配置在demod中。
例如，demod中预先配置有增益调节方式F1、F2、F3和F4，其中F1对应的增益为A1，F2对应的增益为A2，F3对应的增益为A3，F4对应的增益为A4。以F1对应的增益为A1为例，增益调节方式F1规定了将如图6所示的电阻衰减网络中的电阻R1、R2、R3、 R 4、R5和R6分别调整为S1、S2、S3、S4、S5和S6，将如图8所示的差分放大器中的电阻Rin1、Rin2、Rf1和Rf2分别调整为L1、L2、L3和L6。若demod确定得到的对数字信号解调后的信号的幅度不满足需求的情况下，例如，假设demod对数字信号解调后的信号的幅度为K1，当前demod中设置的增益调节方式为F1，则在这种情况下，若demod需要选择的增益调节方式为F4，则demod可以直接选择F4，在这种情况下，电阻衰减网络的增益和差分放大器的增益组合后为增益A4。然而，在F1对应的增益A1和F4对应的增益A4若相差较大，为了避免demod直接将增益调节方式从F1调节到F4时，导致电视上播放的信号产生乱码。在具体实现时，可选的，demod可以先将F1调节到F2，然后从F2调节到F3，在从F3调节到F4。或者，demod可以先将F1调节到F3，然后从F3调节到F4。本申请实施例对demod具体如何将当前设置的调节增益方式调节到需要设置的增益调节方式上，对此本申请实施例不做限定。
此外，本申请实施例还可以在电视调谐器中设置控制模块，如功率控制器等。通过功率控制器接收到的来自差分放大器的信号的幅度，来调节电阻衰减网络的增益和差分放大器的增益。
其中，控制模块调节电阻衰减网络的增益和差分放大器的增益的方式与demod调节电阻衰减网络的增益和差分放大器的增益的方式类似，在此不再赘述。
在本申请实施例中，一种可能的实施方式中，电阻衰减网络可以为π型电阻衰减网络(可简称为R-π衰减网络)，差分放大器可以为LNA，滤波器可以为低通滤波器(low pass filter，LPF)。示例的，如图11所示为一种可能的电视调谐器的结构示意图。如图11所示的电视调谐器包括全频带接收机和demod。其中全频带接收机包括单转双电路(S2D)、R-π衰减网络、LNA、LPF和ADC。
需要说明的是，本申请实施例电视调谐器中包括的全频带接收机中所包括的单转双电路、电阻衰减网络、差分放大器的具体实现方式相应的可以参见图2所示的全频带接收机中单转双电路、电阻衰减网络和差分放大器的具体实现方式，在此不再赘述。
还需要说明的是，本申请实施例对图11所示的电视调谐器中包括的全频带接收机所包括的器件不做限制。例如，全频带接收机可以包括更少的器件，也可以包括更多的器件。例如，全频带接收机可以只包括单转双电路、电阻衰减网络和差分放大器，在这种情况下，电视调谐器包括全频带接收机、LPF、ADC和demod。再例如，全频带接收机也可以包括单转双电路、电阻衰减网络、差分放大器、低噪放大器、LPF和ADC，在这种情况下，电视调谐器包括全频带接收机和demod。
其中，由于本申请实施例的全频带接收机的具有低噪声、高线性度、宽带和抗干扰的特性，因此为了便于实现，一种可能的实施方式中，将全频带接收机和demod集成在同一个芯片上。另外一种可能的实施方式中，将全频带接收机包括的电阻衰减网络和差分放大器、滤波器、ADC和demod集成在同一个芯片上。又一种可能的实施方式中，将全频带接收机包括的差分放大器、滤波器、ADC和demod集成在同一个芯片上。
一种可能的实施方式中，本申请实施例的全频带接收机还可以包括可编程增益放大器(programmable gain amplifier，PGA)。当全频带接收机包括单转双电路、电阻衰减网络、差分放大器、PGA、滤波器和ADC时，为了便于实现，可选的，可以将本申请实施例的全频带接收机中PGA、滤波器、ADC和demod集成在同一个芯片上，也可以将本申请实施例的全频带接收机中电阻衰减网络和差分放大器、PGA、滤波器、ADC和demod集成在同一 个芯片上，还可以将本申请实施例的全频带接收机包括的差分放大器、PGA、滤波器、ADC和demod集成在同一个芯片上，对此本申请实施例不作限定。
如图12所示，为本申请实施例提供的另一种电视调谐器的结构示意图，包括全频带接收机、至少两个混频接收器和解调器，其中，至少两个混频接收器中每个混频接收器用于对通过全频带接收机处理后得到的信号进行放大、变频、滤波和模数转换处理，并将处理后得到的信号输入到解调器；解调器用于对经过至少两个混频接收器分别处理得到的信号，进行解调。通过上述技术方案有助于提高抗干扰性能。
本申请实施例图12所示的电视调谐器中全频带接收机的具体实现方式可以参见图7所示的全频带接收机的具体实现方式在此不再赘述。
再具体实现时，本申请实施例中混频接收器可以包括放大器、混频器、滤波器和ADC，本申请实施例对放大器、混频器、滤波器和ADC之间的连接顺序不作限定，可选的，本申请实施例的混频接收器如图13所示。
此外，还需要说明的是，本申请实施例中的差分放大器还可以作为PGA使用。
本申请实施例中涉及到的滤波器通常情况下为低通滤波器，但本申请实施例对此不作限定。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种全频带接收机，其特征在于，包括：单转双电路、电阻衰减网络和差分放大器，且所述电阻衰减网络的增益和所述差分放大器的增益是可调的；
    其中，所述单转双电路，用于将电视信号转换为第一差分信号，并将所述第一差分信号输入到所述电阻衰减网络；
    所述电阻衰减网络，用于对所述第一差分信号进行衰减，得到第二差分信号，并将所述第二差分信号输入到所述差分放大器；
    所述差分放大器，用于对所述第二差分信号进行放大。
  2. 如权利要求1所述的全频带接收机，其特征在于，所述单转双电路为片上无源巴伦，或者，所述单转双电路为有源巴伦。
  3. 如权利要求2所述的全频带接收机，其特征在于，所述片上无源巴伦包括第一线圈、第二线圈、第一电容和第二电容，其中所述第一线圈与所述第一电容并联，所述第二线圈与所述第二电容并联，所述第一线圈与所述第一电容并联的一端用于接收所述射频信号，所述第一线圈与所述第一电容并联的另一端接地，所述第二线圈与所述第二电容并联的一端为所述片上无源巴伦的一个输出端、与所述电阻衰减网络的一个输入端连接，所述第二线圈与所述第二电容并联的另一端为所述片上无源巴伦的另一个输出端、与所述电阻衰减网络的另一个输入端连接。
  4. 如权利要求1或2所述的全频带接收机，其特征在于，所述电阻衰减网络为π型电阻衰减网络；其中，所述π型电阻衰减网络中包括的电阻的阻值是可调的，用于调整所述π型电阻衰减网络的增益。
  5. 如权利要求1至4任一所述的全频带接收机，其特征在于，所述电阻衰减网络包括第一部分和第二部分；
    所述电阻衰减网络，用于对所述第一差分信号进行衰减，包括：
    所述电阻衰减网络的第一部分，用于对所述第一路信号进行相应的衰减，得到所述第三路信号；
    所述电阻衰减网络的第二部分，用于对所述第二路信号进行相应的衰减，得到第四路信号；
    其中，所述第一路信号和所述第二路信号构成所述第一差分信号；所述第三路信号和所述第四路信号构成所述第二差分信号；所述第一部分的第一端为所述电阻衰减网络的一个输入端，所述第一部分的第一端与所述单转双电路的一个输出端连接，所述第二部分的第一端为所述电阻衰减网络的另一个输入端，所述第二部分的第一端与所述单转双电路的另一个输出端连接；所述第一部分的第二端为所述电阻衰减网络的一个输出端，所述第一部分的第二端与所述差分放大器的一个输入端连接；所述第二部分的第二端为所述电阻衰减网络的另一个输出端，所述第二部分的第二端与所述差分放大器的另一个输入端连接；所述第一部分的第三端、第四端以及所述第二部分的第三端和第四端分别与节点VSS连接；所述节点VSS为电容的一端，所述电容的另一端与地连接；或者，所述节点VSS的电压为0。
  6. 如权利要求1至5任一所述的全频带接收机，其特征在于，所述差分放大器的闭环带宽是可调的。
  7. 如权利要求6所述的全频带接收机，其特征在于，所述差分放大器包括第一输入 电阻、第一反馈电容、第一反馈电阻、第二输入电阻、第二反馈电容、第二反馈电阻、第一级运算放大器、可调电容和第二级运算放大器；且所述第一反馈电容的电容值、所述第二反馈电容的电容值和所述可调电容的电容值是可调的，用于调整所述差分放大器的闭环带宽；所述第一输入电阻的阻值、所述第一反馈电阻的阻值、所述第二输入电阻的阻值和所述第二反馈电阻的阻值是可调的，用于调整所述差分放大器的增益；
    其中，所述第一输入电阻的一端为所述差分放大器的一个输入端，所述第一输入电阻的一端与所述电阻衰减网络的一个输出端连接，所述第一输入电阻的另一端分别与第一并联电路的一端、以及所述第一级运算放大器的正相输入端连接，所述第一并联电路为所述第一反馈电容和所述第一反馈电阻组成的并联电路；
    所述第一级运算放大器的负相输出端分别与所述可调电容的一端、所述第二级运算放大器的正相输入端连接；
    所述第二级运算放大器的正相输出端与所述第一并联电路的另一端连接；
    所述第二输入电阻的一端为所述差分放大器的另一个输入端，所述第二输入电阻的一端与所述电阻衰减网络的另一输出端连接，所述第二输入电阻的另一端分别与第二并联电路的一端、以及所述第一级运算放大器的负相输入端连接，所述第二并联电路为所述第二反馈电容和所述第二反馈电阻组成的并联电路；
    所述第一级运算放大器的正相输出端分别与所述可调电容的另一端、所述第二级运算放大器的负相输入端连接；
    所述第二级运算放大器的负相输出端与所述第二并联电路的另一端连接。
  8. 如权利要求1至7任一所述的全频带接收机，其特征在于，所述全频带接收机还包括：滤波器和模数转换器ADC；其中，
    所述滤波器，用于对放大后的所述第二差分信号进行滤波，得到第三差分信号，并将所述第三差分信号输入到所述ADC；
    所述ADC，用于对所述第三差分信号进行模数转换，得到数字信号。
  9. 如权利要求1至8任一所述的全频带接收机，其特征在于，所述全频带接收机集成在一个芯片上；或者，所述全频带接收机中包括的所述电阻衰减网络和所述差分放大器集成在一个芯片上。
  10. 一种电视调谐器，其特征在于，包括：全频带接收机和解调器demod；其中，所述全频带接收机包括单转双电路、电阻衰减网络、差分放大器、滤波器和模数转换器ADC；且所述电阻衰减网络的增益和所述差分放大器的增益是可调的；
    所述单转双电路，用于将电视信号转换为第一差分信号，并将所述第一差分信号输入到所述电阻衰减网络；
    所述电阻衰减网络，用于对所述第一差分信号进行衰减，得到第二差分信号，并将所述第二差分信号输入到所述差分放大器；
    所述差分放大器，用于对所述第二差分信号进行放大，并将放大后的所述第二差分信号输入到所述滤波器；
    所述滤波器，用于对放大后的所述第二差分信号进行滤波，得到第三差分信号，并将所述第三差分信号输入到所述ADC；
    所述ADC，用于对所述第三差分信号进行模数转换，得到数字信号，并将所述数字信号输入到所述demod；
    所述demod，用于对所述数字信号进行解调。
  11. 如权利要求10所述的电视调谐器，其特征在于，所述demod还用于：
    根据对所述数字信号解调后信号的幅度，从预设的至少一个增益调节方式中选择一个增益调节方式，调整所述电阻衰减网络的增益和所述差分放大器的增益。
  12. 如权利要求10或11所述的电视调谐器，其特征在于，所述demod还用于：
    根据对所述数字信号解调后信号的带宽，调整所述差分放大器的闭环带宽。
  13. 如权利要求10至12任一所述的电视调谐器，其特征在于，所述全频带接收机和所述demod集成在一个芯片上；或者，所述电阻衰减网络、所述差分放大器、所述滤波器、所述ADC、和所述demod集成在一个芯片上。
  14. 一种电视调谐器，其特征在于，包括：如权利要求1至7任一所述的全频带接收机、和至少两个混频接收器、解调器demod；其中，
    所述至少两个混频接收器中每个混频接收器，用于对通过所述全频带接收机处理后得到的信号进行放大、变频、滤波和模数转换处理，并将所述处理后得到的信号输入到所述demod；
    所述demod，用于对经过所述至少两个混频接收器分别处理得到的信号，进行解调。
  15. 如权利要求14所述的电视调谐器，其特征在于，所述至少两个混频接收器中每个混频接收器包括放大器、混频器、滤波器和模数转换器ADC。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111555998A (zh) * 2020-04-21 2020-08-18 上海航天测控通信研究所 星载原子钟的下变频信号处理方法和变频组件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101170656A (zh) * 2006-10-25 2008-04-30 晨星半导体股份有限公司 电视调谐器
EP2110946A1 (en) * 2008-04-18 2009-10-21 STMicroelectronics (Grenoble) SAS Differential RF amplifier
CN103684274A (zh) * 2012-09-12 2014-03-26 澜起科技（上海）有限公司 具有单端转差分能力和滤波作用的宽带低噪声放大器
CN104994322A (zh) * 2015-06-30 2015-10-21 深圳市九洲电器有限公司 一种电视信号处理的装置和电视机顶盒

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101820508A (zh) * 2009-02-26 2010-09-01 上海融创名睿微电子有限公司 数字移动电视接收机调谐器单端转差分射频前端电路
JP2010288125A (ja) * 2009-06-12 2010-12-24 Alps Electric Co Ltd テレビジョン放送チューナ
CN201674469U (zh) * 2010-03-25 2010-12-15 上海沙丘微电子有限公司 带有自动增益控制的音频功率放大器电路
EP2506443B1 (en) * 2011-03-31 2016-11-30 Nxp B.V. Receiver comprising amplifier with Miller effect feedback
CN203482306U (zh) * 2012-05-10 2014-03-12 硅实验室股份有限公司 使用集成电感器的低成本接收器
CN103501417A (zh) * 2013-09-18 2014-01-08 西安电子工程研究所 一种基于运算放大器的雷达多通道视频接收机
CN105024662A (zh) * 2014-04-16 2015-11-04 清华大学 一种高带外抑制的跨阻放大器
CN104092471B (zh) * 2014-07-04 2016-04-20 三维通信股份有限公司 一种高动态高增益宽带接收机
CN104363025B (zh) * 2014-11-11 2017-10-17 北京旋极星源技术有限公司 一种移动通信中频拉远系统的射频接收芯片及接收机
US10347414B2 (en) * 2015-05-14 2019-07-09 Maxlinear, Inc. Method and system for winding transformers to maximize symmetry of the primary and secondary coils
CN205693639U (zh) * 2016-03-10 2016-11-16 北京联盛德微电子有限责任公司 一种基于前馈与弱正反馈的全差分运算放大器
TWI625932B (zh) * 2016-03-14 2018-06-01 美國亞德諾半導體公司 寬頻放大器之有效線性化
CN105978515B (zh) * 2016-05-03 2018-10-19 华南理工大学 宽调整范围高集成度变压器耦合射频功率放大器
CN106778413B (zh) * 2016-12-05 2019-04-26 中国科学技术大学 一种应用于超高频rfid的集成模拟自干扰抵消电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101170656A (zh) * 2006-10-25 2008-04-30 晨星半导体股份有限公司 电视调谐器
EP2110946A1 (en) * 2008-04-18 2009-10-21 STMicroelectronics (Grenoble) SAS Differential RF amplifier
CN103684274A (zh) * 2012-09-12 2014-03-26 澜起科技（上海）有限公司 具有单端转差分能力和滤波作用的宽带低噪声放大器
CN104994322A (zh) * 2015-06-30 2015-10-21 深圳市九洲电器有限公司 一种电视信号处理的装置和电视机顶盒

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DONGGU IM ET AL.: "A CMOS Active Feedback Balun-LNA With High IIP2 for Wideband Digital TV Receivers", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 58, no. 12, 31 December 2010 (2010-12-31), pages 3566 - 3579, XP011339603 *
LIU, XUEMIN ET AL.: "Design of Wideband Gain-variable LAN Based on Mobile Digital TV Applications", VIDEO ENGINEERING, vol. 35, no. 7, 31 July 2011 (2011-07-31) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111555998A (zh) * 2020-04-21 2020-08-18 上海航天测控通信研究所 星载原子钟的下变频信号处理方法和变频组件
CN111555998B (zh) * 2020-04-21 2023-03-24 上海航天测控通信研究所 星载原子钟的下变频信号处理方法和变频组件

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