WO2019196119A1 - 一种信号衰减网络和无线信号接收机 - Google Patents

一种信号衰减网络和无线信号接收机 Download PDF

Info

Publication number
WO2019196119A1
WO2019196119A1 PCT/CN2018/083105 CN2018083105W WO2019196119A1 WO 2019196119 A1 WO2019196119 A1 WO 2019196119A1 CN 2018083105 W CN2018083105 W CN 2018083105W WO 2019196119 A1 WO2019196119 A1 WO 2019196119A1
Authority
WO
WIPO (PCT)
Prior art keywords
resistor
differential
coupled
signal
input
Prior art date
Application number
PCT/CN2018/083105
Other languages
English (en)
French (fr)
Inventor
侯斌
莫秉轩
张立国
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/083105 priority Critical patent/WO2019196119A1/zh
Priority to CN201880084964.5A priority patent/CN111543007A/zh
Publication of WO2019196119A1 publication Critical patent/WO2019196119A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/24—Frequency- independent attenuators
    • H03H7/25—Frequency- independent attenuators comprising an element controlled by an electric or magnetic variable

Definitions

  • the present application relates to the field of signal processing technologies, and in particular, to a signal attenuation network and a wireless signal receiver.
  • FIG. 1 is a schematic diagram of a circuit structure of a ⁇ -type resistance attenuation network.
  • the ⁇ -type resistance attenuation network includes differential input terminals Vip and Vin, differential output terminals Vop and Von, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, and resistor R6.
  • FIG. 2 is a schematic diagram showing the circuit structure of a T-type resistance attenuation network.
  • the T-type resistor attenuation network includes differential inputs Vip and Vin, differential outputs Vop and Von, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5 and resistor R6.
  • the resistor R1 and the resistor R2 are connected in series via the node 1 and coupled between Vip and Vop.
  • the resistor R3 and the resistor R4 are connected in series via the node 2, coupled between Vin and Von, and the resistor R5 and the resistor R6 are connected in series and coupled to the node 1 and
  • capacitor C1, capacitor C2, capacitor C3, and capacitor C4 are the parasitic capacitances of the T-type resistor attenuation network.
  • FIG. 3 is a diagram showing the relationship between the adjustable range of the gain of the ⁇ -type resistance attenuation network shown in FIG. 1 and the bandwidth of the signal that can be processed.
  • the frequency range of the signal that can be processed is 0.2 GHz to 2 GHz.
  • the frequency range of the signal that can be processed is 0.2 GHz to A2 GHz.
  • the gain of the ⁇ -type resistance attenuation network is further increased, for example, when the gain of the ⁇ -type resistance attenuation network is -40 dB, the frequency range of the signal that can be processed is 0.2 GHz to A1 GHz.
  • the resistor attenuation network cannot achieve high dynamic range adjustment of the wideband signal, and the signal processing performance is poor.
  • the present application provides a signal attenuation network and a wireless signal receiver, which contribute to high dynamic range adjustment of a wideband signal and improve signal processing performance.
  • a signal attenuation network of an embodiment of the present application includes a resistance attenuation network and a compensation capacitor coupled to the resistance attenuation network.
  • the resistance attenuation network includes a first differential input, a first differential output, a first resistor network, a second resistor network, and a third resistor network.
  • the first differential input includes a first input and a second input.
  • the first differential output includes a first output and a second output.
  • a first resistance attenuation network is coupled between the first input and the first output.
  • a first resistor network is coupled between the first input and the first output.
  • a second resistor network is coupled between the second input and the second output.
  • a third resistor network is coupled between the first resistor network and the second resistor network.
  • a compensation capacitor is coupled between the first resistor network and the second resistor network to compensate for parasitic capacitance of the resistor attenuation network.
  • the compensation capacitor may include at least one cross capacitance.
  • the compensation capacitor for compensating the parasitic capacitance of the resistance attenuation network since the compensation capacitor for compensating the parasitic capacitance of the resistance attenuation network is introduced in the resistance attenuation network, it helps to reduce the influence of the parasitic capacitance in the resistance attenuation network, thereby contributing to the signal attenuation network to a certain extent. It achieves high dynamic range adjustment of wideband signals and improves signal processing capability.
  • the first resistor network includes a first resistor.
  • the second resistor network includes a second resistor.
  • the third resistor network includes a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor.
  • the third resistor and the fourth resistor are coupled between the first input and the second input, and the third resistor and the fourth resistor are connected in series.
  • the fifth resistor and the sixth resistor are coupled between the first output and the second output, and the fifth resistor and the sixth resistor are connected in series.
  • the first resistor network includes a first resistor and a second resistor.
  • the second resistor network includes a third resistor and a fourth resistor.
  • the third resistor network includes a fifth resistor and a sixth resistor.
  • the first resistor and the second resistor are coupled between the first input and the first output, and the first resistor and the second resistor are connected in series via the first node.
  • the third resistor and the fourth resistor are coupled between the second input and the second output, and the third resistor and the fourth resistor are connected in series via the second node.
  • the fifth resistor and the sixth resistor are coupled between the first node and the second node, and the fifth resistor and the sixth resistor are connected in series.
  • the compensation capacitor includes a first capacitor and a second capacitor.
  • a first capacitive coupling is between the first input and the second output.
  • a second capacitive coupling is between the second input and the first output.
  • the compensation capacitor includes a third capacitor and a fourth capacitor.
  • a third capacitive coupling is between the first input and the second node.
  • a fourth capacitive coupling is between the second input and the first node.
  • the compensation capacitor includes a fifth capacitor and a sixth capacitor.
  • a fifth capacitive coupling is between the second node and the first output.
  • a sixth capacitive coupling is between the first node and the second output.
  • the signal attenuation network also includes a grounded capacitor.
  • the ground capacitance is coupled to a common mode point of the third resistor network.
  • the wireless signal receiver of the embodiment of the present application includes a single-ended to differential circuit, a signal attenuation network and a differential amplifier of any of the first aspect or the first aspect.
  • the single-ended to differential circuit is used to convert the wireless signal into a first differential signal and input the first differential signal to the signal attenuation network.
  • the signal attenuation network is configured to attenuate the first differential signal to obtain a second differential signal, and input the second differential signal to the differential amplifier.
  • a differential amplifier is used to amplify the second differential signal to obtain a third differential signal.
  • the wireless signal receiver in the embodiment of the present application helps to reduce the influence of parasitic capacitance by using the signal attenuation network of any of the first aspect or the first aspect, thereby helping to improve the dynamic adjustment of the wireless signal receiver. range.
  • the wireless signal receiver also includes a buffer for common mode rejection.
  • the buffer is used to process the third differential signal to obtain a fourth differential signal.
  • a buffer for common mode rejection helps to eliminate the imbalance of the positive signal and the negative signal in the differential signal.
  • the wireless signal receiver When the wireless signal receiver is applied to a TV tuner, it helps to improve the effective utilization of the dynamic range of the analog-to-digital converter in the TV tuner, thereby improving the signal quality of the TV tuner output and improving the user experience.
  • the differential amplifier and buffer are integrated into the same device. Through the above technical solutions, it helps to improve the integration of the wireless signal receiver.
  • the buffer includes a second differential input, a second differential output, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a first transistor, and a second a transistor, a third transistor, and a fourth transistor.
  • the second differential input includes a third input and a fourth input.
  • the second differential output includes a third output and a fourth output.
  • a seventh capacitive coupling is between the third input and the gate of the first transistor.
  • An eighth capacitive coupling is between the fourth input and the gate of the second transistor.
  • a ninth capacitive coupling is between the fourth input and the gate of the third transistor.
  • a tenth capacitive coupling is between the third input and the gate of the fourth transistor.
  • a drain of the first transistor is coupled to a drain of the second transistor and coupled to a voltage source.
  • a drain of the third transistor is coupled to the third output.
  • a drain of the fourth transistor is coupled to the fourth output.
  • a source of the first transistor is coupled to the third output.
  • a source of the second transistor is coupled to the fourth output.
  • the source of the third transistor is coupled to ground.
  • the source of the fourth transistor is coupled to ground.
  • the wireless signal receiver of the embodiment of the present application includes a single-ended to differential circuit, a signal attenuation circuit, a differential amplifier, and a buffer for common mode rejection.
  • the single-ended to differential circuit is used to convert the wireless signal into a first differential signal and input the first differential signal to the signal attenuation network.
  • the signal attenuation network is configured to attenuate the first differential signal to obtain a second differential signal, and input the second differential signal to the differential amplifier.
  • the differential amplifier is used to amplify the second differential signal to obtain a third differential signal, and input the third differential signal to the buffer.
  • the buffer is used to process the third differential signal to obtain a fourth differential signal.
  • Embodiments of the present application help to eliminate the imbalance of the positive and negative signals in the differential signal by introducing a buffer for common mode rejection in the wireless signal receiver.
  • the wireless signal receiver When the wireless signal receiver is applied to a TV tuner, it helps to improve the effective utilization of the dynamic frequency range of the analog-to-digital converter in the TV tuner, thereby improving the signal quality of the TV tuner output and improving the user experience.
  • the differential amplifier and the buffer are integrated in the same module.
  • the buffer includes a differential input, a differential output, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first transistor, a second transistor, and a third Transistor and fourth transistor.
  • the differential input includes a first input and a second input.
  • the differential output includes a first output and a second output.
  • a first capacitive coupling is between the first input and the gate of the first transistor.
  • a second capacitive coupling is between the second input and the gate of the second transistor.
  • a third capacitive coupling is between the second input and the gate of the third transistor.
  • a fourth capacitive coupling is between the first input and the gate of the fourth transistor.
  • a drain of the first transistor is coupled to a drain of the second transistor and coupled to a voltage source.
  • a drain of the third transistor is coupled to the first output.
  • a drain of the fourth transistor is coupled to the second output.
  • a source of the first transistor is coupled to the first output.
  • a source of the second transistor is coupled to the second output.
  • the source of the third transistor is coupled to ground.
  • the source of the fourth transistor is coupled to ground.
  • the coupling involved in each embodiment in the present application refers to the direct or indirect connection of two components to each other. This connection can allow electrical signals to communicate between the two components.
  • FIG. 1 is a schematic structural view of a ⁇ -type resistance attenuation network
  • FIG. 2 is a schematic structural view of a T-type resistance attenuation network
  • FIG. 3 is a schematic diagram showing the relationship between the adjustable range of the gain of the ⁇ -type resistance attenuation network shown in FIG. 1 and the bandwidth of a signal that can be processed;
  • FIG. 4 is a schematic structural diagram of a television tuner to which an embodiment of the present application is applied;
  • FIG. 5 is a schematic structural diagram of a wireless signal receiver according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a signal attenuation network according to an embodiment of the present application.
  • 15 is a schematic structural diagram of a wireless signal receiver according to an embodiment of the present application.
  • 16 is a schematic structural diagram of a circuit of a buffer for common mode rejection according to an embodiment of the present application.
  • 17 is a schematic structural diagram of a wireless signal receiver according to an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a wireless signal receiver according to an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of a wireless signal receiver according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a signal receiving system applicable to an embodiment of the present application.
  • the signal receiving system includes a low noise block (LNB) and a signal receiving terminal 400.
  • the signal receiving terminal 400 includes a wireless signal receiver 410 and a demodulator 420.
  • the wireless signal transmitted by the antenna is transmitted to the signal receiving terminal 400 after being amplified by the LNB.
  • the signal from the LNB is processed by the signal receiving terminal 400 and output to other terminal devices.
  • LNB low noise block
  • the wireless signal when the signal receiving system shown in FIG. 4 is applied to a scene of reception of a television signal, the wireless signal is a television signal.
  • it can be a satellite television signal, a terrestrial television signal, a closed circuit television signal, or the like.
  • a satellite television signal refers to a television signal transmitted by a satellite.
  • the terrestrial television signal refers to the television signal transmitted by the terrestrial television tower.
  • a closed-circuit television signal refers to a television signal transmitted wirelessly, such as a closed-circuit television signal transmitted wirelessly to a monitor by an installed camera in a building.
  • the wireless signal When the signal receiving system shown in FIG. 4 is applied to a signal receiving scene of cellular communication, the wireless signal is a cellular signal.
  • the wireless signal When the signal receiving system shown in FIG. 4 is applied to microwave communication, the wireless signal is a microwave signal.
  • the wireless signal receiver is an important device in the signal receiving terminal.
  • the signal processing performance of the wireless signal receiver directly affects the performance of the signal receiving terminal.
  • the structure of the wireless signal receiver may be as shown in FIG. 5.
  • the wireless signal receiver includes a single-ended to differential circuit, a signal attenuation network, and a differential amplifier.
  • the single-ended to differential circuit is configured to convert the wireless signal into a first differential signal and input the first differential signal to the resistance attenuation network.
  • the signal attenuation network is configured to attenuate the first differential signal to obtain a second differential signal, and input the second differential signal to the differential amplifier.
  • a differential amplifier is used to amplify the second differential signal to obtain a third differential signal.
  • the compensation capacitor in the signal attenuation network reduces the influence of parasitic capacitance in the resistor attenuation network, it helps to improve the signal processing capability of the wireless signal receiver in the high dynamic frequency range.
  • the compensation capacitor may include at least one cross capacitance.
  • FIG. 6 it is a schematic structural diagram of a possible signal attenuation network according to an embodiment of the present application.
  • the signal attenuation network includes a resistance attenuation network and a compensation capacitor coupled to the resistance attenuation network.
  • the resistance attenuation network includes a first differential input, a first differential output, a first resistor network 601, a second resistor network 602, and a third resistor network 603.
  • the first differential input includes a first input Vip and a second input Vin.
  • the first differential output includes a first output Vop and a second output Von.
  • the first resistor network 601 is coupled between the first input terminal Vip and the first output terminal Vop.
  • a second resistor network 602 is coupled between the second input terminal Vin and the second output terminal Von.
  • a third resistor network 603 is coupled between the first resistor network 601 and the second resistor network 602.
  • the compensation capacitor is coupled between the first resistor network 601 and the second resistor network 602 for compensating for parasitic capacitance of the resistor attenuation network.
  • the coupling involved in the embodiments of the present application refers to the direct or indirect connection of two components to each other. This connection can allow electrical signals to communicate between the two components.
  • the coupling mode of the compensation capacitor is not limited in the embodiment of the present application. As long as the compensation capacitor can compensate or cancel the parasitic capacitance.
  • the compensation capacitor includes a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 is coupled between the first input terminal Vip and the second output terminal Von, and the second capacitor C1 is coupled to the second input terminal Vin and the first output terminal. Between Vop.
  • the first capacitor C1 and the second capacitor C2 can be regarded as cross capacitors. It should be noted that each of the first capacitor C1 and the second capacitor C2 may be a capacitor, or a circuit including a plurality of capacitors coupled in series or in parallel, which is not limited thereto.
  • the first resistor network 601 includes a first resistor R1
  • the second resistor network 602 includes a second resistor
  • the third resistor network includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.
  • the capacitor includes a first capacitor C1 and a second capacitor C2.
  • C is a parasitic capacitance.
  • the first resistor R1 is coupled between the first input terminal Vip and the first output terminal Vop.
  • the second resistor is coupled between the second input terminal Vin and the second output terminal Von.
  • the third resistor R3 and the fourth resistor R4 are connected in series and coupled between the first input terminal Vip and the second input terminal Vin.
  • the fifth resistor R5 and the sixth resistor R6 are connected in series and coupled between the first output terminal Vop and the second output terminal Von.
  • the first capacitor C1 is coupled between the first input terminal Vip and the second output terminal Von.
  • the second capacitor C2 is coupled between the second input terminal Vin and the first output terminal Vop.
  • Figure 9 shows a specific implementation of another possible signal attenuation network.
  • the first resistor network 601 includes a first resistor R1 and a second resistor R2.
  • the second resistor network 602 includes a third resistor R3 and a fourth resistor R4.
  • the third resistor network 603 includes a fifth resistor R5 and a sixth resistor R6.
  • the compensation capacitor includes a first capacitor C1 and a second capacitor C2.
  • C is a parasitic capacitance.
  • the first resistor R1 and the second resistor R2 are connected in series via the first node P and coupled between the first input terminal Vip and the first output terminal Vop.
  • the third resistor R3 and the fourth resistor R4 are connected in series via the second node Q and coupled between the second input terminal Vin and the second output terminal Von.
  • the fifth resistor R5 and the sixth resistor R6 are connected in series and coupled between the first node P and the second node Q.
  • the first resistor network 601 includes a first resistor R1 and a second resistor R2.
  • the second resistor network 602 includes a third resistor R3 and a fourth resistor R4.
  • the third resistor network 603 includes a fifth resistor R5 and a sixth resistor R6.
  • the first resistor R1 and the second resistor R2 are connected in series via the first node P and coupled between the first input terminal Vip and the first output terminal Vop.
  • the third resistor R3 and the fourth resistor R4 are connected in series via the second node Q and coupled between the second input terminal Vin and the second output terminal Von.
  • the compensation capacitor includes a third capacitor C3 and a fourth capacitor C4.
  • the third capacitor C3 is coupled between the first input terminal Vip and the second node Q.
  • the fourth capacitor C4 is coupled between the second input terminal Vin and the first node P.
  • FIG 11 shows a schematic diagram of yet another alternative signal attenuation network.
  • the first resistor network 601 includes a first resistor R1 and a second resistor R2.
  • the second resistor network 602 includes a third resistor R3 and a fourth resistor R4.
  • the third resistor network 603 includes a fifth resistor R5 and a sixth resistor R6.
  • the first resistor R1 and the second resistor R2 are connected in series via the first node P and coupled between the first input terminal Vip and the first output terminal Vop.
  • the third resistor R3 and the fourth resistor R4 are connected in series via the second node Q and coupled between the second input terminal Vin and the second output terminal Von.
  • the compensation capacitor includes a fifth capacitor C5 and a sixth capacitor C6.
  • the fifth capacitor C5 is coupled between the first node P and the second output terminal Von.
  • a sixth capacitor C6 is coupled between the second node Q and the first output terminal Vop.
  • the first resistor network 601 includes a first resistor R1 and a second resistor R2.
  • the second resistor network 602 includes a third resistor R3 and a fourth resistor R4.
  • the third resistor network 603 includes a fifth resistor R5 and a sixth resistor R6.
  • the first resistor R1 and the second resistor R2 are connected in series via the first node P and coupled between the first input terminal Vip and the first output terminal Vop.
  • the third resistor R3 and the fourth resistor R4 are connected in series via the second node Q and coupled between the second input terminal Vin and the second output terminal Von.
  • the compensation capacitor includes a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6.
  • the third capacitor C3 is coupled between the first input terminal Vip and the second node Q.
  • the fourth capacitor C4 is coupled between the second input terminal Vin and the first node P.
  • the fifth capacitor C5 is coupled between the first node P and the second output terminal Von.
  • a sixth capacitor C6 is coupled between the second node Q and the first output terminal Vop.
  • the third capacitor C3 and the fourth capacitor C4 can be regarded as cross capacitors, and the fifth capacitor C5 and the sixth capacitor C6 can be regarded as cross capacitors.
  • the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are involved.
  • the resistance of at least one of the fifth resistor R5 or the sixth resistor R6 may be adjustable, and one or more of the resistors may be unadjustable, which is not limited in this embodiment.
  • the first resistor R1 is adjustable.
  • the first resistor R1 may be a circuit coupled by a plurality of resistors, and the resistance of the first resistor R1 is controlled by a switch.
  • the first resistor R1 can also be an adjustable resistor. The specific implementation manner in which the resistance of the resistor is adjustable is not limited in the embodiment of the present application.
  • the capacitance of any one or more capacitors included in the compensation capacitors in the embodiments of the present application may be adjustable or not adjustable, which is not limited in this embodiment.
  • the capacitance of the first capacitor C1 is adjustable.
  • the first capacitor C1 When the first capacitor C1 is implemented, it may be a circuit that is coupled by a plurality of capacitors, and the magnitude of the capacitance of the first capacitor C1 is controlled by the switch.
  • the first capacitor C1 can also be a tunable capacitor.
  • the specific implementation manner in which the capacitance of the capacitor is adjustable is not limited in the embodiment of the present application.
  • any of the resistors in the above embodiments may include a plurality of mutually coupled resistors.
  • the signal attenuating network in the embodiment of the present application can be applied to other technical fields that require high dynamic range adjustment of the wideband signal, which is not limited in this embodiment of the present application.
  • the signal attenuation network also includes a grounding capacitor. Wherein the ground capacitance is coupled to a common mode point of the signal attenuation network to eliminate the imbalance.
  • the common mode point of the signal attenuation network is a coupling point in which the third resistor R3 and the fourth resistor R4 are connected in series, and a series coupling point of the fifth resistor R5 and the sixth resistor R6.
  • M1 is a coupling point of the third resistor R3 and the fourth resistor R4 in series
  • M2 is a series coupling point of the fifth resistor R5 and the sixth resistor R6.
  • Capacitor Ca and capacitor Cb are grounded capacitors. Wherein capacitor Ca is coupled to M1 and capacitor Cb is coupled to M2. It should be noted that the capacitance of the capacitor Ca and the capacitance of the capacitor Cb may be equal or not equal.
  • the capacitance of the capacitor Ca and the capacitance of the capacitor Cb can be set according to the bandwidth requirements and application scenarios.
  • the common mode point of the signal attenuation network is the coupling point of the fifth resistor R5 and the sixth resistor R6 in series.
  • M is a common mode point in which the fifth resistor R5 and the sixth resistor R6 are connected in series.
  • Capacitor C0 is a grounded capacitor. Wherein capacitor C0 is coupled to M.
  • the connection manner of the grounding capacitance is similar to the connection manner of the grounding capacitance in the signal attenuation network shown in FIG. 9, and details are not described herein again.
  • a buffer for common mode rejection can also be introduced in the wireless signal receiver shown in FIG. 5 to eliminate the imbalance of the positive signal and the negative signal of the differential signal.
  • FIG. 15 a schematic structural diagram of a possible wireless signal reception.
  • Specific examples include single-ended to differential circuits, wireless signal receivers, differential amplifiers, and buffers for common mode rejection.
  • the single-ended to differential circuit is configured to convert the wireless signal into a first differential signal and input the first differential signal to the resistance attenuation network.
  • the signal attenuation network is configured to attenuate the first differential signal to obtain a second differential signal, and input the second differential signal to the differential amplifier.
  • a differential amplifier is used to amplify the second differential signal to obtain a third differential signal.
  • the buffer is used to process the third differential signal to obtain a fourth differential signal. It will be appreciated that the processing of the buffers is typically used to boost signal drive capability or to achieve front-to-back signal isolation.
  • the buffer includes a second differential input terminal, a second differential output terminal, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a first transistor M1, a second transistor M2, and a third Transistor M3 and fourth transistor M4.
  • the second differential input includes a third input Vinp and a fourth input Vinn.
  • the second differential output includes a third output Voup and a fourth output Voun.
  • the seventh capacitor C7 is coupled between the third input terminal Vinp and the gate of the first transistor M1.
  • the eighth capacitor C8 is coupled between the fourth input terminal Vinn and the gate of the second transistor M2.
  • a ninth capacitor C9 is coupled between the fourth input terminal Vinn and the gate of the third transistor M3.
  • the tenth capacitor C10 is coupled between the third input terminal Vinp and the gate of the fourth transistor M4.
  • four transistors are all N-type metal oxide semiconductor (MOS) transistors as an example.
  • the drain of the first transistor M1 is coupled to the drain of the second transistor M2 and to the voltage source.
  • the drain of the third transistor M3 is coupled to a third output terminal Voup.
  • the drain of the fourth transistor M4 is coupled to the fourth output terminal Voun.
  • the source of the first transistor M1 is coupled to a third output terminal Voup.
  • the source of the second transistor M2 is coupled to the fourth output terminal Voun.
  • the source of the third transistor M3 is coupled to ground.
  • the source of the fourth transistor M4 is coupled to ground.
  • RL is the equivalent load impedance of the next stage.
  • the amplitudes of the two signals in the fourth differential signal obtained by the buffer shown in FIG. 16 are equal and opposite. , thereby eliminating the imbalance of the differential signal.
  • the embodiment of the present application does not limit the circuit structure of the buffer for common mode suppression.
  • FIG. 16 is only an example and does not constitute a limitation on the embodiments of the present application.
  • the buffer for common mode rejection in the embodiment of the present application may also be other circuit structures, such as a high common mode rejection structure implemented by a cross-coupling or a fully differential circuit similar to the example, as long as the differential signal is eliminated by common mode rejection. Unbalanced.
  • the differential amplifier and the buffer for common mode rejection in the embodiments of the present application may be two independent devices. To increase integration, differential amplifiers and buffers for common mode rejection can be integrated on a single device.
  • the single-ended to differential circuit may be a passive balun or an active balun, which is not limited thereto.
  • the differential amplifier in the embodiment of the present application may be a low noise amplifier (LNA) or the like.
  • the wireless signal receiver in the embodiment of the present application is not limited to include the above components, and may further include a programmable gain amplifier (PGA), a low pass filter, and an analog-to-digital converter. , ADC) and so on.
  • PGA programmable gain amplifier
  • ADC analog-to-digital converter
  • FIG. 17 including a single-ended to differential circuit, a signal attenuation network, a differential amplifier, a PGA, a low-pass filter, and an ADC, Integrate single-ended to differential circuits, signal attenuation networks, differential amplifiers, PGAs, low-pass filters, and ADCs on a single chip.
  • FIG. 17 including a single-ended to differential circuit, a signal attenuation network, a differential amplifier, a PGA, a low-pass filter, and an ADC, Integrate single-ended to differential circuits, signal attenuation networks, differential amplifiers, PGAs, low-pass filters, and ADCs on a single chip.
  • the wireless signal receiver is further coupled to a demodulator.
  • the wireless signal receiver can be further integrated with the demodulator.
  • the wireless signal receiver of the embodiment of the present application can be applied to a fully integrated chip technology of digital television full band capture (FBC). Specifically, the wireless signal receiver of the embodiment of the present application supports digital video broadcasting (C-DVB-C), digital terrestrial television broadcasting DVB-T, digital satellite television broadcasting, digital television under the DVB-S protocol. Signal reception.
  • C-DVB-C digital video broadcasting
  • DVB-T digital terrestrial television broadcasting
  • DVB-S protocol digital satellite television broadcasting
  • FIG. 19 is a schematic structural diagram of another wireless signal receiver according to an embodiment of the present application.
  • the wireless signal receiver includes a single-ended to differential circuit, an attenuation network, a differential amplifier, and a buffer for common mode rejection.
  • the single-ended to differential circuit is configured to convert the wireless signal into a first differential signal and input the first differential signal to the attenuation network.
  • the attenuation network is configured to attenuate the first differential signal to obtain a second differential signal and input the second differential signal to the differential amplifier.
  • the differential amplifier is used to amplify the second differential signal to obtain a third differential signal, and input the third differential signal to the buffer.
  • a buffer is configured to process the third differential signal to obtain a fourth differential signal.
  • the attenuation network in the embodiment of the present application may be a resistance attenuation network, for example, the ⁇ -type resistance attenuation network shown in FIG. 1 of the prior art, or the T-type resistance attenuation network shown in FIG. 2, which may also be involved in the embodiment of the present application.
  • the signal attenuation network is not limited. Therefore, FIG. 15 can be regarded as a specific example of FIG.
  • the single-ended to differential circuit may be a passive balun or an active balun, which is not limited thereto.
  • the differential amplifier in the embodiment of the present application may be a low noise amplifier (LNA) or the like.
  • the buffer for common mode suppression in the embodiment of the present application does not limit the circuit structure of the buffer for common mode suppression.
  • FIG. 16 is only an example and does not constitute a limitation on the embodiments of the present application.
  • the buffer for common mode rejection in the embodiment of the present application may also be other circuit structures, such as a high common mode rejection structure implemented by a cross-coupling or a fully differential circuit similar to the example, as long as the differential signal is eliminated by common mode rejection. Unbalanced.
  • differential amplifier and the buffer for common mode rejection in the embodiments of the present application may be two independent devices.
  • differential amplifiers and buffers for common mode rejection can be integrated on a single device.
  • the wireless signal receiver in the embodiment of the present application is not limited to include the above components, and may also include a PGA, a low pass filter, an ADC, and the like.
  • an optional wireless signal receiver is integrated on one chip.
  • the wireless signal receiver can be further integrated with the demodulator.
  • the wireless signal receiver of the embodiment of the present application can be applied to the fully integrated chip technology of the digital television FBC. Specifically, the wireless signal receiver of the embodiment of the present application supports reception of digital television signals under the DVB-C, DVB-T, and DVB-S protocols.

Landscapes

  • Amplifiers (AREA)

Abstract

一种信号衰减网络和无线信号接收机，涉及信号处理技术领域。其中信号衰减网络包括包括电阻衰减网络和补偿电容。电阻衰减网络包括第一差分输入端、第一差分输出端、第一电阻网络、第二电阻网络和第三电阻网络。第一差分输入端包括第一输入端和第二输入端。第一差分输出端包括第一输出端和第二输出端。第一电阻衰减网络耦合在第一输入端和第一输出端之间。第一电阻网络耦合在第一输入端和第一输出端之间。第二电阻网络耦合在第二输入端和第二输出端之间。第三电阻网络耦合在第一电阻网络和第二电阻网络之间。补偿电容耦合用于对电阻衰减网络的寄生电容做补偿。通过上述技术方案有助于降低电阻衰减网络中寄生电容的影响，提高信号处理能力。

Description

一种信号衰减网络和无线信号接收机 技术领域
本申请涉及信号处理技术领域，特别涉及一种信号衰减网络和无线信号接收机。
背景技术
衰减器广泛的应用于电子设备中，主要用于调整信号的大小。常见的衰减器为电阻衰减网络，例如π型电阻衰减网络和T型电阻衰减网络。其中，图1所示为一种π型电阻衰减网络的电路结构示意图。从图1中可以看出，π型电阻衰减网络包括差分输入端Vip和Vin、差分输出端Vop和Von、电阻R1、电阻R2、电阻R3、电阻R4、电阻R5和电阻R6。其中，电阻R1耦合在Vip和Vop之间，电阻R2耦合在Vin和Von之间，电阻R3和电阻R4串联、耦合在Vip和Vin之间，电阻R5和电阻R6串联、耦合在Vop和Von之间，电容C1和电容C2为π型电阻衰减网络的寄生电容。图2所示为一种T型电阻衰减网络的电路结构示意图。从图2中可以看出，T型电阻衰减网络包括差分输入端Vip和Vin、差分输出端Vop和Von、电阻R1、电阻R2、电阻R3、电阻R4、电阻R5和电阻R6。其中，电阻R1和电阻R2经由节点1串联、耦合在Vip和Vop之间，电阻R3和电阻R4经由节点2串联、耦合在Vin和Von之间，电阻R5和电阻R6串联、耦合在节点1和节点2之间，电容C1、电容C2、电容C3和电容C4为T型电阻衰减网络的寄生电容。
然而，对于电阻衰减网络来说，由于寄生电容的存在，导致随着电阻衰减网络处理的信号的带宽的增大，电阻衰减网络的增益的可调节范围在降低。如图3所示为图1所示的π型电阻衰减网络的增益的可调节范围和能够处理的信号的带宽之间关系的示意图。从图3中可以看出，如图1所示的π型电阻衰减网络的增益为-20dB时，可以处理得信号的频率范围为0.2GHz～2GHz。而当π型电阻衰减网络的增益为-30dB时，可以处理得信号的频率范围为0.2GHz～A2GHz。当π型电阻衰减网络的增益进一步增大时，例如π型电阻衰减网络的增益为-40dB时，可以处理得信号的频率范围为0.2GHz～A1GHz。其中，A1<A2<2。
综上所述，由于寄生电容的存在，电阻衰减网络无法实现对宽带信号的高动态范围调节，信号处理性能较差。
发明内容
本申请提供一种信号衰减网络和无线信号接收机，有助于实现对宽带信号的高动态范围调节，提高信号处理性能。
第一方面，本申请实施例的信号衰减网络，包括电阻衰减网络和与所述电阻衰减网络相耦合的补偿电容。所述电阻衰减网络包括第一差分输入端、第一差分输出端、第一电阻网络、第二电阻网络和第三电阻网络。第一差分输入端包括第一输入端和第二输入端。第一差分输出端包括第一输出端和第二输出端。第一电阻衰减网络耦合在第一输入端和第一输出端之间。第一电阻网络耦合在第一输入端和第一输出端之间。第二电阻网络耦合在第二输入端和第二输出端之间。第三电阻网络耦合在第一电阻网络和第二电阻网络之间。补偿电容耦合在第一电阻网络和第二电阻网络之间，用于对电阻衰减网络的寄生电容做补偿。可选地，所述补偿电容可以包括至少一个交叉电容。
本申请实施例中由于在电阻衰减网络中引入了对电阻衰减网络的寄生电容做补偿的 补偿电容，因而有助于降低电阻衰减网络中寄生电容的影响，从而有助于信号衰减网络在一定程度上实现对宽带信号的高动态范围调节，提高信号处理能力。
在一种可能的设计中，第一电阻网络包括第一电阻。第二电阻网络包括第二电阻。第三电阻网络包括第三电阻、第四电阻、第五电阻和第六电阻。第三电阻和第四电阻耦合在第一输入端和第二输入端之间、且第三电阻和第四电阻串联。第五电阻和第六电阻耦合在第一输出端和第二输出端之间、且第五电阻和第六电阻串联。通过上述技术方案，有助于简化电阻衰减网络的实现方式。
在一种可能的设计中，第一电阻网络包括第一电阻和第二电阻。第二电阻网络包括第三电阻和第四电阻。第三电阻网络包括第五电阻和第六电阻。第一电阻和第二电阻耦合在第一输入端和第一输出端之间、且第一电阻和第二电阻经由第一节点相串联。第三电阻和第四电阻耦合在第二输入端和第二输出端之间、且第三电阻和第四电阻经由第二节点相串联。第五电阻和第六电阻耦合在第一节点和第二节点之间、且第五电阻和第六电阻串联。通过上述技术方案，有助于简化电阻衰减网络的实现方式。
在一种可能的设计中，补偿电容包括第一电容和第二电容。第一电容耦合在第一输入端和第二输出端之间。第二电容耦合在第二输入端和第一输出端之间。通过上述技术方案，有助于简化补偿电容的实现方式。
在一种可能的设计中，补偿电容包括第三电容和第四电容。第三电容耦合在第一输入端和第二节点之间。第四电容耦合在第二输入端和第一节点之间。通过上述技术方案，有助于简化补偿电容的实现方式。
在一种可能的设计中，补偿电容包括第五电容和第六电容。第五电容耦合在第二节点和第一输出端之间。第六电容耦合在第一节点和第二输出端之间。通过上述技术方案，有助于简化补偿电容的实现方式。
在一种可能的设计中，信号衰减网络还包括接地电容。接地电容耦合至第三电阻网络的共模点。通过上述技术方案，有助于消除第一差分输出端输出的差分信号中的正相(positive)信号和负相(negative)信号的不平衡。
第二方面，本申请实施例的无线信号接收机，包括单端转差分电路、第一方面或第一方面任一可能设计的信号衰减网络和差分放大器。单端转差分电路用于将无线信号转换为第一差分信号，并将第一差分信号输入到信号衰减网络。信号衰减网络用于对第一差分信号进行衰减，得到第二差分信号，并将第二差分信号输入到差分放大器。差分放大器用于对第二差分信号进行放大，得到第三差分信号。
本申请实施例中的无线信号接收机由于采用第一方面或第一方面任一可能设计的信号衰减网络，因而有助于降低寄生电容的影响，从而有助于提高无线信号接收机的动态调节范围。
在一种可能的设计中，无线信号接收机还包括用于共模抑制的缓冲器。缓冲器用于对第三差分信号进行处理，得到第四差分信号。通过在无线信号接收机中引入用于共模抑制的缓冲器，有助于消除差分信号的中的positive信号和negative信号的不平衡。当将无线信号接收机应用于电视调谐器中时，有助于提高对电视调谐器中模数转换器动态范围的有效利用率，从而提高电视调谐器输出的信号质量，提高用户体验。
在一种可能的设计中，差分放大器和缓冲器被集成在同一个器件中。通过上述技术方案，有助于提高无线信号接收机的集成度。
为了简化实现方式，在一种可能的设计中，缓冲器包括第二差分输入端、第二差分输出端、第七电容、第八电容、第九电容、第十电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管。第二差分输入端包括第三输入端和第四输入端。第二差分输出端包括第三输出端和第四输出端。第七电容耦合在第三输入端和第一晶体管的栅极之间。第八电容耦合在第四输入端和第二晶体管的栅极之间。第九电容耦合在第四输入端和第三晶体管的栅极之间。第十电容耦合在第三输入端和第四晶体管的栅极之间。第一晶体管的漏极耦合至第二晶体管的漏极并耦合至电压源。第三晶体管的漏极耦合至第三输出端。第四晶体管的漏极耦合至第四输出端。第一晶体管的源极耦合至第三输出端。第二晶体管的源极耦合至第四输出端。第三晶体管的源极耦合至地。第四晶体管的源极耦合至地。
第三方面，本申请实施例的无线信号接收机包括单端转差分电路、信号衰减电路、差分放大器和用于共模抑制的缓冲器。单端转差分电路用于将无线信号转换为第一差分信号，并将第一差分信号输入到信号衰减网络。信号衰减网络用于对第一差分信号进行衰减，得到第二差分信号，并将第二差分信号输入到差分放大器。差分放大器用于对第二差分信号进行放大，得到第三差分信号，并将第三差分信号输入到缓冲器。缓冲器用于对第三差分信号进行处理，得到第四差分信号。
本申请实施例通过在无线信号接收机中引入用于共模抑制的缓冲器，有助于消除差分信号的中的positive信号和negative信号的不平衡。当将无线信号接收机应用于电视调谐器中时，有助于提高对电视调谐器中模数转换器动态频率范围的有效利用率，从而提高电视调谐器输出的信号质量，提高用户体验。
为了提高集成度，在一种可能的设计中，差分放大器和缓冲器被集成在同一个模块中。
为了简化实现方式，在一种可能的设计中，缓冲器包括差分输入端、差分输出端、第一电容、第二电容、第三电容、第四电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管。差分输入端包括第一输入端和第二输入端。差分输出端包括第一输出端和第二输出端。第一电容耦合在第一输入端和第一晶体管的栅极之间。第二电容耦合在第二输入端和第二晶体管的栅极之间。第三电容耦合在第二输入端和第三晶体管的栅极之间。第四电容耦合在第一输入端和第四晶体管的栅极之间。第一晶体管的漏极耦合至第二晶体管的漏极并耦合至电压源。第三晶体管的漏极耦合至第一输出端。第四晶体管的漏极耦合至第二输出端。第一晶体管的源极耦合至第一输出端。第二晶体管的源极耦合至第二输出端。第三晶体管的源极耦合至地。第四晶体管的源极耦合至地。
需要说明的是，本申请中各个实施例所涉及的耦合是指两个部件彼此直接或间接的连接。这种连接可以允许电信号在两个部件之间通信。
附图说明
图1为π型电阻衰减网络的结构示意图；
图2为T型电阻衰减网络的结构示意图；
图3为图1所示的π型电阻衰减网络的增益的可调节范围和能够处理的信号的带宽之间关系的示意图；
图4为本申请实施例适用的一种电视调谐器的结构示意图；
图5为本申请实施例无线信号接收机的结构示意图；
图6为本申请实施例信号衰减网络的结构示意图；
图7为本申请实施例信号衰减网络的结构示意图；
图8为本申请实施例信号衰减网络的结构示意图；
图9为本申请实施例信号衰减网络的结构示意图；
图10为本申请实施例信号衰减网络的结构示意图；
图11为本申请实施例信号衰减网络的结构示意图；
图12为本申请实施例信号衰减网络的结构示意图；
图13为本申请实施例信号衰减网络的结构示意图；
图14为本申请实施例信号衰减网络的结构示意图；
图15为本申请实施例无线信号接收机的结构示意图；
图16为本申请实施例用于共模抑制的缓冲器的电路结构示意图；
图17为本申请实施例无线信号接收机的结构示意图；
图18为本申请实施例无线信号接收机的结构示意图；
图19为本申请实施例无线信号接收机的结构示意图。
具体实施方式
本申请实施例可以应用于电视信号的接收、微波通信、蜂窝通信、短距离通信，如无线保真(wireless fidelity，WiFi)通信等信号接收的场景中。如图4所示，为本申请实施例适用的一种信号接收系统的结构示意图。其中，信号接收系统包括低噪声块(low noise block，LNB)和信号接收终端400。具体的，信号接收终端400包括无线信号接收机410和解调器420。由天线发射的无线信号经过LNB的放大处理后发送给信号接收终端400。由信号接收终端400对来自LNB的信号进行处理后，输出给其他终端设备。
应理解，当图4所示的信号接收系统应用于电视信号的接收的场景中时，无线信号为电视信号。例如可以为卫星电视信号、地面电视信号、闭路电视信号等。具体的，卫星电视信号指的是由卫星发射的电视信号。地面电视信号指的是由地面电视塔发射的电视信号。闭路电视信号指的是通过无线方式传送的电视信号，如大楼内的安装的摄像头通过无线方式向监视器发送的信号为闭路电视信号。当图4所示的信号接收系统应用于蜂窝通信的信号接收场景中时，无线信号为蜂窝信号。当图4所示的信号接收系统应用于微波通信时，无线信号为微波信号。
而无线信号接收机是信号接收终端中的重要器件。无线信号接收机信号处理性能，直接影响信号接收终端的性能。当无线信号的带宽较大时，为了使得信号接收终端输出的信号质量较高，可选的，无线信号接收机的结构可以如图5所示。具体的，无线信号接收机包括单端转差分电路、信号衰减网络和差分放大器。其中单端转差分电路用于将无线信号转换为第一差分信号，并将第一差分信号输入到电阻衰减网络。信号衰减网络用于对所述第一差分信号进行衰减，得到第二差分信号，并将第二差分信号输入到差分放大器。差分放大器用于对第二差分信号进行放大，得到第三差分信号。
由于信号衰减网络中通过补偿电容降低了电阻衰减网络中寄生电容影响，从而有助于提高无线信号接收机的高动态频率范围的信号处理能力。可选地，所述补偿电容可以包括至少一个交叉电容。具体如图6所示，为本申请实施例一种可能的信号衰减网络的结构示意图。具体的，信号衰减网络包括电阻衰减网络和与电阻衰减网络相耦合的补偿电容。电阻衰减网络包括第一差分输入端、第一差分输出端、第一电阻网络601、第二电阻网络602 和第三电阻网络603。第一差分输入端包括第一输入端Vip和第二输入端Vin。第一差分输出端包括第一输出端Vop和第二输出端Von。第一电阻网络601耦合在第一输入端Vip和第一输出端Vop之间。第二电阻网络602耦合在第二输入端Vin和第二输出端Von之间。第三电阻网络603耦合在第一电阻网络601和第二电阻网络602之间。补偿电容耦合在第一电阻网络601和第二电阻网络602之间，用于对电阻衰减网络的寄生电容做补偿。
需要说明的是，本申请实施例涉及的耦合是指两个部件彼此直接或间接的连接。这种连接可以允许电信号在两个部件之间通信。其中，本申请实施例对补偿电容的耦合方式不作限定。只要补偿电容能够补偿或者抵消寄生电容即可。
为了便于实现，如图7所示一种可能的信号衰减网络的实现方式。补偿电容包括第一电容C1和第二电容C2，其中第一电容C1耦合在第一输入端Vip和第二输出端Von之间，第二电容C1耦合在第二输入端Vin和第一输出端Vop之间。该第一电容C1和第二电容C2可以被视为交叉电容。需要说明的是，第一电容C1和第二电容C2中的每一个可以为一个电容，也可以为串联或并联等方式耦合的包括多个电容的电路，对此不作限定。
在具体实现时，如图8所示为一种可能的信号衰减电路的实现方式。具体的，第一电阻网络601包括第一电阻R1，第二电阻网络602包括第二电阻，第三电阻网络包括第三电阻R3、第四电阻R4、第五电阻R5和第六电阻R6，补偿电容包括第一电容C1和第二电容C2。C为寄生电容。第一电阻R1耦合在第一输入端Vip和第一输出端Vop之间。第二电阻耦合在第二输入端Vin和第二输出端Von之间。第三电阻R3和第四电阻R4串联、耦合在第一输入端Vip和第二输入端Vin之间。第五电阻R5和第六电阻R6串联、耦合在第一输出端Vop和第二输出端Von之间。第一电容C1耦合在第一输入端Vip和第二输出端Von之间。第二电容C2耦合在第二输入端Vin和第一输出端Vop之间。
如图9所示为另一种可能的信号衰减网络的具体实现方式。具体的，第一电阻网络601包括第一电阻R1和第二电阻R2。第二电阻网络602包括第三电阻R3和第四电阻R4。第三电阻网络603包括第五电阻R5和第六电阻R6。补偿电容包括第一电容C1和第二电容C2。C为寄生电容。第一电阻R1和第二电阻R2经由第一节点P相串联、且耦合在第一输入端Vip和第一输出端Vop之间。第三电阻R3和第四电阻R4经由第二节点Q相串联、且耦合在第二输入端Vin和第二输出端Von之间。第五电阻R5和第六电阻R6串联、且耦合在第一节点P和第二节点Q之间。
如图10所示为再一种可选的信号衰减网络的示意图。第一电阻网络601包括第一电阻R1和第二电阻R2。第二电阻网络602包括第三电阻R3和第四电阻R4。第三电阻网络603包括第五电阻R5和第六电阻R6。第一电阻R1和第二电阻R2经由第一节点P相串联、且耦合在第一输入端Vip和第一输出端Vop之间。第三电阻R3和第四电阻R4经由第二节点Q相串联、且耦合在第二输入端Vin和第二输出端Von之间。补偿电容包括第三电容C3和第四电容C4。第三电容C3耦合在第一输入端Vip和第二节点Q之间。第四电容C4耦合在第二输入端Vin和第一节点P之间。
如图11所示为又一种可选的信号衰减网络的示意图。第一电阻网络601包括第一电阻R1和第二电阻R2。第二电阻网络602包括第三电阻R3和第四电阻R4。第三电阻网络603包括第五电阻R5和第六电阻R6。第一电阻R1和第二电阻R2经由第一节点P相串联、且耦合在第一输入端Vip和第一输出端Vop之间。第三电阻R3和第四电阻R4经由第二节点Q相串联、且耦合在第二输入端Vin和第二输出端Von之间。补偿电容包括第五电容C5 和第六电容C6。第五电容C5耦合在第一节点P和第二输出端Von之间。第六电容C6耦合在第二节点Q和第一输出端Vop之间。
如图12所示为又一种可选的信号衰减网络的示意图。第一电阻网络601包括第一电阻R1和第二电阻R2。第二电阻网络602包括第三电阻R3和第四电阻R4。第三电阻网络603包括第五电阻R5和第六电阻R6。第一电阻R1和第二电阻R2经由第一节点P相串联、且耦合在第一输入端Vip和第一输出端Vop之间。第三电阻R3和第四电阻R4经由第二节点Q相串联、且耦合在第二输入端Vin和第二输出端Von之间。补偿电容包括第三电容C3、第四电容C4、第五电容C5和第六电容C6。第三电容C3耦合在第一输入端Vip和第二节点Q之间。第四电容C4耦合在第二输入端Vin和第一节点P之间。第五电容C5耦合在第一节点P和第二输出端Von之间。第六电容C6耦合在第二节点Q和第一输出端Vop之间。第三电容C3和第四电容C4可被视为交叉电容，且第五电容C5和第六电容C6可被视为交叉电容。
需要说明的是，图8、图9、图10、图11和图12所示的信号衰减网络中，所涉及到的第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5或第六电阻R6中的至少一个的阻值可以是可调的，其中的一个或多个也可以是不可调的，本实施例对此不作限定。例如第一电阻R1是可调的，第一电阻R1在具体实现时，可以为一个由多个电阻耦合的电路，通过开关控制第一电阻R1的阻值的大小。第一电阻R1还可以为一个可调电阻。本申请实施例对电阻的阻值是可调的具体实现方式不作限定。
本申请实施例中涉及到的补偿电容所包括的任一个或多个电容的容值可以是可调的，也可以是不可调的，本实施例对此也不做限定。例如第一电容C1的容值是可调的，第一电容C1在具体实现时，可以为一个由多个电容耦合的电路，通过开关控制第一电容C1的容值的大小。第一电容C1还可以为一个可调电容。本申请实施例对电容的容值是可调的具体实现方式不作限定。
以上实施例中的任一个电阻可以包括多个互相耦合的电阻。此外，本申请实施例中的信号衰减网络还可以应用于其他需要对宽带信号进行高动态范围调节的技术领域，本申请实施例对此不作限定。
为了消除差分信号中的positive信号和negative信号的不平衡，即消除PN不平衡，可选的，信号衰减网络还包括接地电容。其中，接地电容耦合至信号衰减网络的共模点，以消除所述不平衡。
以图8所示的信号衰减网络为例。信号衰减网络的共模点为第三电阻R3和第四电阻R4串联的耦合点、以及第五电阻R5和第六电阻R6的串联耦合点。示例的，如图13所示，M1为第三电阻R3和第四电阻R4串联的耦合点、M2为第五电阻R5和第六电阻R6的串联耦合点。电容Ca和电容Cb为接地电容。其中电容Ca耦合至M1，电容Cb耦合至M2。需要说明的是，电容Ca的容值和电容Cb的容值可以相等，也可以不相等。电容Ca的容值和电容Cb的容值可以根据带宽需要及应用场景进行相应的设定。
以图9所示的信号衰减网络为例。信号衰减网络的共模点为第五电阻R5和第六电阻R6串联的耦合点。示例的，如图14所示，M为第五电阻R5和第六电阻R6串联的共模点。电容C0为接地电容。其中电容C0耦合至M。在图10、图11和图12所示的信号衰减网络中，其接地电容的连接方式与图9所示的信号衰减网络中接地电容的连接方式类似，在此不再赘述。
此外，本申请实施例中还可以在图5所示的无线信号接收机中引入用于共模抑制的缓 冲器来消除差分信号的positive信号和negative信号的不平衡。可选的，如图15所示，一种可能的无线信号接收的结构示意图。具体的包括单端转差分电路、无线信号接收机、差分放大器和用于共模抑制的缓冲器。其中单端转差分电路用于将无线信号转换为第一差分信号，并将第一差分信号输入到电阻衰减网络。信号衰减网络用于对所述第一差分信号进行衰减，得到第二差分信号，并将第二差分信号输入到差分放大器。差分放大器用于对第二差分信号进行放大，得到第三差分信号。缓冲器用于对第三差分信号进行处理，得到第四差分信号。可以理解，缓冲器的所述处理通常用于提升信号驱动能力或实现前后级信号隔离。
如图16所示，为一种可能的用于共模抑制的缓冲器的电路结构示意图。具体的，缓冲器包括第二差分输入端、第二差分输出端、第七电容C7、第八电容C8、第九电容C9、第十电容C10、第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4。第二差分输入端包括第三输入端Vinp和第四输入端Vinn。第二差分输出端包括第三输出端Voup和第四输出端Voun。第七电容C7耦合在第三输入端Vinp和第一晶体管M1的栅极之间。第八电容C8耦合在第四输入端Vinn和第二晶体管M2的栅极之间。第九电容C9耦合在第四输入端Vinn和第三晶体管M3的栅极之间。第十电容C10耦合在第三输入端Vinp和第四晶体管M4的栅极之间。本实施例以四个晶体管均为N型金属氧化物半导体(MOS)管为例。第一晶体管M1的漏极耦合至第二晶体管M2的漏极并耦合至电压源。第三晶体管M3的漏极耦合至第三输出端Voup。第四晶体管M4的漏极耦合至第四输出端Voun。第一晶体管M1的源极耦合至第三输出端Voup。第二晶体管M2的源极耦合至第四输出端Voun。第三晶体管M3的源极耦合至地。第四晶体管M4的源极耦合至地。其中RL为下一级负载等效阻抗。
在图15对应的第三差分信号中的两路信号的幅度大小不平衡的情况下，通过图16所示的缓冲器，得到的第四差分信号中的两路信号的幅度大小相等、方向相反，从而消除了差分信号的不平衡。
需要说明的是，本申请实施例不限定用于共模抑制的缓冲器的电路结构。图16仅为一种示例说明，不构成对本申请实施例的限定。本申请实施例中用于共模抑制的缓冲器还可以为其他的电路结构，比如通过类似示例的交叉耦合或全差分电路实现的高共模抑制结构，只要满足通过共模抑制消除差分信号的不平衡即可。
本申请实施例中差分放大器和用于共模抑制的缓冲器可以为两个独立的器件。为了提高集成度，差分放大器和用于共模抑制的缓冲器可以被集成在一个器件上。此外，在本申请实施例中，单端转差分电路可以为无源巴伦，也可以为有源巴伦，对此不作限定。本申请实施例中的差分放大器可以为低噪放大器(low noise amplifier，LNA)等。
应理解，本申请实施例中的无线信号接收机不限于包括上述部件，还可以包括可编程增益放大器(programmable gain amplifier，PGA)、低通滤波器、模数转换器(analog-to-digital converter，ADC)等。为了提高无线信号接收的集成度，可选的，在无线信号接收机如图17所示，包括单端转差分电路、信号衰减网络、差分放大器、PGA、低通滤波器和ADC的情况下，将单端转差分电路、信号衰减网络、差分放大器、PGA、低通滤波器和ADC集成在一个芯片上。可选的，在无线信号接收机如图18所示，包括单端转差分电路、信号衰减网络、差分放大器、用于共模抑制的缓冲器、PGA、低通滤波器和ADC的情况下，将单端转差分电路、信号衰减网络、差分放大器、用于共模抑制的缓冲器、PGA、低通滤波器和ADC集成在一个芯片上。在图17和图18中，无线信号接收机进一步耦合至解调器。可选地， 无线信号接收机可以进一步与解调器集成。
本申请实施例的无线信号接收机可以应用于数字电视全频带接收(full band capture，FBC)的全集成芯片技术中。具体的，本申请实施例的无线信号接收机支持数字有线电视广播(digital video broadcasting-C，DVB-C)、数字地面无线电视广播DVB-T、数字卫星电视广播DVB-S协议下的数字电视信号的接收。
如图19所示，本申请实施例的另一种无线信号接收机的结构示意图。具体的，无线信号接收机包括单端转差分电路、衰减网络、差分放大器和用于共模抑制的缓冲器。其中，单端转差分电路用于将无线信号转换为第一差分信号，并将第一差分信号输入到衰减网络。衰减网络用于对第一差分信号进行衰减，得到第二差分信号，并将第二差分信号输入到差分放大器。差分放大器用于对第二差分信号进行放大，得到第三差分信号，并将第三差分信号输入到缓冲器。缓冲器用于对所述第三差分信号进行处理，得到第四差分信号。
本申请实施例中衰减网络可以为电阻衰减网络，例如现有技术的图1所示的π型电阻衰减网络、或图2所示的T型电阻衰减网络，也可以为本申请实施例中涉及的信号衰减网络，对此不作限定。因此，图15可以被视为是图19的一种具体示例。
在本申请实施例中，单端转差分电路可以为无源巴伦，也可以为有源巴伦，对此不作限定。本申请实施例中的差分放大器可以为低噪放大器(low noise amplifier，LNA)等。
本申请实施例中的用于共模抑制的缓冲器的具体电路结构可以参见图16所示的缓冲器的电路结构，在此不再赘述。需要说明的是，本申请实施例不限定用于共模抑制的缓冲器的电路结构。图16仅为一种示例说明，不构成对本申请实施例的限定。本申请实施例中用于共模抑制的缓冲器还可以为其他的电路结构，比如通过类似示例的交叉耦合或全差分电路实现的高共模抑制结构，只要满足通过共模抑制消除差分信号的不平衡即可。
本申请实施例中差分放大器和用于共模抑制的缓冲器可以为两个独立的器件。为了提高集成度，差分放大器和用于共模抑制的缓冲器可以被集成在一个器件上。
应理解，本申请实施例中的无线信号接收机不限于包括上述部件，还可以包括PGA、低通滤波器、ADC等。为了提高无线信号接收的集成度，可选的，无线信号接收机集成在一个芯片上。可选地，无线信号接收机可以进一步与解调器集成。
本申请实施例的无线信号接收机可以应用于数字电视FBC的全集成芯片技术中。具体的，本申请实施例的无线信号接收机支持DVB-C、DVB-T、DVB-S协议下的数字电视信号的接收。
本申请的各实施方式可以任意进行组合，以实现不同的技术效果。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种信号衰减网络，其特征在于，所述信号衰减网络包括电阻衰减网络和与所述电阻衰减网络相耦合的补偿电容；
    所述电阻衰减网络包括第一差分输入端、第一差分输出端、第一电阻网络、第二电阻网络和第三电阻网络；所述第一差分输入端包括第一输入端和第二输入端，所述第一差分输出端包括第一输出端和第二输出端；
    所述第一电阻网络耦合在所述第一输入端和所述第一输出端之间，所述第二电阻网络耦合在所述第二输入端和所述第二输出端之间，所述第三电阻网络耦合在所述第一电阻网络和所述第二电阻网络之间；
    所述补偿电容，耦合在所述第一电阻网络和所述第二电阻网络之间，用于对所述电阻衰减网络的寄生电容做补偿。
  2. 如权利要求1所述的信号衰减网络，其特征在于，所述第一电阻网络包括第一电阻，所述第二电阻网络包括第二电阻，所述第三电阻网络包括第三电阻、第四电阻、第五电阻和第六电阻；
    所述第三电阻和所述第四电阻耦合在所述第一输入端和所述第二输入端之间、且所述第三电阻和第四电阻串联；所述第五电阻和所述第六电阻耦合在所述第一输出端和所述第二输出端之间、且所述第五电阻和所述第六电阻串联。
  3. 如权利要求1所述的信号衰减网络，其特征在于，所述第一电阻网络包括第一电阻和第二电阻，所述第二电阻网络包括第三电阻和第四电阻，所述第三电阻网络包括第五电阻和第六电阻；
    所述第一电阻和所述第二电阻耦合在所述第一输入端和所述第一输出端之间、且所述第一电阻和所述第二电阻经由第一节点相串联；所述第三电阻和所述第四电阻耦合在所述第二输入端和所述第二输出端之间、且所述第三电阻和所述第四电阻经由第二节点相串联；所述第五电阻和所述第六电阻耦合在所述第一节点和第二节点之间、且所述第五电阻和所述第六电阻串联。
  4. 如权利要求1至3任一所述的信号衰减网络，其特征在在于，所述补偿电容包括第一电容和第二电容；所述第一电容耦合在所述第一输入端和所述第二输出端之间；所述第二电容耦合在所述第二输入端和所述第一输出端之间。
  5. 如权利要求3所述的信号衰减网络，其特征在在于，所述补偿电容包括第三电容和第四电容；所述第三电容耦合在所述第一输入端和所述第二节点之间；所述第四电容耦合在所述第二输入端和所述第一节点之间。
  6. 如权利要求3或5所述的信号衰减网络，其特征在于，所述补偿电容包括第五电容和第六电容；所述第五电容耦合在第二节点和第一输出端之间，所述第六电容耦合在第一节点和第二输出端之间。
  7. 如权利要求1至6任一所述的信号衰减网络，其特征在于，所述信号衰减网络还包括接地电容；
    所述接地电容耦合至所述第三电阻网络的共模点。
  8. 一种无线信号接收机，其特征在于，包括单端转差分电路、如权利要求1至7任一所述的信号衰减网络和差分放大器；
    所述单端转差分电路，用于将无线信号转换为第一差分信号，并将所述第一差分信号输入到所述信号衰减网络；
    所述信号衰减网络，用于对所述第一差分信号进行衰减，得到第二差分信号，并将所述第二差分信号输入到所述差分放大器；
    所述差分放大器，用于对所述第二差分信号进行放大，得到第三差分信号。
  9. 如权利要求8所述的无线信号接收机，其特征在于，还包括用于共模抑制的缓冲器；
    所述缓冲器，用于对所述第三差分信号进行处理，得到第四差分信号。
  10. 如权利要求8或9所述的无线信号接收机，其特征在于，所述差分放大器和所述缓冲器被集成在同一个器件中。
  11. 如权利要求8至10中任一所述的无线信号接收机，其特征在于，所述缓冲器包括第二差分输入端、第二差分输出端、第七电容、第八电容、第九电容、第十电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述第二差分输入端包括第三输入端和第四输入端，所述第二差分输出端包括第三输出端和第四输出端；
    所述第七电容耦合在所述第三输入端和所述第一晶体管的栅极之间；所述第八电容耦合在所述第四输入端和所述第二晶体管的栅极之间；所述第九电容耦合在所述第四输入端和所述第三晶体管的栅极之间；所述第十电容耦合在所述第三输入端和所述第四晶体管的栅极之间；
    所述第一晶体管的漏极耦合至所述第二晶体管的漏极并耦合至电压源，所述第三晶体管的漏极耦合至所述第三输出端，所述第四晶体管的漏极耦合至所述第四输出端；
    所述第一晶体管的源极耦合至所述第三输出端，所述第二晶体管的源极耦合至所述第四输出端，所述第三晶体管的源极耦合至地，所述第四晶体管的源极耦合至地。
  12. 一种无线信号接收机，其特征在于，包括单端转差分电路、衰减网络、差分放大器和用于共模抑制的缓冲器；
    所述单端转差分电路，用于将无线信号转换为第一差分信号，并将所述第一差分信号输入到所述衰减网络；
    所述衰减网络，用于对所述第一差分信号进行衰减，得到第二差分信号，并将所述第二差分信号输入到所述差分放大器；
    所述差分放大器，用于对所述第二差分信号进行放大，得到第三差分信号，并将所述第三差分信号输入到所述缓冲器；
    所述缓冲器，用于对所述第三差分信号进行处理，得到第四差分信号。
  13. 如权利要求12所述的无线信号接收机，其特征在于，所述差分放大器和所述缓冲器被集成在同一个器件中。
  14. 如权利要求12或13所述的无线信号接收机，其特征在于，所述缓冲器包括差分输入端、差分输出端、第一电容、第二电容、第三电容、第四电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述差分输入端包括第一输入端和第二输入端，所述差分输出端包括第一输出端和第二输出端；
    所述第一电容耦合在所述第一输入端和所述第一晶体管的栅极之间；所述第二电容耦 合在所述第二输入端和所述第二晶体管的栅极之间；所述第三电容耦合在所述第二输入端和所述第三晶体管的栅极之间；所述第四电容耦合在所述第一输入端和所述第四晶体管的栅极之间；
    所述第一晶体管的漏极耦合至所述第二晶体管的漏极并耦合至电压源，所述第三晶体管的漏极耦合至所述第一输出端，所述第四晶体管的漏极耦合至所述第二输出端；
    所述第一晶体管的源极耦合至所述第一输出端，所述第二晶体管的源极耦合至所述第二输出端，所述第三晶体管的源极耦合至地，所述第四晶体管的源极耦合至地。
PCT/CN2018/083105 2018-04-13 2018-04-13 一种信号衰减网络和无线信号接收机 WO2019196119A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2018/083105 WO2019196119A1 (zh) 2018-04-13 2018-04-13 一种信号衰减网络和无线信号接收机
CN201880084964.5A CN111543007A (zh) 2018-04-13 2018-04-13 一种信号衰减网络和无线信号接收机

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/083105 WO2019196119A1 (zh) 2018-04-13 2018-04-13 一种信号衰减网络和无线信号接收机

Publications (1)

Publication Number Publication Date
WO2019196119A1 true WO2019196119A1 (zh) 2019-10-17

Family

ID=68163841

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/083105 WO2019196119A1 (zh) 2018-04-13 2018-04-13 一种信号衰减网络和无线信号接收机

Country Status (2)

Country Link
CN (1) CN111543007A (zh)
WO (1) WO2019196119A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101599759A (zh) * 2008-06-06 2009-12-09 阿尔特拉公司 高数据率hssi接收器中的增强灵敏度和降低偏移变化
CN102790595A (zh) * 2011-05-20 2012-11-21 杭州中科微电子有限公司 一种单端转差分增益可配置射频宽带增益放大器
CN102916666A (zh) * 2011-08-02 2013-02-06 中国科学院微电子研究所 一种宽带可编程增益放大器
US20130043962A1 (en) * 2011-08-17 2013-02-21 Rf Micro Devices, Inc. Digital step attenuator utilizing thermometer encoded multi-bit attenuator stages
CN107005216A (zh) * 2014-12-03 2017-08-01 瑞典爱立信有限公司 衰减器

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7123070B2 (en) * 2004-05-24 2006-10-17 Industrial Technology Research Institute (Itri) High frequency gain amplifier with phase compensation circuit
CN100488039C (zh) * 2004-07-20 2009-05-13 华为技术有限公司 热敏衰减器及无线收发信机
US7162375B2 (en) * 2005-02-04 2007-01-09 Tektronix, Inc. Differential termination and attenuator network for a measurement probe having an automated common mode termination voltage generator
CN101079606A (zh) * 2007-04-18 2007-11-28 阎跃军 微带分段可变衰减器
US7848713B2 (en) * 2007-09-10 2010-12-07 Qualcomm Incorporated Common mode signal attenuation for a differential duplexer
CN101546992B (zh) * 2008-03-29 2011-10-26 华为技术有限公司 一种滤波方法及滤波器
US8022785B2 (en) * 2008-12-03 2011-09-20 Arcom Digital, Llc Step attenuator circuit with improved insertion loss
CN102811050B (zh) * 2012-08-01 2015-01-21 华为技术有限公司 一种缓冲器和数字步进衰减器
CN103427780B (zh) * 2013-08-31 2016-01-20 西安电子科技大学 半分布式无源可变衰减器
CN104052710B (zh) * 2014-06-24 2017-07-14 华为技术有限公司 数字发射机的调制电路、数字发射机和信号调制方法
US9634650B2 (en) * 2015-06-26 2017-04-25 Peregrine Semiconductor Corporation State change stabilization in a phase shifter/attenuator circuit
US10333495B2 (en) * 2015-07-10 2019-06-25 Qorvo Us, Inc. Compensated programmable RF attenuator
CN104953975B (zh) * 2015-07-12 2017-10-17 北京理工大学 一种桥式差分无源衰减器
US9531359B1 (en) * 2015-10-08 2016-12-27 Peregrine Semiconductor Corporation Multi-state attenuator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101599759A (zh) * 2008-06-06 2009-12-09 阿尔特拉公司 高数据率hssi接收器中的增强灵敏度和降低偏移变化
CN102790595A (zh) * 2011-05-20 2012-11-21 杭州中科微电子有限公司 一种单端转差分增益可配置射频宽带增益放大器
CN102916666A (zh) * 2011-08-02 2013-02-06 中国科学院微电子研究所 一种宽带可编程增益放大器
US20130043962A1 (en) * 2011-08-17 2013-02-21 Rf Micro Devices, Inc. Digital step attenuator utilizing thermometer encoded multi-bit attenuator stages
CN107005216A (zh) * 2014-12-03 2017-08-01 瑞典爱立信有限公司 衰减器

Also Published As

Publication number Publication date
CN111543007A (zh) 2020-08-14

Similar Documents

Publication Publication Date Title
JP5420638B2 (ja) 高度に線形な埋込みフィルタリングパッシブミキサ
US7372335B2 (en) Wideband circuits and methods
US8629723B2 (en) Low noise amplifier including a single-ended input
EP1875605B1 (en) Differential inductor based low noise amplifier
KR102262208B1 (ko) 잡음 제거기를 구비한 저항성 광대역 저잡음 증폭기
CN107809220B (zh) 低噪声放大器、射频集成电路、信号接收模块及射频收发芯片
US9673769B2 (en) Variable gain circuit and tuner system provided with same
JP2009207031A (ja) 増幅回路
WO2019196119A1 (zh) 一种信号衰减网络和无线信号接收机
KR101719313B1 (ko) 멀티밴드를 위한 고선형 특성을 갖는 저잡음 증폭기
CN101378248A (zh) 低噪声放大器以及包括该低噪声放大器的调谐器
CN111903119B (zh) 一种全频带接收机和电视调谐器
JP2009519657A (ja) 拡張ミキサー装置
WO2013175681A1 (ja) ダイレクトコンバージョン方式の受信機
US11606069B2 (en) Single-ended-to-differential amplifier and radio frequency receiver
Alzaher et al. Dual-mode bluetooth/wireless local area network channel-select filter for direct conversion receivers
Takamatsu et al. A tunable low-noise amplifier for digital TV applications
US20170373710A1 (en) Wireless communication receiver
Zheng et al. A Blocker-Tolerant Receiver With+ 20dBm IIP3, 13.7 MHz-BB-BW and< 3.5 dB NF for SAW-Less sub-6GHz applications
US20070298740A1 (en) Fm radio receiver
CN114827508A (zh) 环通输出电路、电视调谐器和射频接收系统
Choi et al. A Feedback Wideband CMOS LNA Employing Active Inductor-Based Bandwidth Extension Technique
Tekin et al. A Low Noise, Low Distortion Radio Design
JP2009188672A (ja) 増幅器、半導体装置、および通信装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18914396

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18914396

Country of ref document: EP

Kind code of ref document: A1