WO2019157992A1 - 一种cmos高温基准电压源 - Google Patents

一种cmos高温基准电压源 Download PDF

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WO2019157992A1
WO2019157992A1 PCT/CN2019/074472 CN2019074472W WO2019157992A1 WO 2019157992 A1 WO2019157992 A1 WO 2019157992A1 CN 2019074472 W CN2019074472 W CN 2019074472W WO 2019157992 A1 WO2019157992 A1 WO 2019157992A1
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circuit
nmos
resistor
nmos transistor
impedance circuit
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PCT/CN2019/074472
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English (en)
French (fr)
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陈乐峰
陆文正
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杭州芯元微电子有限公司
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature

Definitions

  • the present invention relates to CMOS voltage sources, and more particularly to a CMOS high temperature reference voltage source.
  • ADCs and digital-to-analog converter DACs it is essential to implement a high-temperature reference in a standard CM
  • FIG. 1 is a schematic diagram of a conventional bandgap reference circuit.
  • the conventional bandgap reference circuit includes resistors R1, R2, and R3, two transistors Q1 and Q2, two PMOS transistors MP1 and MP2, and a transconductance operational amplifier OTA1.
  • the reference voltage Vref is outputted between -40 ° C and 150 ° C by the conventional band gap reference circuit shown in FIG. 1 .
  • Figure 2 is a graph showing the reference voltage and temperature variation of a conventional bandgap reference circuit. As shown in Figure 2, the reference voltage and temperature variation of the conventional bandgap reference circuit is stable between -40 ° C and 150 ° C; when approaching 150 ° C, the reference voltage variation becomes very significant.
  • the embodiment of the present invention does not adopt a BJT-based bandgap Bandgap reference architecture.
  • a MOSFET and a resistor are used, and a wide range expansion is achieved by binary weighted combination up to 230 ° C. Ultra high temperature environment.
  • Embodiments of the present invention provide a CMOS high temperature reference voltage source.
  • the CMOS high-temperature reference voltage source includes: a bias circuit that provides a bias current at an output terminal; a reference core circuit including: a first PMOS transistor whose source is connected to a power supply, a gate connected to an output of the bias circuit; and a low-dropout linearity a voltage regulator coupled between the drain of the first PMOS transistor and the ground; the first voltage dividing circuit, in parallel with the low dropout linear regulator, comprising a first impedance circuit and a second impedance circuit connected in series with each other;
  • the first impedance circuit includes a first MOS transistor;
  • the second impedance circuit includes a plurality of second MOS transistors that are selectively turned on and off under the control of the switch, and the number of the second MOS transistors that are turned on and off can be determined according to a temperature change;
  • a first node between an impedance circuit and a second impedance circuit provides a first
  • the first MOS transistor is a first NMOS transistor; the first impedance circuit further includes: a first resistor; wherein a source of the first NMOS transistor is connected to a first end of the first resistor The gate of the first NMOS transistor is connected to the second end of the first resistor.
  • the plurality of second MOS tubes are connected in parallel with each other.
  • the plurality of second MOS transistors are n second NMOS transistors
  • the second impedance circuit further includes: n switches respectively coupled between the gates and the sources of the n second NMOS transistors, N reverse switches are coupled between the gate and the drain of the n second NMOS transistors, respectively.
  • the reference core circuit further comprises: a second voltage dividing circuit, in parallel with the low dropout linear regulator, comprising a third impedance circuit and a fourth impedance circuit connected in series with each other; wherein the third impedance circuit comprises a third MOS
  • the fourth impedance circuit includes a plurality of fourth MOS transistors that are selectively turned on and off under the control of the switch, and the number of the fourth MOS transistors that are turned on and off can be determined according to the temperature change; the third voltage dividing circuit is coupled in the first A voltage output and a second voltage output; a third node in the third voltage divider circuit provides a third voltage output.
  • the third MOS transistor is a third NMOS transistor; the third impedance circuit structure further includes a second resistor; wherein a source of the third NMOS transistor is connected to the first end of the second resistor The gate of the third NMOS transistor is connected to the second end of the second resistor.
  • the plurality of fourth MOS tubes are connected in parallel with each other.
  • the plurality of fourth MOS transistors are n fourth NMOS transistors;
  • the fourth impedance circuit comprises: n second switches respectively coupled between the gate and the source of the n fourth NMOS transistors And n second reverse switches respectively coupled between the gate and the drain of the n fourth NMOS transistors.
  • the third voltage dividing circuit includes a third resistor and a fourth resistor connected in series; the third node is located between the third resistor and the fourth resistor.
  • the first NMOS transistor is a depletion mode NMOS transistor
  • the n second NMOS transistors are enhancement type NMOS transistors.
  • the third NMOS transistor is a depletion mode NMOS transistor
  • the n fourth NMOS transistors are enhancement type NMOS transistors.
  • Vtn is a threshold voltage of the first NMOS transistor
  • Vtx is a threshold voltage of n second NMOS transistors
  • a control coefficient K is determined by parameters of the first NMOS transistor and the n second NMOS transistor materials , specifically
  • Wn is the width of the first NMOS transistor
  • Ln is the length of the first NMOS transistor
  • Un is the mobility of the first NMOS transistor
  • Cox is the MOS transistor oxide capacitance
  • Wx is the second NMOS transistor
  • the width, Lx is the length of the second NMOS transistor
  • Ux is the mobility of the second NMOS transistor
  • m is the number selected by the n second NMOS transistors.
  • Embodiments of the present invention utilize a reference weighted architecture of binary weighted combination MOSFETs and resistors through a reference core circuit to achieve a low temperature coefficient voltage reference that extends over a wide range to 230 °C.
  • the architecture features high power supply noise rejection, low output noise and low operating temperature coefficient in the simulation, such as -40 ° C ⁇ 230 ° C.
  • FIG. 1 is a schematic diagram of a conventional bandgap reference circuit
  • FIG. 2 is a graph showing a reference voltage and temperature variation of a conventional bandgap reference circuit
  • FIG. 3 is a schematic diagram of a CMOS high-temperature reference voltage source circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of another CMOS high temperature reference voltage source circuit according to an embodiment of the present invention.
  • FIG. 5 is a graph of reference voltage and temperature changes shown in FIG. 4.
  • FIG. 5 is a graph of reference voltage and temperature changes shown in FIG. 4.
  • FIG. 3 is a schematic diagram of a CMOS high temperature reference voltage source circuit implemented in accordance with one embodiment of the present invention.
  • the CMOS high temperature reference circuit includes a start circuit and a bias circuit for properly biasing the reference core circuit.
  • the startup circuit includes a PMOS transistor P1, a PMOS transistor P2, and three NMOS transistors N1, N2, and N3.
  • the three NMOS transistors are sequentially connected in sequence, the source of N1 is connected to the drain of N2, and the source of N2 is connected.
  • the drain of the N3, the source of N3 is grounded or the power supply VSS, the source of P1 is connected to the power supply VDD, the drain is connected to the drain of N1, the source of P2 is connected to the power supply VDD, and the drain is connected to the bias circuit.
  • the gate of P1 is connected to its own drain, the gate of three NMOS transistors is connected to its own drain, and the gate of P2 is connected to the drain of P1.
  • P1, N1, N2, and N3 are shorted by the gate drain and have diode unidirectional conduction characteristics.
  • VDD voltage
  • P1, N1, N2 and N3 are turned on accordingly, so the P2 gate voltage is gradually increased; when the P2 gate reaches the conduction condition, the P2 is conducted. Pass, give the bias circuit a starting current.
  • NMOS transistors in the startup circuit can be arbitrarily selected according to the corresponding requirements without affecting the normal operation of the bias circuit.
  • a bias circuit is used to provide a bias current to the reference core circuit.
  • the bias circuit includes a PMOS transistor P3, a PMOS transistor M3, an NMOS transistor M1, an NMOS transistor M2, and a resistor RB.
  • the sources of P3 and M3 are connected to VDD, and the gates are connected in common.
  • the drain of P3 is connected to the drain of M2, the drain of M3 is connected to the drain of M1, the gate of M3 is connected to the gate of M1, the gate of M2 is also connected to its own drain, and the gate of M3 is also with itself.
  • the drain is connected, the source of M2 is connected to VSS, the source of M1 is connected to one end of resistor RB, and the other end of RB is connected to VSS.
  • the gate of M3 acts as the output of the bias circuit and is connected to the reference core circuit.
  • the gate voltage of M2 gradually rises, making M2 conductive. Since M1 and M2 form the first current mirror, M3 and M4 in the reference core circuit form a second current mirror, and the bias circuit generates a bias current IB at the branch where M2 is located, and M1 mirrors the bias current IB of M2.
  • the bias current IB is calculated by dividing the difference between the gate and source voltages Vgs of M1 and M2 by the resistance of RB. Then, a bias current is transmitted to the reference core circuit through a second current mirror composed of M3 and M4.
  • the reference core circuit specifically includes: a first PMOS transistor M4, a low dropout linear regulator LDO, a first impedance circuit and a second impedance circuit connected in series; wherein the first PMOS transistor M4 is connected to the power source VDD, the gate The bias circuit is connected, and one end of the first impedance circuit and the second impedance circuit connected in series with each other is connected to the drain of the first PMOS transistor M4, and the other end is connected to the ground or the power source VSS.
  • the first impedance circuit and the second impedance circuit form a first voltage dividing circuit
  • the first impedance circuit is implemented by a MOS tube
  • the second impedance circuit is implemented by a plurality of MOS tubes
  • the plurality of MOS tubes can be changed by temperature, by a plurality of switches The switching is selected separately, and the node between the first impedance circuit and the second impedance circuit provides a first voltage output.
  • the first impedance circuit may be: a first NMOS transistor Mn1 and a first resistor R1; the second impedance circuit may be: n switches, n reverse switches, and n NMOS transistors Mx1 to Mxn Composition.
  • the first NMOS transistor Mn1 may be a depletion mode NMOS transistor, and the n NMOS transistors Mx1 M Mxn may be enhancement NMOS transistors. Depletion and enhancement are similar in temperature characteristics, but their Vth is positive and negative and may be offset.
  • the source of the PMOS transistor M4 is connected to the power supply VDD, the gate receives the bias voltage of the bias circuit, the drain is connected to one end of the LDO, and the other end of the LDO is connected to VSS.
  • the drain of M4 is also connected to the drain of Mn1, the source of Mn1 is connected to the first end of R1, and the second end of R1 is connected to the corresponding first end of n reverse switches Sx1N ⁇ SxnN, and n
  • the drains of the enhancement type NMOS transistors Mx1 to Mxn are connected.
  • the second ends of the n reverse switches are connected to the gates of the n enhancement NMOS transistors Mx1 to Mxn, and the sources of the n enhancement NMOS transistors Mx1 to Mxn are connected to VSS.
  • the gate of each of the n enhancement type NMOS transistors Mx1 to Mxn is also connected to one end of a corresponding one of the n switches Sx1 to Sxn, and the other end of each of the n switches Sx1 to Sxn Connected to VSS.
  • first NMOS transistor Mn1 and the first resistor R1 constitute a first impedance circuit for realizing voltage division.
  • other equivalent circuits may also be substituted.
  • the reference core circuit controls n NMOS transistors Mx1 to Mxn through switches Sx1 to Sxn and reverse switches Sx1N to SxnN for coarsely adjusting the temperature coefficient.
  • the reference current IREF flowing out of the PMOS transistor M4 is equal to a times IB.
  • the value of a is determined by the voltage value and driving capability of the reference core circuit. In one embodiment, a can take a value of 2, 3 or 4.
  • the reference current IREF is used to provide a stable current that is not affected by temperature to the reference core circuit, ensuring overall stability and accuracy when the circuit is operating.
  • the output reference voltage VREF is determined by the magnitude of Mn1 and the size of the n enhancement NMOS transistors Mx1 to Mxn and their threshold voltages.
  • R1 can be set to zero.
  • resistor R1 is used to fine tune the temperature coefficient.
  • R1 acts as a trimming resistor for fine-tuning the temperature coefficient of VREF.
  • R1 can be a programmable resistor or use various types of resistors.
  • Vtn is a threshold voltage of Mn1
  • Vtx is a threshold voltage of Mx1 to Mxn, where Vtn ⁇ 0 and Vtx>0.
  • Wn is the width of Mn1
  • Ln is the length of Mn1.
  • Wx is the width of Mx1 to Mxn, and Lx is the length of Mx1 to Mxn.
  • Un is the mobility of Mn1
  • Ux is the mobility of Mx1 to Mxn.
  • Vgsx is the gate source voltage of Mx1 to Mxn
  • Ids is the drain source current of Mn. Therefore, the reference voltage VREF1 is
  • Cox is the MOS tube oxide layer capacitance
  • m is the number selected from Mx1 to Mxn, that is, the number of switches Sx1 to Sxn are turned on.
  • the reference voltage VREF1 is linearly determined by the threshold voltage of Mn1 and the threshold voltage of Mx1 to Mxn.
  • the K value can be reduced, which is equivalent to the increase of Kx, and the number m of Mx1 to Mxn increases, which means that more Mx needs to be selected, and VREF will be positively biased.
  • the K value can be increased, which is equivalent to the decrease of Kx. Selecting more MOS transistors is disconnected, so that the temperature coefficient is lowered and VREF is negatively biased.
  • the temperature coefficient can be adjusted under different temperature ranges, so that the reference voltage source can provide a stable reference voltage.
  • the above circuit can be adapted to the operating range of -40 ° C to 125 ° C. Under different temperature working conditions, the temperature coefficient is adjusted by adjusting the opening of the MOS tube.
  • the above reference core circuit can be based on CMOS silicon bulk or SOI processes.
  • the first item It still exists, especially in the wide temperature range, which still affects the temperature coefficient.
  • FIG. 4 is a schematic diagram of another CMOS high temperature reference voltage source circuit according to an embodiment of the present invention.
  • temperature dependent compensation requires a complementary temperature coefficient reference circuit in the range of -40 ° C to 200 ° C.
  • a temperature coefficient reference circuit is added to the basis of FIG.
  • the reference core circuit further includes: a third resistor R3, a fourth resistor R4, a third impedance circuit and a fourth impedance circuit connected in series with each other; wherein the third impedance circuit connected in series with each other and one end of the third impedance circuit of the fourth impedance circuit It is connected to the drain of the first PMOS transistor M4, and the other end is connected to the ground or the power source VSS.
  • the third impedance circuit and the fourth impedance circuit form a second voltage dividing circuit
  • the third impedance circuit is implemented by a MOS tube
  • the fourth impedance circuit is implemented by a plurality of MOS tubes
  • the plurality of MOS tubes can be changed according to temperature
  • the switches are respectively selected to be turned on and off, and the node between the third impedance circuit and the fourth impedance circuit provides a second voltage output.
  • the third resistor R3 and the fourth resistor R4 are connected in series between the first voltage output and the second voltage output, and the node between the third resistor R3 and the fourth resistor R4 provides a third voltage output.
  • the third impedance circuit structure may be: a second NMOS transistor Mn2 and a second resistor R2; and the fourth impedance circuit may be: n switches Sy1 to Syn, n reverse switches Sy1N to SynN and n NMOS tubes My1 to Myn connected in parallel with each other.
  • the drain of the depletion mode NMOS transistor Mn2 is connected to the drain of M4.
  • the source of Mn2 is connected to the first end of the second resistor R2, the second end of R2 is connected to the drains of the n enhancement NMOS tubes My1 to yn, and the second end of R2 is also connected with n reverse switches Sy1N ⁇
  • the first end of the corresponding switch in the SynN is connected, and the second end of the corresponding switch of the n reverse switches Sy1N to SynN is connected to the gate of each of the n enhanced NMOS transistors My1 to Myn.
  • the source of each of the n enhancement NMOS transistors My1 to Myn is connected to VSS.
  • each of the n enhanced NMOS transistors My1 to Myn is also connected to one end of a corresponding one of the n switches Sy1 to Syn, and the other end of each of the n switches Sy1 to Syn Connected to VSS.
  • the switches Sy1 to Syn are turned on, the switches in the corresponding reverse switches Sy1N to SynN are closed, and vice versa.
  • the resistors R3 and R4 are connected in series between VREF1 and VREF2, and the weighted VREF_ZERO reference voltage is output between resistors R3 and R4.
  • Mn1 and Mn2 are depletion mode NMOS transistors whose threshold voltage is greater than 0;
  • Mx1 to Mxn and My1 to Myn are enhancement type NMOS transistors whose threshold voltage is less than zero.
  • R1, R2 may be set to zero for ease of calculation.
  • resistors R1 and R2 are used to fine tune the temperature coefficient.
  • R1 and R2 act as trimmer resistors to fine tune the temperature coefficient of VREF.
  • R1 and E2 can be programmable resistors or use various types of resistors.
  • the temperature coefficient of VREF2 is obtained by selecting K2, which is complementary to VREF and VREF2 as compensation for the VREF temperature coefficient.
  • the temperature coefficient fluctuation of VREF_ZERO can be minimized so that a smooth low temperature coefficient can be achieved over a wide temperature range.
  • the final reference voltage VREF_ZERO is appropriately weighted by R3 and R4 to become a linear combination of VREF1 and VREF2, so that the temperature coefficient Becomes evener. This achieves a reference voltage with a very low temperature coefficient and a high temperature range.
  • VREF_ZERO can be widely used in high temperature ADCs and DACs.
  • more Mn can be selected in parallel depending on the requirements. Not shown in the figure.
  • q is the number of Mns connected in parallel.
  • the number q of Mn and the number m of Mx1 to Mxn may be different, and the difference is the value used as the trimming temperature coefficient.
  • FIG. 5 is a graph of reference voltage and temperature changes shown in FIG. 4.
  • FIG. 5 is a graph of reference voltage and temperature changes shown in FIG. 4.

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Abstract

一种CMOS高温基准电压源，电压源包括：基准核心电路，基准核心电路具体包括：第一PMOS管M4、低压差线性稳压器LDO、彼此串联的第一阻抗电路和第二阻抗电路；还包括：第三电阻R3、第四电阻R4、彼此串联的第三阻抗电路和第四阻抗电路，通过基准核心电路，采用二进制加权组合MOSFET和电阻器的参考电压架构，以实现大范围扩展至230℃的低温度系数电压基准，该架构在模拟中具有高电源噪声抑制，低输出噪声和低工作温度系数，如-40℃～230℃。

Description

一种CMOS高温基准电压源 技术领域
本发明涉及CMOS电压源，尤其是涉及一种CMOS高温基准电压源。
背景技术
传统上，COMS硅体工艺可以在-40℃至150℃的温度范围内广泛使用。当工作在额外更高的电压下将导致那些小的带隙器件产生异常操作，例如硅体带隙器电压＝1.12eV。为了满足150℃以上的使用，人们选择其他更高带隙的工艺，如SiGe(带隙＝3.2eV)。在标准的CMOS工艺(包括硅块或者SOI)中，针对150℃或更高的设计目标，特别是对于那些基于BJT的带隙基准电压源，很少有解决方案。当温度高于150℃时，由于泄露和发射极低效率，BJT极有可能失效。因此，对于模数转换器ADC和数模转换器DAC来说，在标准CMOS工艺中实现高温基准电压源是必不可少的。
图1为传统带隙参考电路示意图。如图1所示，传统带隙参考电路包括电阻R1、R2和R3，两个三极管Q1和Q2，两个PMOS管MP1和MP2，还有一个跨导运算放大器OTA1。通过图1所示的传统带隙参考电路，使得参考电压Vref在-40℃至150℃之间输出基准电压。
图2为传统带隙参考电路参考电压与温度变化曲线图。如图2所示，传统带隙参考电路参考电压与温度变化在-40℃至150℃之间曲线平稳；当接近150℃时，参考电压变化变得十分明显。
发明内容
本发明实施例没有采用基于BJT的带隙Bandgap参考架构，没有BJT的 参考电路，不需要任何BJT器件，而是使用MOSFET和电阻器，通过二进制加权组合，实现大范围扩展直至230℃，应用于超高温的环境。
本发明实施例提供一种CMOS高温基准电压源。该CMOS高温基准电压源包括：偏置电路，在输出端提供偏置电流；基准核心电路，包括：第一PMOS管，其源极连接电源，栅极连接偏置电路的输出端；低压差线性稳压器，耦合在所述第一PMOS管的漏极与地之间；第一分压电路，与低压差线性稳压器并联，包括彼此串联的第一阻抗电路和第二阻抗电路；其中，第一阻抗电路包括第一MOS管；第二阻抗电路包括分别在开关的控制下选择通断的多个第二MOS管,且通断的第二MOS管的数量可以根据温度变化确定；第一阻抗电路和第二阻抗电路之间的第一节点提供第一电压输出。
优选地，第一MOS管是第一NMOS管；所述第一阻抗电路还包括：第一电阻器；其中，所述第一NMOS管的源极与所述第一电阻器的第一端相连，所述第一NMOS管的栅极与所述第一电阻器的第二端相连。
优选地，所述多个第二MOS管彼此并联。
优选地，所述多个第二MOS管是n个第二NMOS管，所述第二阻抗电路还包括：分别耦合在n个第二NMOS管的栅极和源极之间的n个开关、分别耦合在n个第二NMOS管的栅极和漏极之间的n个反向开关。
优选地，所述基准核心电路还包括：第二分压电路，与低压差线性稳压器并联，包括彼此串联的第三阻抗电路和第四阻抗电路；其中，第三阻抗电路包括第三MOS管；第四阻抗电路包括分别在开关的控制下选择通断的多个第四MOS管实现,且通断的第四MOS管的数量可以根据温度变化确定；第三分压电路，耦合在第一电压输出和第二电压输出之间；第三分压电路中的第三节点提供第三电压输出。
优选地，第三MOS管是第三NMOS管；所述第三阻抗电路结构还包括第二电阻器；其中，所述第三NMOS管的源极与所述第二电阻器的第一端相连，所述第三NMOS管的栅极与所述第二电阻器的第二端相连。
优选地，所述多个第四MOS管彼此并联。
优选地，所述多个第四MOS管是n个第四NMOS管；所述第四阻抗电路包括：分别耦合在n个第四NMOS管的栅极和源极之间的n个第二开关、分别耦合在n个第四NMOS管的栅极和漏极之间的n个第二反向开关。
优选地，第三分压电路包括串联的第三电阻和第四电阻；第三节点位于所述第三电阻和所述第四电阻之间。
优选地，所述第一NMOS管为耗尽型NMOS管，所述n个第二NMOS管为增强型NMOS管。
优选地，所述第三NMOS管为耗尽型NMOS管，所述n个第四NMOS管为增强型NMOS管。
优选地，通过选择控制系数K，使得
Figure PCTCN2019074472-appb-000001
其中，Vtn为所述第一NMOS管的阈值电压，Vtx为n个第二NMOS管的阈值电压；控制系数K由所述第一NMOS管和所述n个第二NMOS管材料的参数共同决定，具体为
Figure PCTCN2019074472-appb-000002
其中
Figure PCTCN2019074472-appb-000003
Figure PCTCN2019074472-appb-000004
Wn为所述第一NMOS管的宽度，Ln为所述第一NMOS管的长度，Un为所述第一NMOS管的迁移率，Cox为MOS管氧化层电容；Wx为所述第二NMOS管的宽度，Lx为所述第二NMOS管的长度，Ux为所述第二NMOS管的迁移率；m为所述n个第二NMOS管选中的个数。
本发明实施例通过基准核心电路，采用二进制加权组合MOSFET和电阻器的参考电压架构，以实现大范围扩展至230℃的低温度系数电压基准。该架构 在模拟中具有高电源噪声抑制，低输出噪声和低工作温度系数，如-40℃～230℃。
附图说明
图1为传统带隙参考电路示意图；
图2为传统带隙参考电路参考电压与温度变化曲线图；
图3为本发明实施例提供的一种CMOS高温基准电压源电路示意图；
图4为本发明实施例提供的另一种CMOS高温基准电压源电路示意图；
图5为图4所示的参考电压与温度变化曲线图。
具体实施方式
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
图3为根据本发明一个实施例实现的一种CMOS高温基准电压源电路示意图。
如图3所示，CMOS高温基准电压源电路包括启动电路和偏置电路，用于正确偏置基准核心电路。其中，启动电路用于启动偏置电路，使得该电路在电源上电时，能驱动电路摆脱简并偏置点，正常启动并稳定工作，防止偏置电路工作点在偏置电流IB＝0的状态。
在一个实施例中，启动电路包括PMOS管P1、PMOS管P2和3个NMOS管N1、N2、N3。3个NMOS管依次顺序连接，N1的源极连接N2的漏极，N2的源极连接第N3的漏极，N3的源极接地或电源VSS，P1的源极与电源VDD连接，漏极与N1的漏极相连，P2的源极与电源VDD连接，漏极与偏置电路相连，P1的栅极与自身的漏极相连，3个NMOS管的栅极与自身的漏极相连，P2的栅极与P1的漏极相连。
P1、N1、N2和N3通过栅极漏极短接，具有二极管单向导通特性。当电压VDD从0开始上升时当电压达到一定导通的电压时，P1、N1、N2和N3 相应导通，因此P2栅极电压逐步升高；当P2栅极达到导通条件后，P2导通，给偏置电路一个启动电流。
本领域技术人员应当注意，启动电路中NMOS管个数在不影响偏置电路正常工作情况下，可以根据相应需求任意选取。
偏置电路用于为参考核心电路提供偏置电流。在一个例子中，偏置电路包括：PMOS管P3、PMOS管M3、NMOS管M1、NMOS管M2和电阻器RB。P3和M3的源极接VDD，且栅极共联。P3的漏极与M2的漏极相连，M3的漏极与M1的漏极相连，M3与M1栅极共联，M2的栅极同时还与自身漏极相连，M3的栅极同时还与自身漏极相连，M2的源极接VSS，M1的源极接电阻器RB的一端，RB的另一端接VSS。M3的栅极作为偏置电路的输出，连接基准核心电路。
在启动电路提供启动电流后，M2的栅极电压逐渐升高，使得M2导通。由于M1和M2构成第一电流镜，M3和参考核心电路中的M4构成第二电流镜，偏置电路在M2所在支路产生偏置电流IB，M1镜像M2的偏置电流IB。当IB电流逐渐增大，M2的压降升高，P2的漏极电压升高，连接启动电路和偏置电路的P2就会关断。偏置电流IB由M1和M2的栅极源极电压Vgs的差值除以RB的阻值计算得到。然后，通过M3和M4构成的第二电流镜将偏置电流传输给基准核心电路。
本领域人员值得注意，上述启动电路和偏置电路在现有技术中有很多方法可以实现，在此不再赘述。
所述基准核心电路具体包括：第一PMOS管M4、低压差线性稳压器LDO、彼此串联的第一阻抗电路和第二阻抗电路；其中，第一PMOS管M4源极连接电源VDD，栅极连接偏置电路，彼此串联的第一阻抗电路和第二阻抗电路中所述第一阻抗电路的一端与所述第一PMOS管M4漏极相连，另一端与地或电源VSS连接。
第一阻抗电路和第二阻抗电路构成第一分压电路，第一阻抗电路由MOS 管实现,第二阻抗电路由多个MOS管实现,且多个MOS管可以根据温度变化,由多个开关分别选择通断,第一阻抗电路和第二阻抗电路之间的节点提供第一电压输出。
在一个实施例中，第一阻抗电路可以为：第一NMOS管Mn1和第一电阻器R1构成；第二阻抗电路可以为：n个开关、n个反向开关和n个NMOS管Mx1～Mxn构成。
其中，第一NMOS管Mn1可以为耗尽型NMOS管，n个NMOS管Mx1～Mxn可以为增强型NMOS管。耗尽型与增强型在温度特性上类似，但是它们的Vth有正有负，有可能相抵消。
PMOS管M4的源极连接电源VDD，栅极接收偏置电路的偏置电压，漏极连接LDO一端，LDO另一端接VSS。M4的漏极同时还连接Mn1的漏极，Mn1的源极连接R1的第一端，R1的第二端与n个反向开关Sx1N～SxnN中相对应的第一端连接，同时与n个增强型NMOS管Mx1～Mxn的漏极相连。n个反向开关的第二端与n个增强型NMOS管Mx1～Mxn的栅极相连，n个增强型NMOS管Mx1～Mxn的源极与VSS相连。n个增强型NMOS管Mx1～Mxn中的每个NMOS管的栅极同时还与n个开关Sx1～Sxn中相对应的开关的一端相连，n个开关Sx1～Sxn中的每个开关的另一端与VSS相连。
本领域人员值得注意的是，其中第一NMOS管Mn1和第一电阻器R1构成第一阻抗电路，为电路实现分压。在其它实施例中，还可以替换成其他等效电路。
基准核心电路通过开关Sx1～Sxn和反向开关Sx1N～SxnN控制n个NMOS管Mx1～Mxn，用以粗调温度系数。当开关Sx1～Sxn打开时，相对应的反向开关Sx1N～SxnN中的开关就会闭合，反之亦然。PMOS管M4流出的基准电流IREF等于a倍的IB。a的取值由基准核心电路的电压值与驱动能力决定。在一个实施例中,a可以取值为2、3或4。基准电流IREF用于给基准核心电路提供一个不受温度影响的稳定电流，保证电路工作时整体的稳定性和 精准度。输出的基准电压VREF由Mn1的大小以及n个增强型NMOS管Mx1～Mxn的大小和他们的阈值电压决定的。
为方便计算，可以将R1设置为0。在其他实施例中，电阻器R1用于微调温度系数。R1作为微调电阻，用于微调VREF的温度系数。Ids*R1本身相比Vref要小很多，比如Vref＝830mV,Ids*R1＝15mV；但是可以利用R1的正负温度特性来微调Vref最终的值，例如，Vref如果偏正温度特性，可选择负温度特性的电阻R1。本领域技术人员应当注意R1可以是可编程电阻器或者使用各种类型的电阻器。
Vtn为Mn1的阈值电压，Vtx为Mx1～Mxn的阈值电压，其中Vtn＜0且Vtx＞0。Wn为Mn1的宽度，Ln为Mn1的长度。Wx为Mx1～Mxn的宽度，Lx为Mx1～Mxn的长度。Un是Mn1的迁移率，Ux是Mx1～Mxn的迁移率。Vgsx为Mx1～Mxn的栅极源极电压，Ids为Mn的漏极源极电流。因此参考电压VREF1为
Figure PCTCN2019074472-appb-000005
其中
Kn＝UnCoxWnLn
Figure PCTCN2019074472-appb-000006
Cox为MOS管氧化层电容，m为Mx1～Mxn选中的个数，即开关Sx1～Sxn打开的个数。
令
Figure PCTCN2019074472-appb-000007
则
VREF1＝K(-Vtn)+Vtx
由此可见，参考电压VREF1由Mn1的阈值电压和Mx1～Mxn的阈值电压 线性决定。
所以VREF1的温度系数为
Figure PCTCN2019074472-appb-000008
可以看出，如果正确的选择K，那么后两项可以相互抵消。
当温度系数偏高时，可以减小K值，相当于Kx增大，Mx1～Mxn的个数m增大，也就意味着需要选择更多的Mx，VREF便会正偏。反之，当温度系数偏低时，可以增加K值，相当于Kx减小，选择断开更多的MOS管，使得温度系数下降，VREF便会负偏。
通过上述电路，可以实现在不同温度范围下，调节温度系数，使得基准电压源能够提供一个稳定的基准电压。上述电路可以适合于-40℃至125℃的工作范围。在不同温度工作环境下，通过调节MOS管的开启，实现调节温度系数。本领域技术人员应当注意，上述基准核心电路基于CMOS硅散装或者SOI工艺均可。
然而，第一项
Figure PCTCN2019074472-appb-000009
仍然存在，特别是在温度较宽的使用范围，仍会影响温度系数。
图4为本发明实施例提供的另一种CMOS高温基准电压源电路示意图。
在另一个实施例中，在-40℃至200℃的范围内，温度依赖性补偿需要一个互补的温度系数参考电路。
如图4所示，在图3的基础上增加了一套温度系数参考电路。基准核心电路还包括：第三电阻R3、第四电阻R4、彼此串联的第三阻抗电路和第四阻抗电路；其中，彼此串联的第三阻抗电路和第四阻抗电路中第三阻抗电路的一端与第一PMOS管M4漏极相连，另一端与地或电源VSS连接。
第三阻抗电路和第四阻抗电路构成第二分压电路，第三阻抗电路由MOS管实现,第四阻抗电路由多个MOS管实现,且所述多个MOS管可以根据温度变化,由多个开关分别选择通断,第三阻抗电路和第四阻抗电路之间的节点提供第二电压输出。
第三电阻R3和第四电阻R4串联在第一电压输出和第二电压输出之间，第三电阻R3和第四电阻R4之间的节点提供第三电压输出。
在本实施例中，第三阻抗电路结构可以为：第二NMOS管Mn2和第二电阻器R2；第四阻抗电路可以为：n个开关Sy1～Syn、n个反向开关Sy1N～SynN和n个彼此并联的NMOS管My1～Myn。
在本实施例中，将耗尽型NMOS管Mn2的漏极连接在M4的漏极上。Mn2的源极连接第二电阻器R2的第一端，R2的第二端与n个增强型NMOS管My1～yn的漏极相连，同时R2的第二端还与n个反向开关Sy1N～SynN中相对应的开关的第一端相连，n个反向开关Sy1N～SynN中相对应的开关的第二端与n个增强型NMOS管My1～Myn中的每个NMOS管的栅极相连，n个增强型NMOS管My1～Myn中的每个NMOS管的源极与VSS相连。n个增强型NMOS管My1～Myn中的每个NMOS管的栅极同时还与n个开关Sy1～Syn中相对应的开关的一端相连，n个开关Sy1～Syn中的每个开关的另一端与VSS相连。当开关Sy1～Syn打开时，相对应的反向开关Sy1N～SynN中的开关就会闭合，反之亦然。将VREF1与VREF2之间串联电阻R3和R4，在电阻R3和R4之间输出加权后的VREF_ZERO基准电压。
在本实施例中，Mn1和Mn2为耗尽型NMOS管，其阈值电压大于0；Mx1～Mxn和My1～Myn为增强型NMOS管，其阈值电压小于0。
在一个实施例中，为方便计算，可以将R1、R2设置为0。在其他实施例中，电阻器R1和R2用于微调温度系数。R1和R2作为微调电阻器，用于微调VREF的温度系数。本领域技术人员应当注意R1和E2可以是可编程电阻器或者使用各种类型的电阻器。
结合图3可知,VREF1的温度系数为
Figure PCTCN2019074472-appb-000010
可以看出，如果正确的选择K，那么后两项可以相互抵消。然而第一项
Figure PCTCN2019074472-appb-000011
扔然存在，特别是在温度较宽的使用范围，仍会影响温度系数。
于是对VREF2使用上述相同的方法，
Figure PCTCN2019074472-appb-000012
通过选择K2来获得VREF2的温度系数，作为VREF温度系数的补偿，实现VREF和VREF2的互补。
将上述方程①和②组合起来，便有了
Figure PCTCN2019074472-appb-000013
通过对R3和R4的调整，可以最大限度的降低VREF_ZERO的温度系数的波动，以便可以在很宽的温度范围内实现平稳的低温度系数。
通过调整VREF1与VREF2之间不同的n个增强型NMOS管，他们的温度系数将会有不同的变化，最终基准电压VREF_ZERO通过R3和R4适当的加权，成为VREF1与VREF2的线性组合，使得温度系数变得更加平坦。从而实现了极低温度系数高温度范围的基准电压。
VREF_ZERO可以广泛应用于高温ADC和DAC。
在另一个实施例中，根据不同需求，还可以选择并联更多的Mn。图中未示出。
其中
Figure PCTCN2019074472-appb-000014
q为并联的Mn的个数。Mn的个数q和Mx1～Mxn的个数m可以不同，不同是取值用作微调温度系数。
图5为图4所示的参考电压与温度变化曲线图。
如图5所示，通过加权后的参考电压与温度变化，可以看出曲线在-40℃至200℃之间变化十分平稳。从而实现了极低温度系数高温度范围的基准电压。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而 已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

  1. 一种CMOS高温基准电压源，其特征在于，包括：
    偏置电路，在输出端提供偏置电流；
    基准核心电路，包括：
    第一PMOS管(M4)，其源极连接电源(VDD)，栅极连接偏置电路的输出端；
    低压差线性稳压器(LDO)，耦合在所述第一PMOS管(M4)的漏极与地(VSS)之间；
    第一分压电路，与低压差线性稳压器并联，包括彼此串联的第一阻抗电路和第二阻抗电路；其中，第一阻抗电路包括第一MOS管；第二阻抗电路包括分别在开关的控制下选择通断的多个第二MOS管,且通断的第二MOS管的数量可以根据温度变化确定；第一阻抗电路和第二阻抗电路之间的第一节点提供第一电压输出。
  2. 根据权利要求1所述的电路，其特征在于，第一MOS管是第一NMOS管(Mn1)；所述第一阻抗电路还包括：第一电阻器(R1)；其中，所述第一NMOS管(Mn1)的源极与所述第一电阻器(R1)的第一端相连，所述第一NMOS管(Mn1)的栅极与所述第一电阻器(R1)的第二端相连。
  3. 根据权利要求1所述的电路，其特征在于，所述多个第二MOS管彼此并联。
  4. 根据权利要求3所述的电路，其特征在于，所述多个第二MOS管是n个第二NMOS管(Mx1～Mxn)，所述第二阻抗电路还包括：分别耦合在n个第二NMOS管的栅极和源极之间的n个开关(Sx1～Sxn)、分别耦合在n个第二NMOS管的栅极和漏极之间的n个反向开关(Sx1N～SxnN)。
  5. 根据权利要求1所述的电路，其特征在于，所述基准核心电路还包括：
    第二分压电路，与低压差线性稳压器并联，包括彼此串联的第三阻抗 电路和第四阻抗电路；其中，第三阻抗电路包括第三MOS管；第四阻抗电路包括分别在开关的控制下选择通断的多个第四MOS管实现,且通断的第四MOS管的数量可以根据温度变化确定；
    第三分压电路，耦合在第一电压输出和第二电压输出之间；第三分压电路中的第三节点提供第三电压输出。
  6. 根据权利要求5所述的电路，其特征在于，第三MOS管是第三NMOS管(Mn2)；所述第三阻抗电路结构还包括第二电阻器(R2)；其中，所述第三NMOS管(Mn2)的源极与所述第二电阻器(R2)的第一端相连，所述第三NMOS管(Mn2)的栅极与所述第二电阻器(R2)的第二端相连。
  7. 根据权利要求5所述的电路，其特征在于，所述多个第四MOS管彼此并联。
  8. 根据权利要求7所述的电路，其特征在于，所述多个第四MOS管是n个第四NMOS管(My1～Myn)；所述第四阻抗电路包括：分别耦合在n个第四NMOS管的栅极和源极之间的n个第二开关(Sy1～Syn)、分别耦合在n个第四NMOS管的栅极和漏极之间的n个第二反向开关(Sy1N～SynN)。
  9. 根据权利要求5所述的电路，其特征在于，第三分压电路包括串联的第三电阻(R3)和第四电阻(R4)；第三节点位于所述第三电阻(R3)和所述第四电阻(R4)之间。
  10. 根据权利要求4所述的电路，其特征在于，所述第一NMOS管(Mn1)为耗尽型NMOS管，所述n个第二NMOS管(Mx1～Mxn)为增强型NMOS管。
  11. 根据权利要求8所述的电路，其特征在于，所述第三NMOS管(Mn2)为耗尽型NMOS管，所述n个第四NMOS管(My1～Myn)为增强型NMOS管。
  12. 根据权利要求4所述的电路，其特征在于，通过选择控制系数K，使得
    Figure PCTCN2019074472-appb-100001
    其中，Vtn为所述第一NMOS管(Mn1)的阈值电压，Vtx为n个第二NMOS管(Mx1～Mxn)的阈值电压；控制系数K由所述第一NMOS管(Mn1)和所述n个第二NMOS管(Mx1～Mxn)材料的参数共同决定， 具体为
    Figure PCTCN2019074472-appb-100002
    其中
    Figure PCTCN2019074472-appb-100003
    Figure PCTCN2019074472-appb-100004
    Wn为所述第一NMOS管(Mn1)的宽度，Ln为所述第一NMOS管(Mn1)的长度，Un为所述第一NMOS管(Mn1)的迁移率，Cox为MOS管氧化层电容；Wx为所述第二NMOS管(Mx1-Mxn)的宽度，Lx为所述第二NMOS管(Mx1-Mxn)的长度，Ux为所述第二NMOS管(Mx1-Mxn)的迁移率；m为所述n个第二NMOS管(Mx1～Mxn)选中的个数。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104503530A (zh) * 2015-01-09 2015-04-08 中国科学技术大学 一种高性能高可靠度的低压cmos基准电压源
CN105739596A (zh) * 2016-03-04 2016-07-06 广东顺德中山大学卡内基梅隆大学国际联合研究院 一种应用二次正温度系数补偿的高精度基准电压源电路
US9785180B2 (en) * 2016-03-11 2017-10-10 Qorvo Us, Inc. Bias circuitry
CN107368143A (zh) * 2017-08-29 2017-11-21 电子科技大学 一种低功耗的基准电压源
US20170357285A1 (en) * 2016-06-14 2017-12-14 The Regents Of The University Of Michigan Variation-Tolerant Voltage Reference
CN108319323A (zh) * 2018-02-13 2018-07-24 杭州芯元微电子有限公司 一种cmos高温基准电压源

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5883507A (en) * 1997-05-09 1999-03-16 Stmicroelectronics, Inc. Low power temperature compensated, current source and associated method
CN103684347B (zh) * 2012-09-11 2016-07-06 瑞昱半导体股份有限公司 可调式阻抗电路以及阻抗设定方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104503530A (zh) * 2015-01-09 2015-04-08 中国科学技术大学 一种高性能高可靠度的低压cmos基准电压源
CN105739596A (zh) * 2016-03-04 2016-07-06 广东顺德中山大学卡内基梅隆大学国际联合研究院 一种应用二次正温度系数补偿的高精度基准电压源电路
US9785180B2 (en) * 2016-03-11 2017-10-10 Qorvo Us, Inc. Bias circuitry
US20170357285A1 (en) * 2016-06-14 2017-12-14 The Regents Of The University Of Michigan Variation-Tolerant Voltage Reference
CN107368143A (zh) * 2017-08-29 2017-11-21 电子科技大学 一种低功耗的基准电压源
CN108319323A (zh) * 2018-02-13 2018-07-24 杭州芯元微电子有限公司 一种cmos高温基准电压源

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