WO2019154375A1 - 光学次模块及光模块 - Google Patents

光学次模块及光模块 Download PDF

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Publication number
WO2019154375A1
WO2019154375A1 PCT/CN2019/074614 CN2019074614W WO2019154375A1 WO 2019154375 A1 WO2019154375 A1 WO 2019154375A1 CN 2019074614 W CN2019074614 W CN 2019074614W WO 2019154375 A1 WO2019154375 A1 WO 2019154375A1
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WO
WIPO (PCT)
Prior art keywords
pin
adapter plate
electrical
chip
module
Prior art date
Application number
PCT/CN2019/074614
Other languages
English (en)
French (fr)
Inventor
王永强
Original Assignee
青岛海信宽带多媒体技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201810141454.9A external-priority patent/CN108387979A/zh
Priority claimed from CN201810141503.9A external-priority patent/CN108333694B/zh
Priority claimed from CN201810140868.XA external-priority patent/CN108333693B/zh
Application filed by 青岛海信宽带多媒体技术有限公司 filed Critical 青岛海信宽带多媒体技术有限公司
Publication of WO2019154375A1 publication Critical patent/WO2019154375A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements

Definitions

  • the present application relates to the field of optical communication technologies, and in particular, to an optical sub-module and an optical module.
  • COB Chip-on-Borad packaging technology
  • TO Transistor-Outline packaging technology
  • the coaxial TO package Because the coaxial TO package has many advantages such as simple package, good versatility and fast production efficiency, it is widely used in optical communication products.
  • the base of the coaxial package generally includes a base and a pin disposed on the base, and the top surface of the base is used for mounting an optical communication device such as a chip.
  • an optical communication device such as a chip.
  • the conventional base includes a total of 7 to 8 pins, the pins are disposed on the periphery of the base, and the intermediate portion is used to mount devices such as communication chips.
  • the base cannot leave enough area to install the communication chip.
  • the embodiment of the present application provides an optical sub-module and an optical module.
  • the present application provides an optical sub-module including a base, a chip, an electrical adapter plate, and a first pin passing through the base; the electrical adapter plate is mounted on an upper surface of the base; The chip is mounted on an upper surface of the electrical riser board, the first pin is located on a lower surface of the electrical riser board; the electrical riser board has a conductive line, and the conductive line implements the first An electrical connection between a pin and the chip.
  • the optical sub-module can reserve enough space for mounting electronic devices such as chips. Even if there are many pins arranged on the optical sub-module, for example, more than 10, the optical sub-module can still adopt coaxial TO packaging technology.
  • the encapsulation is performed so that the optical sub-module can ensure the installation space of the electronic components such as chips on the optical sub-module under the premise of satisfying the additional pins.
  • the present application further provides an optical module, where the optical module includes the optical sub-module described above.
  • FIG. 1 is a schematic structural view of an optical sub-module according to a first embodiment of the present application
  • FIG. 3 is a schematic structural view of a base in an optical sub-module according to a first embodiment of the present application
  • FIG. 4a is a schematic structural view of a first electrical adapter plate in an optical sub-module according to a first embodiment of the present application
  • 4b is a schematic diagram of a lower surface of a first electrical adapter plate in the optical sub-module of the first embodiment of the present application;
  • Figure 4c is a cross-sectional view taken along line A-A of Figure 4b;
  • 4d is a schematic diagram of the upper surface of the first electrical adapter plate in the optical sub-module of the first embodiment of the present application;
  • 4e is a schematic view of a lower surface of a second electrical adapter plate in the optical sub-module of the first embodiment of the present application;
  • FIG. 5 is a schematic perspective structural view of a coaxial package base in an optical sub-module according to a second embodiment of the present application.
  • FIG. 6 is an exploded view of a coaxial package base in an optical sub-module according to a second embodiment of the present application.
  • FIG. 7 is a schematic structural view of an electrical adapter plate placed on a base in an optical sub-module according to a second embodiment of the present application.
  • FIG. 8 is a schematic structural view of a second electrical transfer board stacked on a first electrical transfer board in an optical sub-module according to a second embodiment of the present application;
  • Figure 9 is a schematic cross-sectional view of Figure 8.
  • FIG. 10 is a schematic structural view showing a pin of an optical sub-module mounted on a base according to a second embodiment of the present application;
  • FIG. 11 is a schematic perspective structural view of a coaxial package base in an optical sub-module according to a third embodiment of the present application.
  • FIG. 12 is a schematic structural view showing a second electrical transfer board stacked on a first electrical transfer board in an optical sub-module according to a third embodiment of the present application;
  • Figure 13 is a schematic cross-sectional view of Figure 12;
  • FIG. 14 is a schematic perspective structural view of a coaxial package base in an optical sub-module according to a fourth embodiment of the present application.
  • FIG. 15 is a schematic perspective structural view of an optical sub-module according to a second embodiment of the present application.
  • the base of the coaxial package of the conventional optical sub-module generally has 7 to 8 pins.
  • the number of pins exceeds a certain number, for example, 10, most of the space on the base is managed. The foot is occupied and there is not enough space for the installation of optical communication electronics.
  • the conventional base has been unable to adapt to the current high transmission rate optical communication products, so that the coaxial package
  • the application of technology to high transmission rate optical communication products is limited.
  • the present application proposes a new optical sub-module that can reserve enough space for mounting electronic devices such as chips, even if there are many pins disposed on the optical sub-module, for example More than 10, the optical sub-module can still be packaged using coaxial TO packaging technology.
  • the optical sub-module may be a transmitting optical sub-assembly (TOSA), or a receiving optical sub-assembly (ROSA), or a light transmitting and receiving integrated optical transmitting and receiving module.
  • TOSA transmitting optical sub-assembly
  • ROSA receiving optical sub-assembly
  • BOSA Bi-Directional optical sub-assembly
  • the optical sub-module includes: a base, a chip, an electrical adapter board, and a first pin disposed on the base for transmitting a signal, and the electrical adapter board is mounted on the upper surface of the base, The chip is mounted on the upper surface of the electrical riser board, and the first pin is located on the lower surface of the electrical riser board; wherein the electrical riser board has a conductive line, and the conductive line realizes an electrical connection between the first pin and the chip.
  • the first pin 21 is located in a projection area of the electrical adapter plate 30 on the base 10, and the lower surface of the electrical adapter plate 30 is provided with a conductive In line 40, one end of the conductive line 40 is electrically connected to the first pin 21, and the other end thereof is electrically connected to the chip 50.
  • the base 10 in order to realize the signal transmission of the optical sub-module and ensure the transmission rate of the optical sub-module, as shown in FIG. 3, the base 10 is provided with a first pin 21; wherein the base 10 is provided with a a first through hole 11 is formed in the first through hole 11 , and a diameter of the first through hole 11 is larger than a diameter of the first pin 21 to ensure that the first pin 21 can pass through the inside of the first through hole 11 .
  • a sealing material is filled between the first pin 21 and the inner wall of the first through hole 11.
  • the sealing material is a glass material.
  • the electrical adapter plate 30 provided by the embodiment of the present application can achieve the above-mentioned functions by providing a mounting space for the chip or other electronic device and ensuring signal transmission between the pin and the chip.
  • the electrical adapter plate 30 is disposed on the base 10.
  • the electrical adapter plate 30 may be supported by a support member disposed on the base 10, or electrically connected.
  • the board 30 is attached to the base 10 and is supported by the base 10.
  • the electrical adapter plate 30 is a ceramic plate.
  • the first pin 21 is located in the projection area of the electrical adapter plate 30 on the base 10. wherein, as shown in FIG. 2, the projection area (shown by a broken line) refers to the electrical adapter plate 30 along the central axis of the base 10. The projection area on the base 10 in the direction (see the Z direction in the figure).
  • the electrical adapter plate 30 includes a lower surface 31 facing the base 10 and opposite the lower surface 31, that is, away from the upper surface 32 of the base 10. Alternatively, the chip 50 is disposed on the upper surface 32. The mounting space is provided for the chip 50 by the electrical adapter plate 30.
  • a conductive line 40 is disposed on the lower surface 31 of the electrical adapter plate 30 toward the base 10.
  • the first end 41 of the conductive line 40 is electrically connected to the first pin 21, and the other end of the conductive line 40, that is, the second end 42
  • the signal is transmitted between the first pin 21 and the chip 50 through the conductive line 40.
  • the second end 42 can also be a pad.
  • the conductive line 40 is disposed along the direction from the first end 41 to the outer edge of the electrical riser board 30, and the end adjacent to the outer edge of the electrical riser board 30 is the second end 42, and the second end 42 and the chip 50 electrical connections. That is, the conductive line 40 includes two ends, that is, the first end 41 and the second end 42, and the second end 42 is disposed closer to the outer edge of the electrical adapter plate 30 than the first end 41.
  • the outer edge of the electrical adapter plate 30 refers to the edge or edge of the electrical adapter plate 30.
  • a conductive line 40 is disposed on the lower surface 31 of the electrical adapter plate 30.
  • the end of the first pin 21 is electrically connected to the first end 41 of the conductive line 40, and the chip 50 disposed on the electrical adapter plate 30 is mounted and electrically conductive.
  • the second end 42 of the line 40 is electrically connected, and the first pin 21 disposed near the center of the base 10 or the electrical adapter plate 30 is electrically connected to the conductive line 40 disposed in a direction toward the outer edge of the electrical adapter plate 30.
  • the chip 50 is electrically connected to one end of the conductive line 40 adjacent to the outer edge of the electrical adapter plate 30 to direct the signal transmission path of the first pin 21 and the chip 50 in the direction from the center of the electrical adapter plate 30 to the outer edge thereof.
  • the arrangement further circumvents the space area for accommodating the mounting chip 50 on the electrical adapter plate 30, and ensures the installation space of the electronic components of the chip and the like on the optical sub-module under the premise of satisfying the additional pins, and satisfies the high optical communication product.
  • the conductive line 40 can be formed by plating a conductive metal layer on the lower surface 31.
  • a first via 33 is disposed on the electrical adapter plate 30 at a position corresponding to the second end 42 of the conductive line 40.
  • the first via 33 is electrically connected to the second end 42 and the chip 50 is firstly connected.
  • the holes 33 are electrically connected to form an electrical connection between the second end 42 and the chip 50 to complete signal transmission between the first pin 21 and the chip 50.
  • the first via hole 33 is disposed through the lower surface 31 and the upper surface 32 of the electrical riser board 30 so as to pass the first pin 21 located under the lower surface 31 and the chip 50 located on the upper surface 32 through the first pass.
  • the holes 33 are electrically connected.
  • a conductive metal layer is disposed on the inner wall of the first via 33.
  • the conductive metal layer is The gold material layer, the silver material layer or other metal material layer, further, the conductive metal layer may be disposed on the inner wall of the first via hole 33 by means of electroplating.
  • a conductive metal layer is disposed at the end of the first via 33 at the lower surface 31 and the upper surface 32 to improve electrical Connection stability.
  • the chip 50 disposed on the electrical adapter plate 30 is connected to the first via hole 33 through a gold wire, and the gold wire, the first via hole 33 and the conductive line 40 are implemented between the chip 50 and the first pin 21 Signal transmission.
  • the chip 50 may be a laser chip, a light detecting chip, a driving chip, or a semiconductor electric cooler (TEC) chip.
  • TEC semiconductor electric cooler
  • the embodiment of the present application is not specifically limited herein.
  • the electrical adapter plate 30 in the embodiment of the present application may also provide a mounting area for other electronic devices to meet the corresponding functional requirements of the product.
  • the electronic device disposed on the electrical adapter plate 30 includes The light emitter, the light receiver, the diode, the resistor, the capacitor, the inductor, etc. (some electronic components are not shown), and the disposed electronic device is electrically connected to the first pin 21 to realize signal transmission between the two.
  • the base 10 is further provided with a second pin 22 for transmitting a signal, wherein the second pin 22 is located outside the projection area or in the projection area (the dotted line in the figure) On the boundary shown, the second pin 22 is disposed closer to the edge of the base 10 than the first pin 21, that is, the second pin 22 is disposed on the periphery of the first pin 21.
  • a second via hole 34 corresponding to the second pin 22 is disposed on the electrical adapter plate 30, and the second via hole 34 is disposed through the lower surface 31 and the upper surface 32 of the electrical adapter plate 30 so as to be located on the lower surface
  • the second pin 22 below the 31 is electrically connected to the chip 50 on the upper surface 32 by a second via 34 disposed through the upper surface 32 and the lower surface 31.
  • a conductive metal layer is disposed on the inner wall of the second pin 22, wherein the second pin 22
  • the material of the conductive metal layer and the processing method of the inner wall are the same as those of the inner wall of the first pin 21, which will not be described herein.
  • the second pin 22 and the chip 50 are connected by a gold wire to realize signal transmission.
  • first via hole 33 and the second via hole 34 opened on the electrical adapter plate 30 can be disposed along the outer edge of the electrical adapter plate 30, thereby the first via hole 33 and the second hole.
  • the via hole 34 is in the form of a semicircular or arc-shaped via hole.
  • the first via hole 33 and the second via hole 34 are formed.
  • the chip 50 can be provided with a larger mounting area on the upper surface 32 of the electrical riser plate 30.
  • the first via hole 33 and the second via hole 34 are opened on the electrical adapter plate 30 in the form of a circular via hole.
  • the main difference between the first electrical adapter plate and the second electrical adapter plate in this embodiment is that in the first electrical adapter plate, the first via 33 and the second via are 34 is in the form of a semicircular or arcuate via; in the second electrical adapter plate, the first via 33 and the second via 34 are in the form of circular vias.
  • other features of the electrical adapter plate are applicable to the first electrical adapter plate and the second electrical adapter plate.
  • the base 10 is further provided with a third pin 23 for transmitting a signal, wherein the third pin 23 has a signal transmission rate greater than the first pin 21 and the second pin 22, and is disposed on the base 10
  • the third pin 23 can meet the transmission requirement of the optical sub-module for the high-frequency signal.
  • the third pin 23 is directly connected to the chip 50, wherein In order to prevent the third pin 23 from interfering with the mounting space of the chip 50 on the electrical adapter plate 30, a notch 35 is formed on the electrical adapter plate 30 and at a position corresponding to the third pin 23, of course, A notch or a through hole may be disposed; the third pin 23 is disposed through the corresponding notch 35, and the third pin 23 is directly electrically connected to the chip 50. Optionally, the third pin 23 and the chip 50 pass through. The gold wire is electrically connected, thereby ensuring the transmission quality of the high frequency signal transmitted by the third pin 23.
  • the third pin 23 is disposed closer to the edge of the base 10 than the first pin 21, that is, the second pin 22 is disposed on the periphery of the first pin 21, thereby being electrically
  • a notch 35 corresponding to the third pin 23 on the board 30 is disposed adjacent to the outer edge of the electrical adapter plate 30, and provides a larger mounting area for the chip 50 on the electrical adapter plate 30.
  • the optical sub-module provided by the embodiment of the present application includes a base, a chip, an electrical adapter board, and a first pin that is disposed on the base and configured to transmit a signal, where the first pin is located at the In the projection area of the electrical adapter plate on the base, the lower surface of the electrical adapter plate is provided with a conductive line, one end of the conductive line is electrically connected to the first pin, and the other end is disposed at the The chip is electrically connected to the electrical transfer board.
  • the first pin located in the projection area of the base of the electrical adapter plate is connected to the conductive path disposed on the electrical adapter plate, and electrically connects the first pin and the chip via the conductive path to realize the first pin and The signal transmission between the chips, thereby providing the chip with the installation space occupied by the additional pins on the base through the electrical adapter board, and realizing the communication between the pins and the chip through the conductive lines disposed on the electrical adapter board
  • the connection enables the optical sub-module to ensure the installation space of the electronic components such as the chip on the optical sub-module under the premise of satisfying the additional pins.
  • the optical sub-module may further include a cap (not shown), the cap is combined with the base to form a package space, and the chip and the electrical adapter plate are disposed in the package space.
  • a lens is disposed in the cap, and the lens is used to shape or change the optical path to enable the chip to receive or emit an optical signal through the lens.
  • the electrical adapter plate is one, and the first pin is located on the lower surface of the electrical adapter plate. After the assembly is completed, the electrical adapter plate covers the first pin, and a circuit is formed on the lower surface of the electrical adapter plate.
  • One end of the circuit is connected to the first pin, and the other end extends toward the edge of the adapter plate to avoid the chip on the surface of the electrical adapter plate, and then extends through the metal layer of the via hole or the edge to extend to the electrical adapter plate.
  • the upper surface is connected to the pad to achieve electrical connection between the first pin and the pad.
  • the number of electrical adapter plates is not limited to one, but may be two or more.
  • FIG. 5 is a perspective structural view of a coaxial package base in an optical sub-module according to some embodiments of the present application
  • FIG. 6 is an exploded view of a coaxial package base in an optical sub-module according to some embodiments of the present application.
  • the coaxial package base 10 of the embodiment includes a base 11, a first pin 12, a first electrical adapter plate 13, and a second electrical adapter plate 14.
  • the first pin 12 is mounted on the base 11, and the first pin 12 extends from one side of the base 11 to the other side.
  • the first electrical adapter plate 13 is mounted on the top surface of the base 11 on the other side, that is, the first electrical adapter plate 13 is mounted on the upper surface of the base 11; the first pin 12 and the first electrical adapter plate 13 are under Surface contact.
  • the second electrical adapter plate 14 is mounted on the upper surface of the first electrical adapter plate 13.
  • the first electrical adapter plate 13 and the second electrical adapter plate 14 may be made of the same material, for example, the first electrical adapter plate 13 and the second electrical adapter plate 14 are both ceramic plates made of a ceramic material.
  • the first electrical adapter plate 13 and the second electrical adapter plate 14 may also be made of different insulating materials. Since the circuit needs to be formed on the electrical adapter plate, the material of the electrical adapter plate itself needs to be insulated to place a conductive material such as metal at a position where the circuit is formed.
  • Figure 7 is a schematic view of the electrical adapter plate placed on the base in some embodiments.
  • a plurality of spaced-apart first via holes 131 are formed on the first electrical adapter plate 13.
  • the inner wall of the first via hole 131 is plated with a conductive layer, and the conductive layer may be a metal layer, and the metal layer may be a gold material layer. Silver material layer, etc.
  • the first via 131 penetrates from the upper surface to the lower surface of the first electrical adapter plate 13 such that the first via 131 can be electrically connected to the first pin 12 mounted on the base 11.
  • a small amount of metal layer (the metal layer may be a pad) is also plated in the peripheral region of the two ports of the first via 131.
  • the size of the first via 131 may be slightly smaller than the size of the first pin 12 such that the first pin 12 can contact the metal layer around the port of the first via 131.
  • the first via 131 is disposed at an intermediate portion of the first electrical riser plate 13 to transfer the electrical connection point of the first pin mounted at the intermediate portion of the base 11 to the edge region.
  • a plurality of conductive lines 132 are formed on the upper surface of the first electrical adapter plate 13.
  • the conductive line 132 extends from the first via 131 to a predetermined area of the first electrical riser board 13 , and the conductive line 132 is electrically connected to the first via 131 .
  • the predetermined area is an edge area.
  • the conductive line 132 can be widened, thickened or enlarged near the end 1322 of the edge region.
  • a plurality of conductive grooves 133 are spaced apart from the outer peripheral side wall of the first electrical adapter plate 13.
  • the conductive groove 133 is substantially semi-circular and extends from the lower surface of the first electrical riser plate 13 to the upper surface of the first electrical riser plate 13.
  • the conductive groove 133 is electrically connected to the first pin 12 disposed on the outer circumference of the first electrical adapter plate 13.
  • the inner wall of the groove of the conductive groove 133 is plated with a conductive layer, and the conductive layer may be a metal layer, which may be a gold material layer, a silver material layer or other metal material layer.
  • the metal layer may be a pad
  • a small amount of metal layer is also plated in the peripheral region of the upper and lower ports of the conductive groove 133.
  • the conductive layer of the inner wall of the conductive recess 133, the conductive layer of the inner wall of the first via 131 and the conductive line 132 constitute a conductive transfer line for transferring the first pin to a predetermined area of the first electrical adapter plate 13.
  • FIG. 8 is a schematic structural view of a second electrical transfer board stacked on a first electrical transfer board in some embodiments.
  • the second electrical adapter plate 14 is mounted on the upper surface of the first electrical adapter plate 13 by bonding or soldering, and the upper surface of the second electrical adapter plate 14 (ie, the side away from the first connecting plate 13) is divided. There are two areas, one of which is the installation area 141 and the other area is the transition area 142.
  • the mounting region 141 is plated with a metal layer for mounting electronic devices such as chips.
  • a plurality of second via holes 143 are spaced apart from the outer peripheral sidewall of the transfer region 142.
  • the number of the second via holes 143 is determined according to the number of the first pins 12, and the second via holes 143 and the first electrical vias
  • the conductive recess 133 on the tab 13 is aligned with the end 1322 of the conductive trace 132.
  • the conductive layer on the inner wall of the second via 143 constitutes a conductive via of the second electrical riser board 14.
  • FIG. 9 is a cross-sectional view of FIG. 8.
  • the metal layer 135 and the metal layer 136 are respectively plated on the periphery of the upper port and the lower port of the first via 131 of the first electrical adapter plate 131.
  • the metal layer 135 and the metal layer 136 may also be pads.
  • the metal layer 135 around the lower port is electrically connected to the first pin 12 located in the middle portion of the base 11.
  • the metal layer 136 and the conductive line 132 around the upper port are electrically connected.
  • the conductive line 132 is electrically connected to the second via 143, and the end 1322 of the conductive line 132 is raised, widened and thickened relative to other portions to allow the conductive line 132 to contact the inner wall of the second via 143.
  • the periphery of the port of the second via 143 away from the first electrical riser plate 13 is also plated with a metal layer through which electrical connection to an electronic device such as a chip can be achieved.
  • the periphery of the upper port of the conductive recess 133 of the first electrical adapter plate 131 is plated with a metal layer (not shown), and the periphery of the lower port is also plated with a metal layer 137, and the metal layer 137 is first adjacent to the edge of the base 11.
  • the metal layer around the upper port is in contact with the second via 143 of the second electrical adapter plate 14, so that the first pin 12 and the second electrical adapter plate 14 near the edge of the base 11 are realized.
  • the electrical connection of the two vias 143 is plated with a metal layer (not shown), and the periphery of the lower port is also plated with a metal layer 137, and the metal layer 137 is first adjacent to the edge of the base 11.
  • the electrical adapter plate of the present application transfers the electrical connection point of the first pin 12 mounted on the base 11 to the predetermined area of the electrical adapter plate through the first via 131, the conductive line 132 and the conductive groove 133.
  • the connection point of the first pin 12 and the chip is gathered in a predetermined area of the first electrical adapter plate 13, and the connection points are simultaneously transferred to a predetermined area of the second electrical adapter plate 14 so that the second electricity
  • the adapter board 14 can leave enough space for mounting the optical communication electronic device, and even if the optical sub-module has many pins, it can be packaged by the coaxial TO packaging technology.
  • the optical sub-module further includes a second pin for high speed signal transmission.
  • the second pin cannot use the electrical adapter board, so the second pin is disposed on the base of the electrical adapter board.
  • the non-projected area of the surface, the electrical adapter plate does not cover the second pin.
  • the second pin is required to be connected as close as possible to the chip, so that a gap is formed in the electrical adapter plate so that the second pin is embedded or passed through the electrical adapter plate to achieve a close connection with the chip on the electrical adapter plate.
  • the optical sub-module further includes a second pin 121 and a second pin 122 for transmitting high frequency signals.
  • the line or pin transmitting high-frequency signals is prevented from being bent to affect the transmission quality of the signal, and the second pin 121 and the second pin 122 are not switched, as shown in FIG. 5 and FIG.
  • the second pin 121 and the second pin 122 are not transferred and directly pass through the first electrical adapter plate 13 and the second electrical adapter plate 14.
  • the first electrical adapter plate 13 and the second electrical adapter plate 14 are respectively provided with notches 134 and notches 144 through which the pins for transmitting high frequency signals are transmitted at respective outer periphery.
  • the notch 134 of the first electrical adapter plate 13 and the notch 144 of the second electrical adapter plate 14 are aligned to facilitate direct extension of the non-switching high speed pin.
  • FIG. 10 is a schematic structural view of a pin mounted on a base.
  • the base 11 is provided with a plurality of through holes 111 through which the first pins 12 pass.
  • the size of the through holes 111 matches the diameter of the first pin 12, that is, the size of the through holes 111 is slightly larger than that of the first pin 12. size.
  • a sealing material layer 112 is filled between the first pin 12 and the inner wall of the through hole 111.
  • the sealing material layer 112 may be a layer of glass material. The sealing material layer 112 is filled after the first pin 12 is placed in the through hole 111.
  • the surface of the second electrical adapter plate 14 is further mounted with a driving chip electrically connected to the corresponding pin 12 through a conductive line on the second electrical adapter plate.
  • FIG. 11 is a perspective structural view of a coaxial package base of the present application in some embodiments.
  • the coaxial package base 20 of the embodiment includes a base 21, a plurality of pins 22, a first electrical adapter plate 23, and a second electrical adapter plate 24.
  • a plurality of pins 22 are mounted on the base 21 and penetrate from one side of the base 21 to the other side.
  • the first electrical adapter plate 23 is mounted on the top surface of the base 21 on the other side, and the second electrical adapter plate 24 is mounted on the first electrical adapter plate 23.
  • the base 21 and the pin 22 are similar in structure and function to the base 11 and the pin 12 of the above-described embodiment, and are not described herein again.
  • the difference between this embodiment and the above embodiment mainly lies in the first electrical adapter plate and the second electrical adapter plate, which will be mainly described below.
  • the first electrical adapter plate 23 and the second electrical adapter plate 24 may be made of the same material.
  • the first electrical adapter plate 23 and the second electrical adapter plate 24 are both ceramic plates made of a ceramic material.
  • first electrical adapter plate 23 and the second electrical adapter plate 24 can also be made of different materials.
  • FIG. 12 is a schematic structural view showing a second electrical transfer plate stacked on a first electrical transfer plate in some embodiments
  • FIG. 13 is a cross-sectional view of FIG.
  • the first electrical adapter plate 23 is provided with a plurality of via holes 231 electrically connected to the pins mounted in the intermediate portion of the base 21.
  • a plurality of conductive grooves 233 are disposed on the outer peripheral side wall of the first electrical adapter plate 23.
  • the conductive grooves 233 are electrically connected to the pins 22 mounted outside the intermediate portion of the base 21.
  • the conductive grooves 233 and the two ports of the via holes 231 are both plated with a metal layer 251.
  • a plurality of conductive lines 232 are disposed on the upper surface of the first electrical adapter plate 23, and a portion of the conductive lines 232 are electrically connected to the via holes 231, and a portion of the conductive lines 232 are electrically connected to the conductive grooves 233.
  • the conductive layer on the inner wall of the via 231, the conductive layer on the inside of the conductive recess 233, and the conductive line 23 constitute the conductive via of the first electrical riser board 23.
  • the second electrical adapter plate 24 covers the upper surface of the first electrical adapter plate 23.
  • the upper surface of the second electrical adapter plate 24 is divided into two regions, one of which is the mounting region 241 and the other region is the adapter. Area 242.
  • the mounting region 241 is plated with a metal layer 252 for mounting an electronic device such as a chip, which can serve as a ground for the electronic device.
  • the transition region 242 is provided with a plurality of conductive vias 243, and the conductive vias 243 are spaced apart around the central axis of the second electrical riser board 24 and arranged in a circular shape.
  • the via 243 is electrically connected to the electronic device mounted on the mounting region 241 by a wire.
  • the conductive layer of the via 243 constitutes a conductive via of the second electrical riser board 24.
  • a part of the conductive line 232 on the upper surface of the first electrical adapter plate 23 connects the conductive recess 233 and the through hole 243 of the second electrical adapter plate 24, and the other part of the conductive line 232 connects the via 231 and the second electrical adapter plate 24.
  • Via 243 whereby all conductive grooves 233 and vias 231 on the first electrical riser plate 23 can be electrically connected to the vias 243 on the second electrical riser board 24 to place all of the pins 22
  • the electrical connection point is transferred into the transition region 242 of the second electrical riser board 24, thereby preserving sufficient space in the mounting area 241 to mount the electronics.
  • the through hole may be disposed on the first electrical adapter plate 23 and the second electrical adapter plate 24, and the inner wall of the through hole is not A conductive metal layer is disposed such that the high speed pins can extend directly through the through holes through the first electrical riser plate 23 and the second electrical transfer plate 24 without being transferred.
  • Figure 14 is a perspective view of a coaxial package of the present application in some embodiments.
  • the coaxial package base 30 of the present embodiment is substantially the same as the coaxial package base 10 of the above embodiment, except that the coaxial package base 30 of the embodiment is provided with a vertical mounting plate 35, and the first in this embodiment.
  • the shape of the electrical adapter plate 33 and the second electrical adapter plate 34 are different from those of the first electrical adapter plate 13 and the second electrical adapter plate 14 in the above-described embodiments.
  • the coaxial package base 30 of the embodiment includes a base 31, a plurality of pins 32, a first electrical adapter plate 33, and a second electrical adapter plate 34.
  • a plurality of pins 32 are mounted on the base 31 and penetrate from one side of the base 31 to the other side.
  • the first electrical adapter plate 33 is mounted on the top surface of the base 31 on the other side, and the second electrical adapter plate 34 is mounted on the first electrical adapter plate 33.
  • the second electrical adapter plate 34 has a horizontal mounting surface 341 for mounting electronic components such as chips.
  • the first electrical adapter plate 33 and the second electrical adapter plate 34 are identical in shape and polygonal in shape, and the shapes of the two are determined according to the mounting position of the vertical mounting plate 35.
  • the first electrical adapter plate 33 and the second electrical adapter plate 34 in this embodiment are the same as the above-described embodiments except that the shape is different from the above embodiment, and therefore, details are not described herein again.
  • the vertical mounting plate 35 is vertically mounted on the second electrical adapter plate 34 with a vertical mounting surface 351 for vertical mounting of the electronics.
  • the vertical mounting plate 35 can be directly mounted on the grounded pin and electrically connected to the grounded pin.
  • the coaxial package base 30 of the present embodiment not only has a horizontal mounting surface 341 but also a vertical mounting surface 351. Thereby, the coaxial package base 30 of the embodiment can be applied to an electronic device that needs to be horizontally mounted or vertically mounted. The device broadens the application range of the coaxial package base of the present application.
  • FIG. 15 is a schematic structural view of an optical sub-module in some embodiments.
  • the optical sub-module 100 of the present embodiment includes the coaxial package base 10 described in the above embodiments and the electronic device 40 mounted on the coaxial package base 10.
  • the electronic device 40 may include a chip, a refrigerator, a light emitter, and a light receiver. , diodes, resistors, capacitors, inductors, etc. (some electronic components are not shown).
  • the various components of the electronic device 40 can be electrically connected to the conductive recesses 143 of the second electrical riser board 14 via wires 41.
  • the first pin 12 is transferred to a predetermined area of the first electrical riser board 13 through the conductive line or conductive recess 133 of the first electrical riser board 13, and the conductive line or conductive recess 133 of the first electrical riser board 13
  • the first pin 12 is transferred to the second electrical adapter plate 14 through the conductive recess 143 of the second electrical adapter plate 14.
  • the electronic device 40 is connected to the conductive recess 143 of the second electrical adapter plate 14 via the wire 41 to achieve electrical connection with the corresponding first pin 12.
  • a sufficient space can be reserved on the second electrical adapter plate 14 to mount the electronic device 40.
  • the second pins 121, 122 for transmitting high frequency signals are directly transmitted through the first electrical adapter plate 13 and the second electrical adapter plate 14, and are directly electrically connected to the electronic device 40 through the wires 41.
  • the optical sub-module 10 of the present application is mainly used as an example to illustrate the optical sub-module 100 of the present application.
  • the coaxial sub-mount 100 of the optical sub-module 100 of the present application may also adopt the same.
  • the application discloses a coaxial package base in other embodiments.
  • An embodiment of the present application further provides an optical module, where the optical module includes the optical sub-module in any of the foregoing embodiments.

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Abstract

一种光学次模块及光模块。光学次模块包括底座（10）、多条管脚（21）、电转接板（30）和芯片（50）。管脚（21）安装在底座（10）上。电转接板（30）安装在底座（10）的顶面，电转接板（30）上设置有导电线路（40），导电线路（40）与对应的管脚（21）电连接，以将管脚（21）的电连接点转接至电转接板（30）上。芯片（50）安装在电转接板（30）的表面，且芯片（50）通过电转接板（30）上的导电线路（40）与对应的管脚（21）电连接。该光学次模块能够留出足够的空间用于安装电子器件，确保该光学次模块可采用TO封装技术进行封装。

Description

光学次模块及光模块
本申请要求在2018年02月11日提交中国专利局、申请号为201810140868.X、申请名称为“光学次模块及光模块”的中国专利申请的优先权，在2018年02月11日提交中国专利局、申请号为201810141503.9、申请名称为“一种光学次模块及光模块”的中国专利申请的优先权，在2018年02月11日提交中国专利局、申请号为201810141454.9、申请名称为“光学次模块”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及光通信技术领域，特别涉及一种光学次模块及光模块。
背景技术
光通信产品例如光学次模块等采用的封装技术主要有两种，一种是COB(Chip-on-Borad)封装技术，即板上芯片封装；另一种是TO(Transistor-Outline)封装技术，即同轴TO封装。由于同轴TO封装具有封装简单、通用性好、生产效率快等多种优势，在光通信产品中得到广泛应用。
目前，同轴封装的底座通常包括底座和设置在底座上的管脚，底座的顶面用于安装芯片等光学通信器件。随着光通信产品的传输速率的不断提高，为了满足光通信产品高传输速率的要求，需在底座的顶面安装更多的器件，例如，制冷器，因此，必须在底座上设置更多的管脚来连接其他器件。传统的底座包括的管脚数量一般在7～8个，管脚设置在底座的外围，中间区域用于安装通信芯片等器件，然而，对于多管脚的光学通信产品，例如，超过10个管脚的光通信产品，底座无法留出足够的区域安装通信芯片。
发明内容
为了解决目前底座无法留出足够的区域安装通信芯片等电子器件的问题， 本申请实施例提供了一种光学次模块及光模块。
第一方面，本申请提供了一种光学次模块，包括底座、芯片、电转接板及穿过所述底座的第一管脚；所述电转接板安装于所述底座的上表面；所述芯片安装于所述电转接板的上表面，所述第一管脚位于所述电转接板的下表面；所述电转接板具有导电线路，所述导电线路实现所述第一管脚与所述芯片之间的电连接。
该光学次模块能够预留出足够的空间用于安装芯片等电子器件，即便在该光学次模块上布设的管脚较多，例如超过10个，该光学次模块仍可采用同轴TO封装技术进行封装，使得光学次模块在满足增设管脚的前提下，可保证芯片等电子器件在光学次模块上的安装空间。
第二方面，本申请还提供一种光模块，该光模块包括上述的光学次模块。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施例的光学次模块的结构示意图；
图2为本申请第一实施例的光学次模块的分解图；
图3为本申请第一实施例的光学次模块中底座的结构示意图；
图4a为本申请第一实施例的光学次模块中第一种电转接板的结构示意图；
图4b为本申请第一实施例的光学次模块中第一种电转接板的下表面的示意图；
图4c为图4b的A-A剖视图；
图4d为本申请第一实施例的光学次模块中第一种电转接板的上表面的示意图；
图4e为本申请第一实施例的光学次模块中第二种电转接板的下表面的示 意图；
图5为本申请第二实施例的光学次模块中同轴封装底座的立体结构示意图；
图6为本申请第二实施例的光学次模块中同轴封装底座的分解图；
图7为本申请第二实施例的光学次模块中电转接板放置在底座上的结构示意图；
图8为本申请第二实施例的光学次模块中第二电转接板叠放在第一电转接板上的结构示意图；
图9为图8的剖面结构示意图；
图10为本申请第二实施例的光学次模块中管脚安装在底座上的结构示意图；
图11为本申请第三实施例的光学次模块中同轴封装底座的立体结构示意图；
图12为本申请第三实施例的光学次模块中第二电转接板叠放在第一电转接板上的结构示意图；
图13为图12的剖面结构示意图；
图14为本申请第四实施例的光学次模块中同轴封装底座的立体结构示意图；
图15为本申请第二实施例的光学次模块的立体结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
如前所述，传统的光学次模块的同轴封装的底座包含的管脚数量一般为7～8个，当管脚超过一定数量时，例如10个，底座上的大部分空间就会被管脚占用，无法留出足够的空间供光通信电子器件的安装。特别是对于传输速率较高的光通信产品，其涉及的电子器件多，所需的管脚数量也较多，因此， 传统底座已无法适应于目前高传输速率的光通信产品，使同轴封装技术在高传输速率的光通信产品上的应用受到了限制。针对此种问题，本申请提出一种新的光学次模块，该光学次模块能够预留出足够的空间用于安装芯片等电子器件，即便在该光学次模块上布设的管脚较多，例如超过10个，该光学次模块仍可采用同轴TO封装技术进行封装。
该光学次模块可以是光发射次模块(transmitting optical sub-assembly,简称TOSA)，也可以是光接收次模块(receiving optical sub-assembly,简称ROSA)，也可以是光发射接收一体的光发射接收次模块(Bi-Directional optical sub-assembly,简称BOSA)。
第一方面
本申请实施例提供了一种光学次模块。本申请所提供的一些实施例中，光学次模块包括：底座、芯片、电转接板和穿设于底座且用于传输信号的第一管脚，电转接板安装于底座的上表面，芯片安装于电转接板的上表面，第一管脚位于电转接板的下表面；其中，电转接板具有导电线路，该导电线路实现第一管脚与芯片之间的电连接。
请参照图1-4e所示，本申请所提供的一些实施例中，第一管脚21位于电转接板30在底座10上的投影区域内，电转接板30的下表面设有导电线路40，该导电线路40的一端与第一管脚21电连接，其另一端与芯片50电连接。
在一些实施例中，为实现光学次模块的信号传输并保证光学次模块的传输速率，请参照图3所示，底座10上穿设有第一管脚21；其中，底座10上开设有供第一管脚21穿设的第一通孔11，第一通孔11的直径尺寸大于第一管脚21的直径尺寸，以保证第一管脚21可穿设于第一通孔11的内部。为防止封焊漏气的发生，在第一管脚21与第一通孔11内壁之间填充设置密封材料。在一些实施例中，该密封材料为玻璃材料。
为满足光通信产品高传输速率和传输容量的需求，需在底座上增设管脚进行信号传输，在不改变现有底座结构形式的基础上，在底座上原先设置芯片的附近区域增添设置管脚，以使所增设的管脚满足产品信号传输的要求。 在此增设管脚的布设方式下，为芯片或其他电子器件提供安装放置空间并保证管脚与芯片之间的信号传输，本申请实施例提供的电转接板30以实现上述作用。
具体的，如图1和图2所示，电转接板30设置在底座10上，可选的，电转接板30可由设置在底座10上的支撑部件所支撑固定，或，电转接板30与底座10贴合并由底座10支撑，本申请实施例在此不做具体限定。可选的，电转接板30为陶瓷板。
第一管脚21位于电转接板30在底座10上的投影区域内，其中，请参见图2所示，该投影区域(虚线示出)是指电转接板30沿底座10中心轴线的方向(请参见图中Z向)在底座10上的投影区域。
电转接板30包括朝向底座10的下表面31和与下表面31相对，也就是远离底座10的上表面32，可选的，芯片50设置在上表面32上。由电转接板30为芯片50提供安装放置空间。
为实现位于投影区域内的第一管脚21与设置在电转接板30上的芯片50进行电连接，以使第一管脚21与芯片50进行信号传输，请参见图4a-4e所示，在电转接板30朝向底座10的下表面31上设置导电线路40，导电线路40的第一端41与第一管脚21电连接，导电线路40的另一端，即，第二端42与设置在电转接板30上的芯片50电连接，以此通过导电线路40实现第一管脚21与芯片50的信号传输；需要说明的是，该第二端42也可以为焊盘。
具体的，导电线路40是沿由第一端41指向电转接板30外缘的方向所设置，其靠近电转接板30外缘的一端为第二端42，由第二端42与芯片50电连接。也就是说，导电线路40包括两端，即第一端41和第二端42，第二端42较第一端41靠近于电转接板30的外缘所设置。其中，电转接板30的外缘是指电转接板30的边缘或缘部。
在电转接板30的下表面31上设置导电线路40，第一管脚21的端部与导电线路40的第一端41电连接，安装布设在电转接板30上的芯片50与导电线路40的第二端42电连接，将靠近于底座10或电转接板30中心所设置的 第一管脚21与沿朝向电转接板30外缘的方向所设置的导电线路40电连接，芯片50与导电线路40上靠近电转接板30外缘的一端电连接，以将第一管脚21与芯片50的信号传输通路沿由电转接板30中心指向其外缘的方向所设置，进而使电转接板30上避让出用于容纳安装芯片50的空间区域，在满足增设管脚的前提下，保证芯片等电子器件在光学次模块上的安装空间，满足光通信产品高传输速率和传输容量的需求。需要说明的是，导电线路40可通过在下表面31上电镀导电金属层的形式所形成。
进一步的，在电转接板30上与导电线路40的第二端42相对应的位置设置有第一过孔33，第一过孔33与第二端42电连接，芯片50与第一过孔33电连接，进而实现第二端42与芯片50的电连接，完成第一管脚21与芯片50之间的信号传输的。其中，第一过孔33贯穿电转接板30的下表面31和上表面32所设置，以便与位于下表面31下方的第一管脚21与位于上表面32上的芯片50通过第一过孔33电连接。
为实现第一过孔33的导电性，保证第一管脚21与芯片50之间的电连接和信号传输，在第一过孔33的内壁设置导电金属层，可选的，导电金属层为金材料层、银材料层或其他金属材料层，进一步的，导电金属层可通过电镀的加工方式设置在第一过孔33的内壁上。为方便第一过孔33与导电通路40的第二端42和芯片50的电连接，在第一过孔33位于下表面31和上表面32的端部的设置有导电金属层，以提高电气连接稳定性。
进一步的，设置在电转接板30上的芯片50通过金线与第一过孔33相连，由金线、第一过孔33和导电线路40实现芯片50和第一管脚21之间的信号传输。可选的，芯片50可为激光芯片、光探测芯片、驱动芯片或半导体制冷器(Thermo Electric Cooler，TEC)芯片，本申请实施例在此不做具体限定。需要说明的是，本申请实施例中的电转接板30也可为其他电子器件提供安装区域，以满足产品相应的功能需求，可选的，设置在电转接板30上的电子器件包括光发射器、光接收器、二极管、电阻、电容、电感等(部分电子元器件未图示)，所设置的电子器件与第一管脚21电连接，以实现二者之间的信号 传输。
进一步的，本申请提供的实施例中，底座10上还穿设有用于传输信号的第二管脚22，其中，第二管脚22位于投影区域之外，或是在投影区域(图中虚线所示)的边界上，第二管脚22较第一管脚21靠近于底座10的边缘所设置，也就是说，第二管脚22在第一管脚21的外围所布设。在电转接板30上设置与第二管脚22所对应的第二过孔34，第二过孔34贯穿电转接板30的下表面31和上表面32所设置，以便与位于下表面31下方的第二管脚22与位于上表面32上的芯片50通过贯穿上表面32和下表面31设置的第二过孔34电连接。为实现第二过孔34的导电性，保证第二管脚22与芯片50之间的电连接和信号传输，在第二管脚22的内壁设置导电金属层，其中，在第二管脚22内壁所设置的导电金属层的材料和加工方式与第一管脚21内壁相同，本申请实施例在此不做赘述。第二管脚22与芯片50通过金线连接，以实现信号传输。
需要说明的是，在电转接板30上所开设的第一过孔33和第二过孔34可沿电转接板30的外缘所设置，由此，第一过孔33和第二过孔34以呈半圆或圆弧状的过孔形式，具体请参见图4b所示，在本实施例提供的第一种电转接板中，将第一过孔33和第二过孔34靠近于电转接板30的外缘部所设置，由此可为芯片50在电转接板30的上表面32上提供更大的安装区域。可选的，如图4e所示，在本实施例提供的第二种转接板中，将第一过孔33和第二过孔34以圆形过孔形式开设在电转接板30上。需要说明的是，本实施例中的第一种电转接板和第二种电转接板的主要区别在于：在第一种电转接板中，第一过孔33和第二过孔34以呈半圆或圆弧状过孔的形式；在第二种电转接板中，第一过孔33和第二过孔34为圆形过孔的形式。本实施例中，对于电转接板的其他特征描述均适用于第一种电转接板和第二种电转接板。
进一步的，底座10上还穿设有用于传输信号的第三管脚23，其中，第三管脚23对信号的传输速率大于第一管脚21和第二管脚22，通过设置在底座10上的第三管脚23可满足光学次模块对高频信号的传输需求，为保证第三管 脚23的高频信号的传输质量，将第三管脚23直接与芯片50进行电连接，其中，为使得第三管脚23对芯片50在电转接板30上的安装空间不产生干涉，在电转接板30上且对应于第三管脚23的设置位置处开设缺口35，当然，也可以设置槽口或通孔；第三管脚23穿设于所对应开设的缺口35，且第三管脚23直接与芯片50电连接，可选的，第三管脚23与芯片50通过金线实现电连接，进而可保证由第三管脚23所传输的高频信号的传输质量。其中，第三管脚23较第一管脚21靠近于底座10的边缘所设置，也就是说，第二管脚22在第一管脚21的外围所布设，由此，可将在电转接板30上与第三管脚23对应开设的缺口35靠近电转接板30的外缘所设置，在电转接板30上为芯片50提供更大的安装区域。
综上所述，本申请实施例所提供的光学次模块包括底座、芯片、电转接板和穿设于所述底座且用于传输信号的第一管脚，所述第一管脚位于所述电转接板在所述底座上的投影区域内，所述电转接板的下表面设置导电线路，该导电线路的一端与所述第一管脚电连接，其另一端与设置在所述电转接板上的芯片电连接。位于电转接板在底座投影区域内的第一管脚与设置在电转接板上的导电通路相连，并经由导电通路实现第一管脚与芯片的电连接，以实现第一管脚与芯片之间的信号传输，由此，通过电转接板为芯片提供因底座上增设管脚所占据的安装空间，并通过设置在电转接板上的导电线路实现管脚与芯片的通信电连接，使得光学次模块在满足增设管脚的前提下，可保证芯片等电子器件在光学次模块上的安装空间。
进一步的，在其他实施例中，光学次模块还可以包括管帽(图中未示出)，管帽与底座结合以形成封装空间，芯片及电转接板置于该封装空间内。管帽中设置有透镜，透镜用于对光路进行整形或改变，以实现芯片通过透镜接收或发射光信号。在上述实施例中，电转接板为一个，第一管脚位于电转接板下表面，装配完成后，电转接板覆盖第一管脚，在电转接板的下表面形成电路，电路的一端与第一管脚连接，另一端向转接板边缘延伸，以避让电转接板上表面的芯片，然后通过过孔或边缘镀有的金属层，以延伸至电转接板的 上表面，实现与焊盘连接，从而实现第一管脚与焊盘的电连接。但是，电转接板的数量并不仅限于为一个，也可以为两个甚至更多个。
在本申请提供的一些实施例中，电转接板为两个，分别为第一电转接板和第二电转接板。如图5和图6所示，图5为本申请一些实施例的光学次模块中同轴封装底座的立体结构图，图6为本申请一些实施例的光学次模块中同轴封装底座的爆炸图。本实施例的同轴封装底座10包括底座11、第一管脚12、第一电转接板13和第二电转接板14。第一管脚12安装在底座11上，且第一管脚12的从底座11的一侧贯穿至另一侧。第一管脚12的一端部略突出于底座11的另一侧，即第一管脚12的一端部略突出于底座11的上表面。第一电转接板13安装在底座11位于另一侧的顶面，即第一电转接板13安装在底座11的上表面；第一管脚12与第一电转接板13的下表面接触。第二电转接板14安装在第一电转接板13的上表面。
第一电转接板13和第二电转接板14可以由相同材料制成，例如，第一电转接板13和第二电转接板14均为由陶瓷材料制成的陶瓷板。
在其它实施例中，第一电转接板13和第二电转接板14也可以由不同的绝缘材料制成。由于需要在电转接板上形成电路，所以电转接板本身材质需要绝缘，以在形成电路的位置放置金属等导电材料。
结合图7所示，图7为在一些实施例中电转接板放置在底座上的结构示意图。第一电转接板13上形成多个间隔分布的第一过孔131，第一过孔131的内壁上镀有导电层，该导电层可以是金属层，该金属层可以是金材料层、银材料层等。第一过孔131从第一电转接板13的上表面贯穿到下表面，使得第一过孔131能够与安装在底座11的第一管脚12电连接。为方便线路的连接，在第一过孔131两端口的周边区域也镀有少量的金属层(该金属层可以是焊盘)。第一过孔131的尺寸可以略小于第一管脚12的尺寸，使得第一管脚12能够接触第一过孔131端口周边的金属层。在本实施例中，第一过孔131设置在第一电转接板13的中间部分，以将安装在底座11中间部分的第一管脚的电连接点转接至边缘区域。
第一电转接板13的上表面形成多条导电线路132。导电线路132从第一过孔131处一直延伸至第一电转接板13的预定区域，且导电线路132与第一过孔131电连接。在本实施例中，该预定区域为边缘区域。藉此，将中间部分的第一管脚12的电连接点转接至边缘区域，使各第一管脚12与芯片等电子器件的连接点聚集在边缘区域。
为加强导电线路132与第二电转接板14对应的第二过孔143的连接，可将导电线路132靠近边缘区域的末端1322加宽、加厚或加大。
第一电转接板13的外周侧壁上间隔设置有多个导电凹槽133。导电凹槽133大致呈半圆形，其从第一电转接板13的下表面延伸至第一电转接板13的上表面。导电凹槽133与布设在第一电转接板13外周的第一管脚12电连接。
该导电凹槽133的凹槽内壁镀有一层导电层，该导电层可以是金属层，该金属层可以是金材料层、银材料层或其他金属材料层。为方便线路的连接，在导电凹槽133的上、下两端口的周边区域也镀有少量的金属层(该金属层可以为焊盘)。
上述导电凹槽133内壁的导电层、第一过孔131内壁的导电层和导电线路132构成用于将第一管脚转接至第一电转接板13预定区域的导电转接线路。
结合图8所示，图8为在一些实施例中第二电转接板叠放在第一电转接板上的结构示意图。第二电转接板14通过粘结或焊接的方式安装在第一电转接板13的上表面，第二电转接板14的上表面(即远离第一连接板13的一面)被分为两个区域，其中一个区域为安装区域141，另一个区域为转接区域142。安装区域141上镀有金属层，用于安装芯片等电子器件。转接区域142的外周侧壁上间隔设置有多个第二过孔143，该第二过孔143的数量根据第一管脚12的数量而定，且第二过孔143与第一电转接板13上的导电凹槽133和导电线路132的末端1322相对齐。该第二过孔143内壁的导电层构成第二电转接板14的导电转接线路。
第一电转接板13的导电凹槽133、导电线路132与第二电转接板14的第二过孔143形成电连接。具体的，请参阅图9，图9为图8的剖面示意图，在 第一电转接板131的第一过孔131的上端口和下端口的周边分别镀有金属层135和金属层136(其中，金属层135和金属层136也可以为焊盘)，下端口周边的金属层135与位于底座11中间区域的第一管脚12电连接，上端口周边的金属层136与导电线路132电连接，导电线路132与第二过孔143电连接，导电线路132的末端1322相对于其它部分被加高、加宽和加厚，以使导电线路132能接触到第二过孔143的内壁。第二过孔143远离第一电转接板13的端口的周边也同样镀有金属层，通过该金属层可实现与芯片等电子器件的电连接。
第一电转接板131的导电凹槽133的上端口的周边镀有金属层(未图示)，其下端口的周边也镀有金属层137，金属层137与靠近底座11边缘的第一管脚12接触，上端口周边的金属层与第二电转接板14的第二过孔143接触，如此，实现靠近底座11边缘的第一管脚12与第二电转接板14的第二过孔143的电连接。
因此，本申请的电转接板将安装在底座11上的第一管脚12的电连接点通过第一过孔131、导电线路132和导电凹槽133转接至电转接板的预定区域，使第一管脚12与芯片的连接点聚集在第一电转接板13的预定区域，该些连接点同时又被转接至第二电转接板14的预定区域，使得第二电转接板14上能够留出足够的空间用于安装光通信电子器件，即使光学次模块所含管脚较多的情况下，仍能够采用同轴TO封装技术进行封装。
进一步的，光学次模块还包括用于高速信号传输的第二管脚。考虑到通过电转接板方案实现的电转接，不利于高速信号的传输，所以本实施例中第二管脚不能使用电转接板，所以第二管脚设置在电转接板在底座表面的非投影区域，电转接板不会覆盖第二管脚。第二管脚要求与芯片尽可能近距离连接，所以在电转接板上开设缺口，以便第二管脚嵌入或穿过电转接板，实现与电转接板上芯片的近距离连接。
本申请提供的实施例中，光学次模块还包括用于传输高频信号的第二管脚121和第二管脚122。为了满足高频信号传输的需求，避免传输高频信号的 线路或管脚弯曲而影响信号的传输质量，第二管脚121和第二管脚122不转接，如图5和图6所示，第二管脚121和第二管脚122不转接且直接透过第一电转接板13和第二电转接板14。对应的，第一电转接板13和第二电转接板14在各自的外周边分别设置有供传输高频信号的管脚透过的槽口134和槽口144。第一电转接板13的槽口134和第二电转接板14的槽口144相对齐，以方便不转接的高速管脚直接伸出。
如图10所示，图10为管脚安装在底座上的结构示意图。底座11上设置有多个供第一管脚12穿过的贯穿孔111，贯穿孔111的尺寸与第一管脚12的直径尺寸匹配，即贯穿孔111的尺寸略大于第一管脚12的尺寸。为防止封焊易漏气的问题，在第一管脚12与贯穿孔111的内壁之间填充有密封材料层112。密封材料层112可以为玻璃材料层。其中，该密封材料层112是在第一管脚12放入至贯穿孔111后再填充的。
进一步，如图15所示，第二电转接板14的表面还安装有驱动芯片，该驱动芯片通过第二电转接板上的导电线路与对应的管脚12电连接。
在一些实施例中，如图11所示，图11为在一些实施例中本申请的同轴封装底座的立体结构示意图。本实施例的同轴封装底座20包括底座21、多条管脚22、第一电转接板23和第二电转接板24。多条管脚22安装在底座21上，且从底座21的一侧贯穿至另一侧。第一电转接板23安装在底座21位于该另一侧的顶面，第二电转接板24安装在第一电转接板23上。
本实施例中底座21和管脚22与上面所述实施例的底座11和管脚12结构、功能相似，在此不再赘述。本实施例与上面实施例的区别主要在于第一电转接板和第二电转接板，以下将重点说明。
第一电转接板23和第二电转接板24可以由相同材料制成，例如，第一电转接板23和第二电转接板24均为由陶瓷材料制成的陶瓷板。
在其它实施例中，第一电转接板23和第二电转接板24也可以由不同的材料制成。
结合图12和图13所示，图12为在一些实施例中第二电转接板叠放在第 一电转接板上的结构示意图，图13为图12的剖面示意图。第一电转接板23上设置有多个过孔231，该些过孔231与安装在底座21中间区域的管脚电连接。第一电转接板23的外周侧壁上设置有多个导电凹槽233。该些导电凹槽233与安装在底座21中间区域之外的管脚22电连接。该些导电凹槽233和该些过孔231的两端口周边均镀有金属层251。第一电转接板23的上表面布设有多条导电线路232，部分导电线路232与过孔231电连接，部分导电线路232与导电凹槽233电连接。
上述过孔231的内壁上的导电层、导电凹槽233内部上的导电层以及上述导电线路23构成第一电转接板23的导电转接线路。
第二电转接板24覆盖在第一电转接板23的上表面，第二电转接板24的上表面被分成两个区域，其中一个区域为安装区域241，另一个区域为转接区域242。安装区域241上镀有金属层252，用于安装芯片等电子器件，该金属层252可作为电子器件的接地端。转接区域242设置多个导电穿孔243，且该些导电穿孔243围绕第二电转接板24的中心轴间隔设置且排列成圆形。过孔243通过导线可与安装在安装区域241的电子器件电连接。
上述过孔243的导电层构成第二电转接板24的导电转接线路。
第一电转接板23上表面的部分导电线路232连接导电凹槽233和第二电转接板24的过孔243，另一部分导电线路232连接过孔231和第二电转接板24的过孔243，藉此，第一电转接板23上的所有导电凹槽233、过孔231能够与第二电转接板24上的过孔243电连接，以将所有的管脚22的电连接点转接至第二电转接板24的转接区域242中，进而在安装区域241中预留足够的空间安装电子器件。
此外，在本实施例中，为适应于传输高频信号的高速管脚，也可在第一电转接板23和第二电转接板24上设置通孔，该通孔的内壁上不设置导电的金属层，如此，该类高速管脚可穿过通孔直接伸出第一电转接板23和第二电转接板24，而不经过转接。
在一些实施例中，如图14所示，图14为在一些实施例中本申请同轴封 装底座的立体结构示意图。本实施例的同轴封装底座30与上面实施例中的同轴封装底座10大致相同，区别在于：本实施例的同轴封装底座30设置有垂直安装板35，以及本实施例中的第一电转接板33、第二电转接板34的形状不同于上面所述实施例中的第一电转接板13、第二电转接板14的形状。
本实施例的同轴封装底座30包括底座31、多条管脚32、第一电转接板33和第二电转接板34。多条管脚32安装在底座31上，且从底座31的一侧贯穿至另一侧。第一电转接板33安装在底座31位于另一侧的顶面，第二电转接板34安装在第一电转接板33上。第二电转接板34具有供芯片等电子器件安装的水平安装面341。
第一电转接板33和第二电转接板34形状相同且呈多边形，两者的形状根据垂直安装板35的安装位置而定。本实施例中的第一电转接板33和第二电转接板34除形状与上面实施例不同外，其它结构和功能均与上面所述实施例相同，因此，在此不再赘述。
垂直安装板35垂直安装在第二电转接板34上，其具有供电子器件垂直安装的垂直安装面351。垂直安装板35可直接安装在接地的管脚上，并与接地的管脚电连接。
因此，本实施例的同轴封装底座30不仅具有水平安装面341，还具有垂直安装面351，藉此，本实施例的同轴封装底座30可适用于即需水平安装也需垂直安装的电子器件，扩宽了本申请的同轴封装底座的应用范围。
在一具体实施方式中，如图15所示，图15为在一些实施例中光学次模块的结构示意图。本实施例的光学次模块100包括上述实施例所述的同轴封装底座10和安装在同轴封装底座10的电子器件40，电子器件40可以包括芯片、制冷器、光发射器、光接收器、二极管、电阻、电容、电感等(部分电子元器件未图示)。电子器件40的各个器件可通过导线41与第二电转接板14的导电凹槽143电连接。第一管脚12通过第一电转接板13的导电线路或导电凹槽133转接至第一电转接板13的预定区域，第一电转接板13的导电线路或导电凹槽133再通过第二电转接板14的导电凹槽143将第一管脚12 转接至第二电转接板14上。如此，电子器件40通过导线41连接第二电转接板14的导电凹槽143，即可实现与对应第一管脚12的电连接。并且，由于第一电转接板13的转接作用，第二电转接板14上可预留出足够的空间安装电子器件40。
此外，对于用于传输高频信号的第二管脚121、122则直接透过第一电转接板13和第二电转接板14，并通过导线41直接与电子器件40电连接。
本实施例主要以第二实施例的同轴封装底座10为例，说明本申请的光学次模块100，但并不限于此，本申请的光学次模块100的同轴封装底座同样也可以采用本申请揭露其他实施方式中的同轴封装底座。
第二方面
本申请实施例还提供了一种光模块，该光模块包括上述任意实施例中的光学次模块。
以上所述仅为本申请的较佳实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种光学次模块，其特征在于，包括底座、芯片、电转接板及穿过所述底座的第一管脚；
    所述电转接板安装于所述底座的上表面；
    所述芯片安装于所述电转接板的上表面，所述第一管脚位于所述电转接板的下表面；
    所述电转接板具有导电线路，所述导电线路实现所述第一管脚与所述芯片之间的电连接。
  2. 如权利要求1所述的光学次模块，其特征在于，所述第一管脚位于所述电转接板在所述底座上的投影区域内；
    所述电转接板的下表面设有所述导电线路，所述导电线路的一端与所述第一管脚电连接，其另一端与所述芯片电连接。
  3. 如权利要求2所述的光学次模块，其特征在于，所述导电线路沿其与所述第一管脚连接的一端指向所述电转接板外缘的方向设置，所述导电线路靠近所述电转接板外缘的一端与所述芯片电连接。
  4. 如权利要求3所述的光学次模块，其特征在于，所述导电线路靠近所述电转接板外缘的一端与设置在所述电转接板上的第一过孔的一端电连接，所述芯片与所述第一过孔的另一端电连接。
  5. 如权利要求1所述的光学次模块，其特征在于，还包括第二管脚；
    所述第二管脚位于所述电转接板在所述底座上的投影区域外；
    所述第二管脚与设置在所述电转接板上的第二过孔的一端电连接，所述芯片与所述第二过孔的另一端电连接。
  6. 如权利要求1所述的光学次模块，其特征在于，还包括第三管脚；
    所述第三管脚穿过所述电转接板与所述芯片电连接；
    其中，所述第三管脚的传输速率大于所述第一管脚的传输速率。
  7. 如权利要求6所述的光学次模块，其特征在于，所述电转接板上具有 槽口或通孔，所述第三管脚穿设于所述槽口或通孔内。
  8. 如权利要求1所述的光学次模块，其特征在于，所述电转接板包括第一转接板和第二转接板；
    所述第一转接板安装于所述底座的上表面，所述第一管脚与所述第一转接板的下表面电连接，所述第一转接板的上表面设置有所述导电线路；
    所述第二转接板安装于所述第一转接板的上表面；
    所述芯片安装于所述第二转接板的上表面，所述第二转接板在所述芯片周围设有焊盘，所述芯片与所述焊盘电连接；
    所述导电线路的一端与所述第一转接板的下表面电连接，另一端与所述焊盘电连接。
  9. 如权利要求8所述的光学次模块，其特征在于，所述第一转接板具有第一过孔，所述第一管脚与所述第一过孔的一端电连接；
    所述导电线路的一端与所述第一过孔的另一端电连接，以实现所述导电线路的一端与所述第一转接板的下表面电连接。
  10. 如权利要求8所述的光学次模块，其特征在于，所述第二转接板具有第二过孔，所述导电线路的另一端与所述第二过孔的一端电连接，所述第二过孔的另一端与所述焊盘电连接，以实现所述导电线路的另一端与所述焊盘电连接。
  11. 如权利要求8所述的光学次模块，其特征在于，所述第二转接板的外周侧壁上设置有导线，所述导电线路的另一端与所述导线的一端电连接，所述导线的另一端与所述焊盘电连接，以实现所述导电线路另一端与所述焊盘电连接。
  12. 如权利要求8所述的光学次模块，其特征在于，还包括第二管脚；
    所述第一转接板的边缘区域和所述第二转接板的边缘区域均设置有供所述第二管脚延伸透过的槽口或通孔，使得所述第二管脚从所述第一连接板的下表面延伸至所述第二连接板的上表面。
  13. 如权利要求1至12任一所述的光学次模块，其特征在于，还包括，具有透镜的管帽，所述管帽与所述底座结合以封装所述光学次模块，所述芯片通过所述透镜接收或发射光信号。
  14. 如权利要求1至12任一所述的光学次模块，其特征在于，所述芯片为激光芯片、光探测芯片、驱动芯片或TEC芯片。
  15. 如权利要求1至12任一所述的光学次模块，其特征在于，还包括安装板，所述安装板具有安装面；
    所述安装板安装于所述电转接板的上表面，且所述安装面与所述电转接板的上表面相互垂直。
  16. 一种光模块，其特征在于，包括权利要求1至权利要求15任一项所述光学次模块。
PCT/CN2019/074614 2018-02-11 2019-02-02 光学次模块及光模块 WO2019154375A1 (zh)

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